ABES ENGINEERING COLLEGE, GHAZIABAD

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

COURSE MATERIAL

SUBJECT NAME: Microprocessor & Microcontroller

SUBJECT CODE : KEC502
BRANCH/SEM : ECE/5th

FACULTY MENTOR: Dr. Sanjay Kr. Singh

TEAM MEMBERS : Ms. Ranjeeta Yadav

Ms. Tania Gupta
Mr. Rajeev Kumar Pandey
 CHAPTER-3: 16-BIT MICROPROCESSORS (8086) &
PERIPHERAL DEVICES
3.1 16-bit Microprocessors (8086)

3.1.1 8086 Features

3.1.2 8086 Architecture,
3.1.3 Physical address generation,
3.1.4 Memory Segmentation
3.1.5 Memory organization
3.1.6 8086 Pin Description
3.1.7 Addressing modes
3.1.8 Questions Related to the topic

3.2 Peripheral Devices

3.2.1 8259 programmable interrupt controllers

3.2.2 8253/8254programmable timer/counter
3.2.3 8251 USART and RS232C
3.2.4 8237 DMA Controller
3.2.5 8255 programmable peripheral interfaces
 3.1 16-BIT MICROPROCESSORS (8086)

3.1.1 8086 FEATURES

Features of 8086
• It is a 16-bit Microprocessor. It’s ALU, internal registers work with 16-bit binary words.
• 8086 has a 20-bit address bus that can access up to 220= 1 MB memory locations.
• 8086 has a 16-bit data bus. It can read or write data to a memory/port either 16bits or 8 bits
at a time.
• It can support up to 64K I/O ports.
• It provides 14, 16 -bit registers.
• Frequency range of 8086 is 6-10 MHz
• It has multiplexed address and data bus AD0- AD15 and A16 – A19.
• It requires a single-phase clock with a 33% duty cycle to provide internal timing.
• It can prefetch up to 6 instruction bytes from memory and queues to up instruction
execution.
• It requires a +5V power supply.
• A 40-pin dual in-line package.
• 8086 is designed to operate in two modes, Minimum mode, and Maximum mode.
o The minimum mode is selected by applying logic 1 to the MN / MX input pin. This
is a single microprocessor configuration.
o The maximum mode is selected by applying logic 0 to the MN / MX input pin. This
is a multi-microprocessors configuration.

3.1.2 8086 ARCHITECTURES

8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit) and BIU (Bus Interface
Unit).

EU (Execution Unit)

The execution unit gives instructions to BIU stating from where to fetch the data and then decode and execute
those instructions. Its function is to control operations on data using the instruction decoder & ALU. EU has
no direct connection with system buses as shown in the above figure, it performs operations over data through
BIU.

Let us now discuss the functional parts of 8086 microprocessors.

ALU

It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.
 Fig 3.1 8086 architecture

Flag Register

It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result stored in
the accumulator. It has 9 flags, and they are divided into 2 groups − Conditional Flags and Control Flags.

Fig 3.2 Flag Register of 8086

Conditional Flags
It represents the result of the last arithmetic or logical instruction executed. Following is the list of
conditional flags −
• Carry flag − This flag indicates an overflow condition for arithmetic operations.

• Auxiliary flag − When an operation is performed at ALU, it results in a carry/borrow

from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e.
carry given by D3 bit to D4 is AF flag. The processor uses this flag to perform binary to
BCD conversion.

• Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order
8-bits of the result contains an even number of 1’s, then the Parity Flag is set. For an odd
number of 1’s, the Parity Flag is reset.

• Zero flag − This flag is set to 1 when the result of an arithmetic or logical operation is
zero else it is set to 0.

• Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is
negative, then the sign flag is set to 1 else set to 0.

• Overflow flag − This flag represents the result when the system capacity is exceeded.

Control Flags
Control flags control the operations of the execution unit. Following is the list of control flags −
• Trap flag − It is used for single-step control and allows the user to execute one instruction
at a time for debugging. If it is set, then the program can be run in a single-step mode.

• Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the

interruption of a program. It is set to 1 for interrupt enabled condition and set to 0 for
interrupt disabled condition.

• Direction flag − It is used in string operation. As the name suggests when it is set then
string bytes are accessed from the higher memory address to the lower memory address
and vice-versa.

General purpose register

There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers can
be used individually to store 8-bit data and can be used in pairs to store 16bit data. The valid register
pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred to as the AX, BX, CX, and
DX respectively.
• AX register − It is also known as the accumulator register. It is used to store operands for
arithmetic operations.
• BX register − It is used as a base register. It is used to store the starting base address of the
memory area within the data segment.
• CX register − It is referred to as counter. It is used in loop instruction to store the loop counter.
• DX register − This register is used to hold the I/O port addresses for I/O instruction.
Stack Pointer register

It is a 16-bit register, which holds the address from the start of the segment to the memory location, where a
word was most recently stored on the stack.

BIU (Bus Interface Unit)

BIU takes care of all data and address transfers on the buses for the EU like sending addresses, fetching
instructions from the memory, reading data from the ports and the memory as well as writing data to the ports
and the memory. EU has no direct connection with System Buses, so this is possible with the BIU. EU and
BIU relate to the Internal Bus.
It has the following functional parts −
• Instruction queue − BIU contains the instruction queue. BIU gets upto 6 bytes of next
instructions and stores them in the instruction queue. When EU executes instructions and is
ready for its next instruction, then it simply reads the instruction from this instruction queue
resulting in increased execution speed.

• Fetching the next instruction while the current instruction executes is called pipelining.

• Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of
instructions and data in memory, which are used by the processor to access memory locations.
It also contains 1 pointer register IP, which holds the address of the next instruction to executed
by the EU.
o CS − It stands for Code Segment. It is used for addressing a memory location in
the code segment of the memory, where the executable program is stored.
o DS − It stands for Data Segment. It consists of data used by the program and is
accessed in the data segment by an offset address or the content of other registers
that holds the offset address.
o SS − It stands for Stack Segment. It handles memory to store data and addresses
during execution.
o ES − It stands for Extra Segment. ES is an additional data segment, which is
used by the string to hold the extra destination data.

• Instruction pointer − It is a 16-bit register used to hold the address of the next instruction to
be executed.

3.1.3 MEMORY SEGMENTATION

Memory segmentation is nothing which is the method where the whole memory is divided into smaller parts.
In 8086 microprocessor memory is divided into four parts which is known as segments. These segments are
data segment, code segment, the stack segment and extra segment.

The total memory size is divided into segments of various sizes. A segment is just an area in memory. The
process of dividing memory this way is called Segmentation.
In memory, data is stored as bytes. Each byte has a specific address. Intel 8086 has 20 lines address bus.
With 20 address lines, the memory that can be addressed is 220 bytes. 220= 1,048,576 bytes (1 MB). 8086
can access memory with address ranges from 00000 H t o FFFFFH

In 8086, memory has four different types of segments. These are:

• Code Segment,
• Data Segment,
• Stack Segment,
• Extra Segment

Each of these segments is addressed by an address stored in the corresponding segment register. These
registers of 16-bit in size. Each register stores the base address (starting address) of the corresponding
segment. Because the segment registers cannot store 20 bits, they only store the upper 16 bits.

Fig 3.3 Memory segmentation

How is a 20-bit address obtained if there are only 16- bit registers? The 20-bit address of a byte is called
its physical Address. But it is specified as a Logical Address. The logical address is in the form of Base
Address: Offset is the displacement of the memory location from the starting location of the segment.

3.1.4 PHYSICAL ADDRESS GENERATION

The 8086 addresses a segmented memory. The complete physical address which is 20-bits long is generated using
segment and offset registers each of the size 16-bit. The content of a segment registers called a segment address,
and the content of an offset register is also called an offset address. To get total physical address, put the lower
nibble 0H to the segment address and add the offset address. The figure shows the formation of 20-bit physical
address.
 Fig 3.4 Physical Address Generation

Fig 3.5 Example of Physical Address Generation

Q1) The value of Code Segment (CS) Register is 4042H and the value of different offsets is as follows:
BX: 2025H , IP: 0580H , DI: 4247H
Calculate the effective address of the memory location pointed by the CS register.

Ans:

The offset of the CS Register is the IP register.

Therefore, the effective address of the memory location pointed by the CS register is calculated as follows:
Effective address= Base address of CS register X 10H + Address of IP
 = 4042H X 10H + 0580H
= (40420 + 0580)H
= 41000H

Q2) Calculate the effective address for the following register:

SS: 3860H, SP: 1735H, BP: 4826H

Ans:

Both SP and BP are the offsets for Stack Register (SS). The address calculated when BP is taken as the offset
gives the starting address of the stack. The address when SP is taken as the offset denotes the memory
location where the top of the stack lies.

Therefore, the effective address for both these cases is:

(SS X 10H) + SP = 3640H X 10H + 1735H

= 36400H + 1735H
= 38135H
(SS X 10H) + BP = 3640H X 10H + 4826H
= 36400H + 4826H
= 41226H

Q3) The value of the DS register is 3032H. And the BX register contains a 16 bit value which is equal to
3032H. 0008H is added to BX.
ADD BX, 0008H
The register AX contains some value which needs to be stored at a location as follows:
MOV [BX], AX
Calculate the address at which the value of the AX will be stored.

Ans:

After executing the first instruction, the value of BX Register is as follows:

BX = 3040H

The BX register is an offset of the Data Segment (DS) register. So, the location at which the value of the AX
register will be stored is calculated as follows:

(DS X 10H) + BX = 3032H X 10H +3040H

= 30320H + 3040H
= 33360H

Q4) You are provided the following values:

DS: 3056H, IP: 1023H, BP: 2322H and SP: 3029H
Can you calculate the effective address of the memory location as per the DS register?
Ans:

No, the effective address of the DS register cannot be calculated from the given values because none of the
given offset is an offset of the DS Register. This can be done only in the case of segment override prefix, but
as it is not mentioned here, we will not follow that.

3.1.5 Memory Organization of 8086 Microprocessor

There are 20 address lines in the 8086 microprocessor. This gives us 220 different memory locations. Hence
the total size is 220 Bytes (as each memory location is Byte Addressable, i.e. one byte of data can be stored at
every single location), which is equal to 1MB.

Even the memory is byte-addressable, yet the 8086 microprocessor an easily handle up to 16 bits of data at a
time through its 16 data lines. So, to organize the memory efficiently, the entire memory in 8086 is divided
into two memory banks: odd bank and the even bank.

Fig 3.6 Memory Organisation

The way in which data is read or written is decided by the value of BHE, and the last address bit, that is the
A0 line. It is done in the following way:

BHE' A0 Operation performed on memory

0 0 16 bits of data will be read or written into the memory
0 1 8 bits of data will be read/written into the odd memory bank
1 0 8 bits of data will be read/written into the even memory bank
1 1 No operation is performed

To read or write 8 bits of data, it would require only 1 CPU cycle, no matter the data is stored in any of the
memory banks, but to read or write 16 bits of data, the BIU of the 8086 may require either 1 or 2 memory
cycles depending upon whether the lower byte of word is located at even or odd memory address.
 1. If the lower byte of the word is stored at even memory bank and the upper byte is stored at odd
memory bank then the CPU will require only 1 memory cycle. So, it is better to store data in this way.
2. If the lower byte of the word is located at an odd memory address, then the CPU will require 2
memory cycles. The first memory cycle is required for accessing the lower byte of the word through
the higher data bus, i.e. D15 to D8, and the second memory cycle is required for accessing the upper
byte of the word through the lower data bus, i.e. D7 to D0.

3.1.6 Pin Description of 8086 Microprocessor

Figure 3.7 shows the Pin diagram of 8086. The Intel 8086 is 40 pin DIP Microprocessor. 8086 was the first 16-bit
microprocessor available in a 40-pin DIP (Dual Inline Package) chip. Let us now discuss in detail the pin
configuration of an 8086 Microprocessor.
The 8086 can operate in two modes these are the minimum mode and the maximum mode. For minimum mode, a
unique processor system with a single 8086 and for Maximum mode a multi-processor system with more than one
8086. MN/MX- is an input pin used to select one of this mode. when MN/MX is high the 8086 operates in
minimum mode. In this mode the 8086 is configured to support small single processor.

Fig 3.7 Pin diagram of 8086

 Pins Function

AD15 – AD0 These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries
16-bit address and after that it carries 16-bit data.

A16 – A19 These are the 4 address/status buses. During the first clock cycle, it carries 4-
bit address and later it carries status signals.

Vcc It uses 5V DC supply at VCC pin 40

GND These are ground at VSS pin 1 and 20.

Clock Clock signal is provided through Pin-19. It provides timing to the processor for
operations. Its frequency is different for different versions, i.e. 5MHz, 8MHz
and 10MHz.

S7/BHE BHE stands for Bus High Enable. It is available at pin 34 and used to indicate
the transfer of data using data bus D8-D15. This signal is low during the first
clock cycle, thereafter it is active.

Read (RD) It is available at pin 32 and is used to read signal for Read operation.

𝐑𝐞𝐚𝐝𝐲 It is available at pin 32. It is an acknowledgement signal from I/O devices that
data is transferred. It is an active high signal. When it is high, it indicates that
the device is ready to transfer data. When it is low, it indicates wait state.

RESET It is available at pin 21 and is used to restart the execution. It causes the
processor to immediately terminate its present activity. This signal is active
high for the first 4 clock cycles to RESET the microprocessor.

INTR It is available at pin 18. It is an interrupt request signal, which is sampled

during the last clock cycle of each instruction to determine if the processor
considered this as an interrupt or not.

NMI It stands for non-maskable interrupt and is available at pin 17. It is an edge
triggered input, which causes an interrupt request to the microprocessor.

TEST This signal is like wait state and is available at pin 23. When this signal is high,
then the processor has to wait for IDLE state, else the execution continues.

MN/MX It stands for Minimum/Maximum and is available at pin 33. It indicates what
mode the processor is to operate in; when it is high, it works in the minimum
mode and vice-versa.

INTA It is an interrupt acknowledgement signal and id available at pin 24. When the
microprocessor receives this signal, it acknowledges the interrupt.

ALE It stands for address enable latch and is available at pin 25. A positive pulse is
generated each time the processor begins any operation. This signal indicates
 Pins Function

the availability of a valid address on the address/data lines.

DEN It stands for Data Enable and is available at pin 26. It is used to enable
Transceiver 8286. The transceiver is a device used to separate data from the
address/data bus.

DT/R It stands for Data Transmit/Receive signal and is available at pin 27. It decides
the direction of data flow through the transceiver. When it is high, data is
transmitted out and vice-versa.

M/IO This signal is used to distinguish between memory and I/O operations. When it
is high, it indicates I/O operation and when it is low indicating the memory
operation. It is available at pin 28.

WR It stands for write signal and is available at pin 29. It is used to write the data
into the memory or the output device depending on the status of M/IO signal.

HLDA It stands for Hold Acknowledgement signal and is available at pin 30. This
signal acknowledges the HOLD signal.

HOLD This signal indicates to the processor that external devices are requesting to
access the address/data buses. It is available at pin 31.

QS1 and QS0 These are queue status signals and are available at pins 24 and 25. These
signals provide the status of the instruction queue.

S0, S1, S2 These are the status signals that provide the status of the operation, which is
used by the Bus Controller 8288 to generate memory & I/O control signals.
These are available at Pins 26, 27, and 28.

LOCK When this signal is active, it indicates to the other processors not to ask the
CPU to leave the system bus. It is activated using the LOCK prefix on any
instruction and is available at pin 29.

RQ/GT1 and These are the Request/Grant signals used by the other processors requesting the
RQ/GT0 CPU to release the system bus. When the signal is received by the CPU, then it
sends an acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.
There are some conditions for QS0 and QS1. These conditions are as follows.

QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

The S2, S1 and S0 are the status signals. Here is a list of status and their bit patterns.

S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive

3.1.7 Addressing Modes of 8086

The way of specifying data to be operated by an instruction is known as addressing modes. This
specifies that the given data is immediate data or an address. It also specifies whether the given operand
is register or register pair.
Types of addressing modes:
1. Register mode – In this type of addressing mode both the operands are registers.

Example:
MOV AX, BX
XOR AX, DX
ADD AL, BL
2. Immediate mode – In this type of addressing mode the source operand is a 8 bit or 16 bit
data. Destination operand can never be immediate data.

Example:
MOV AX, 2000
MOV CL, 0A
ADD AL, 45
AND AX, 0000
Note that to initialize the value of segment register an register is required.
MOV AX, 2000
MOV CS, AX

3. Displacement or direct mode – In this type of addressing mode the effective address is
directly given in the instruction as displacement.
Example:
MOV AX, [DISP]
MOV AX, [0500]

4. Register indirect mode – In this addressing mode the effective address is in SI, DI or BX.
Example:
Physical Address = Segment Address + Effective Address
MOV AX, [DI]
ADD AL, [BX]
MOV AX, [SI]
5. Based indexed mode – In this the effective address is sum of base register and index
register.
Base register: BX, BP
Index register: SI, DI
The physical memory address is calculated according to the base register.
Example:
MOV AL, [BP+SI]
MOV AX, [BX+DI]
6. Indexed mode – In this type of addressing mode the effective address is sum of index
register and displacement.
Example:
MOV AX, [SI+2000]
MOV AL, [DI+3000]
7. Based mode – In this the effective address is the sum of base register and displacement.
Example:
MOV AL, [BP+ 0100]
8. Based indexed displacement mode – In this type of addressing mode the effective address
is the sum of index register, base register and displacement.
Example:
MOV AL, [SI+BP+2000]
 9. String mode – This addressing mode is related to string instructions. In this, the value of
SI and DI are auto incremented and decremented depending upon the value of directional
flag.
Example:
MOVS B
MOVS W
10. Input/Output mode – This addressing mode is related with input output operations.
Example:
IN A, 45
OUT A, 50
11. Relative mode –
In this the effective address is calculated with reference to instruction pointer.
Example:
JNZ 8 bit address
IP=IP+8 bit address

3.1.8 UNIVERSITY QUESTIONS RELATED TO THE TOPIC

Two-mark questions
Q-1. What do you mean by instruction queue of 8086?
Q-2. What do you mean by pipelining?
Q-3. Draw the block diagram of EU.

Five-mark questions
Q-4. What are the features of the Intel 8086 Microprocessor?
Q-5. Differentiate between 8085 and 8086 Microprocessors?

Ten-mark questions
Q-6. Explain the architecture of 8086. Draw and explain the architecture of the 8086 microprocessors.
Q-7. With a neat diagram, describe the Bus Interface Unit and Execution Unit of 8086. State the
function of each block.
Q-8. Explain the addressing modes of 8086.
 3.1 PERIPHERAL DEVICES

3.2.1 8259 programmable interrupt controllers

Functional Description:
The 8259 A has eight interrupt request inputs, IR0- IR7.The 8259 A uses its INT output to
interrupt the 8085A via INTR pin.The 8259Areceives interrupt acknowledge pulses from the at
its input.Vector address used by the 8085 A to transfer control to the service subroutine of the
interrupting device, is provided by the 8259 A on the data bus.
The 8259A is a programmable device that must be initialized by command words sent by the.
After initialization the 8259A mode of operation can be changed by operation command words.
The descriptions of various blocks are,
Data bus buffer:
This 3- state, bidirectional 8-bit buffer is used to interface the 8259Ato the system data bus.
Control words and status information are transferred through the data bus buffer.
Read/Write & control logic:
The function of this block is to accept OUTPUT commands from the CPU. It contains the
initialization command word (ICW) register and operation command word OCW) register which
store the various control formats for device operation. This function block also allows the status
of 8259A to be transferred to the data bus.
Interrupt request register (IRR):
IRR stores all the interrupt inputs that are requesting service.It keeps track of which interrupt
inputs are asking for service. If an interrupt input is unmasked, and has an interrupt signal on it,
then the corresponding bit in the IRR will be set.
Interrupt mask register (IMR):
The IMR is used to disable (Mask) or enable (Unmask) individual interrupt inputs.Each bit in
this register corresponds to the interrupt input with the same number. The IMR operation on the
IRR. Masking of higher priority input will not affect the interrupt request lines of lower
priority.To unmask any interrupt the corresponding bit is set „0‟.

In service register (ISR):

The in service registers keeps tracks of which interrupt inputs are currently being serviced.For
each input that is currently being serviced the corresponding bit will be set in the in service
register.Each of these 3-reg can be read as status reg.Priority Resolver:
This logic block determines the priorities of the set in the IRR. The highest priority is selected
and strobed into the corresponding bit of the ISR during pulse.
Cascade buffer/comparator:
This function blocks stores and compare the address of all 8259A‟s in the register.The associated
3-I/O pins (CAS0-CAS2) are outputs when8259A is used a master.As a master, the 8259A sends
the ID of the interrupting slave device onto the cas2-cas0.The slave thus selected will send its
pre-programmed subroutine address on to the data bus. Priority Modes of 8259 :
The priority modes availaible in 8259 is
Fully Nested Mode
Automatic Rotation Mode
Specific Rotation Mode
Fully Nested Mode:
This is a general purpose mode in which all IR‟s are arranged from highest to lowest
ie.IR0 is the highest and IR7 is the lowest one.Any IR can be assigned the highest priority,the
priority sequence will begin at that IR.
Automatic Rotation Mode:
In this mode, a device which one is being serviced will be considered as a lowest priority
In the next time.
Specific Rotation Mode:
This mode is similar to the automatic rotation mode except the user can select any IR for
the lowest priority, thus fixing any other priorities.
End of Interrupts (EOI):
After the completion of an interrupt service, the corresponding ISR bit needs to be
reset.This is called the End of Interrupt.(EOI).It can be issued in 3 formats.They are Non
Specific EOI Command:
When the 8259 receives this command,it resets the highest priority ISR bit.
Specific EOI Command:
It specifies which ISR bit to be reset.
Automatic EOI Command:
When the 8259 receives the third INTA signal, the ISR bit is reset.The major drawback
of this mode is that ISR does not have information on which IR is being serviced.
There are four Initialization Command Word ICW1,ICW2,ICW3&ICW4 and three
Operation Control Word OCW1,OCW2 &OCW3

Initialization Command Word 1 (ICW1)

D7 D6 D5 D4 D3 D2 D1 D0

A7 A6 A5 1 LTIM ADI SNGL IC4

D0- 1=ICW4 is needed, 0= No ICW4 needed D1-

1=Single 8259, 0=Cascading 8259's D2- 1=Interval of
4,0=Interval of 8 D3- 1=level triggered mode, 0=edge
triggered mode D5,D6,D7 – Interrupt Vector Address
Initialization Command Word 2 (ICW2)
D7 D6 D5 D4 D3 D2 D1 D0

A15/T7 A14/T6 A13/T5 A12/T4 A11/T3 A10 A9 A8

A15-A7 – Interrupt Vector Address (8085 mode) T7 –

T3 - Interrupt Vector Address (8086 mode)

Operation Control Word 1 ( OCW1)

D7 D6 D5 D4 D3 D2 D1 D0

M7 M6 M5 M4 M3 M2 M1 M0

M7-M0 – 1 – Interrupt Mask Set

0 – Interrupt Mask Reset

3.2.2 8253/8254 Programmable timer/counter Controllers

The Intel 8253 and 8254 are Programmable Interval Timers (PITs), which perform timing and
counting functions and has the same pinout.

8253 8254

Operating frequency is 0-2.6 Mhz. Operating frequency is 0-10 Mhz.

Uses N-MOS technology. Uses H-MOS technology.

Read Back command is not available. Read Back command is available.

Reads and Writes of the same counter cannot be Reads and Writes of the same counter can be
interleaved. interleaved.
 BLOCK DIAGRAM OF INTEL 8253/8254

The timer has three counters.or timers which are named as "Counter 0", "Counter 1" and
"Counter 2".Each counter has 2 input pins – "CLK" (clock input) and "GATE" – and 1-pin,
"OUT", for data output. The 3 counters are 16-bit down counters independent of each other, and
can be easily read by the CPU. The first counter is used to generate atimekeeping interrupt.The
second counter is used to trigger the refresh of DRAM memory. The last counter is used to
generate tones via the PC speaker.
Data/Bus Buffer:

This block contains the logic to buffer the data bus to / from the microprocessor, and to the
internal registers. It has 8 input pins, usually labelled as D7..D0, where D7 is the MSB.

Read/Write Logic:

The Read/Write Logic block has 5 pins.

/RD: read signal

 /WR: write signal
/CS: chip select signal
A0, A1: address lines
Control Word Register:
To initialize the counters, the microprocessor must write a control word (CW) in this register.
This can be done by setting proper values for the pins of the Read/Write Logic block and then by
sending the control word to the Data/Bus Buffer block.The control word register contains 8 bits,
labeled D7..D0 (D7 is the MSB).

D7 D6 D5 D4 D3 D2 D1 D0

SC1 SC2 RW1 RW0 M2 M1 M0 BCD

D0 – 1 = BCD Counter , 0 – Binary Counter

D3 D2 D1

M2 M1 M0 Mode
0 0 0 Mode0

0 0 1 Mode1

X 1 0 Mode2

X 1 1 Mode3

1 0 0 Mode4

1 0 1 Mode5

D5 D4

RW1 RW0 Operation

0 0 Counter Latching Operation

0 1 Read/Write LSB only

 1 0 Read/Write MSB only

1 1 Read/Write LSB and then MSB

D7 D6

SC1 SC0 Operation

0 0 Select Counter 0

0 1 Select Counter 1

1 0 Select Counter 2

1 1 Illegal

READ BACK COMMAND (ONLY AVAILABLE IN 8254)

D7 D6 D5 D4 D3 D2 D1 D0

1 1 COUNT STATUS CNT2 CNT1 CNT0 0

D5 – 0 = Latch Count of Selected Counters. D4

– 0 = Latch Status of Selected Counters. D3 – 1

= Select Counter 2

D2 – 1 = Select Counter 1

D1 – 1 = Select Counter 0

Operation Modes
Mode 0 : Interrupt on Terminal Count
Mode 0 is used for the generation of accurate time delay under software control. In this mode, the
counter will start counting from the initial COUNT value loaded into it, down
 to 0. Counting rate is equal to the input clock frequency. The OUT pin is set low after the
Control Word is written, and counting starts one clock cycle after the COUNT programmed.
OUT remains low until the counter reaches 0, at which point OUT will be set high until the
counter is reloaded or the Control Word is written. The Gate signal should remain active high for
normal counting. If Gate goes low counting, gets terminated and current count is latched till Gate
pulse goes high again.
Mode 1 : Programmable One Shot
In this mode 8253 can be used as Monostable Multivibrator. GATE input is used as trigger input.
OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin the
one-shot pulse and will remain low until the Counter reaches zero. OUT will then go high and
remain high until the CLK pulse after the next trigger.
Mode 2: Rate Generator
In this mode, the device acts as a divide-by-n counter, which is commonly used to generate a
real-time clock interrupt. Counting process will start the next clock cycle after the COUNT is
sent. OUT will then remain high until the counter reaches 1, and will go low for one clock pulse.
OUT will then go high again, and the whole process repeats itself.

Mode 3 : Square Wave Generator

This mode is similar to mode 2. The duration of the high and low clock pulses of the output will
be different from mode 2.If „N „is the number loaded into the counter , the output will be
High for N/2 counts and N/2 counts for Low if N is Even.
High for (N+1)/2 counts and (N-1)/2 counts for Low if N is Odd.

Mode 4 : Software Triggered Strobe

After Control Word and COUNT is loaded, the output will remain high until the counter reaches
zero.The counter will then generate a low pulse for 1 clock cycle (a strobe) – after that the output
will become high again.
Mode 5 : Hardware-Triggered Strobe
This mode is similar to mode 4. However, the counting process is triggered by the GATE input.
After receiving the Control Word and COUNT, the output will be set high.
 When the GATE input is high , it will start counting. When the counter reaches 0, the output will
go low for one clock cycle – after that it will become high again, to repeat the cycle.

3.2.3 8251 USART and RS232C

3.2.4 8237 DMA Controller

DMA Controller: A DMA controller is a device, usually peripheral to a CPU that is

programmed to perform a sequence of data transfers on behalf of the CPU.A DMA
controller can directly access memory and is used to transfer data from one memory
location to another, or from an I/O device to memory and vice versa.A DMA controller
manages several DMA channels, each of which can be programmed to perform a sequence
of these DMA transfers.A DMA request signal for each channel is routed to the DMA
controller.When the DMA controller sees a DMA request, it responds by performing one
or many data transfers from that I/O device into system memory or vice versa.Channels
must be enabled by the processor for the DMA controller to respond to DMA requests.A
DMA controller typically shares the system memory and I/O bus with the CPU and has
both bus master and slave capability. The diagram of DMA controller architecture and how
the DMA controller interacts with the CPU.In bus master mode, the DMA controller
acquires the system bus (address, data, and control lines)from the CPU to perform the
DMA transfers. Because the CPU releases the system bus for the duration of the transfer,
the process is sometimes referred to as cycle stealing.In bus slave mode, the DMA
controller is accessed by the CPU, which programs the DMAcontroller's internal registers
to set up DMA transfers.The internal registers consist of source and destination address
registers and transfer count registers for each DMA channel, as well as control and status
registers for initiating, monitoring, and sustaining the operation of the DMAcontroller.

DMA Transfer Types and Modes :

DMA controllers vary as to the type of DMA transfers and the number of DMA
channels. The two types of DMA transfers are
i) flyby DMA transfers
ii) fetch-and-deposit DMAtransfers.
iii) The three common transfer modes are single, block, and demand
transfer modes.
A 8237 DMA controller IC :

CLK: CLOCK INPUT:

The Clock Input is used to generate the timing signals which control82C37A operations.

CS: CHIP SELECT:

Chip Select is an active low input used to enable the controller onto the data bus for CPU
communications.

Fig:Architecture of DMA Controller

RESET:
This is an active high input which clears the Command, Status, Request, and Temporary
registers, the First/Last Flip-Flop, and the mode register counter.The Mask registeris set to ignore
requests.

READY:
This signal can be used to extend the memory read and write pulses from the 82C37A to
accommodate slow memories or I/O devices.
HLDA: HOLD ACKNOWLEDGE:
The active high Hold Acknowledge from the CPU indicates that it has relinquished control of the
system busses.

DREQ0-DREQ3: DMA REQUEST:

The DMA Request (DREQ) lines are individual asynchronous channel request inputs
used by peripheral circuits to obtain DMA service.In Fixed Priority, DREQ0 has the highest
priority and DREQ3 has the lowest priority.A request is generated by activating the DREQ line
of a channel. DACK will acknowledge the recognition of a DREQ signal.RESET initializes these
lines to active high.DREQ must be maintained until the corresponding DACK goes active.DREQ
will not be recognized while the clock is stopped.Unused DREQ inputs should be pulled High or
Low(inactive) and the corresponding mask bit set.

DB0-DB7: DATA BUS:

The Data Bus lines are bidirectional three-state signals connected to the system data bus.
The outputs are enabled in the Program condition during the I/O Read to output the contents of a
register to the CPU.The outputs are disabled and the inputs are read during an I/O Write cycle
when the CPU is programming the 82C37A control registers. During DMA cycles, the most
significant 8-bits of the address are output onto the data bus to be strobed into an external latch
by ADSTB. In memory-to-memory operations, data from the memory enters the 82C37A on the
data bus during the read- from-memory transfer, then during the write-to memory transfer, the
data bus outputs write the data into the new memory location.

IOR: READ:
I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input
control signal used by the CPU to read the control registers. In the active cycle, it is an output
control signal used by the 82C37A to access data from the peripheral during a DMAWrite
transfer.
IOW: WRITE:
I/O Write is a bidirectional active low three-state line.
In the Idle cycle, it is an input control signal used by the CPU to load information into the
82C37A. In the active cycle, it is an output control signal used by the 82C37A to load data to
the peripheral during a DMA
Read transfer.

EOP: END OF PROCESS:

End of Process (EOP) is an active low bidirectional signal. The 82C37A allows an
external signal to terminate an active DMA service by pulling the EOP pin low. A pulse is
generated by the 82C37A when terminal count (TC) for any channel is reached, except for
channel 0 in memory-to-memory mode. During memory-to-memory transfers, EOP will be
output when the TC for channel 1 occurs. The EOP pin is driven by an open drain transistor on-
chip, and requires an external pull-up resistor to VCC. When an EOP pulse occurs, whether
internally or externally generated, the 82C37A will terminate the service, and if auto-initialize is
enabled, the base registers will be written to the current registers of that channel. The mask bit
and TC bit in the status word will be set for the currently active channel by EOP unless the
channel is programmed for auto initialize. In that case, the mask bit remains clear.

A0-A3: ADDRESS: The four least significant address lines are bidirectional three-state signals.
In the Idle cycle, they are inputs and are used by the 82C37A to address the control register to
be loaded or read. In the Active cycle, they are outputs and provide the lower 4-bits of the
output
address.

A4-A7: ADDRESS: The four most significant address lines are three-state outputs and provide 4-
bits of address. These lines are enabled only during the DMA service.
HRQ: HOLD REQUEST: The Hold Request (HRQ) output is used to request control of the
system bus. When a DREQ occurs and the corresponding mask bit is clear, or a software DMA
request is made, the 82C37A issues HRQ. The HLDA signal then informs the controller when
access to the system busses is permitted. For stand-alone operation where the 82C37A always
controls the busses, HRQ may be tied to HLDA. This will result in one S0 state before the
transfer.

DACK0-DACK3: DMA ACKNOWLEDGE:

DMA acknowledge is used to notify the individual peripherals when one has been granted a
DMA cycle. RESET initializes them to active low.

AEN: ADDRESS ENABLE:

Address Enable enables the 8-bit latch containing the upper 8address bits onto the system
address bus. AEN can also be used to disable other system busdrivers during DMA
transfers.AEN is active high.
ADSTB: ADDRESS STROBE:
This is an active high signal used to control latching of the upper address byte. During block
operations, ADSTB will only be issued when the upper address byte must be updated. ADSTB
timing is referenced to the falling edge of the 82C37A clock.

MEMR: MEMORY READ:

The Memory Read signal is an active low three-state output used to access data from the
selected memory location during a DMA Read or a memory-to-memory transfer.

MEMW MEMORY WRITE:

The Memory Write signal is an active low three-state output used to write data to the selected
memory location during a DMA Write or a memory-to-memory transfer.

NC: NO CONNECT: Pin 5 is open and should not be tested for continuity.
Functional Description
The 82C37A direct memory access controller is designed to improve the data transfer
rate in systems which must transfer data from an I/O device to memory, or move a block of
memory to an I/O device. It will also perform memory-to-memory block moves, or fill a block
of memory with data from a single location. Operating modes are provided to handle single
byte transfers as well as discontinuous data streams, which allows the 82C37A to control data
movement.Memory-to-memory operations require temporary internal storage of the data byte
between generation of the source and destination addresses, so memory-to-memory
transferstake place at less than half the rate of I/O operations, but still much faster than with
centralprocessor techniques. The block diagram of the 82C37A consists of timing and control
block, priority block, and internal registers are the main components. The timing and control
block derives internal timing from clock input, and generates external control signals. The
Priority Encoder block resolves priority contention between DMA channels requesting service
simultaneously.

DMA Operation:
In a system, the 82C37A address and control outputs and data bus pins are basically connected in
parallel with the system busses. An external latch is required for the upper address byte. While
inactive, the controller‟s outputs are in a high impedance state. When activated by a DMArequest
and bus control is relinquished by the host, the 82C37A drives the busses and generates the
control signals to perform the data transfer.The operation performed by activating one of the four
DMA request inputs has previously been programmed into the controller via the
Command,Mode, Address, and Word Count registers.For example, if a block of data is to be
transferredfrom RAM to an I/O device, the starting address of the data is loaded into the 82C37A
Current and Base Address registers for a particular channel, and the length of the block is loaded
into the channel‟s Word Count register. The corresponding Mode register is programmed for a
memory to-I/O operation (read transfer), and various options are selected by the Command
register and the other Mode register bits.The channel‟s mask bit is cleared to
 enable recognition of a DMArequest (DREQ). The DREQ can either be a hardware
signal or a software command. Once initiated, the block DMA transfer will proceed as
the controller outputs the data address,simultaneous MEMR and IOW pulses, and
selects an I/O device via the DMA acknowledge(DACK) outputs.The data byte flows
directly from the RAM to the I/O device. After each byte is transferred, the address is
automatically incremented (or decremented) and the word count is decremented.The
operation is then repeated for the next byte. The controller stops transferring data
when the Word Count register underflows, or an external EOP is applied.

3.2.5 8255 Programmable Peripheral Interfaces

The Programmable Peripheral Interface (PPI) chip is a peripheral chip. It is made in 40-pin DIP.
The 8255 is used to give the CPU access to programmable parallel I/O. The 8255 has 24
input/output pins in all. These are divided into three 8-bit ports.

BLOCK DIAGRAM OF 8255 PPI:

Fig 3.7 Block Diagram of 8255

Port A and port B can be used as 8-bit input/output ports. Port C can be used as an 8- bit
input/output port or as two 4-bit input/output ports or to produce handshake signals for ports A and
B.
The three ports are further grouped as follows:

1 Group A consists of port A and the upper part of port C.

2 Group B consists of port B and the lower part of port C.

Eight data lines (D0 - D7) are available to read/write data into the ports or control register. The RD
and WR pin, are active low signals for read and write operations.
The address lines A1 and A0 allow to successively access any one of the ports or the control
register. The control signal chip selects CS is used to enable the 8255 chips. when CS = '0', the
8255 is enabled. The RESET input is connected to the RESET pin of 8085. When the system is
reset, all the ports are initialized as input lines.

The control register or the command word register is an 8-bit register used to select the modes of
operation and input/output designation of the ports.

Operational modes of 8255

There are two basic operational modes of 8255:

Bit set/reset Mode (BSR

Mode). Input/Output Mode
(I/O Mode).

Bit set/reset (BSR) mode

The Bit Set/Reset (BSR) mode is applicable to port C only. Each line of port C (PC0 -PC7) can be
set/reset by suitably loading the control word register. BSR mode and I/O mode are independent
and the selection of BSR mode does not affect the operation of other ports in I/O mode.

A1 A0 Port Selected

0 0 Port A

0 1 Port B

1 0 Port C

1 1 Control Word Register

CONTROL WORD FOR BSR MODE:

D7 D6 D5 D4 D3 D2 D1 D0

0 * * * B2 B1 B0 S/R

D7 bit is always 0 for BSR mode.

Bits D6, D5 and D4 are don't care bits.
Bits D3, D2 and D1 are used to select the pin of
Port C. Bit D0 is used to set/reset the selected pin
of Port C.

Selection of port C pin is determined as follows:

B2 B1 B0 Pin of Port C Selected
0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7

INPUT/OUTPUT MODE

This mode is selected when D7 bit of the Control Word Register is 1. There are

three I/O modes

1. Mode 0 - Simple I/O

2. Mode 1 - Strobed I/O
3. Mode 2 - Strobed Bi-directional I/O
CONTROL WORD FORMAT FOR I/O MODE:

D7 D6 D5 D4 D3 D2 D1 D0

Mode 0 - Simple I/O

In this mode, the ports can be used for simple I/O operations without handshaking signals.
Port A- 8
bit port.
Port B – 8 bit
port.
Port C – two 4 bit ports. (Port C upper & Port C lower)
Mode 0 features:
Output ports are latched. Input ports are buffered, not latched. Ports do not have a
handshake or interrupt capability. With 4 ports, 16 different combinations of I/O are
possible.
Mode 1:- Strobed I/O
Port A or Port B for handshake (strobed) input or output
operation. Port A + Port C upper function as handshake
signals.
Port B + Port C lower function as handshake signals.
Mode 1 features:
Two ports i.e. port A and B can be used as 8-bit i/o ports. Each port uses three lines of
port c as handshake signal and the remaining two signals can be used as i/o ports.
Interrupt logic is supported. Input and Output data are latched.

Input Handshaking signals

1. IBF (Input Buffer Full)

2. STB (Strobed Input)
3. INTR (Interrupt request)
4. INTE (Interrupt enable)
Output Handshaking signals

1. OBF (Output Buffer Full)

2. ACK (Acknowledge)
3. INTR (Interrupt request)
4. INTE (Interrupt enable)
Mode 2: Strobed Bidirectional I/O
Port A can be used for bidirectional handshake data transfer. Pins PC4 - PC7 are used
as handshake lines for port A. Acknowledgment and handshaking signals are provided
to maintain proper data flow and synchronization between the data transmitter and
receiver.
3.2.6 UNIVERSITY QUESTIONS RELATED TO THE TOPIC

Ten-mark questions
Q-9. Explain architecture of 8259. Show the connection diagram of 8259 with 8085. List out the
sequence of operation performed by 8259 after an interrupt request occurs.
Q-10.Explain architecture and modes of operation of DMA controller (8237). Also explain its
interfacing with microprocessor.
Q-11.Explain the architecture and different modes of operation of 8255. Also explain its
interfacing with microprocessor.
Q-12.What is the basic difference between 8253 and 8254 timer counters? How 10 KHz square
wave can be generated with 1 MHz frequency connected to counter-0?
Q-13.Write a note on 8254. Explain programming and modes available.
Q-14.Explain the architecture of 8251 USART?

GATE questions

Q-15.The 8255 Programmable Peripheral Interface is used as described below.

I. An A/D converter is interfaced to a microprocessor through an 8255. the conversion
is initiated by a signal from the 8255 on Port C. A signal on Port C causes data to be
strobed into Port A.
Ans - MODE 1
II. Two computers exchange data using a pair of 8255s. Port A works as a bidirectional data
port supported by appropriate handshaking signals.
The appropriate modes of operation of the 8255 for I and II would be

Ans - MODE 2