Numicro Family Nano100 Series Datasheet: Arm Cortex - M 32-Bit Microcontroller

NUMICRO® NANO100 (B) DATASHEET
ARM® Cortex® -M
32-bit Microcontroller
NuMicro® Family
Nano100 Series
Datasheet
NANO100 SERIES DATASHEET

The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system
design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.

www.nuvoton.com
May 31, 2016 Page 1 of 160 Revision 1.08

Table of Contents
LIST OF FIGURES ........................................................................................................................... 6
LIST OF TABLES ............................................................................................................................. 7
1 GENERAL DESCRIPTION ..................................................................................................... 8
2 FEATURES ........................................................................................................................... 10
2.1 Nano100 Features – Base Line ................................................................................. 10
2.2 Nano110 Features – LCD Line .................................................................................. 16
2.3 Nano120 Features – USB Connectivity Line.............................................................. 22
2.4 Nano130 Features – Advanced Line .......................................................................... 28
3 PARTS INFORMATION LIST AND PIN CONFIGURATION ................................................ 34
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3.1 NuMicro Nano100 Series Selection Code ................................................................ 34
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3.2 NuMicro Nano100 Products Selection Guide ........................................................... 35
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3.2.1 NuMicro Nano100 Base Line Selection Guide .............................................................. 35
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3.2.2 NuMicro Nano110 LCD Line Selection Guide ............................................................... 35
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3.2.3 NuMicro Nano120 USB Connectivity Line Selection Guide .......................................... 35
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3.2.4 NuMicro Nano130 Advanced Line Selection Guide ...................................................... 36
3.3 Pin Configuration ........................................................................................................ 37
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3.3.1 NuMicro Nano100 Pin Diagrams .................................................................................. 37
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3.4 Pin Description ........................................................................................................... 47
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3.4.1 NuMicro Nano100 Pin Description ................................................................................ 47
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4 BLOCK DIAGRAM ................................................................................................................ 97
4.1 Nano100 Block Diagram ............................................................................................ 97
4.4 Nano130 Block Diagram .......................................................................................... 100
5 FUNCTIONAL DESCRIPTION............................................................................................ 101
5.1 Memory Organization ............................................................................................... 101
5.1.1 Overview ...................................................................................................................... 101
5.1.2 Memory Map ................................................................................................................ 101
5.2 Nested Vectored Interrupt Controller (NVIC) ........................................................... 103
5.2.1 Overview ...................................................................................................................... 103
5.2.2 Features ....................................................................................................................... 103
5.3 System Manager ...................................................................................................... 104
5.3.1 Overview ...................................................................................................................... 104
5.3.2 Features ....................................................................................................................... 104
5.4 Clock Controller ........................................................................................................ 105
5.4.1 Overview ...................................................................................................................... 105
5.4.2 Features ....................................................................................................................... 105

5.5 Analog to Digital Converter (ADC) ........................................................................... 106
5.5.1 Overview ...................................................................................................................... 106
5.5.2 Features ....................................................................................................................... 106
5.6 Digital to Analog Converter (DAC) ........................................................................... 107
5.6.1 Overview ...................................................................................................................... 107
5.6.2 Features ....................................................................................................................... 107
5.7 DMA Controller ......................................................................................................... 108
5.7.1 Overview ...................................................................................................................... 108
5.7.2 Features ....................................................................................................................... 108
5.8 External Bus Interface .............................................................................................. 110
5.8.1 Overview ...................................................................................................................... 110
5.8.2 Features ....................................................................................................................... 110
5.9 FLASH Memory Controller (FMC) ............................................................................ 111
5.9.1 Overview ...................................................................................................................... 111
5.9.2 Features ....................................................................................................................... 111
5.10 General Purpose I/O Controller ................................................................................ 112
5.10.1 Overview .................................................................................................................... 112
5.10.2 Features ..................................................................................................................... 112
2
5.11 I C ............................................................................................................................. 113
5.11.1 Overview .................................................................................................................... 113
5.11.2 Features ..................................................................................................................... 114
2
5.12 I S ............................................................................................................................. 115
5.12.1 Overview .................................................................................................................... 115
5.12.2 Features ..................................................................................................................... 115
5.13 LCD Display Driver ................................................................................................... 116

5.13.1 Overview .................................................................................................................... 116
5.13.2 Features ..................................................................................................................... 116
5.14 Pulse Width Modulation (PWM) ............................................................................... 117
5.14.1 Overview .................................................................................................................... 117
5.14.2 Features ..................................................................................................................... 118
5.15 RTC .......................................................................................................................... 119
5.15.1 Overview .................................................................................................................... 119
5.15.2 Features ..................................................................................................................... 119
5.16 Smart Card Host Interface (SC) ............................................................................... 119
5.16.1 Overview .................................................................................................................... 119
5.16.2 Features ..................................................................................................................... 119
5.17 SPI ............................................................................................................................ 121
5.17.1 Overview .................................................................................................................... 121
5.17.2 Features ..................................................................................................................... 121
5.18 Timer Controller ........................................................................................................ 122
5.18.1 Overview .................................................................................................................... 122
5.18.2 Features ..................................................................................................................... 122
5.19 UART Controller ....................................................................................................... 123

5.19.1 Overview .................................................................................................................... 123

5.19.2 The LIN mode is selected by setting the LIN_EN bit in UART_FUN_SEL register. In LIN
mode, one start bit and 8-bit data format with 1-bit stop bit are required in accordance with the
LIN standard. Features.............................................................................................................. 124
5.20 USB .......................................................................................................................... 126
5.20.1 Overview .................................................................................................................... 126
5.20.2 Features ..................................................................................................................... 126
5.21 Watchdog Timer Controller ...................................................................................... 127
5.21.1 Overview .................................................................................................................... 127
5.21.2 Features ..................................................................................................................... 127
5.22 Window Watchdog Timer Controller ........................................................................ 128
5.22.1 Overview .................................................................................................................... 128
5.22.2 Features ..................................................................................................................... 128
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6 ARM CORTEX™-M0 CORE ............................................................................................. 129
6.1 Overview................................................................................................................... 129
6.2 Features ................................................................................................................... 129
7 APPLICATION CIRCUIT ..................................................................................................... 131
7.1 LCD Charge Pump ................................................................................................... 131
7.1.1 C-type 1/3 Bias ............................................................................................................. 131
7.1.2 C-type 1/2 Bias ............................................................................................................. 131
7.1.3 Internal R-type .............................................................................................................. 131
7.1.4 External R-type ............................................................................................................. 132
7.2 ADC Application Circuit ............................................................................................ 133
7.2.1 Voltage Reference Source ........................................................................................... 133
7.3 DAC Application Circuit ............................................................................................ 135
7.3.1 Voltage Reference Source ........................................................................................... 135
7.4 Whole Chip Application Circuit ................................................................................. 137

8 POWER COMSUMPTION .................................................................................................. 138
9 ELECTRICAL CHARACTERISTIC ..................................................................................... 139
9.1 Absolute Maximum Ratings...................................................................................... 139
9.2 Nano100/Nano110/Nano120/Nano130 DC Electrical Characteristics ..................... 139
9.3 AC Electrical Characteristics .................................................................................... 145
9.3.1 External Input Clock ..................................................................................................... 145
9.3.2 External 4~24 MHz XTAL Oscillator ............................................................................. 145
9.3.3 External 32.768 kHz Crystal ......................................................................................... 146
9.3.4 Internal 12 MHz Oscillator ............................................................................................ 146
9.3.5 Internal 10 kHz Oscillator ............................................................................................. 146
9.4 Analog Characteristics ............................................................................................. 146
9.4.1 12-bit ADC .................................................................................................................... 146
9.4.2 Brown-out Detector....................................................................................................... 147
9.4.3 Power-on Reset ............................................................................................................ 148
9.4.4 Temperature Sensor..................................................................................................... 148
9.4.5 12-bit DAC .................................................................................................................... 148
9.4.6 LCD .............................................................................................................................. 149
9.4.7 Internal Voltage Reference ........................................................................................... 149

9.4.8 USB PHY Specifications ............................................................................................... 149

9.5 Flash DC Electrical Characteristics .......................................................................... 151
10 PACKAGE DIMENSIONS ................................................................................................... 152
10.1 LQFP128 (14x14x1.4 mm footprint 2.0 mm) ............................................................ 152
10.2 LQFP64 (10x10x1.4 mm footprint 2.0 mm) .............................................................. 153
10.3 LQFP64 (7x7x1.4 mm footprint 2.0 mm) .................................................................. 154
10.4 LQFP48 (7x7x1.4 mm footprint 2.0 mm) .................................................................. 156
10.5 QFN48 (7x7x0.85 mm) ............................................................................................. 157
11 REVISION HISTORY .......................................................................................................... 158

LIST OF FIGURES
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Figure 3‑1 NuMicro Nano100 Series Selection Code .................................................................. 34
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Figure 3‑2 NuMicro Nano100 LQFP 128-pin Diagram ................................................................ 37
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Figure 3‑3 NuMicro Nano100 LQFP 64-pin Diagram .................................................................. 38
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Figure 3‑4 NuMicro Nano100 LQFP 48-pin Diagram ................................................................... 39
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Figure 3‑5 NuMicro Nano110 LQFP 128-pin Diagram................................................................. 40
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Figure 3‑10 NuMicro Nano130 LQFP 128-pin Diagram............................................................... 45
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Figure 4‑1 NuMicro Nano100 Block Diagram .............................................................................. 97
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Figure 4‑4 NuMicro Nano130 Block Diagram ............................................................................ 100
Figure 6‑1 M0 Functional Block ................................................................................................... 129
Figure 9‑1 Typical Crystal Application Circuit .............................................................................. 145

LIST OF TABLES
Table 1‑1 Connectivity Support Table ............................................................................................. 9
Table 3‑1 Nano100 Base Line Selection Table ............................................................................. 35
Table 3‑2 Nano110 LCD Line Selection Table .............................................................................. 35
Table 3‑3 Nano120 USB Connectivity Line Selection Table ......................................................... 35
Table 3‑4 Nano130 Advanced Line Selection Table ..................................................................... 36
Table 5‑12 UART Baud Rate Equation ....................................................................................... 123
Table 5‑13 UART Baud Rate Setting .......................................................................................... 124

1 GENERAL DESCRIPTION
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The Nano100 series ultra-low power 32-bit microcontroller is embedded with ARM Cortex™-M0
core operated at a wide voltage range from 1.8V to 3.6V and runs up to 42 MHz frequency with
32K/64K/128K bytes embedded Flash and 8K/16K-byte embedded SRAM. Integrating LCD 4x40
or 6x38 (COM/Segment), USB 2.0 full-speed function, RTC, 12-bit SAR ADC, 12-bit DAC and
2 2
provides high performance connectivity peripheral interfaces such as UART, SPI, I C, I S, GPIOs,
EBI (External Bus Interface) for external memory-mapped device access and ISO-7816-3 for
Smart card, the Nano100 series supports Brown-out Detector, Power-down mode with RAM
retention and fast wake-up via many peripheral interfaces.
The Nano100 series provides low power voltage, low power consumption, low standby current,
high integration peripherals, high-efficiency operation, fast wake-up function and the lowest cost
32-bit microcontrollers. The Nano100 series is suitable for a wide range of battery device
applications such as:
 Portable Data Collector
 Portable Medical Monitor
 Portable RFID Reader
 Portable Barcode Scanner
 Security Alarm System
 System Supervisors
 Power Metering
 USB Accessories
 Smart Card Reader
 Wireless Game Control Device
 IPTV Remote Smart Keyboard
 Wireless Sensors Node Device (WSN)
 Wireless RF4CE Remote Control

 Wireless Audio
 Wireless Automatic Meter Reader (AMR)
 Electronic Toll Collection (ETC)
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The Nano100 Base line, an ultra-low power 32-bit microcontroller with the embedded ARM
Cortex™-M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 42 MHz
frequency with 32K/64K/128K bytes embedded flash and 8K/16K bytes embedded SRAM. It
integrates RTC, 12- channels 12-bit SAR ADC, 2-channels 12-bit DAC and provides high
2 2
performance connectivity peripheral interfaces such as 2xUART, 3xSPI, 2xI C, I S, GPIOs, EBI
(External Bus Interface) for external memory-mapped device access and 3xISO-7816-3 for Smart
card. The Nano100 Base line supports Brown-out Detector, Power-down mode with RAM
retention and fast wake-up via many peripheral interfaces.
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The Nano110 LCD line, an ultra-low power 32-bit microcontroller with the embedded ARM
integrates LCD 4x40 or 6x38 (COM/Segment). RTC, 12-channels 12-bit SAR ADC, 2-channels
12-bit DAC and provides high performance connectivity peripheral interfaces such as 2xUART,
2 2
2xSPI, 2xI C, I S, GPIOs, EBI (External Bus Interface) for external memory-mapped device
access and 3xISO-7816-3 for Smart card. The Nano110 LCD line supports Brown-out Detector,
Power-down mode with RAM retention and fast wake-up via many peripheral interfaces.

The Nano120 USB Connectivity line, an ultra-low power 32-bit microcontroller with the embedded
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ARM Cortex™-M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 42
MHz frequency with 32K/64K/128K bytes embedded flash and 8K/16K bytes embedded SRAM. It
integrates USB 2.0 full-speed device function, RTC, 12-channels12-bit SAR ADC, 2-channels 12-
bit DAC and provides high performance connectivity peripheral interfaces such as 2xUART,
3xSPI, 2xI2C, I2S, GPIOs, EBI (External Bus Interface) for external memory-mapped device
access and 3xISO-7816-3 for Smart card. The Nano120 USB Connectivity line supports Brown-
out Detector, Power-down mode with RAM retention and fast wake-up via many peripheral
interfaces.
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The Nano130 Advanced line, an ultra-low power 32-bit microcontroller with the embedded ARM
integrated LCD 4x40 or 6x38 (COM/Segment), USB 2.0 full-speed device function, RTC, 8-
channels 12-bit SAR ADC, 2-channels 12-bit DAC and provides high performance connectivity
2 2
peripheral interfaces such as 2xUART, 2xSPI, 2xI C, I S, GPIOs, EBI (External Bus Interface) for
external memory-mapped device access and 3xISO-7816-3 for Smart card. The Nano130
Advanced line supports Brown-out Detector, Power-down mode with RAM retention and fast
wake-up via many peripheral interfaces.
2 2
Product Line UART SPI I C I S USB LCD ADC DAC RTC EBI SC Timer
Nano100 ● ● ● ● ● ● ● ● ● ●
Nano110 ● ● ● ● ● ● ● ● ● ● ●
Nano120 ● ● ● ● ● ● ● ● ● ● ●
Nano130 ● ● ● ● ● ● ● ● ● ● ● ●
Table 1‑1 Connectivity Support Table

2 FEATURES
The equipped features are dependent on the product line and their sub products.
2.1 Nano100 Features – Base Line

 Core
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 ARM Cortex™-M0 core running up to 42 MHz
 One 24-bit system timer
 Supports Low Power Sleep mode
 Single-cycle 32-bit hardware multiplier
 NVIC for the 32 interrupt inputs, each with 4-levels of priority
 Serial Wire Debug supports with 2 watchpoints/4 breakpoints
 Brown-out
 Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation
 Flash EPROM Memory
 Runs up to 42 MHz with zero wait state for discontinuous address read access
 64K/32K/123K bytes application program memory (APROM)
 4 KB in system programming (ISP) loader program memory (LDROM)
 Programmable data flash start address and memory size with 512 bytes page
erase unit
 In System Program (ISP)/In Application Program (IAP) to update on-chip Flash
EPROM
 SRAM Memory
 16K/8K bytes embedded SRAM
 Supports DMA mode

 DMA: Supports 8 channels: one VDMA channel, 6 PDMA channels and one CRC
channel
 VDMA
 Memory-to-memory transfer
 Supports block transfer with stride
 Supports word/half-word/byte boundary address
 Supports address direction: increment and decrement
 PDMA
 Peripheral-to-memory, memory-to-peripheral, and memory-to-memory
transfer
 Supports word boundary address
 Supports word alignment transfer length in memory-to-memory mode
 Supports word/half-word/byte alignment transfer length in peripheral-to-
memory and memory-to-peripheral mode
 Supports word/half-word/byte transfer data width from/to peripheral

 Supports address direction: increment, fixed, and wrap around

 CRC
 Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and
CRC-32
16 12 5
 CRC-CCITT: X +X +X +1
8 2
 CRC-8: X + X + X + 1
16 15 2
 CRC-16: X +X +X +1
32 26 23 22 16 12 11 10 8 7 5
 CRC-32: X + X +X +X +X +X +X +X +X +X +X +
4 2
X +X +X+1
 Clock Control
 Flexible selection for different applications
 Built-in 12 MHz OSC, can be trimmed to 0.25% deviation within all temperature
range when turning on auto-trim function (system must have external 32.768
kHz crystal input) otherwise 12 MHz OSC has 2 % deviation within all
temperarure range.
 Low power 10 kHz OSC for watchdog and low power system operation
 Supports one PLL, up to 120 MHz, for high performance system operation and
USB application (48 MHz).
 External 4~24 MHz crystal input for precise timing operation
 External 32.768 kHz crystal input for RTC function and low power system
operation
 GPIO
 Three I/O modes:
 Push-Pull output

 Open-Drain output
 Input only with high impendence
 All inputs with Schmitt trigger
 I/O pin configured as interrupt source with edge/level setting
 Supports High Driver and High Sink I/O mode
 Supports input 5V tolerance, except PA.0 ~ PA.7, PD.0 ~ PD.1 and PC.6 ~ PC.7
 Timer
 Supports 4 sets of 32-bit timers, each with 24-bit up-counting timer and one 8-bit
pre-scale counter
 Independent Clock Source for each timer
 Provides one-shot,periodic, output toggle and continuous operation modes
 Internal trigger event to ADC, DAC and PDMA
 Supports PDMA mode
 Wake system up from Power-down mode
 Watchdog Timer
 Clock Source from LIRC (Internal 10 kHz Low Speed Oscillator Clock)

 Selectable time-out period from 1.6 ms ~ 26 sec (depending on clock source)

 Interrupt or reset selectable when watchdog time-out
 Window Watchdog Timer(WWDT)
 6-bit down counter and 6-bit compare value to make the window period flexible
 Selectable WWDT clock pre-scale counter to make WWDT time-out interval
variable.
 RTC
 Supports software compensation by setting frequency compensate register
(FCR)
 Supports RTC counter (second, minute, hour) and calendar counter (day,
month, year)
 Supports Alarm registers (second, minute, hour, day, month, year)
 Selectable 12-hour or 24-hour mode
 Automatic leap year recognition
 Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
 Supports 80 bytes spare registers and a snoop pin to clear the content of these
spare registers
 PWM/Capture
 Supports 2 PWM modules, each has two 16-bit PWM generators
 Provides eight PWM outputs or four complementary paired PWM outputs
 Each PWM generator equipped with one clock divider, one 8-bit prescaler, two
clock selectors, and one Dead-zone generator for complementary paired PWM
 (Shared with PWM timers) with eight 16-bit digital capture timers provides eight
rising/ falling/both capture inputs.
 Supports One-shot and Continuous mode
 Supports Capture interrupt
 UART
 Up to two 16-byte FIFO UART controllers
 UART ports with flow control (TX, RX, CTSn and RTSn)
 Supports IrDA (SIR) function
 Supports LIN function
 Supports RS-485 9 bit mode and direction control.
 Programmable baud rate generator
 SPI
 Up to three sets of SPI controller
 Master up to 32 MHz, and Slave up to 16 MHz

 Supports SPI/MICROWIRE Master/Slave mode
 Full duplex synchronous serial data transfer
 Variable length of transfer data from 4 to 32 bits
 MSB or LSB first data transfer
 RX and TX on both rising or falling edge of serial clock independently
 Two slave/device select lines when SPI controller is used as the master, and 1
slave/device select line when SPI controller is used as the slave
 Supports byte suspend mode in 32-bit transmission
 Supports two channel PDMA requests, one for transmit and another for receive
 Supports three wire mode, no slave select signal, bi-direction interface
2
 IC
2
 Up to two sets of I C device
 Master/Slave up to 1 Mbit/s
 Bi-directional data transfer between masters and slaves
 Multi-master bus (no central master)
 Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
 Serial clock synchronization allows devices with different bit rates to
communicate via one serial bus
 Serial clock synchronization used as a handshake mechanism to suspend and
resume serial transfer

2 2
 Built-in 14-bit time-out counter requesting the I C interrupt if the I C bus hangs
up and timer-out counter overflows
 Programmable clocks allowing for versatile rate control
 Supports 7-bit addressing mode
 Supports multiple address recognition (four slave addresses with mask option)
2
 IS
 Interface with external audio CODEC
 Operated as either Master or Slave mode
 Capable of handling 8, 16, 24 and 32 bit word sizes
 Supports Mono and stereo audio data
2
 Supports I S and MSB justified data format
 Provides two 8 word FIFO data buffers: one for transmitting and the other for
receiving
 Generates interrupt requests when buffer levels cross a programmable
boundary
 Supports two PDMA requests: one for transmitting and the other for receiving
 ADC
 12-bit SAR ADC up to 2Msps conversion rate

 Up to 12-ch single-ended input from external pin (PA.0 ~ PA.7 and PD.0 ~ PD.3)
 Six internal channels from DAC0, DAC1, internal reference voltage (Int_VREF),
Temperature sensor, AVDD, and AVSS.
 Supports three reference voltage sources from VREF pin, internal reference
voltage (Int_VREF), and AVDD.
 Supports Single Scan, Single Cycle Scan, and Continuous Scan mode
 Each channel with individual result register
 Only scan on enabled channels
 Threshold voltage detection (comparator function)
 Conversion started by software programming or external input
 Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3) to
enable ADC
 DAC
 12-bit monotonic output with 400K conversion rate
 Synchronized update capability for two DACs (group function)
 Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3),
software or PDMA to trigger DAC to conversion
 SmartCard (SC)
 Compliant to ISO-7816-3 T=0, T=1
 Supports up to three ISO-7816-3 ports

 Separates receive/transmit 4 bytes entry FIFO for data payloads
 Programmable transmission clock frequency
 Programmable receiver buffer trigger level
 Programmable guard time selection (11 ETU ~ 266 ETU)
 A 24-bit and two 8-bit time-out counters for Answer to Reset (ATR) and waiting
times processing
 Supports auto inverse convention function
 Supports stop clock level and clock stop (clock keep) function
 Supports transmitter and receiver error retry and error limit function
 Supports hardware activation sequence process
 Supports hardware warm reset sequence process
 Supports hardware deactivation sequence process
 Supports hardware auto deactivation sequence when detect the card is removal
 Supports UART mode (Half Duplex)
 EBI (External bus interface) support

 Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode

 Supports 8bit/16bit data width
 Supports byte write in 16-bit Data Width mode
 One built-in temperature sensor with 1℃ resolution
 96-bit unique ID
 128-bit unique customer ID
 Operating Temperature: -40℃~85℃
 Packages:
 All Green package (RoHS)
 LQFP 128-pin(14x14) / 64-pin(7x7) / 48-pin(7x7) / QFN 48-pin(7x7)

2.2 Nano110 Features – LCD Line

 Core
®
 Brown-out
 Runs up to 42 MHz with zero wait state for discontinuous address read access.
 4 KB In System Programming (ISP) loader program memory (LDROM)
erase unit
 In System Program (ISP)/In Application Program (IAP) to update on chip Flash
EPROM
 SRAM Memory
 DMA : Supports 8 channels: one VDMA channel,6 PDMA channels, and one CRC
channel
 VDMA
 PDMA
transfer
 CRC

CRC-32
16 12 5
8 2
 CRC-8: X + X + X + 1
16 15 2
 CRC-16: X +X +X +1
32 26 23 22 16 12 11 10 8 7 5
 CRC-32: X + X +X +X +X +X +X +X +X +X +X +
4 2
X +X +X+1
 Clock Control
 Built-in 12 MHz OSC, can be trimmed to 0.25% deviation within all temperature
temperarure range.
operation
 GPIO

 Supports input 5V tolerance, except PA.0 ~ PA.7, PD.0 ~ PD.1 and PC.6 ~
PC.7)
 Timer
 Supports 4 sets of 32-bit timers, each with 24-bit up-timer and one 8-bit pre-
scale counter
 Internal trigger event to ADC, DAC and PDMA module
 Watchdog Timer
 Clock Source from LIRC (Internal 10 kHz Low Speed Oscillator Clock)
 Interrupt or reset selectable when watchdog time-out


variable.
 RTC
(FCR)
month, year)
1/16, 1/8, 1/4, 1/2 and 1 second
spare registers
 PWM/Capture
 Supports 2 PWM modules, each has two 16-bit PWM generators
clock selectors, and one Dead-zone generator for complementary paired PWM

 UART
 Supports RS-485 9 bit mode and direction control (Low Density Only)
 SPI

 Two slave/device select lines when SPI controller is as the master, and 1
slave/device select line when SPI controller is as the slave
 Supports three wire mode, no slave select signal, bi-direction interface
2
 IC
2
 Master/Slave up to 1Mbit/s
 Bidirectional data transfer between masters and slaves
 Serial clock synchronization allowing devices with different bit rates to
2 2
 Built-in 14-bit time-out counter requestING the I C interrupt if the I C bus hangs
 Programmable clocks allow versatile rate control

 Supports multiple address recognition (four slave address with mask option)
2
 IS
2
receiving
boundary
 ADC
Temperature sensor, AVDD, and AVSS

 Single scan/single cycle scan/continuous scan
 Conversion start by software programming or external input
 Supports up to four timer time-out events (TMR0, TMR1, TMR2, and TMR3) to
enable ADC
 DAC
 SmartCard (SC)
 Separates receive / transmit 4 bytes entry FIFO for data payloads

 A 24-bit and two 8-bit time-out counter for Answer to Reset (ATR) and waiting
times processing
 LCD
 LCD driver for up to 4 COM x 40 SEG or 6 COM x 38 SEG
 Supports Static,1/2 bias and 1/3 bias voltage
 Four display modes; Static, 1/2 duty, 1/3 duty,1/4 duty, 1/5 duty and 1/6 duty.

 Selectable LCD frequency by frequency divider

 Configurable frame frequency
 Internal Charge pump, adjustable contrast adjustment
 Configurable Charge pump frequency
 Blinking capability
 Supports R-type/C-type method
 LCD frame interrupt
 Packages:
 LQFP 128-pin(14x14) / 64-pin(10x10) / 64-pin(7x7)

2.3 Nano120 Features – USB Connectivity Line

 Core
®
 Brown-out
 4KB in system programming (ISP) loader program memory (LDROM)
erase unit
EPROM
 SRAM Memory
 DMA: Support 8 channels: one VDMA channel, 6 PDMA channels, and one CRC
channel
 VDMA
 PDMA
transfer
 Supports address: increment, fixed, and wrap around
 CRC

CRC-32
16 12 5
8 2
 CRC-8: X + X + X + 1
16 15 2
 CRC-16: X +X +X +1
32 26 23 22 16 12 11 10 8 7 5
 CRC-32: X + X +X +X +X +X +X +X +X +X +X +
4 2
X +X +X+1
 Clock Control
 Built-in 12MHz OSC, can be trimmed to 0.25% deviation within all temperature
temperarure range
 Low power 10 kHz OSC for watchdog and low power system operatin
operation
 GPIO

 I/O pin can be configured as interrupt source with edge/level setting
 High driver and high sink IO mode support
 Supports input 5V tolerance (except ADC and DAC shared pins)
 Timer
 Supports 4 sets of 32-bit timers, each with 24-bit up-timer and one 8-bit pre-
scale counter
 Internal trigger event to ADC, DAC and PDMA module
 Watchdog Timer
 Clock Source from LIRC. (Internal 10 kHz Low Speed Oscillator Clock)
 Interrupt or reset selectable on watchdog time-out

variable.
 RTC
(FCR)
month, year)
1/16, 1/8, 1/4, 1/2 and 1 second
 Wake system up from Power-down or Idle mode
 Support 80 bytes spare registers and a snoop pin to clear the content of these
spare registers
 PWM/Capture
 Supports 2 PWM module, each has two 16-bit PWM generators
 Provide eight PWM outputs or four complementary paired PWM outputs
clock selectors, and one Dead-Zone generator for complementary paired PWM
 Supports one shot and continuous mode

 UART
 Supports RS-485 9 bit mode and direction control. (Low Density Only)
 SPI

 Two slave/device select lines when SPI controller is as the master, and 1
slave/device select line when SPI controller is as the slave
 Supports three wire, no slave select signal, bi-direction interface
2
 IC
2
2 2
 Built-in 14-bit time-out counter requesting the I C interrupt if the I C bus hangs
 Programmable clocks allow versatile rate control

2
 IS
2
receiving
boundary
 ADC
 Up to 12-ch single-ended input from external pin (PA.0 ~ PA.7 and PD.0 ~
PD.3).

voltage (Int_VREF), and AVDD
 Supports single scan, single cycle scan, and continuous scan modes
enable ADC
 DAC
 Supports up to four timer time-out event (TMR0, TMR1, TMR2 and TMR3),
 SmartCard (SC)
 Separates receive / transmit 4 bytes entry FIFO for data payloads

times processing
 USB 2.0 Full-Speed Device
 One set of USB 2.0 FS Device 12 Mbps
 On-chip USB Transceiver

 Provides 1 interrupt source with 4 interrupt events

 Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
 Auto suspend function when no bus signaling for 3 ms
 Provides 8 programmable endpoints
 Includes 512 Bytes internal SRAM as USB buffer
 Provides remote wake-up capability
 EBI (External bus interface) support
 Supports byte write in 16-bit Data Width mode
 Packages:
 LQFP 128-pin(14x14) / 64-pin(7x7) / 48-pin(7x7)

2.4 Nano130 Features – Advanced Line

 Core
®
 Brown-out
 4KB in system programming (ISP) loader program memory (LDROM)
erase unit
EPROM
 SRAM Memory
 DMA : Supports 8 channels: one VDMA channel,6 PDMA channels, and one CRC
egiste
 VDMA
 PDMA
transfer
 CRC

CRC-32
16 12 5
8 2
 CRC-8: X + X + X + 1
16 15 2
 CRC-16: X +X +X +1
32 26 23 22 16 12 11 10 8 7 5
 CRC-32: X + X +X +X +X +X +X +X +X +X +X +
4 2
X +X +X+1
 Clock Control
 Built-in 12MHz OSC, can be trimmed to 0.25% deviation within all temperature
temperarure range.
operation
 GPIO

 Supports input 5V tolerance (except ADC and DAC shared pins)
 Timer
 Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale
counter
 Supports internal trigger event to ADC, DAC and PDMA module
 Watchdog Timer
 Clock Source is from LIRC. (Internal 10 kHz Low Speed Oscillator Clock)
 Selectable time-out period from 1.6ms ~ 26sec (depends on clock source)
 Interrupt or reset selectable on watchdog time-out
 WDT can wake system up from Power-down mode
variable.
 RTC
(FCR)
month, year)
1/16, 1/8, 1/4, 1/2 and 1 second
spare registers
 PWM/Capture
 Supports 2 PWM module, each with two 16-bit PWM generators
clock selectors, and one Dead-Zone generator for complementary paired PWM
 UART
 Supports RS-485 9 bit mode and direction control (Low Density Only)
 SPI
 Up to 3 sets of SPI controller

 Two slave/device select lines when used as the master, and 1 slave/device
select line when used as the slave
 Supports two channel PDMA request, one for transmit and another for receive
 Supports three wire, no slave select signal, bi-direction interface
2
 IC
2
 Serial clock synchronization can be used as a handshake mechanism to
suspend and resume serial transfer
2 2
 Built-in 14-bit time-out counter will request the I C interrupt if the I C bus hangs
 Programmable clocks allowing for versatile rate control

2
 IS
 Operate as either Master or Slave mode
2
receiving
boundary
 ADC

voltage (Int_VREF), and AVDD

 Single scan/single cycle scan/continuous scan
 Scan on enabled channels
enable ADC
 DAC
 SmartCard (SC)
 Separates receive/transmit 4 bytes entry FIFO for data payloads
times processing
 Supports hardware auto deactivation sequence when detecting the card is
removed
 Support UART mode (Half Duplex)
 LCD
 LCD driver for up to 4 COM x 40 SEG or 6 COM x 38 SEG
 Supports Static,1/2 bias and 1/3 bias voltage
 Four display modes: Static, 1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty and 1/6 duty.
 Selectable LCD frequency by frequency divider

 Configurable frame frequency

 Internal Charge pump, adjustable contrast adjustment
 Configurable Charge pump frequency
 Blinking capability
 Supports R-type/C-type method
 LCD frame interrupt
 USB 2.0 Full-speed Device
 One set of USB 2.0 FS Device 12 Mbps
 On-chip USB Transceiver
 Provides 1 interrupt source with 4 interrupt events
 Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
 Auto suspend function when no bus signaling for 3 ms
 Provides 8 programmable endpoints
 Includes 512 Bytes internal SRAM as USB buffer
 Provides remote wake-up capability
 EBI (External bus interface)
 Supports byte write in 16-bit data width mode

 Packages:
 LQFP 128-pin(14x14) / 64-pin (7x7)

3 PARTS INFORMATION LIST AND PIN CONFIGURATION
3.1 NuMicro® Nano100 Series Selection Code

NANO 1 X X - X X X B N
Ultra-Low Power MCU Temperature

N: -40℃ ~ +85℃
E: -40℃ ~ +105℃
CPU core C: -40℃ ~ +125℃
1: Cortex-M0
5/7: ARM7 Version
9: ARM9 A : Version
B : Version
Product Line Function
SRAM Size
0: Base Line 0 : 2KB
1: LCD Line 1 : 4KB
2: USB Connectivity Line 2 : 8KB
3: LCD + USB Connectivity Line 3 : 16KB
Flash ROM
Reserved A: 8KB
0 ~ 9 Sub Product Line B: 16KB
C: 32KB
Package Type D: 64KB
N : QFN48 (7x7 mm) E: 128KB
L : LQFP 48 (7x7 mm)
R : LQFP 64 (10x10 mm)
S : LQFP 64 (7x7 mm)
K : LQFP 128 (14x14 mm)
®
Figure 3‑1 NuMicro Nano100 Series Selection Code

3.2 NuMicro® Nano100 Products Selection Guide
3.2.1 NuMicro® Nano100 Base Line Selection Guide

ISP Connectivity ICP IRC Operating
Flash SRAM Data Flash Timer 2 PWM ADC DAC
Part No. ROM I/O I S RTC EBI PDMA LCD ISO-7816-3* ISP 10KHz Package Temp.
(Kbytes) (Kbytes) (Kbytes) (32-bit) UART* SPI I2C USB (16-bit) (12-bit) (12-bit)
(Kbytes) IAP 12MHz Range (°C )
NANO100NC2BN 32 8 Configurable 4 38 4 2+2 3 2 - 1 6 7 √ - 8 - 2 2 √ √ QFN48 -40 to +85

NANO100ND2BN 64 8 Configurable 4 38 4 2+2 3 2 - 1 6 7 √ - 8 - 2 2 √ √ QFN48 -40 to +85
NANO100ND3BN 64 16 Configurable 4 38 4 2+2 3 2 - 1 6 7 √ - 8 - 2 2 √ √ QFN48 -40 to +85
NANO100NE3BN 128 16 Configurable 4 38 4 2+2 3 2 - 1 6 7 √ - 8 - 2 2 √ √ QFN48 -40 to +85
NANO100LC2BN 32 8 Configurable 4 38 4 2+2 3 2 - 1 6 7 √ - 8 - 2 2 √ √ LQFP48 -40 to +85
NANO100LD2BN 64 8 Configurable 4 38 4 2+2 3 2 - 1 6 7 √ - 8 - 2 2 √ √ LQFP48 -40 to +85
NANO100LD3BN 64 16 Configurable 4 38 4 2+2 3 2 - 1 6 7 √ - 8 - 2 2 √ √ LQFP48 -40 to +85
NANO100LE3BN 128 16 Configurable 4 38 4 2+2 3 2 - 1 6 7 √ - 8 - 2 2 √ √ LQFP48 -40 to +85
NANO100SC2BN 32 8 Configurable 4 52 4 2+3 3 2 - 1 8 7 √ - 8 - 2 3 √ √ LQFP64* -40 to +85
NANO100SD2BN 64 8 Configurable 4 52 4 2+3 3 2 - 1 8 7 √ - 8 - 2 3 √ √ LQFP64* -40 to +85
NANO100SD3BN 64 16 Configurable 4 52 4 2+3 3 2 - 1 8 7 √ - 8 - 2 3 √ √ LQFP64* -40 to +85
NANO100SE3BN 128 16 Configurable 4 52 4 2+3 3 2 - 1 8 7 √ - 8 - 2 3 √ √ LQFP64* -40 to +85
NANO100KD3BN 64 16 Configurable 4 86 4 2+3 3 2 - 1 8 12 √ √ 8 - 2 3 √ √ LQFP128 -40 to +85
NANO100KE3BN 128 16 Configurable 4 86 4 2+3 3 2 - 1 8 12 √ √ 8 - 2 3 √ √ LQFP128 -40 to +85
*Marked in the table (2+3) means 2 UART+ 3 ISO-7816 UART. LQFP64*:7X7mm
*ISO-7816 UART supports half duplex mode.
Table 3‑1 Nano100 Base Line Selection Table
3.2.2 NuMicro® Nano110 LCD Line Selection Guide

NANO110SC2BN 32 8 Configurable 4 51 4 2+3 3 2 - 1 7 7 √ - 8 4x31, 6x29 2 3 √ √ LQFP64* -40 to +85
NANO110SD2BN 64 8 Configurable 4 51 4 2+3 3 2 - 1 7 7 √ - 8 4x31, 6x29 2 3 √ √ LQFP64* -40 to +85
NANO110SD3BN 64 16 Configurable 4 51 4 2+3 3 2 - 1 7 7 √ - 8 4x31, 6x29 2 3 √ √ LQFP64* -40 to +85
NANO110SE3BN 128 16 Configurable 4 51 4 2+3 3 2 - 1 7 7 √ - 8 4x31, 6x29 2 3 √ √ LQFP64* -40 to +85
NANO110RC2BN 32 8 Configurable 4 51 4 2+3 3 2 - 1 7 7 √ - 8 4x31, 6x29 2 3 √ √ LQFP64 -40 to +85
NANO110RD2BN 64 8 Configurable 4 51 4 2+3 3 2 - 1 7 7 √ - 8 4x31, 6x29 2 3 √ √ LQFP64 -40 to +85
NANO110RD3BN 64 16 Configurable 4 51 4 2+3 3 2 - 1 7 7 √ - 8 4x31, 6x29 2 3 √ √ LQFP64 -40 to +85
NANO110RE3BN 128 16 Configurable 4 51 4 2+3 3 2 - 1 7 7 √ - 8 4x31, 6x29 2 3 √ √ LQFP64 -40 to +85
NANO110KC2BN 32 8 Configurable 4 86 4 2+3 3 2 - 1 8 12 √ √ 8 4x40, 6x38 2 3 √ √ LQFP128 -40 to +85
NANO110KD2BN 64 8 Configurable 4 86 4 2+3 3 2 - 1 8 12 √ √ 8 4x40, 6x38 2 3 √ √ LQFP128 -40 to +85
NANO110KD3BN 64 16 Configurable 4 86 4 2+3 3 2 - 1 8 12 √ √ 8 4x40, 6x38 2 3 √ √ LQFP128 -40 to +85
NANO110KE3BN 128 16 Configurable 4 86 4 2+3 3 2 - 1 8 12 √ √ 8 4x40, 6x38 2 3 √ √ LQFP128 -40 to +85
Table 3‑2 Nano110 LCD Line Selection Table

3.2.3 NuMicro® Nano120 USB Connectivity Line Selection Guide

Flash SRAM Data Flash Timer PWM ADC DAC
Part No. ROM I/O I2S RTC EBI PDMA LCD ISO-7816-3* ISP 10KHz Package Temp.
NANO120LC2BN 32 8 Configurable 4 34 4 2+2 3 2 1 1 4 7 √ - 8 - 2 2 √ √ LQFP48 -40 to +85
NANO120LD2BN 64 8 Configurable 4 34 4 2+2 3 2 1 1 4 7 √ - 8 - 2 2 √ √ LQFP48 -40 to +85
NANO120LD3BN 64 16 Configurable 4 34 4 2+2 3 2 1 1 4 7 √ - 8 - 2 2 √ √ LQFP48 -40 to +85
NANO120LE3BN 128 16 Configurable 4 34 4 2+2 3 2 1 1 4 7 √ - 8 - 2 2 √ √ LQFP48 -40 to +85
NANO120SC2BN 32 8 Configurable 4 48 4 2+3 3 2 1 1 8 7 √ - 8 - 2 3 √ √ LQFP64* -40 to +85
NANO120SD2BN 64 8 Configurable 4 48 4 2+3 3 2 1 1 8 7 √ - 8 - 2 3 √ √ LQFP64* -40 to +85
NANO120SD3BN 64 16 Configurable 4 48 4 2+3 3 2 1 1 8 7 √ - 8 - 2 3 √ √ LQFP64* -40 to +85
NANO120SE3BN 128 16 Configurable 4 48 4 2+3 3 2 1 1 8 7 √ - 8 - 2 3 √ √ LQFP64* -40 to +85
NANO120KD3BN 64 16 Configurable 4 86 4 2+3 3 2 1 1 8 8 √ √ 8 - 2 3 √ √ LQFP128 -40 to +85
NANO120KE3BN 128 16 Configurable 4 86 4 2+3 3 2 1 1 8 8 √ √ 8 - 2 3 √ √ LQFP128 -40 to +85
Table 3‑3 Nano120 USB Connectivity Line Selection Table

3.2.4 NuMicro® Nano130 Advanced Line Selection Guide

NANO130SC2BN 32 8 Configurable 4 47 4 2+3 3 2 1 1 7 7 √ - 8 4x31, 6x29 2 3 √ √ LQFP64* -40 to +85
NANO130SD2BN 64 8 Configurable 4 47 4 2+3 3 2 1 1 7 7 √ - 8 4x31, 6x29 2 3 √ √ LQFP64* -40 to +85
NANO130SD3BN 64 16 Configurable 4 47 4 2+3 3 2 1 1 7 7 √ - 8 4x31, 6x29 2 3 √ √ LQFP64* -40 to +85
NANO130SE3BN 128 16 Configurable 4 47 4 2+3 3 2 1 1 7 7 √ - 8 4x31, 6x29 2 3 √ √ LQFP64* -40 to +85
NANO130KC2BN 32 8 Configurable 4 86 4 2+3 3 2 1 1 8 8 √ √ 8 4x40, 6x38 2 3 √ √ LQFP128 -40 to +85
NANO130KD2BN 64 8 Configurable 4 86 4 2+3 3 2 1 1 8 8 √ √ 8 4x40, 6x38 2 3 √ √ LQFP128 -40 to +85
NANO130KD3BN 64 16 Configurable 4 86 4 2+3 3 2 1 1 8 8 √ √ 8 4x40, 6x38 2 3 √ √ LQFP128 -40 to +85
NANO130KE3BN 128 16 Configurable 4 86 4 2+3 3 2 1 1 8 8 √ √ 8 4x40, 6x38 2 3 √ √ LQFP128 -40 to +85
Table 3‑4 Nano130 Advanced Line Selection Table


3.3 Pin Configuration
3.3.1 NuMicro® Nano100 Pin Diagrams

®
3.3.1.1 NuMicro Nano100 LQFP 128-pin
ICE_DAT/PF.0
ICE_CLK/PF.1
PA.7/AD7
PA.6/AD6
PA.5/AD5
PA.4/AD4
PA.3/AD3
PA.2/AD2
PA.1/AD1
PA.0/AD0
PC.10
PC.11
PC.12
PC.13
PA.12
PA.13
PA.14
PA.15
AVSS
AVSS
PC.8
PC.9
PE.0
PE.1
PE.2
PE.3
PE.4
VDD
VSS
VSS
NC
NC
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VREF 97 64 PB.9
NC 98 63 PB.10
AVDD 99 62 PB.11
AD8/PD.0 100 61 PE.5
AD9/PD.1 101 60 NC
AD10/PD.2 102 59 NC
AD11/PD.3 103 58 PE.6
NC 104 57 PC.0
PD.4 105 56 PC.1
PD.5 106 55 PC.2
PC.7 107 54 PC.3
PC.6 108 53 PC.4
PC.15 109 52 PC.5
PC.14 110 51 PD.15
PB.15 111 50 PD.14
NC 112
NANO100 49 PD.7
XT1_IN 113 LQFP 128-pin 48 PD.6
XT1_OUT 114 47 PB.3
NC 115 46 PB.2
nRESET 116 45 PB.1
VSS 117 44 PB.0
VSS 118 43 NC
NC 119 42 NC
VDD 120 41 NC
NC 121 40 NC

PF.4 122 39 NC
PF.5 123 38 PE.7
VSS 124 37 PE.8
PVSS 125 36 PE.9
PB.8 126 35 PE.10
PE.15 127 34 PE.11
PE.14 128 33 PE.12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
PE.13
PB.14
PB.13
PB.12
X32O
X32I
NC
PA.11
PA.10
PA.9
PA.8
PD.8
PD.9
PD.10
PD.11
PD.12
PD.13
PB.4
PB.5
PB.6
PB.7
NC
LDO_CAP
NC
NC
VDD
NC
VSS
VSS
VSS
VSS
NC
®
Figure 3‑2 NuMicro Nano100 LQFP 128-pin Diagram

®
ICE_DAT/PF.0
ICE_CLK/PF.1
PA.4/AD4
PA.3/AD3
PA.2/AD2
PA.1/AD1
PA.0/AD0
PC.10
PC.11
PA.12
PA.13
PA.14
PA.15
AVSS
PC.8
PC.9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD5/PA.5 49 32 PB.9
AD6/PA.6 50 31 PB.10
VREF 51 30 PB.11
AVDD 52 29 PE.5
PC.7 53 28 PC.0
PC.6 54 27 PC.1
PC.15 55 26 PC.2
PC.14 56 NANO100 25 PC.3
PB.15 57 LQFP 64-pin 24 PD.15
XT1_IN 58 23 PD.14
XT1_OUT 59 22 PD.7
nRESET 60 21 PD.6
VSS 61 20 PB.3
VDD 62 19 PB.2
PVSS 63 18 PB.1
PB.8 64 17 PB.0
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
PB.14
PB.13
PB.12
X32O
X32I
PA.11
PA.10
PA.9
PA.8
PB.4
PB.5
PB.6
PB.7
LDO_CAP
VDD
VSS
®

®
3.3.1.3 NuMicro Nano100 LQFP/QFN 48-pin
ICE_DAT/PF.0
ICE_CLK/PF.1
PA.4/AD4
PA.3/AD3
PA.2/AD2
PA.1/AD1
PA.0/AD0
PA.12
PA.13
PA.14
PA.15
AVSS
36
35
34
33
32
31
30
29
28
27
26
25
AD5/PA.5 37 24 PB.9
AD6/PA.6 38 23 PB.10
VREF 39 22 PB.11
AVDD 40 21 PE.5
PC.7 41 20 PC.0
PC.6 42 NANO100 19 PC.1
PB.15 43 LQFP/QFN 48-pin 18 PC.2
XT1_IN 44 17 PC.3
XT1_OUT 45 16 PB.3
nRESET 46 15 PB.2
PVSS 47 14 PB.1
PB.8 48 13 PB.0
10
11
12
1
2
3
4
5
6
7
8
9
PB.12
X32O
X32I
PA.11
PA.10
PA.9
PA.8
PB.4
PB.5
LDO_CAP
VDD
VSS

®


®
PA.7/AD7/LCD_SEG36
PA.6/AD6/LCD_SEG37
PA.5/AD5/LCD_SEG38
PA.4/AD4/LCD_SEG39
ICE_DAT/PF.0
ICE_CK/PF.1
PC.10
PC.11
PC.12
PC.13
PA.12
PA.13
PA.14
PA.15
AVSS
AVSS
PC.8
PC.9
PA.3
PA.2
PA.1
PA.0
PE.0
PE.1
PE.2
PE.3
PE.4
VDD
VSS
VSS
NC
NC
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VREF 97 64 PB.9/LCD_V3
NC 98 63 PB.10/LCD_V2
AVDD 99 62 PB.11/LCD_V1
AD8/PD.0 100 61 PE.5
AD9/PD.1 101 60 NC
AD10/PD.2 102 59 VLCD
AD11/PD.3 103 58 PE.6
NC 104 57 PC.0/LCD_DH1
LCD_SEG35/PD.4 105 56 PC.1/LCD_DH2
LCD_SEG34/PD.5 106 55 PC.2/LCD_COM0
PC.7 107 54 PC.3/LCD_COM1
LCD_SEG33/PC.15 109 52 PC.5/LCD_COM3
LCD_SEG32/PC.14 110 51 PD.15/LCD_SEG0(COM4)
LCD_SEG31/PB.15 111 50 PD.14/LCD_SEG1(COM5)
NC 112
NANO110 49 PD.7/LCD_SEG2
XT1_IN 113 LQFP 128-pin 48 PD.6/LCD_SEG3
XT1_OUT 114 47 PB.3/LCD_SEG4
NC 115 46 PB.2/LCD_SEG5
nRESET 116 45 PB.1/LCD_SEG6
VSS 117 44 PB.0/LCD_SEG7
VSS 118 43 NC
NC 119 42 NC
VDD 120 41 NC
NC 121 40 NC
PF.4 122 39 NC
PF.5 123 38 PE.7/LCD_SEG8
VSS 124 37 PE.8/LCD_SEG9
PVSS 125 36 PE.9

LCD_SEG30/PB.8 126 35 PE.10
LCD_SEG29/PE.15 127 34 PE.11
LCD_SEG28/PE.14 128 33 PE.12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
LCD_SEG27/PE.13
LCD_SEG26//PB.14
LCD_SEG25/PB.13
LCD_SEG24/PB.12
X32O
X32I
NC
LCD_SEG23/PA.11
LCD_SEG22/PA.10
LCD_SEG21/PA.9
LCD_SEG20/PA.8
LCD_SEG19/PD.8
LCD_SEG18/PD.9
LCD_SEG17/PD.10
LCD_SEG16/PD.11
LCD_SEG15/PD.12
LCD_SEG14/PD.13
LCD_SEG13/PB.4
LCD_SEG12/PB.5
LCD_SEG11/PB.6
LCD_SEG10/PB.7
NC
LDO_CAP
NC
NC
VDD
NC
VSS
VSS
VSS
VSS
NC
®

®
PA.4/AD4/LCD_SEG21
PA.3/AD3/LCD_SEG22
PA.2/AD2/LCD_SEG23
PC.10/LCD_SEG30
PC.11/LCD_SEG31
PA.12/LCD_SEG24
PA.13/LCD_SEG25
PA.14/LCD_SEG26
PA.15/LCD_SEG27
PC.8/LCD_SEG28
PC.9/LCD_SEG29
ICE_DAT/PF.0
ICE_CLK/PF.1
PA.1/AD1
PA.0/AD0
AVSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LCD_SEG20/AD5/PA.5 49 32 PB.9/LCD_V3
AVDD 52 29 LCD_VLCD
LCD_SEG17/PC.7 53 28 PC.0/LCD_DH1
PC.6 54 27 PC.1/LCD_DH2
LCD_SEG15/PC.14 56 Nano110 25 PC.3/LCD_COM1
LCD_SEG14/PB.15 57 LQFP 64-pin 24 PD.15
XT1_IN 58 23 PD.14
XT1_OUT 59 22 PD.7
nRESET 60 21 PD.6
VSS 61 20 PB.3/LCD_COM2
VDD 62 19 PB.2/LCD_COM3
PVSS 63 18 PB.1/LCD_SEG0(COM4)
LCD_SEG13/PB.8 64 17 PB.0/LCD_SEG1(COM5)
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9

LCD_SEG12/PB.14
LCD_SEG11/PB.13
LCD_SGE10/PB.12
X32O
X32I
LCD_SGE9/PA.11
LCD_SGE8/PA.10
LCD_SGE7/PA.9
LCD_SGE6/PA.8
LCD_SGE5/PB.4
LCD_SGE4/PB.5
LCD_SGE3/PB.6
LCD_SGE2/PB.7
LDO_CAP
VDD
VSS
®


®
ICE_DAT/PF.0
ICE_CLK/PF.1
PC.10
PC.11
PC.12
PC.13
PA.12
PA.13
PA.14
PA.15
AVSS
AVSS
PC.8
PC.9
PA.7
PA.6
PA.5
PA.4
PA.3
PA.2
PA.1
PA.0
PE.0
PE.1
PE.2
PE.3
PE.4
VDD
VSS
VSS
NC
NC
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VREF 97 64 PB.9
NC 98 63 PB.10
AVDD 99 62 PB.11
PD.0 100 61 PE.5
PD.1 101 60 NC
PD.2 102 59 NC
PD.3 103 58 PE.6
NC 104 57 PC.0
PD.4 105 56 PC.1
PD.5 106 55 PC.2
PC.7 107 54 PC.3
PC.6 108 53 PC.4
PC.15 109 52 PC.5
PC.14 110 51 PD.15
PB.15 111 50 PD.14
NC 112
NANO120 49 PD.7
XT1_IN 113 LQFP 128-pin 48 PD.6
XT1_OUT 114 47 PB.3
NC 115 46 PB.2
nRESET 116 45 PB.1
VSS 117 44 PB.0
VSS 118 43 USB_D+
NC 119 42 USB_D-
VDD 120 41 USB_VDD33_CAP
NC 121 40 USB_VBUS
PF.4 122 39 NC
PF.5 123 38 PE.7
VSS 124 37 PE.8
PVSS 125 36 PE.9

PB.8 126 35 PE.10
PE.15 127 34 PE.11
PE.14 128 33 PE.12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
PE.13
PB.14
PB.13
PB.12
X32O
X32I
NC
PA.11
PA.10
PA.9
PA.8
PD.8
PD.9
PD.10
PD.11
PD.12
PD.13
PB.4
PB.5
PB.6
PB.7
NC
LDO_CAP
NC
NC
VDD
NC
VSS
VSS
VSS
VSS
NC
®

®
ICE_DAT/PF.0
ICE_CLK/PF.1
PC.10
PC.11
PA.12
PA.13
PA.14
PA.15
AVSS
PC.8
PC.9
PA.4
PA.3
PA.2
PA.1
PA.0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PA.5 49 32 PB.9
PA.6 50 31 PB.10
VREF 51 30 PB.11
AVDD 52 29 PE.5
PC.7 53 28 PC.0
PC.6 54 27 PC.1
PC.15 55 26 PC.2
PC.14 56 NANO120 25 PC.3
PB.15 57 LQFP 64-pin 24 PB.3
XT1_IN 58 23 PB.2
XT1_OUT 59 22 PB.1
nRESET 60 21 PB.0
VSS 61 20 USB_D+
VDD 62 19 USB_D-
PVSS 63 18 USB_VDD33_CAP
PB.8 64 17 USB_VBUS
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9

PB.14
PB.13
PB.12
X32O
X32I
PA.11
PA.10
PA.9
PA.8
PB.4
PB.5
PB.6
PB.7
LDO
VDD
VSS
®

®
ICE_DAT/PF.0
ICE_CLK/PF.1
PA.12
PA.13
PA.14
PA.15
AVSS
PA.4
PA.3
PA.2
PA.1
PA.0
36
35
34
33
32
31
30
29
28
27
26
25
PA.5 37 24 PC.0
PA.6 38 23 PC.1
VREF 39 22 PC.2
AVDD 40 21 PC.3
PC.7 41 20 PB.3
PC.6 42 NANO120 19 PB.2
PB.15 43 LQFP 48-pin 18 PB.1
XT1_IN 44 17 PB.0
XT1_OUT 45 16 USB_D+
nRESET 46 15 USB_D-
PB.8 48 13 USB_VBUS
10
11
12
1
2
3
4
5
6
7
8
9
PB.12
X32O
X32I
PA.11
PA.10
PA.9
PA.8
PB.4
PB.5
LDO_CAP
VDD
VSS
®


®
PA.7/AD7/LCD_SEG36
PA.6/AD6/LCD_SEG37
PA.5/AD5/LCD_SEG38
PA.4/AD4/LCD_SEG39
ICE_DAT/PF.0
ICE_CLK/PF.1
PA.3/AD3
PA.2/AD2
PA.1/AD1
PA.0/AD0
PC.10
PC.11
PC.12
PC.13
PA.12
PA.13
PA.14
PA.15
AVSS
AVSS
PC.8
PC.9
PE.0
PE.1
PE.2
PE.3
PE.4
VDD
VSS
VSS
NC
NC
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
NC 98 63 PB.10/LCD_V2
AVDD 99 62 PB.11/LCD_V1
AD8/PD.0 100 61 PE.5
AD9/PD.1 101 60 NC
AD10/PD.2 102 59 VLCD
AD11/PD.3 103 58 PE.6
NC 104 57 PC.0/LCD_DH1
LCD_SEG35/PD.4 105 56 PC.1/LCD_DH2
LCD_SEG34/PD.5 106 55 PC.2/LCD_COM0
LCD_SEG32/PC.14 110 51 PD.15/LCD_SEG0(COM4)
LCD_SEG31/PB.15 111 50 PD.14/LCD_SEG1(COM5)
NC 112
NANO130 49 PD.7/LCD_SEG2
XT1_IN 113 LQFP 128-pin 48 PD.6/LCD_SEG3
XT1_OUT 114 47 PB.3/LCD_SEG4
NC 115 46 PB.2/LCD_SEG5
nRESET 116 45 PB.1/LCD_SEG6
VSS 117 44 PB.0/LCD_SEG7
VSS 118 43 USB_D+
NC 119 42 USB_D-
VDD 120 41 USB_VDD33_CAP
NC 121 40 USB_VBUS
PF.4 122 39 NC
PF.5 123 38 PE.7/LCD_SEG8
VSS 124 37 PE.8/LCD_SEG9

PVSS 125 36 PE.9
LCD_SEG30/PB.8 126 35 PE.10
LCD_SEG29/PE.15 127 34 PE.11
LCD_SEG28/PE.14 128 33 PE.12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
LCD_SEG27/PE.13
LCD_SEG26/PB.14
LCD_SEG25/PB.13
LCD_SEG24/PB.12
X32O
X32I
NC
LCD_SEG23/PA.11
LCD_SEG22/PA.10
LCD_SEG21/PA.9
LCD_SEG20/PA.8
LCD_SEG19/PD.8
LCD_SEG18/PD.9
LCD_SEG17/PD.10
LCD_SEG16/PD.11
LCD_SEG15/PD.12
LCD_SEG14/PD.13
LCD_SET13/PB.4
LCD_SEG12/PB.5
LCD_SEG11/PB.6
LCD_SEG10/PB.7
NC
LDO
NC
NC
VDD
NC
VSS
VSS
VSS
VSS
NC
®

®
PA.4/AD4/LCD_SEG21
PA.3/AD3/LCD_SEG22
PA.2/AD2/LCD_SEG23
PC.10/LCD_SEG30
PC.11/LCD_SEG31
PA.12/LCD_SEG24
PA.13/LCD_SEG25
PA.14/LCD_SEG26
PA.15/LCD_SEG27
PC.8/LCD_SEG28
PC.9/LCD_SEG29
ICE_DAT/PF.0
ICE_CLK/PF.1
PA.1/AD1
PA.0/AD0
AVSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AVDD 52 29 VLCD
LCD_SEG17/PC.7 53 28 PC.0/LCD_DH1
PC.6 54 27 PC.1/LCD_DH2
LCD_SEG15/PC.14 56 Nano130 25 PC.3/LCD_COM1
LCD_SEG14/PB.15 57 LQFP 64-pin 24 PB.3/LCD_COM2
XT1_IN 58 23 PB.2/LCD_COM3
XT1_OUT 59 22 PB.1/LCD_SEG0(COM4)
nRESET 60 21 PB.0/LCD_SEG1(COM5)
VSS 61 20 USB_D+
VDD 62 19 USB_D-
LCD_SEG13/PB.8 64 17 USB_VBUS
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
LCD_SEG12/PB.14
LCD_SEG11/PB.13
LCD_SGE10/PB.12
X32O
X32I
LCD_SGE9/PA.11
LCD_SGE8/PA.10
LCD_SGE7/PA.9
LCD_SGE6/PA.8
LCD_SGE5/PB.4
LCD_SGE4/PB.5
LCD_SGE3/PB.6
LCD_SGE2/PB.7
LDO_CAP
VDD
VSS
®

3.4 Pin Description
3.4.1 NuMicro® Nano100 Pin Description

Pin No.
Pin
Pin Name Description
LQFP LQFP LQFP/QFN Type
128-pin 64-pin 48-pin
1 PE.13 I/O General purpose digital I/O pin
PB.14 I/O General purpose digital I/O pin
INT0 I External interrupt0 input pin

2 1
SC2_CD I SmartCard2 card detect pin
nd
SPI2_SS1 I/O SPI2 2 slave select pin

3 2
EBI_AD1 I/O EBI Address/Data bus bit1
4 3 1 EBI_AD0 I/O EBI Address/Data bus bit0
FCLKO O Frequency Divider output pin
5 NC
6 4 2 X32O O External 32.768 kHz crystal output pin
7 5 3 X32I I External 32.768 kHz crystal input pin
8 NC

PA.11 I/O General purpose digital I/O pin
2
I2C1_SCL I/O I C1 clock pin
9 6 4 EBI_nRD O EBI read enable output pin
SC0_RST O SmartCard0 RST pin

st
SPI2_MOSI0 I/O SPI2 1 MOSI (Master Out, Slave In) pin

2
I2C1_SDA I/O I C1 data I/O pin
10 7 5 EBI_nWR O EBI write enable output pin
SC0_PWR O SmartCard0 Power pin

st
SPI2_MISO0 I/O SPI2 1 MISO (Master In, Slave Out) pin

2
11 8 6
SC0_DAT I/O SmartCard0 DATA pin(SC0_UART_RXD)
SPI2_CLK I/O SPI2 serial clock pin

Pin No.
Pin

2
12 9 7
SC0_CLK O SmartCard0 clock pin(SC0_UART_TXD)
st
13 PD.8 I/O General purpose digital I/O pin
UART1_RXD I UART1 Data receiver input pin

19 10 8
st
UART1_TXD O UART1 Data transmitter output pin

20 11 9
UART1_RTSn O UART1 Request to Send output pin

21 12
EBI_ALE O EBI address latch enable output pin
st
UART1_CTSn I UART1 Clear to Send input pin

22 13
EBI_nCS O EBI chip select enable output pin
st
23 NC
24 14 10 LDO_CAP P LDO output pin
25 NC
26 NC

Pin No.
Pin
27 15 11 VDD P Power supply for I/O ports and LDO source
28 NC
29 16 12 VSS P Ground
30 VSS P Ground
31 VSS P Ground
32 VSS P Ground
39 NC
40 NC
41 NC
42 NC
43 NC

44 17 13 UART0_RXD I UART0 Data receiver input pin

st
45 18 14 UART0_TXD O UART0 Data transmitter output pin

st

46 19 15
EBI_nWRL O EBI low byte write enable output pin
47 20 16 UART0_CTSn I UART0 Clear to Send input pin
EBI_nWRH O EBI high byte write enable output pin

Pin No.
Pin
st
48 21 PD.6 I/O General purpose digital I/O pin
PC.5 I/O General purpose digital I/O pin

52
nd

53
nd

st
54 25 17
2
I2S_DO O I S data output

st
55 26 18
2
I2S_DI I I S data input
SC1_PWR O SmartCard1 PWR pin


56 27 19
2
I2S_BCLK I/O I S bit clock pin
General purpose digital I/O pin / Module

PC.0 / MCLKO I/O
clock output pin
st
57 28 20
2
I2S_LRCLK I/O I S left right channel clock
59 NC
60 NC
PE.5 I/O General purpose digital I/O pin

61 29 21
PWM1_CH1 I/O PWM1 Channel1 output

Pin No.
Pin
62 30 22 TM3 O Timer3 external counter input

st

nd

st

nd

65
st

66
st

67
PE.1 I/O General purpose digital I/O pin.
68 PWM1_CH3 I/O PWM1 Channel3 output

st

2
I2S_MCLK O I S master clock output pin

nd
70 SPI1_MOSI1 I/O SPI1 2 MOSI (Master Out, Slave In) pin
PWM1_CH1 O PWM1 Channel1 output

Pin No.
Pin
SNOOPER I Snooper pin
INT1 I External interrupt 1

2
I2C0_SCL O I C0 clock pin

nd
71 PWM1_CH0 O PWM1 Channel0 output

2

st
72 33 SPI1_MOSI0 I/O SPI1 1 MOSI (Master Out, Slave In) pin

st
73 34 SPI1_MISO0 I/O SPI1 1 MISO (Master In, Slave Out) pin
74 35 SPI1_CLK I/O SPI1 serial clock pin

2

st
75 36
EBI_MCLK O EBI external clock output pin
2

2
76 37 25
TC3 I Timer3 capture input
77 38 26 PWM0_CH2 I/O PWM0 Channel2 output

Pin No.
Pin

2

2
ICE_DAT I/O Serial Wired Debugger Data pin
80 41 29 PF.0 I/O General purpose digital I/O pin
ICE_CLK I Serial Wired Debugger Clock pin
PF.1 I/O General purpose digital I/O pin

81 42 30
82 NC
Power supply for I/O ports and LDO source

83 VDD P
for internal PLL and digital circuit
84 NC
85 VSS P Ground
86 VSS P Ground
87 43 31 AVSS AP Ground Pin for analog circuit
88 AVSS AP Ground Pin for analog circuit
89 44 32 AD0 AI ADC analog input0
SC2_CD I SmartCard2 card detect
90 45 33 PA.1 I/O General purpose digital I/O pin

Pin No.
Pin
AD1 AI ADC analog input1

91 46 34

92 47 35

2


2

95 50 38

96

Pin No.
Pin
97 51 39 VREF AP Voltage reference input for ADC
98 NC
99 52 40 AVDD AP Power supply for internal analog circuit
PD.0 I/O General purpose digital I/O pin

st
100 SPI2_SS0 I/O SPI2 1 slave select pin
101 SPI2_CLK I/O SPI2 serial clock pin
SC1_DAT I/O SmartCard1 DATA pin(SC1_UART_RXD).

2
102
st

2
103
st
104 NC

105
2

Pin No.
Pin
nd

2
106 I2S_DO O I S data output
nd
DA1_OUT AO DAC 1 output
DA0_OUT I DAC0 output

108 54 42


109 55
110 56 EBI_AD2 I/O EBI Address/Data bus bit2

111 57 43
112 NC
XT1_IN O External 4~24 MHz crystal output pin

113 58 44

Pin No.
Pin
XT1_OUT I External 4~24 MHz crystal input pin

114 59 45
115 NC
External reset input: Low active, set this pin

116 60 46 nRESET I low reset chip to initial state. With internal
pull-up.
117 61 VSS P Ground
118 VSS P Ground
119 NC

120 62 VDD P
121 NC

122
2

123
2
124 VSS P Ground
125 63 47 PVSS P PLL Ground

STADC I ADC external trigger input.
126 64 48 TM0 I Timer0 external counter input
Note:
Pin Type: I = Digital Input, O = Digital Output; AI = Analog Input; AO = Analog Output; P = Power Pin; AP = Analog Power.


Pin No.
Pin Name Pin Type Description
LQFP LQFP LQFP

1
LCD_SEG27 O LCD segment output 27 at LQFP128

2 1
nd

3 2
4 3 FCLKO O Frequency Divider output pin

5 NC
6 4 X32O O External 32.768 kHz crystal output pin
7 5 X32I I External 32.768 kHz crystal input pin
8 NC

2
EBI_nRD O EBI read enable output pin
9 6 SC0_RST O SmartCard0 RST pin

st

10 7
2

Pin No.
LQFP LQFP LQFP
EBI_nWR O EBI write enable output pin

st

2

11 8

2

12 9
st

13

14

15

16

17

18
19 10 PB.4 I/O General purpose digital I/O pin

Pin No.
LQFP LQFP LQFP

st

20 11

21 12
st


22 13
st
23 NC
24 14 LDO_CAP P LDO output pin
25 NC
26 NC
27 15 VDD P Power supply for I/O ports and LDO source
28 NC
29 16 VSS P Ground

Pin No.
LQFP LQFP LQFP
30 VSS P Ground
31 VSS P Ground
32 VSS P Ground

33

34

35

36

37

38
39 NC
40 NC

41 NC
42 NC
43 NC

st
44 17
LCD segment output 1 at LQFP64 (or as
LCD_SEG1 O
LD_COM5)

45 18 I/O st
SPI1_MISO0 SPI1 1 MISO (Master In, Slave Out) pin

LCD_SEG0 O
LCD_COM4)

Pin No.
LQFP LQFP LQFP

46 19
LCD_COM3 O LCD common output 3 at LQFP64

47 20
st

48 21

49 22

50 23
LCD_SEG1 O
LCD_COM5)

51 24
LCD_SEG0 O
LCD_COM4)

nd

nd
53 SPI0_MISO1 I/O SPI0 2 MISO (Master In, Slave Out) pin

54 25
st

Pin No.
LQFP LQFP LQFP
2

st
2
55 26

2
56 27 SC1_DAT I/O SmartCard1 DATA pin(SC1_UART_RXD)
LCD externl capacitor pin of charge pump

LCD_DH2 O
circuit at LQFP64

LCD_DH2 O
circuit at LQFP128

General purpose digital I/O pin / Module
PC.0 / MCLKO I/O
clock output pin
st
2
57 28 O
SC1_CLK SmartCard1 clock pin(SC1_UART_TXD)

LCD_DH1 O
circuit at LQFP64

LCD_DH1 O
circuit at LQFP128
59 29 LCD_VLCD AO LCD power supply pin
60 NC

62 30

Pin No.
LQFP LQFP LQFP
TM3 O Timer3 external counter input

st
Unit voltage for LCD charge pump circuit at

LCD_V1 O
LQFP64
LCD Unit voltage for LCD charge pump

LCD_V1 O
circuit at LQFP128

nd
63 31 SC2_CLK O SmartCard2 clock pin(SC2_UART_TXD)

st
LCD_V2 O LCD driver biasing voltage at LQFP64

nd


65
st

66
st

67

st

Pin No.
LQFP LQFP LQFP

2

nd

70
INT1 I External interrupt 1

2

nd

2

st
72 33

st
73 34

74 35
2

st
75 36 EBI_MCLK O EBI external clock output pin

2

Pin No.
LQFP LQFP LQFP

2
76 37 TC3 I Timer3 capture input

77 38

78 39
2

79 40
2
80 41 PF.0 I/O General purpose digital I/O pin

81 42

Pin No.
LQFP LQFP LQFP
82 NC

83 VDD P
84 NC
85 VSS P Ground
86 VSS P Ground
87 43 AVSS AP Ground Pin for analog circuit
89 44 AD0 AI ADC analog input0

LCD_SEG23* AO LCD segment output 23 at LQFP64

2

Pin No.
LQFP LQFP LQFP

2

95 50

96 TC2 I Timer2 capture input
LCD_SEG36* AO LCD segment output 36 output at LQFP128
97 51 VREF AP Voltage reference input for ADC
98 NC
99 52 AVDD AP Power supply for internal analog circuit
100 UART1_RXD I UART1 Data receiver input pin

st

Pin No.
LQFP LQFP LQFP
UART1_RTSn UART1 Request to Send output pin

2
102
st
UART1_CTSn UART1 Clear to Send input pin

2
103
st

104 NC

2
nd
LCD_SEG35 AO LCD segment output 35 at LQFP10

2
106
nd
107 53 PC.7 I/O General purpose digital I/O pin

Pin No.
LQFP LQFP LQFP

108 54

109 55

110 56 PWM1_CH3 I/O PWM1 Channel3 output
111 57 SNOOPER I Snooper pin
112 NC

113 58

Pin No.
LQFP LQFP LQFP

114 59
115 NC
External reset input: Low active, set this pin

116 60 nRESET I low reset chip to initial state. With internal
pull-up.
117 61 VSS P Ground
118 VSS P Ground
119 NC

120 62 VDD P
121 NC

122
2

123
2
124 VSS P Ground
125 63 PVSS P PLL Ground

TM0 I Timer0 external counter input
126 64 INT0 I External interrupt0 input pin

127

128
Note:
1. Pin Type: I = Digital Input, O=Digital Output; AI=Analog Input; AO= Analog Output; P=Power Pin; AP=Analog Power;
2. * : Output voltage for ADC/LCD shared pins cannot be higher than VDD because these pins are without 5V tolerance.


Pin No.
Pin
LQFP Pin Name Description
LQFP LQFP Type
128 64 48
1 PE.13 I/O General purpose digital IO pin
PB.14 I/O General purpose digital IO pin

2 1
nd

3 2
5 NC
6 4 2 X32O O External 32.768 kHz crystal output pin
7 5 3 X32I I External 32.768 kHz crystal input pin
8 NC
PA.11 I/O General purpose digital IO pin

2
I2C1_SCL I/O I C 1 clock pin
9 6 4 EBI_nRD O EBI read enable output pin

st

2
I2C1_SDA I/O I C 1 data I/O pin
10 7 5 EBI_nWR O EBI write enable output pin

st

2
11 8 6
12 9 7 PA.8 I/O General purpose digital IO pin

Pin No.
Pin
LQFP LQFP Type
128 64 48
2

st
13 PD.8 I/O General purpose digital IO pin

19 10 8
st

20 11 9

UART1_nRTS O UART1 Request to Send output pin

21 12
st
UART1_nCTS I UART1 Clear to Send input pin

22 13
st
23 NC
24 14 10 LDO_CAP P LDO output pin
25 NC
26 NC
27 15 11 VDD P Power supply for I/O ports and LDO source

Pin No.
Pin
LQFP LQFP Type
128 64 48
28 NC
29 16 12 VSS P Ground
30 VSS P Ground
31 VSS P Ground
32 VSS P Ground
39 NC
40 17 13 USB_VBUS USB POWER SUPPLY: From USB Host or HUB.
USB_VDD33_C Internal Power Regulator Output 3.3V Decoupling

41 18 14 USB
AP Pin
42 19 15 USB_D- USB USB Differential Signal D-
43 20 16 USB_D+ USB USB Differential Signal D+

44 21 17 UART0_RXD I UART0 Data receiver input pin

st
45 22 18 UART0_TXD O UART0 Data transmitter output pin

st

46 23 19

47 24 20
st

Pin No.
Pin
LQFP LQFP Type
128 64 48
PC.5 I/O General purpose digital IO pin

52
nd

53
nd

st
54 25 21
2

st
55 26 22
2


56 27 23
2
General purpose digital IO pin / Module clock

PC.0 / MCLKO I/O
output pin
st
57 28 24
2
59 NC
60 NC
PE.5 I/O General purpose digital IO pin

61 29
62 30 PB.11 I/O General purpose digital IO pin

Pin No.
Pin
LQFP LQFP Type
128 64 48

st

nd
63 31 TM2 O Timer2 external counter input

st

nd

65
st

66
st

67

st

2

nd
70

Pin No.
Pin
LQFP LQFP Type
128 64 48
INT1 I External interrupt 1 input pin

2
I2C0_SCL O I C 0 clock pin

nd
71 PWM1_CH0 O PWM1 Channel 0 output

2

st
72 33 SPI1_MOSI0 I/O SPI1 1 MOSI (Master Out, Slave In) pin

st
73 34 SPI1_MISO0 I/O SPI1 1 MISO (Master In, Slave Out) pin
74 35 SPI1_CLK I/O SPI1 serial clock pin

2

st
75 36
EBI_MCLK O EBI external clock output pin
2

2
76 37 25

77 38 26
TC2 I Timer 2 capture input

Pin No.
Pin
LQFP LQFP Type
128 64 48

2

2
80 41 29 PF.0 I/O General purpose digital IO pin
PF.1 I/O General purpose digital IO pin

81 42 30
82 NC
Power supply for I/O ports and LDO source for

83 VDD P
internal PLL and digital circuit
84 NC
85 VSS P Ground
86 VSS P Ground
87 43 31 AVSS AP Ground Pin for analog circuit
89 44 32 AD0 AI ADC analog input0

90 45 33

Pin No.
Pin
LQFP LQFP Type
128 64 48

91 46 34

92 47 35
PA.4 I/O Digital GPIO pin

2


2

95 50 38
96 EBI_AD6 I/O EBI Address/Data bus bit6

Pin No.
Pin
LQFP LQFP Type
128 64 48
97 51 39 VREF AP Voltage reference input for ADC
98 NC
99 52 40 AVDD AP Power supply for internal analog circuit
PD.0 I/O General purpose digital IO pin

st

2

102
st

2
103
st
104 NC

2
105 I2S_DI I I S data input
nd

Pin No.
Pin
LQFP LQFP Type
128 64 48

2
106 I2S_DO O I S data output
nd
DA1+OUT AO DAC 1 output

108 54 42
SC1_CD SmartCard1 card detect pin

109 55

111 57 43
112 NC

113 58 44
114 59 45 XT1_OUT I External 4~24 MHz crystal input pin

Pin No.
Pin
LQFP LQFP Type
128 64 48
115 NC
External reset input: Low active, set this pin low

116 60 46 nRESET I
reset chip to initial state. With internal pull-up.
117 61 VSS P Ground
118 VSS P Ground
119 NC

120 62 VDD P
121 NC

122
2

123
2
124 VSS P Ground
125 63 47 PVSS P PLL Ground

126 64 48 TM0 I Timer0 external counter input
Note:
1. Pin Type: I = Digital Input, O=Digital Output; AI=Analog Input; AO= Analog Output; P=Power Pin; AP=Analog Power;


Pin No.
Pin
LQFP LQFP LQFP Type

1

2 1
nd

3 2
4 3 FCLKO O Frequency Divider output pin

5 NC
6 4 X32O O External 32.768 kHz crystal output pin
7 5 X32I I External 32.768 kHz crystal input pin
8 NC

2
EBI_nRD O EBI read enable output pin

st

10 7
2

Pin No.
Pin
LQFP LQFP LQFP Type
EBI_nWR O EBI write enable output pin

st

2

11 8

2

12 9
st


13

14

15

16

17

18
19 10 PB.4 I/O General purpose digital I/O pin

Pin No.
Pin
LQFP LQFP LQFP Type

st

20 11

21 12
st


22 13
st
23 NC
24 14 LDO_CAP P LDO output pin
25 NC
26 NC
27 15 VDD P Power supply for I/O ports and LDO source
28 NC
29 16 VSS P Ground

Pin No.
Pin
LQFP LQFP LQFP Type
30 VSS P Ground
31 VSS P Ground
32 VSS P Ground

37

38
39 NC
40 17 USB_VBUS USB POWER SUPPLY: From USB Host or HUB.
41 18 USB_VDD33_CAP USB Internal Power Regulator Output 3.3V Decoupling Pin
42 19 USB_D- USB USB Differential Signal D-
43 20 USB_D+ USB USB Differential Signal D+


st
44 21
LCD_SEG1 O
LCD_COM5)

st
45 22
LCD_SEG0 O
LCD_COM4)
46 23 UART0_RTSn O UART0 Request to Send output pin

Pin No.
Pin
LQFP LQFP LQFP Type

47 24
st

48

49

50
LCD_SEG1 O
LCD_COM5)

51
LCD_SEG0 O
LCD_COM4)

nd

nd

st
2
54 25

Pin No.
Pin
LQFP LQFP LQFP Type

st
2
55 26

2
56 27 SC1_DAT I/O SmartCard1 DATA pin(SC1_UART_RXD)
LCD externl capacitor pin of charge pump circuit at

LCD_DH2 O
LQFP64

LCD_DH2 O
LQFP128
General purpose digital I/O pin / Module clock output

PC.0 / MCLKO I/O
pin
st
2
57 28 O
SC1_CLK SmartCard1 clock pin(SC1_UART_TXD)

LCD_DH1 O
LQFP64

LCD_DH1 O
LQFP128
59 29 LCD_VLCD AO LCD power supply pin
60 NC
61 PE.5 General purpose digital I/O pin

st

Pin No.
Pin
LQFP LQFP LQFP Type
LCD Unit voltage for LCD charge pump circuit at

LCD_V1 O
LQFP64
LCD Unit voltage for LCD charge pump circuit at

LCD_V1 O
LQFP128

nd
63 31 SC2_CLK O SmartCard2 clock pin(SC2_UART_TXD)

st

nd

65
st

66
st

67

st

2
70 PC.13 I/O General purpose digital I/O pin

Pin No.
Pin
LQFP LQFP LQFP Type
nd

2

nd

2

st
72 33

st
73 34

74 35
2

st
75 36 EBI_MCLK O EBI external clock output pin

2

2

Pin No.
Pin
LQFP LQFP LQFP Type

77 38

78 39
2


79 40
2
80 41 PF.0 I/O General purpose digital I/O pin

81 42
82 NC

Pin No.
Pin
LQFP LQFP LQFP Type

83 VDD P
84 NC
85 VSS P Ground
86 VSS P Ground
87 43 AVSS AP Ground Pin for analog circuit

93 48 SC2_PWR O SmartCard2 Power pin

2
94 49 PA.5 I/O General purpose digital I/O pin

Pin No.
Pin
LQFP LQFP LQFP Type

2

95 50

96 TC2 I Timer2 capture input
LCD_SEG36* AO LCD segment output 36 output at LQFP128
97 51 VREF AP Voltage reference input for ADC
98 NC
99 52 AVDD AP Power supply for internal analog circuit

st

Pin No.
Pin
LQFP LQFP LQFP Type
TX1 O UART1 Data transmitter output pin

2
102
st

2
103
st
104 NC

2
nd

2
106
nd

107 53

Pin No.
Pin
LQFP LQFP LQFP Type

108 54
SC1_CD SmartCard1 card detect pin

109 55


111 57
112 NC

113 58

114 59

Pin No.
Pin
LQFP LQFP LQFP Type
115 NC
External reset input: Low active, set this pin low reset
116 60 nRESET I
chip to initial state. With internal pull-up.
117 61 VSS P Ground
118 VSS P Ground
119 NC

120 62 VDD P
121 NC

122
2
PF.5 I/O Digital GPI/O pin

123
2
124 VSS P Ground
125 63 PVSS I/O PLL Ground
TM0 I Timer0 external counter input

126 64 INT0 I External interrupt0 input pin

127

128
Note:
1. Pin Type: I=Digital Input, O=Digital Output; AI=Analog Input; AO=Analog Output; P=Power Pin; AP=Analog Power
2. * : Output voltage for ADC/LCD shared pins cannot be higher than VDD because these pins are without 5V tolerance.

4 BLOCK DIAGRAM
4.1 Nano100 Block Diagram
LXT
FLASH P LIRC
Cortex-M0
EBI 123/64/ DMA CLK_CTL L
42 MHz L HXT
32 KB HIRC
1.8V LDO
(input: 1.8 ~ 3.6V)
POR (1.8V)
BOD (1.7/2.0/2.5 V)
ISP 4KB SRAM GPIO
16/8 KB A,B,C,D,E,F
12-b ADC
I2C 1 I2C 0
12-b DAC
PWM 1 PWM 0
1.8/2.5V REF
Timer 2/3 Timer 0/1
UART 1 UART 0
TEMP Sensor
SPI 1 SPI 0
I2S SPI 2
SC 0/UART3 RTC
SC 1/UART4 WDT
SC 2/UART5 Peripherals with PDMA

NOTE: BOD can wake up system.
External interrupts, included in GPIO, can wake up system, too. Peripherals with wake-up
®
Figure 4‑1 NuMicro Nano100 Block Diagram

LXT
FLASH P LIRC
Cortex-M0
42 MHz L HXT
32 KB HIRC
1.8V LDO
(input: 1.8 ~ 3.6V)
POR (1.8V)
BOD (1.7/2.0/2.5 V)
ISP 4KB SRAM GPIO
16/8 KB A,B,C,D,E,F
12-b ADC
I2C 1 I2C 0
12-b DAC
PWM 1 PWM 0
1.8/2.5V REF
Timer 2/3 Timer 0/1
UART 1 UART 0
TEMP Sensor
SPI 1 SPI 0 LCD Booster
I2S SPI 2 LCD LCD COM/SEG

Up to
SC 0/UART3 RTC 4x40/6x38
SC 1/UART4 WDT
®

LXT
FLASH P LIRC
Cortex-M0
42 MHz L HXT
32 KB HIRC
1.8V LDO
(input: 1.8 ~ 3.6V)
POR (1.8V)
BOD (1.7/2.0/2.5 V)
ISP 4KB SRAM GPIO
16/8 KB A,B,C,D,E,F
12-b ADC
I2C 1 I2C 0
12-b DAC
PWM 1 PWM 0
1.8/2.5V REF
Timer 2/3 Timer 0/1
UART 1 UART 0
TEMP Sensor
SPI 1 SPI 0
I2S SPI 2
SC 0/UART3 RTC USB -512B USB PHY

SC 1/UART4 WDT

®

LXT
FLASH P LIRC
Cortex-M0
42 MHz L HXT
32 KB HIRC
1.8V LDO
(input: 1.8 ~ 3.6V)
POR (1.8V)
BOD (1.7/2.0/2.5 V)
ISP 4KB SRAM GPIO
16/8 KB A,B,C,D,E,F
12-b ADC
I2C 1 I2C 0
12-b DAC
PWM 1 PWM 0
1.8/2.5V REF
Timer 2/3 Timer 0/1
UART 1 UART 0
TEMP Sensor
SPI 1 SPI 0 LCD Booster
LCD COM/SEG
I2S SPI 2 LCD
Up to
SC 0/UART3 4x40/6x38
RTC USB -512B
USB PHY
SC 1/UART4 WDT
External interrupts, included in GPIO, can wake up system, too. Peripherals with wake up
®

5 FUNCTIONAL DESCRIPTION
5.1 Memory Organization
5.1.1 Overview
The Nano100 provides 4G-byte addressing space. The memory locations assigned to each on-
chip modules are shown in following. The detailed register definition, memory space, and
programming detailed will be described in the following sections for each on-chip module. The
Nano100 series only supports little-endian data format.
5.1.2 Memory Map

The memory locations assigned to each on-chip controllers are shown in the following table.
Address Space Token Modules
Flash & SRAM Memory Space
0x0000_0000 – 0x0001_FFFF FLASH_BA FLASH Memory Space (128KB)
0x2000_0000 – 0x2000_3FFF SRAM_BA SRAM Memory Space (16KB)
0x6000_0000 --- 0x6001_FFFF EXTMEM_BA External Memory Space(128KB)
AHB Modules Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF GCR_BA System Management Control Registers
0x5000_0200 – 0x5000_02FF CLK_BA Clock Control Registers
0x5000_0300 – 0x5000_03FF INT_BA Interrupt Multiplexer Control Registers
0x5000_4000 – 0x5000_7FFF GPIO_BA GPIO Control Registers
0x5000_8000 – 0x5000_BFFF DMA_BA DMA Control Registers

0x5000_C000 – 0x5000_FFFF FMC_BA Flash Memory Control Registers
0x5001_0000 – 0x5001_03FF EBI_BA External Bus Interface Control Registers
APB1 Modules Space (0x4000_0000 ~ 0x400F_FFFF)
0x4000_4000 – 0x4000_7FFF WDT_BA Watchdog Timer Control Registers
0x4000_8000 – 0x4000_BFFF RTC_BA Real Time Clock (RTC) Control Register
0x4001_0000 – 0x4001_3FFF TMR01_BA Timer0 and Timer1 Control Registers

2
0x4002_0000 – 0x4002_3FFF I2C0_BA I C0 Interface Control Registers
0x4003_0000 – 0x4003_3FFF SPI0_BA SPI0 with Master/Slave function Control Registers
0x4004_0000 – 0x4004_3FFF PWM0_BA PWM0 Control Registers
0x4005_0000 – 0x4005_3FFF UART0_BA UART0 Control Registers
0x4006_0000 – 0x4006_3FFF USBD_BA USB FS device Controller Registers
0x400A_0000 – 0x400A_3FFF DAC_BA Digital-Analog-Converter (DAC) Control Registers
0x400B_0000 – 0x400B_3FFF LCD_BA LCD Control Registers
0x400D_0000 – 0x400D_3FFF SPI2_BA SPI2 with Master/Slave function Control Registers

0x400E_0000 – 0x400E_3FFF ADC12_BA 12-bit Analog-Digital-Converter (ADC12) Control

Registers
APB2 Modules Space (0x4010_0000 ~ 0x401F_FFFF)
0x4011_0000 – 0x4011_3FFF TMR23_BA Timer2 and Timer3 Control Registers

2
0x4012_0000 – 0x4012_3FFF I2C1_BA I C1 Interface Control Registers
0x4013_0000 – 0x4013_3FFF SPI1_BA SPI1 with Master/Slave function Control Registers
0x4014_0000 – 0x4014_3FFF PWM1_BA PWM1 Control Registers
0x4015_0000 – 0x4015_3FFF UART1_BA UART1 Control Registers
0x4019_0000 – 0x4019_3FFF SC0_BA SmartCard0 Control Registers

2
0x401A_0000 – 0x401A_3FFF I2S_BA I S Control Registers
0x401B_0000 – 0x401B_3FFF SC1_BA SmartCard1 Control Registers
0x401C_0000 – 0x401C_3FFF SC2_BA SmartCard2 Control Registers
System Control Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF SCS_BA System Timer Control Registers
0xE000_E100 – 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers
0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Registers


5.2 Nested Vectored Interrupt Controller (NVIC)
5.2.1 Overview
The Cortex-M0 provides an interrupt controller as an integral part of the exception mode, named
as “Nested Vectored Interrupt Controller (NVIC)”. It is closely coupled to the processor kernel and
provides following features:
5.2.2 Features
 Nested and Vectored interrupt support
 Automatic processor state saving and restoration
 Dynamic priority changing
 Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When any interrupts is accepted, the starting address of the interrupt service routine (ISR) is
fetched from a vector table in memory. There is no need to determine which interrupt is accepted
and branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the

overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
®
For more detailed information, please refer to the “ARM Cortex™-M0 Technical Reference
®
Manual” and “ARM v6-M Architecture Reference Manual”.

5.3 System Manager
5.3.1 Overview
System manager mainly controls the power modes, wake-up source, system resets and system
memory map. It also provides information about product ID, chip reset, IP reset, and multi-function pin
control.
5.3.2 Features
 Power modes and wake-up sources
 System resets
 System Memory Map
 System manager registers for :
 Product ID
 Chip and IP reset
 Multi-functional pin control

5.4 Clock Controller
5.4.1 Overview
The clock controller generates clocks for the whole chip, Iincluding system clocks (CPU clock,
HCLKx, and PCLKx) and all peripheral engine clocks. HCLKx means AHB bus clock for
peripherals on AHB bus. PCLKx means APB bus clock for peripherals on APB bus. The clock
controller also implements the power control function with the individually clock ON/OFF control,
clock source selection and a 4-bit clock divider. The chip will not enter power-down mode until
CPU sets the power down enable bit (PD_EN) and CPU executes the WFI instruction. In the
Power-down mode, clock controller turns off the external high frequency crystal, internal high
frequency oscillator, and system clocks (CPU clock, HCLKx, and PCLKx) to reduce the power
consumption to minimum.
5.4.2 Features
 Generates clocks for system clocks and all peripheral engine clocks.
 Each peripheral engine clock can be turned on/off.
 High frequency crystal, internal high frequency oscillator, and system clocks will be
turned off when chip is in Power-down mode.

5.5 Analog to Digital Converter (ADC)
5.5.1 Overview
This chip contains one 12-bit successive approximation analog-to-digital converter (SAR A/D
converter) with 12 external input channels and 6 internal channels. The A/D converter supports
three operation modes: Single, Single-cycle Scan and Continuous Scan mode, and can be started
by software and external STADC/PB.8 pin and timer event start.
Note that the I/O pins used as ADC analog input pins must be configured as input type and off
digital function (GPIOA_OFFD) should be turned on before ADC function is enabled.
5.5.2 Features
 Analog input voltage range: 0~Vref (Max to 3.6V)
 Selectable 12-bits, 10-bits, 8-bits and 6-bits resolution
 Supports sampling time settings (in ADC_CLK unit) for channel 0~11 individually and
channel 12~17 share the same one sampling time setting
 Supports two power-down modes:
 Power-down mode
 Standby mode
 Up to 12 external analog input channels (channel0 ~ channel11), and 6 internal
channels (channel12~channel17) converting six voltage sources, including DAC0,
DAC1, internal band-gap voltage, internal temperature sensor output, AVDD, and
AVSS.
 Maximum ADC clock frequency is 42 MHz and each conversion is 19 clocks+
sampling time depending on the input resistance.
 Three operating modes
 Single mode: A/D conversion is performed one time on a specified channel.
 Single-cycle Scan mode: A/D conversion is performed one cycle on all specified
channels with the sequence from the lowest numbered channel to the highest
numbered channel.
 Continuous Scan mode: A/D converter continuously performs Single-cycle scan
mode until software stops A/D conversion.
 An A/D conversion can be started by:
 Software write 1 to ADST bit
 External pin STADC
 Selects one from four timer events (TMR0, TMR1, TMR2 and TMR3) that enable
ADC and transfer AD results by PDMA
 Conversion results held in data registers for each channel
 Conversion result can be compared with a specified value and user can select
whether to generate an interrupt when conversion result is equal to the compare
register setting.
 Supports Calibration and load Calibration words capability.

5.6 Digital to Analog Converter (DAC)
5.6.1 Overview
DAC is a 12-bit voltage-output digital-to-analog converter. Two DACs are implemented in this
chip.
5.6.2 Features
DAC is a 12-bit voltage-output DAC. DAC can use in conjunction with the PDMA controller. When
two DACs are present, they may be grouped together for synchronous update operation.
Features:
 Int_VREF or VREF or AVDD reference voltage selection
 Synchronized update capability for two DACs
 DAC maximum conversion rate is 500 KSPS

5.7 DMA Controller
5.7.1 Overview
The DMA controller contains six channel peripheral direct memory access (PDMA) controllers, a
video direct memory access (VDMA) controller and a cyclic redundancy check (CRC) generator.
The PDMA controller can transfer data to and from memory or transfer data to and from APB
devices. The DMA has eight channels of DMA including one channel VDMA (Memory-to-Memory)
and six channels PDMA (Peripheral-to-Memory or Memory-to-Peripheral or Memory-to-Memory)
and a CRC controller. For channel0 VDMA, it supports block transfer from memory to memory.
For PDMA channel (DMA CH1~CH6), there is one-word buffer as transfer buffer between the
Peripherals APB devices and Memory. And for channel 0 VDMA, there is a two-word buffer.
Software can stop the DMA operation by disable PDMA [PDMACEN]/VDMA [VDMACEN].
Software can recognize the completion of a DMA operation by software polling or when it receives
an internal DMA interrupt. The DMA controller can increase source or destination address, fixed
or wrap around them as well.
The DMA controller also contains a cyclic redundancy check (CRC) generator that can perform
CRC calculation with programmable polynomial settings. The CRC engine support CPU PIO
mode and DMA transfer mode.
5.7.2 Features
Seven DMA channels and a CRC generator: 1 VDMA channel and 6 PDMA channels. Each
channel can support a unidirectional transfer.
AMBA AHB master/slave interface compatible, for data transfer and register read/write.
Hardware round robin priority scheme.
 VDMA
 Memory-to-memory transfer
 Supports block transfer with stride
 Supports word/half-word/byte boundary address

 Supports address direction: increment and decrement
 PDMA
 Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer
 Supports word boundary address
 Supports word alignment transfer length in memory-to-memory mode
 Supports word/half-word/byte alignment transfer length in peripheral-to-memory
and memory-to-peripheral mode
 Supports word/half-word/byte transfer data width from/to peripheral
 Supports address direction: increment, fixed, and wrap around
 Cyclic Redundancy Check (CRC)
 Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
16 12 5
 CRC-CCITT: X +X +X +1
8 2
 CRC-8: X + X + X + 1
16 15 2
 CRC-16: X +X +X +1
32 26 23 22 16 12 11 10 8 7 5 4
 CRC-32: X +X +X +X +X +X +X +X +X +X +X +X +
2
X +X+1
 Programmable seed value

 Supports programmable order reverse setting for input data and CRC checksum
 Supports programmable 1’s complement setting for input data and CRC
checksum
 Supports CPU PIO mode or DMA transfer mode
 Supports 8/16/32-bit of data width in CPU PIO mode
 8-bit write mode: 1-AHB clock cycle operation
 Supports byte alignment transfer length in CRC DMA mode

5.8 External Bus Interface
5.8.1 Overview
This chip is equipped with an external bus interface (EBI) to access external device. To save the
connections between external device and this chip, EBI support address bus and data bus
multiplex mode. Also, address latch enable (ALE) signal is used to differentiate the address and
data cycle.
5.8.2 Features
 External devices with max. 64 Kbytes size (8-bit data width)/128 Kbytes (16-bit data
width) supported
 Supports variable external bus base clock (MCLK)
 Supports 8-bit or 16-bit data width
 Supports variable data access time (tACC), address latch enable time (tALE) and
address hold time (tAHD)
 Address bus and data bus multiplex mode supported to save the address pins
 Configurable idle cycle supported for different access condition: Write command finish
(W2X), Read-to-Read (R2R), Read-to-Write (R2W)
 Supports PDMA and VDMA transfer

5.9 FLASH Memory Controller (FMC)
5.9.1 Overview
This chip is equipped with 32K/64K/123K bytes on-chip embedded Flash EPROM for application
program memory (APROM) that can be updated through ISP/IAP procedure. In System
Programming (ISP) function enables user to update program memory when chip is soldered on
PCB. After chip powered on Cortex-M0 CPU fetches code from APROM or LDROM decided by
boot select (CBS) in Config0. By the way, this chip also provides DATA Flash Region, the data
flash is shared with original program memory and its start address is configurable and defined by
user in Config1. The data flash size is defined by user application request.
5.9.2 Features
 AHB interface compatible
 Run up to 42 MHz with zero wait state for discontinuous address read access
 32/64/123KB application program memory (APROM)
 4KB in system programming (ISP) loader program memory (LDROM)
 Programmable data flash start address and memory size with 512 bytes page erase
unit
 In System Program (ISP)/In Application Program (IAP) to update on chip Flash
EPROM

5.10 General Purpose I/O Controller
5.10.1 Overview
Up to 86 General Purpose I/O pins can be shared with other function pins; it depends on the chip
configuration. These 86 pins are arranged in 6 ports named with GPIOA, GPIOB, GPIOC,
GPIOD, GPIOE and GPIOF. Ports A ~ E have the maximum of 16 pins while port F have 6 pins.
Each one of the 86 pins is independent and has the corresponding register bits to control the pin
mode function and data.
The I/O type of each of I/O pins can be independently software configured as input, output, and
open-drain mode. Each I/O pin has a very weak individual pull-up resistor which is about 110
K~300 K for VDD from 1.8 V to 3.6 V.
5.10.2 Features
 Up to 86 general purpose I/O pins
 Supports Input, Output, Open-drain Operation mode
 Programmable de-bounce timing
 Each I/O pin can be programmed as either edge-trigger or level-sensitive
 Each I/O pin can be programmed as either low-level active or high-level active
 Each I/O pin can be programmed as either falling-edge trigger or rising-edge trigger

5.11 I2C
5.11.1 Overview
2
I C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
2
exchange between devices. The I C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously. Serial, 8-bit oriented bi-directional data transfers can be made up to 1.0
Mbps.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a
byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock pulse for each data bit
with the MSB being transmitted first. An acknowledge bit follows each transferred byte.
A transition on the SDA line while SCL is high is interpreted as a command (START or STOP).
Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only
during the low period of SCL and must be held stable during the high period of SCL.
2 2
The controller’s on-chip I C logic provides the serial interface that meets the I C bus standard
2
mode specification. The I C controller handles byte transfers autonomously. Pull up resistor is
2
needed for I C operation as these are open drain pins.
2
The I C controller is equipped with two slave address registers. The contents of the registers are
2
irrelevant when I C is in Master mode. In the Slave mode, the seven most significant bits must be
2
loaded with the user’s own slave address. The I C hardware will react if the contents of I2CADDR
are matched with the received slave address.
This controller supports the “General Call (GC)” function. If the GC bit is set this controller will
respond to General Call address (00H). Clear GC bit to disable general call function. When GC bit
2
is set and the I C is in Slave mode, it can receive the general call address which is equal to 00H
2
after master sends general call address to the I C bus, then it will follow status of GC mode. If it is
2
in Master mode, the ACK bit must be cleared when it sends general call address of 00H to the I C
bus.
2
The I C-bus controller supports multiple address recognition with two address mask register.

When the bit in the address mask register is set to one, it means the received corresponding
address bit is don’t-care. If the bit is set to zero, that means the received corresponding register
bit should be exact the same as address register.

5.11.2 Features
 Acts as Master or Slave mode
 Bidirectional data transfer between masters and slaves
 Multi-master bus (no central master)
 Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
 Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
 Serial clock synchronization can be used as a handshake mechanism to suspend and
2 2
 One built-in 14-bit time-out counter requesting the I C interrupt if the I C bus hangs up
and timer-out counter overflows.
 Programmable clock divider allows versatile rate control
 Supports 7-bit addressing mode
 Supports multiple address recognition ( Two slave addresses with mask option)
 Supports Power-down wake-up function

5.12 I2S
5.12.1 Overview
2
The audio controller consists of I S protocol to interface with external audio CODEC. Two 8 word
deep FIFO for receiving path and transmitting path respectively and is capable of handling 8 ~ 32
bit word sizes. PDMA controller handles the data movement between FIFO and memory.
5.12.2 Features

2
I S can operate as either master or Slave mode.
 Capable of handling 8, 16, 24 and 32 bits word sizes.
 Mono and stereo of audio data are supported.

2
I S and MSB justified data format are supported.
 Two FIFO data buffers (each 32 bits) are provided, one is for transmitting and the other is for
receiving.
 Generate interrupt when buffer levels cross a programmable boundary.
 Two PDMA channels request, one is for transmitting and the other is for receiving.

5.13 LCD Display Driver
5.13.1 Overview
The LCD driver can directly drive a LCD glass by creating the ac segment and common voltage
signals automatically. It can support static, 1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty and 1/6 duty LCD
glass with up to 38 segments with 6 COM (segment 0 is used as LCD_COM4 and segment 1 is used
as LCD_COM5) or 40 segments with 4 COM (LCD_COM0 ~ LCD_COM3).
A built-in charge pump function can be enabled to provide the LCD glass with higher voltage than the
system voltage. The LCD driver would generate voltage higher than the threshold voltage in older to
darken a segment and a voltage lower than threshold to make a segment clear. However, the LCD
display segment will degrade if the applied voltage has a DC-component. To avoid this, the generated
waveform by LCD driver are arranged such that average voltage of each segment is zero and the
RMS(root-mean-square) voltage applied on a LCD segment lower than the segment threshold making
LCD clear and RMS voltage higher than the segment threshold making LCD dark.
Note : Output voltage for ADC/LCD shared pins cannot be higher than VDD because these pins are
without 5V tolerance.
(LQFP64 : LCD_SEG17, LCD_SEG19, LCD_SEG20, LCD_SEG21, LCD_SEG22, LCD_SEG23)
(LQFP128 : LCD_SEG36, LCD_SEG37, LCD_SEG38, LCD_SEG39)
5.13.2 Features
 Supports up to 174 dots (6x29) or 124 dots (4x31) in LQFP64 package and 228 dots
(6x38) or 160 dots (4x40) in LQFP100/LQFP128 package Segment/Com pins:
 Common 0-5 multiplexing functions with GPI/O pins
 Segment 0-39 multiplexing function with GPI/O pins
 Supports Static,1/2 bias and 1/3 bias voltage
 Six display modes: Static,1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty or 1/6 duty Selectable
LCD frequency by frequency divider

 Configurable frame frequency
 Internal Charge pump, adjustable contrast adjustment
 Embedded LCD bias reference ladder (R-Type, 200kΩ resisters)
 Configurable Charge pump frequency
 Blinking capability
 Supports R/C-type method
 LCD frame interrupt

5.14 Pulse Width Modulation (PWM)
5.14.1 Overview
This chip has two PWM controllers, each controller has 4 independent PWM outputs, CH0~CH3,
or as 2 complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2 programmable dead-zone
generators.
Each two PWM outputs, (CH0, CH1), (CH2, CH3), share the same 8-bit prescaler, clock divider
providing 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16). Each PWM output has independent 16-bit
PWM down-count counter for PWM period control, and 16-bit comparators for PWM duty control.
Each dead-zone generator has two outputs. The first dead-zone generator output is CH0 and
CH1, and for the second dead-zone generator, the output is CH2 and CH3. The 2 sets of PWM
controller total provide eight independent PWM interrupt flags which are set by hardware when
the corresponding PWM period down counter reaches zero. PWM interrupt will be asserted when
both PWM interrupt source and its corresponding enable bit are active. Each PWM output can be
configured as one-shot mode to produce only one PWM cycle signal or continuous mode to
output PWM waveform continuously.
When DZEN01 of PWMx_CTL is set, CH0 and CH1 perform complementary PWM paired
function; the paired PWM timing, period, duty and dead-time are determined by PWM channel 0
timer and Dead-zone generator 0. Similarly, When DZEN23 of PWMx_CTL is set the
complementary PWM pair of (CH2, CH3) is controlled by PWM channel 2.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers the updated value will be loaded into the 16-bit down counter/
comparator at the time down counter reaching zero. The double buffering feature avoids glitch at
PWM outputs.
When the 16-bit period down counter reaches zero, the interrupt request is generated. If PWM
output is set as continuous mode, when the down counter reaches zero, it is reloaded with CN of
PWMx_DUTYy(y=0~3) Register automatically then start decreases, repeatedly. If the PWM
output is set as one-shot mode, the down counter will stop and generate one interrupt request
when it reaches zero.

The value of PWM counter comparator is used for pulse width modulation. The counter control
logic changes the output level when down-counter value matches the value of compare register.
The alternate feature of the PWM is digital input capture function. If capture function is enabled
the PWM output pin is switched as capture input pin. The capture channel 0 and PWM CH0 share
one timer; and the capture channel 1 and PWM CH1 share one timer, and etc. Therefore user
must setup the PWM timer before enabling capture feature. After capture feature is enabled, the
capture always latches PWM timer to Capture Rising Latch Register (PWMx_CRLy) where
y=0~3, when input channel has a rising transition and latches PWM timer to Capture Falling Latch
Register (PWMx_CFLy) where y=0~3, when input channel has a falling transition. Capture
channel 0 interrupt is programmable by setting PWMx_CAPINTEN. Whenever Capture event
latched for channel 0/1/2/3, the PWM timer 0/1/2/3 will be reload at this moment if the
corresponding reload enable bit specified in CAPCTL are set.
The maximum captured frequency that PWM can capture is dominated by the capture interrupt
latency. When capture interrupt occurs, software will do at least three steps, they are:
Read PWMINTSTS to tell it from interrupt source and Read PWMx_CRLy/PWMx_CFLy(y=0~3) to
get capture value and finally write 1 to clear PWMx_INTSTS. If interrupt latency will take time T0
to finish, the capture signal mustn’t transient during this interval. In this case, the maximum
capture frequency will be 1/T0.

5.14.2 Features
5.14.2.1 PWM Function:

 Two PWM controllers, each controller having 4 independent PWM outputs,
CH0~CH3, or as 2 complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2
programmable dead-zone generators
 Up to 8 PWM channels or 4 PWM paired channels
 Up to 16 bits PWM counter width
 PWM Interrupt request synchronous with PWM period
 Single-shot or Continuous mode
 Four Dead-Zone generators
5.14.2.2 Capture Function:

 Timing control logic shared with PWM timer.
 8 Capture input channels shared with 8 PWM output channels.
 Each channel supports one rising latch register (PWMx_CRLy), one falling latch
register (PWMx_CFLy) and Capture interrupt flag (CAPIFy) where x=0~1,y=0~3.
 Eight 16-bit counters for eight capture channels or four 32-bit counter for four capture
channels when cascade is enabled: when CH01CASKEN is set, the original 16-bit
counter of channel 1 will combine with channel 0’s 16 bit counter for channel 0 input
capture counting and so does CH23CASKEN for channel 2, 3
 Supports PDMA transfer function for PWMx channel 0, 2

5.15 RTC
5.15.1 Overview
Real Time Clock (RTC) unit provides user the real time and calendar message. The Clock Source
of RTC is from an external 32.768 kHz crystal connected at pins X32I and X32O (reference to pin
Description) or from an external 32.768 kHz oscillator output fed at pin X32I. The RTC unit
provides the time message (second, minute, hour) in Time Loading Register (TLR) as well as
calendar message (day, month, year) in Calendar Loading Register (CLR). The data message is
expressed in BCD format. This unit offers alarm function that user can preset the alarm time in
Time Alarm Register (TAR) and alarm calendar in Calendar Alarm Register (CAR).
The RTC unit supports periodic Time Tick and Alarm Match interrupts. The periodic interrupt has
8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by TTR
(TTR[2:0]). When RTC counter in TLR and CLR is equal to alarm setting time registers TAR and
CAR, the alarm interrupt status (RIIR.AIS) is set and the alarm interrupt is requested if the alarm
interrupt is enabled (RIER.AIER=1). The RTC Time Tick (if wake-up CPU function is enabled,
RTC_TTR[TWKE] high) and Alarm Match can cause CPU wake-up from idle or Power-down
mode.
5.15.2 Features
 One time counter (second, minute, hour) and calendar counter (day, month, year) for
user to check the time
 Alarm register (second, minute, hour, day, month, year)
 12-hour or 24-hour mode is selectable
 Leap year compensation automatically
 Day of week counter
 Frequency compensate register (FCR)
 All time and calendar message is expressed in BCD code

 Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
 Supports RTC Time Tick and Alarm Match interrupt
 Supports wake-up CPU from Power-down mode
 Supports 80 bytes spare registers and a snoop pin to clear the content of these spare
registers
5.16 Smart Card Host Interface (SC)
5.16.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal.
5.16.2 Features
 ISO-7816-3 T = 0, T = 1 compliant
 EMV2000 compliant
 Supports up to three ISO-7816-3 ports
 Separates receive / transmit 4 byte entry buffer for data payloads
 Programmable transmission clock frequency
 Programmable receiver buffer trigger level

 Programmable guard time selection (11 ETU ~ 266 ETU)
 A 24-bit and two 8-bit counters for Answer to Reset (ATR) and waiting times
processing
 Supports auto inverse convention function
 Supports stop clock level and clock stop (clock keep) function
 Supports transmitter and receiver error retry and error number limitation function
 Supports hardware activation sequence process
 Supports hardware warm reset sequence process
 Supports hardware deactivation sequence process
 Supports hardware auto deactivation sequence when detected the card removal.
 Support UART mode
 Half duplex, asynchronous communications
 Separate receiving / transmitting 4 bytes entry FIFO for data payloads
 Support programmable baud rate generator for each channel
 Support programmable receiver buffer trigger level
 Programmable transmitting data delay time between the last stop bit leaving the
TX-FIFO and the de-assertion by setting SCx_EGTR [EGT] register
 Programmable even, odd or no parity bit generation and detection
 Programmable stop bit, 1 or 2 stop bit generation

5.17 SPI
5.17.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol.
Devices communicate in Master/Slave mode with 4-wire bi-direction interface. It is used to
perform a serial-to-parallel conversion on data received from a peripheral device, and a parallel-
to-serial conversion on data transmitted to a peripheral device. The SPI controller can be
configured as a master or a slave devicee.
The SPI controller supports wake-up function. When this chip stays in power-down mode, it can
be waked up chip by off-chip device.
This controller supports variable serial clock function for special application and 2-bit transfer
mode to connect 2 off-chip slave devices at the same time. The SPI controller also supports
PDMA function to access the data buffer.
5.17.2 Features
 Supports Master (max. 32 MHz) or Slave (max. 16 MHz) mode operation
 Supports 1 bit and 2 bit transfer mode
 Support Dual IO transfer mode
 Configurable bit length of a transaction from 8 to 32-bit
 Supports MSB first or LSB first transfer sequence
 Two slave select lines supported in Master mode
 Configurable byte or word suspend mode
 Supports byte re-ordering function
 Supports variable serial clock in Master mode
 Provide separate 8-level depth transmit and receive FIFO buffer

 Supports wake-up function
 Supports PDMA transfer
 Supports three wires, no slave select signal, bi-direction interface

5.18 Timer Controller
5.18.1 Overview
This chip is equipped with four timer modules including TIMER0, TIMER1, TIMER2 and TIMER3
(TIMER0/1 is at APB1 and TIMER2/3 is at APB2), which allow user to easily implement a
counting scheme or timing control for applications. The timer can perform functions like frequency
measurement, event counting, interval measurement, clock generation, delay timing, and so on.
The timer can generate an interrupt signal upon timeout, or provide the current value of count
during operation.
5.18.2 Features
 Independent Clock Source for each Timer (TMRx_CLK, x= 0, 1,2,3)
 Time-out period = (Period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit
TCMP)
 Counting cycle time = (1 / TMRx_CLK) * (2^8) * (2^24)
 Internal 8-bit pre-scale counter
 Internal 24-bit up counter is readable through TDR (Timer Data Register)
 Supports One-shot, Periodic,Output Toggle and Countinuous Counting Operation
mode
 Supports external pin capture for interval measurement
 Supports external pin capture for timer counter reset
 Supports Inter-Timer trigger
 Supports Internal trigger event to ADC, DAC and PDMA

5.19 UART Controller
5.19.1 Overview
The UART controllers provides up to two channels of Universal Asynchronous
Receiver/Transmitter (UART) modules that are UART0 and UART1. (UART0 is at APB1 and
UART1 is at APB2).
The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel
conversion on data received from the peripheral, and a parallel-to-serial conversion on data
transmitted from the CPU. The UART controller also supports IrDA (SIR) function mode, LIN
Master/Slave function mode and RS-485 function mode. Each UART channel supports nine types
of interrupts including receiver threshold level reaching interrupt (INT_RDA), transmitter FIFO
empty interrupt (INT_THRE), line status interrupt (break error, parity error, framing error or RS-
485 interrupt) (INT_RLS), time-out interrupt (INT_TOUT), MODEM status interrupt
(INT_MODEM), Buffer error interrupt (INT_BUF_ERR), wake-up interrupt (INT_WAKE), auto-
baud rate detect or auto-baud rate counter overflow flag (INT_ABAUD) and LIN function interrupt
(INT_LIN).
The UART0 and UART1 are built-in with a 16-byte transmitter FIFO (TX_FIFO) and a 16-byte
receiver FIFO (RX_FIFO) that reduces the number of interrupts presented to the CPU. The CPU
can read the status of the UART at any time during the operation. The reported status information
includes the type and condition of the transfer operations being performed by the UART, as well
as 3 error conditions (parity error, framing error or break interrupt) occur while receiving data. The
UART controller supports auto-baud rate detection. The auto-baud rate detection controls the
process of measuring the incoming clock/data rate for the baud rate generation and can be read
and written at user discretion. The UART controller also support incoming data or CTSn wake-up
function. When the system is in power-down mode, an incoming data or CTSn signal will wake-up
CPU from power-down mode. The UART includes a programmable baud rate generator that is
capable of dividing crystal clock input by divisors to produce the clock that transmitter and
receiver need. The baud rate equation is Baud Rate = UART_CLK / [BRD + 1], where BRD are
defined in UART Baud Rate Divider Register (UARTx_BAUD). Below table lists the equations in
the various conditions and the UART baud rate setting table.

DIV_16_EN BRD Baud Rate Equation
Disable (Mode 0) A UART_CLK / (A+1), A must >8
Enable (Mode 1) A UART_CLK / [16 * (A+1)]
Table 5‑1 UART Baud Rate Equation
System clock =12 MHz
Baud rate Mode 0 Mode 1
921600 A=12 Not Supported
460800 A=25 Not Supported
230400 A=51 A=2
115200 A=103 A=6
57600 A=207 A=12
38400 A=311 A=19

19200 A=624 A=38
9600 A=1249 A=77
4800 A=2499 A=155
Table 5‑2 UART Baud Rate Setting
5.19.1.1 Auto-Flow Control

The UART0 and UART1 controllers support auto-flow control function that uses two low-level
signals, CTSn (clear-to-send) and RTSn (request-to-send) to control the flow of data transfer
between the UART and external devices (ex: Modem). When auto-flow is enabled, the UART is
not allowed to receive data until the UART asserts RTSn (RTSn high) to external device. When
the number of bytes in the RX-FIFO equals the value of UART_TLCTL [RTS_TRI_LEV], the
RTSn is de-asserted. The UART sends data out when UART controller detects CTSn is asserted
(CTSn high) from external device. If a valid asserted CTSn is not detected the UART controller
will not send data out.
5.19.1.2 Auto-Baud Rate Detection

The UART0 and UART1 controllers support auto-baud rate detection. The auto-baud rate function
can be used to measure the receiver incoming data baud rate. If enabled the auto-baud feature,
UART controller will measure the bit time of the received data stream and set the divisor latch
registers UART_BARD. Auto-baud rate detection is started by setting the UART_CTL
[ABAUD_EN].
5.19.1.3 UART Wake-Up Function

The UART0 and UART1 controllers support wake-up system function. The wake-up function
includes CTSn wake-up function (UART_CTL [WAKE_CTS_EN]) and data wake-up function
(UART_CTL [WAKE_DATA_EN]). When the system is operation in power-down mode, the UART
can wake-up system by CTSn pin or by incoming data.
5.19.1.4 IrDA Function Mode

The UART controllers also provides Serial IrDA (SIR, Serial Infrared) function (User must set
UART_FUN_SEL to select IrDA function). The SIR specification defines a short-range infrared
asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop bit. The
maximum data rate is 115.2 Kbps (half duplex). The IrDA SIR block contains an IrDA SIR
Protocol encoder/decoder. The IrDA SIR protocol is half-duplex only. So it cannot transmit and
receive data at the same time. The IrDA SIR physical layer specifies a minimum 10 ms transfer
delay between transmission and reception, and in IrDA Operation mode the UART_BAUD setting
must be mode1 (UART_BAUD [DIV_16_EN] = “1”).
5.19.1.5 RS-485 Function Mode

Another alternate function of UART controllers is RS-485 9 bit mode function whose direction
control can be controlled by RTSn pin or GPIO. The RS-485 function mode is selected by setting
the UART_FUN_SEL register to select RS-485 function. The RS-485 driver control is
implemented by using the RTSn control signal from an asynchronous serial port to enable the RS-
485 driver. In RS-485 mode, many characteristics of the RX and TX are same as UART.
5.19.1.6 LIN Function Mode
5.19.2 The LIN mode is selected by setting the LIN_EN bit in UART_FUN_SEL register. In
LIN mode, one start bit and 8-bit data format with 1-bit stop bit are required in
accordance with the LIN standard. Features
 Full duplex, asynchronous communications.

 Separate receiving / transmitting 16 bytes entry FIFO for data payloads.

 Supports hardware auto-flow control/flow control function (CTSn, RTSn) and
programmable (CTSn, RTSn) flow control trigger level.
 Supports programmable baud rate generator for each channel.
 Supports auto-baud rate detect function.
 Supports programmable receiver buffer trigger level.
 Supports incoming data or CTSn to wake-up function.
 Supports 9 bit receiver buffer time-out detection function.
 All UART channels can be served by the PDMA controller.
 Programmable transmitting data delay time between the last stop bit leaving the TX-
FIFO and the de-assertion by setting UART_TMCTL [DLY] register.
 Supports break error, frame error, parity error and receiving / transmitting buffer
overflow detect function.
 Fully programmable serial-interface characteristics:
 Programmable number of data bit, 5, 6, 7, 8 character.
 Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection.
 Programmable stop bit, 1, 1.5, or 2 stop bit generation.
 Supports IrDA SIR function mode
 Supports 3/16 bit period modulation.
 Supports LIN function mode.
 Supports LIN Master/Slave mode
 Supports programmable break generation function for transmitter.

 Supports break detect function for receiver.
 Supports RS-485 function mode.
 Supports RS-485 9bit mode.
 Supports hardware or software controls RTSn or software control GPIO to
control transfer direction.

5.20 USB
5.20.1 Overview
The USB controller is a USB 2.0 full-speed device controller. It is compliant with USB 2.0 full
speed device specification and supports control/bulk/interrupt/isochronous transfer types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There is an internal 512-byte SRAM as data buffer in this controller. For IN token or OUT token
transfer, it is necessary to write data to SRAM or read data from SRAM through the APB
interface. Users need to allocate the effective starting address of SRAM for each endpoint buffer
through “buffer segmentation register (BUFSEG)”.
This device controller contains 8 configurable endpoints. Each endpoint can be configured as IN
or OUT endpoint. The function address of the device and endpoint number in each endpoint shall
be configured properly in advance for receiving or transmitting a data packet correctly. The
transmitting/receiving length in each endpoint is defined in maximum payload register (MXPLD)
and the handshakes between Host and Device are also handled by it.
There are four different interrupt events in this controller. They are the wake-up function, device
plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend
and resume, etc. Any event will cause an interrupt, and users just need to check the related event
flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of events
occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disable function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables the DRVSE0 bit (USB_CTL[4]), the
USB controller will force USB_DP and USB_DM to level low and USB device function is disabled
(disconnected). After disable the DRVSE0 bit, USB_DP will be pulled high by internal pull-high
circuit then host will enumerate the USB device connection again.
Reference: Universal Serial Bus Specification Revision 2.0
5.20.2 Features
This Universal Serial Bus (USB) performs a serial interface with a single connector type for
attaching all USB peripherals to the host system. Following is the feature listing of this USB.
 Compliant with USB 2.0 Full-Speed specification.
 Provide 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB
and BUS).
 Supports Control/Bulk/Interrupt/Isochronous transfer type.
 Supports suspend function when no bus activity existing for 3 ms.
 Provide 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
 512-byte SRAM buffer inside
 Provide remote wake-up capability.

5.21 Watchdog Timer Controller
5.21.1 Overview
The purpose of Watchdog Timer is to perform a system reset after the software running into a
problem. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports the function to wake-up CPU from power-down mode. The watchdog timer
includes an 18-bit free running counter with programmable time-out intervals.
5.21.2 Features
 18-bit free running WDT counter for Watchdog timer time-out interval.
 Selectable time-out interval (2^4 ~ 2^18) and the time-out interval is 104 ms ~ 26.316
s (if WDT_CLK = 10 kHz).
 Reset period = (1 / 10 kHz) * 63, if WDT_CLK = 10 kHz.

5.22 Window Watchdog Timer Controller
5.22.1 Overview
The purpose of Window Watchdog Timer is to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.
5.22.2 Features
 6-bit down counter and 6-bit compare value to make the window period flexible
 Selectable WWDT clock pre-scale counter to make WWDT time-out interval variable

6 ARM® CORTEX™-M0 CORE
6.1 Overview
The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA
AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex-M
profile processor. The profile supports two modes – Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
The following figure shows the functional controller of processor.
Cortex-M 0 components
Cortex-M 0 processor Debug
Interrupts Nested
Breakpoint
Vectored Cortex-M0
and
Interrupt Processor
Watchpoint
Controller Core
Unit
( NVIC)
Wakeup Debug
Interrupt Access
Debugger Port
Controller Bus Matrix
interface ( DAP)
( WIC)
AHB- Lite Serial Wire or

interface JTAG debug port
Figure 6‑1 M0 Functional Block

6.2 Features
 A low gate count processor:
®
 ARMv6-M Thumb instruction set
 Thumb-2 technology
 ARMv6-M compliant 24-bit SysTick timer
 A 32-bit hardware multiplier
 Supports little-endian data accesses
 Capable of deterministic, fixed-latency, interrupt handling
 Load/store-multiples and multi-cycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
 C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
 Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or return from interrupt sleep-on-exit feature
 NVIC:
 32 external interrupt inputs, each with four levels of priority

 Dedicated Non-Maskable Interrupt (NMI) input

 Supports for both level-sensitive and pulse-sensitive interrupt lines
 Wake-up Interrupt Controller (WIC), providing Ultra-low Power Sleep mode
support
 Debug support:
 Four hardware breakpoints
 Two watch points
 Program Counter Sampling Register (PCSR) for non-intrusive code profiling
 Single step and vector catch capabilities
 Bus interfaces:
 Single 32-bit AMBA-3 AHB-Lite system interface providing simple integration to
all system peripherals and memory
 Single 32-bit slave port that supports the DAP (Debug Access Port)

7 APPLICATION CIRCUIT
7.1 LCD Charge Pump
7.1.1 C-type 1/3 Bias
DH VLC
1 D
0.1uF 0.1uF
DH NANO130 V3
2 0.1uF
V2
0.1uF
V1
0.1uF
7.1.2 C-type 1/2 Bias

DH VLC
0.1uF 1 D 0.1uF
DH NANO130 V3 0.1uF
2
V2 0.1uF
V1 0.1uF
7.1.3 Internal R-type

Nano110/130 series MCUs also support external R-type mode (bypass internal R) to reduce
current consumption. For external R-type application, VLCD is normally connected to system
VDD, or it can be connected to VDD through an external variable resistor (VR) which is used for
adjusting LCD contrast.

VDD
VR
VLCD
DH1
200k
NANO110 V3
DH2
NANO130 200k
V2
200k
V1
7.1.4 External R-type

To reduce the current, the resistor ladder value can be increased. At some point, when the
resistor ladder value is increased, the contrast will become affected and the waveform shape will
be altered. Therefore, capacitors around 0.1uF should be chosen and place closed to resistor
ladder based on the contrast and size of the pixels on the glass.
VDD
VR
DH1 VLCD
R1
NANO110 V3
DH2
NANO130 R2
V2
R3
V1

VDD
VR
DH1 VLCD
R1 0.1uF
NANO110 V3
DH2
NANO130 R2 0.1uF
V2
R3 0.1uF
V1
7.2 ADC Application Circuit
7.2.1 Voltage Reference Source
7.2.1.1 AVDD
NANO100
AD0
AVDD AD1
AVDD AD2

M ADC Vref
In Case U AD3
1uF // 0.1F
VREF = AVDD X AD4
VREF AD5
VREF REFSEL[1:0]
EXT_MODE=0 AD6
AD7
1uF // 0.1uF
Int Vref AD8
AD9
AVSS REFSEL[1:0] of ADCR AD10
AVSS 00 AVDD as Voltage reference
01 Int. Vref as Voltage reference
AD11
10 Ext. VREF pin as Voltage reference
11 Reserve

7.2.1.2 Vref Pin
NANO100
AD0
AVDD AD1
AVDD M ADC Vref AD2
In Case U AD3
1uF // 0.1uF
VREF = AVDD X AD4
VREF AD5
VREF REFSEL[1:0]
AD6
EXT_MODE=0
AD7
1uF // 0.1uF
Int Vref AD8
AD9
AVSS AVSS REFSEL[1:0] of ADCR AD10
00 AVDD as Voltage reference
AD11
11 Reserve
7.2.1.3 Int Vref
NANO100
AD0
AVDD AD1
AVDD M ADC Vref AD2
In Case U AD3
1uF // 0.1uF
VREF = AVDD X AD4
VREF AD5
VREF REFSEL[1:0]
AD6
EXT_MODE=1
AD7
1uF // 0.1uF
Int Vref AD8
AD9
AVSS REFSEL[1:0] of ADCR AD10
AVSS 00 AVDD as Voltage reference
AD11
11 Reserve

7.3 DAC Application Circuit
7.3.1 Voltage Reference Source
7.3.1.1 AVDD
NANO100
AVDD
AVDD M
DAC Vref
In Case U
1uF // 0.1uF DAC1_out
VREF = AVDD X
VREF REFSEL[1:0]
VREF EXT_MODE=0
DAC2_out
1uF // 0.1uF
Int Vref
AVSS REFSEL[1:0] of DAC

AVSS 00 Int. Vref as Voltage reference
7.3.1.2 Vref Pin
NANO100
AVDD

AVDD M
DAC Vref
In Case U
VREF = AVDD X
VREF
VREF EXT_MODE=0
REFSEL[1:0]
DAC2_out
1uF // 0.1uF
Int Vref


7.3.1.3 Int Vref
NANO100
AVDD
AVDD M
DAC Vref
In Case U
VREF = AVDD X
VREF
VREF EXT_MODE=1
REFSEL[1:0]
DAC2_out
1uF // 0.1uF
Int Vref


7.4 Whole Chip Application Circuit

DVDD
R1
10K
SW1 0603R
TICE_RST
DVDD DVDD
SW C1
PUSH BUTTON 10uF/10V
TANT-A
CB3 C15 CB4
0.1uF 1uF 0.1uF
TICE_RST
C0603 C0603 C0603
XTAL2
XTAL1
Reset Circuit C13 C14
PIN128
PIN127
PIN126
PIN125
PIN124
PIN123
PIN122
PIN121
PIN120
PIN119
PIN118
PIN117
PIN116
PIN115
PIN114
PIN113
PIN112
PIN111
PIN110
PIN109
PIN108
PIN107
PIN106
PIN105
PIN104
PIN103
PIN102
PIN101
PIN100
PIN99
PIN98
PIN97
0.1uF 1uF
C0603 C0603
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
From ICE Bridge's USB Power
99
98
97
U1
PE.14
PE.15
PB.8
PVSS
VSS
PF.5
PF.4
VSS
VSS
XT1_In
PB.15
PC.14
PC.15
PC.6
PC.7
PD.5
PD.4
PD.3
PD.2
PD.1
PD.0
NC
VDD
NC
RESET
NC
XT1_Out
NC
NC
NC
AVDD
VREF
DVDD
JP4
1 2 TICE_DAT
3 4 TICE_CLK PIN1 1 96 PIN96
5 6 TICE_RST PIN2 2 PE.13 PA.7 95 PIN95
7 8 PIN3 3 PB.14 PA.6 94 PIN94
9 10 PIN4 4 PB.13 PA.5 93 PIN93
HEADER 5PX2 PIN5 5 PB.12 PA.4 92 PIN92
HEADER 5PX2 X32KO PIN6 6 NC PA.3 91 PIN91
X32KI PIN7 7 X32O PA.2 90 PIN90
PIN8 8 X32I PA.1 89 PIN89
PIN9 9 NC PA.0 88 PIN88
PA.11 AVSS
ICE Interface
PIN10 10 87 PIN87
PIN11 11 PA.10 AVSS 86 PIN86
PIN12 12 PA.9 VSS 85 PIN85 DVDD
PIN13 13 PA.8 VSS 84 PIN84
PIN14 14 PD.8 NC 83 PIN83
PIN15 15 PD.9 VDD 82 PIN82
PIN16 16 PD.10 NC 81 PIN81 TICE_CLK
PIN17 17 PD.11 NANO130_LQFP128 ICE_CK/PF.1 80 PIN80 TICE_DAT
PIN18 18 PD.12 ICE_DAT/PF.0 79 PIN79
PIN19 19 PD.13 PA.12 78 PIN78 DVDD
DVDD PIN20 20 PB.4 PA.13 77 PIN77
PIN21 21 PB.5 PA.14 76 PIN76
PIN22 22 PB.6 PA.15 75 PIN75 CB5
C2 PIN23 23 PB.7 PC.8 74 PIN74 0.1uF
C3 R2 PIN24 24 NC PC.9 73 PIN73 C0603
XTAL2 PIN25 25 LDO PC.10 72 PIN72
10uF/10V PIN26 26 NC PC.11 71 PIN71
20pF X2 33 TANT-A PIN27 27 NC PC.12 70 PIN70
0603C 12MHz R4 0603R PIN28 28 VDD PC.13 69 PIN69
XTAL3-1 1M/DNE PIN29 29 NC PE.0 68 PIN68
0603R PIN30 30 VSS PE.1 67 PIN67
C5 PIN31 31 VSS PE.2 66 PIN66
XTAL1 PIN32 32 VSS PE.3 65 PIN65
VSS PE.4
20pF
USB_DM
USB_DP
0603C
VDD33
PD.14
PD.15
PE.12
PE.11
PE.10
VBUS
PB.11
PB.10
VLCD
PD.6
PD.7
PC.5
PC.4
PC.3
PC.2
PC.1
PC.0
PE.9
PE.8
PE.7
PB.0
PB.1
PB.2
PB.3
PE.6
PE.5
PB.9
NC
NC
DVDD
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
C7 CB2
X32KO 0.1uF
C0603
PIN33
PIN34
PIN35
PIN36
PIN37
PIN38
PIN39
PIN40
PIN41
PIN42
PIN43
PIN44
PIN45
PIN46
PIN47
PIN48
PIN49
PIN50
PIN51
PIN52
PIN53
PIN54
PIN55
PIN56
PIN57
PIN58
PIN59
PIN60
PIN61
PIN62
PIN63
PIN64
6pF X1
0603C 32.768KHz
XTAL3-1
C8
X32KI
C12 C9 C10
6pF 1uF 0.1uF 1uF
0603C C0603 C0603 C0603
Crystal

8 POWER COMSUMPTION
Part No Test Condition VDD CPU Clock Current
2.41mA
Operating Mode: 3.3V 12 MHz
200uA/MHz
CPU run while(1) in FLASH ROM
Clock = 12 MHz Crystal Oscillator
Disable all peripherial 1.8V 12 MHz N/A
900uA
Idle Mode: 3.3V 12 MHz
75uA/MHz
CPU stop
Disable all peripherial 1.8V 12 MHz N/A
RTC + LCD Mode: C-type 10uA

(RAM retention)
(Power down with 32K Internal R-type
and LCD enabled) ( With 200kΩ 3.3V - 8.5uA
CPU stop Resistor ladder )
Clock = 32.768 kHz
Nano100 (B) Crystal Oscillator External R-type
series Disable all peripherial ( With 1MΩ 4.5uA
128 KB Flash except RTC and LCD Resistor ladder )
16 KB RAM circuit
Without panel loading C-type/R-type 1.8V - N/A
RTC Mode: (RAM retention) 3.3V - 2.5uA

(Power down with 32K enabled)
CPU stop
Clock = 32.768 kHz Crystal Oscillator
Disable all peripherial except RTC circuit 1.8V - 2.0uA
3.3V - 1uA
Power-down Mode: (RAM retention)
CPU and all clocks stop
1.8V - 0.8uA
Wake-Up from Power-down Mode 3.3V 7us N/A
Note: Wake-up time: 7us from wake-up event to first CPU core valid clock; 10us from interrupt event
to interrupt service routine first instruction.

9 ELECTRICAL CHARACTERISTIC
9.1 Absolute Maximum Ratings
SYMBOL PARAMETER MIN MAX UNIT
DC Power Supply VDDVSS -0.3 +4.0 V
Input Voltage on 5V Tolerance Pin VIN VSS -0.3 VDD +3.7 V
Input Voltage on Any Other Pin without 5V

VIN VSS -0.3 VDD +0.3 V
Tolerance Pin
Oscillator Frequency 1/tCLCL 4 24 MHz
Operating Temperature TA -40 +85 C
Storage Temperature TST -55 +150 C
Maximum Current into VDD - 150 mA
Maximum Current out of VSS - 150 mA
Maximum Current sunk by a I/O Pin - 25 mA
Maximum Current Sourced by a I/O Pin - 25 mA
Maximum Current Sunk by Total I/O Pins - 100 mA
Maximum Current Sourced by Total I/O Pins - 100 mA
Note : Output voltage for ADC/LCD shared pins cannot be higher than VDD because these pins are
without 5V tolerance.

(LQFP64 : LCD_SEG17, LCD_SEG19, LCD_SEG20, LCD_SEG21, LCD_SEG22, LCD_SEG23)
(LQFP128 : LCD_SEG36, LCD_SEG37, LCD_SEG38, LCD_SEG39)
9.2 Nano100/Nano110/Nano120/Nano130 DC Electrical Characteristics

(VDD-VSS=3.3V, TA = 25C, FOSC = 32 MHz unless otherwise specified.)
SPECIFICATIONS
PARAMETER SYM. TEST CONDITIONS
MIN. TYP. MAX. UNIT
Operation voltage VDD 1.8 - 3.6 V VDD =1.8V up to 42 MHz
VSS
Power Ground -0.3 - V
AVSS
VLDO1 1.62 1.8 1.98 V MCU operating in Run or Idle mode

LDO Output Voltage
VLDO2 1.49 1.66 1.83 V MCU operating in Power-down mode

SPECIFICATIONS
MIN. TYP. MAX. UNIT
Analog Operating
AVDD VDD V
Voltage
Reference Voltage Vref 1.8 AVDD V
Run Mode
CPU run while(1) in FLASH ROM
at IRC = 12 MHz
Crystal Oscillator
Disable all peripherial
Disable all peripherial
VDD = 3.6V at 42 MHz,

IDD1 20.5 mA [*5]
all IP and PLL enabled
Operating Current VDD = 3.6V at 42 MHz

IDD2 10.6 mA
Run Mode all IP disabled and PLL enabled
at XTAL 12 MHz, VDD = 1.8V at 42 MHz
IDD3 19.1 mA [*5]
HCLK = 42 MHz all IP and PLL enabled
VDD = 1.8V at 42 MHz

IDD4 10.3 mA
all IP disabled and PLL enabled

IDD5 16.2 mA [*5]
Operating Current VDD = 3.6V at 32 MHz

IDD6 8.3 mA
Run Mode all IP disabled and PLL enabled
at XTAL 12 MHz, VDD = 1.8V at 32 MHz
IDD7 15.3 mA [*5]

IDD8 8.0 mA

IDD9 6.4 mA
all IP enabled and PLL disabled
Operating Current VDD = 3.6V at 12 MHz,

IDD10 2.8 mA
Run Mode all IP and PLL disabled
at XTAL 12 MHz, VDD = 1.8V at 12 MHz,
IDD11 6.3 mA
HCLK = 12 MHz all IP enabled and PLL disabled

IDD12 2.8 mA
all IP and PLL disabled

IDD13 6.7 mA
Run Mode all IP enabled and PLL disabled

SPECIFICATIONS
MIN. TYP. MAX. UNIT
at IRC 12 MHz, VDD = 3.6V at 12 MHz,
IDD14 3.0 mA
HCLK = 12 MHz all IP and PLL disabled

IDD15 6.6 mA

IDD16 3.0 mA

IDD17 3.3 mA

IDD18 1.3 mA
IDD19 3.2 mA

IDD20 1.3 mA
VDD = 3.6V at 32.768 kHz

IDD21 82 uA
all IP enabled and PLL disabled,
Operating Current VDD = 3.6V at 32.768 kHz

IDD22 74 uA

at XTAL 32.768 kHz, VDD = 1.8V at 32.768 kHz
IDD23 77 uA
HCLK = 32.768 kHz all IP enabled and PLL disabled
VDD = 1.8V at 32.768 kHz

IDD24 68 uA
VDD = 3.6V at 10 kHz

IDD25 70 uA
Operating Current VDD = 3.6V at 10 kHz

IDD26 68 uA
at IRC 10 kHz, VDD = 1.8V at 10 kHz
IDD27 65 uA
HCLK = 10 kHz all IP enabled and PLL disabled

IDD28 62 uA
Operating Current VDD= 3.6V at 42 MHz

IIDLE1 14.5 mA [*5]
Idle Mode all IP and PLL enabled
at XTAL 12 MHz, VDD=3.6V at 42 MHz
IIDLE2 4.6 mA
HCLK = 42 MHz all IP disabled and PLL enabled

SPECIFICATIONS
MIN. TYP. MAX. UNIT
VDD = 1.8V at 42MHz

IIDLE3 13.8 mA [*5]

IIDLE4 4.5 mA
VDD= 3.6V at 32 MHz

IIDLE5 11.6 mA [*5]
Operating Current VDD=3.6V at 32 MHz

IIDLE6 3.6 mA
Idle Mode all IP disabled and PLL enabled
at XTAL 12 MHz, VDD = 1.8V at 32MHz
IIDLE7 11.1 mA [*5]

IIDLE8 3.6 mA

IIDLE9 4.7 mA

IIDLE10 0.99 mA
Idle Mode all IP and PLL disabled

IIDLE11 4.6 mA

IIDLE12 0.94 mA

IIDLE13 5.9 mA

IIDLE14 1.3 mA
at IRC 12 MHz, VDD = 1.8V at 12 MHz,
IIDLE15 4.9 mA

IIDLE16 1.3 mA

IIDLE17 2.7 mA
Operating Current all IP enabled and PLL disabled
Idle Mode VDD = 3.6V at 4 MHz,

IIDLE18 0.66 mA
at XTAL 4 MHz, all IP and PLL disabled
HCLK = 4 MHz VDD = 1.8V at 4 MHz,
IIDLE19 2.7 mA

SPECIFICATIONS
MIN. TYP. MAX. UNIT

IIDLE20 0.64 mA
VDD = 3.6V at 32.768 kHz

IIDLE21 78 uA
Operating Current VDD = 3.6V at 32.768 kHz

IIDLE22 69 uA
at XTAL 32.768 kHz, VDD = 1.8V at 32.768 kHz

IIDLE23 72 uA
HCLK = 32.768 kHz all IP enabled and PLL disabled
VDD = 1.8V at 32.768 kHz

IIDLE24 63 uA

IIDLE25 69 uA
Operating Current VDD = 3.6V at 10 kHz

IIDLE26 66 uA
at IRC 10 kHz, VDD = 1.8V at 10 kHz
IIDLE27 63 uA
HCLK = 10 kHz all IP enabled and PLL disabled

IIDLE28 61 uA

VDD = 3.6V, RTC OFF, all clock stop
IPWD1 1.2 A
With RAM Retenstion, IO no loading
VDD = 1.8V, RTC OFF, all clock stop

IPWD2 0.8 A
Standby Current
VDD = 3.6V, RTC ON, all clock stop
Power-down Mode except 32.768 kHz
IPWD3 2.8 A
VDD = 1.8V, RTC ON, all clock stop

IPWD4 2.0 A except 32.768 kHz
Input Pull Up Resistor 40 KΩ VDD = 3.3V

PA, PB, PC, PD, PE, RIN
PF 98 KΩ VDD = 1.8V
Input Leakage Current

PA, PB, PC, PD, PE, ILK -0.1 - +0.1 A VDD = 3.3V, 0<VIN<VDD
PF

SPECIFICATIONS
MIN. TYP. MAX. UNIT
Input Low Voltage PA,

PB, PC, PD, PE, PF VIL1 - 0.4VDD V
(Schmitt input)
Input High Voltage PA,

PB, PC, PD, PE, PF ADC and DAC shared pins without Input
VIH1 0.6VDD 5.5 V
5V tolerance.
(Schmitt input)
Hysteresis voltage of
VHY 0.2VDD V
PA~PF (Schmitt input)
Input Low Voltage

[*2] VIL2 0 - 0.4 VDD = 1.8V
XT1_IN / XT1_OUT
Input High Voltage VDD

[*2] VIH2 1.5 - V VDD = 1.8V
XT1_IN / XT1_OUT +0.2
Input Low Voltage
[*2] VIL4 0 - 0.3 V
X32I / X32O
Input High Voltage

[*2] VIH4 1.5 - 1.98 V
X32I / X32O
Negative going
threshold
VILS 1.28 1.33 1.37 V VDD = 3.3V
(Schmitt input),
/RESET
Positive going
threshold VIHS 1.75 1.98 2.25 V VDD = 3.3V
(SchmittIput), /RESET
VDD = 3.3V,
Source Current PA, ISR21 -10 -14 - mA
VS = Vdd-0.7V
PB, PC, PD, PE, PF
(Push-pull Mode) VDD = 1.8V,
ISR22 -3 -5 - mA
VS = Vdd-0.45V
VDD = 3.3V,
Sink Current PA, PB, ISK21 10 15 - mA
VS = 0.7V
PC, PD, PE, PF
(Push-pull Mode) VDD = 1.8V,
ISK22 3 6 - mA
VS = 0.45V
Note:
1. /RESET pin is a Schmitt trigger input.
2. Crystal Input is a CMOS input.
3. It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected between VDD and
the closest VSS pin of the device.
4. For ensuring power stability, a 4.7uF or higher capacitor must be connected between LDO pin and the closest VSS
pin of the device. Also a 100nF bypass capacitor between LDO and VSS help suppressing output noise.
5. All peripherals’ clock source is from HXT (12 MHz), except SPI from HCLK.

9.3 AC Electrical Characteristics
9.3.1 External Input Clock
SPECIFICATIONS
PARAMETER SYM. TEST CONDITION
MIN. TYP. MAX. UNIT
Clock High Time tCHCX 10 - nS

Clock Low Time tCLCX 10 - nS
Clock Rise Time tCLCH 2 - 15 nS
Clock Fall Time tCHCL 2 - 15 nS
tCLCL
tCLCH
0.7 VDD 90%
tCLCX
10%
0.3 VDD
tCHCL tCHCX
Note: Duty cycle is 50%.
9.3.2 External 4~24 MHz XTAL Oscillator
SPECIFICATIONS
MIN. TYP. MAX. UNIT
Oscillator frequency

fHXT 4 12 24 MHz VDD = 1.8V ~ 3.6V
Temperature o
THXT -40 - +85 C
Operating current IHXT 0.3 mA VDD = 3.0V
9.3.2.1 Typical Crystal Application Circuits
CRYSTAL C1 C2 R
4MHz ~ 24 MHz Optional(Depend on crystal specification) without
C1
XTAL IN
R
XTAL OUT
C2
Figure 9‑1 Typical Crystal Application Circuit

9.3.3 External 32.768 kHz Crystal
SPECIFICATIONS
MIN. TYP. MAX. UNIT
Oscillator frequency fLXT 32.768 kHz VDD = 1.8V ~ 3.6V

Temperature o
TLXT -40 - +85 C
Operating current ILXT 1.2 A VDD = 3.0V
9.3.4 Internal 12 MHz Oscillator
SPECIFICATIONS
MIN. TYP. MAX. UNIT
[1]
Supply voltage VHRC 1.8 V
o
11.88 12 12.12 MHz 25 C, VDD = 3V
o o
Calibrated Internal Oscillator 11.76 12 12.24 MHz -40 C~+85 C, VDD = 1.8V~3.6V
Frequency FHRC o o
-40 C~+85 C, VDD = 1.8V~3.6V
11.97 12 12.03 MHz Enable 32.768K crystal oscillator
and set TRIM_SEL[1:0]=”10”
Operating current IHRC 450 A
Note: Internal oscillator operation voltage comes from LDO.
9.3.5 Internal 10 kHz Oscillator

SPECIFICATIONS
MIN. TYP. MAX. UNIT
[1]
Supply voltage VLRC 1.8 V
o
7 10 13 kHz 25 C, VDD = 3V
Center Frequency FLRC o o
5 10 15 kHz -40 C~+85 C, VDD = 1.8V~3.6V
Operating current ILRC 0.7 A VDD = 3V
Note: Internal oscillator operation voltage comes from LDO.
9.4 Analog Characteristics
9.4.1 12-bit ADC
SPECIFICATIONS
MIN. TYP. MAX. UNIT
Operating voltage AVDD 1.8 3.6 V AVDD = VDD

SPECIFICATIONS
MIN. TYP. MAX. UNIT
AVDD = VDD = 3.0V
IADC42 147 A ADC_VREF = AVDD
ADC Clock Rate = 42 MHz
Operating current
AVDD = VDD = 3.0V
IADC12 50 A ADC_VREF = AVDD
ADC Clock Rate = 12 MHz
Resolution RADC 12 Bit
Reference voltage VREF 1.8 AVDD V
Reference input current (Avg.) IREF 10 A
ADC input voltage VIN 0 VREF V
Conversion time TCONV 0.5 S
Sampling Rate FSPS 2M Hz VDD = 3V
Integral Non-Linearity Error INL ±1 ±2 LSB VREF is external Vref pin
Differential Non-Linearity DNL ±0.8 -1~+1.5 LSB VREF is external Vref pin
Gain error EG - ±2 LSB VREF is external Vref pin
Offset error EOFFSET - ±3 LSB VREF is external Vref pin
Absolute error EABS - ±6 LSB VREF is external Vref pin
ADC Clock frequency FADC 0.25 42 MHz
Clock cycle ADCYC 20 Cycle

Internal Capacitance CIN - 5 - pF
Monotonic - Guaranteed -
9.4.2 Brown-out Detector
SPECIFICATIONS
MIN. TYP. MAX. UNIT
Operating voltage VBOD 1.8 3.6 V

BOD17 Quiescent current IBOD17 1 A AVDD = 3.0V, BOD17 enabled
BOD17 detection level VB17dt 1.6 1.7 1.8 V 25C
BOD20 detection level o
VB20dt 1.9 2.0 2.1 V 25 C
BOD25 detection level o
VB25dt 2.4 2.5 2.6 V 25 C

9.4.3 Power-on Reset
SPECIFICATIONS
MIN. TYP. MAX. UNIT
Reset voltage VPOR - 1.6 - V

Quiescent current IPOR - 1 - nA LDO output > Reset voltage
9.4.4 Temperature Sensor
SPECIFICATIONS
TEST CONDITION
PARAMETER SYM.
(SUPPLY VOLTAGE = 3.36V)
MIN. TYP. MAX. UNIT
Detection Temperature o
TDET -40 +110 C
Operating current ITEMP - 5 - A
Gain o
VTG -1.80 -1.73 -1.65 mV/ C
Offset o
VTO 730 740 750 mV Tempeature at 0 C
Note: Internal operation voltage comes form LDO.
9.4.5 12-bit DAC
SPECIFICATIONS
MIN. TYP. MAX. UNIT
Operating voltage AVDD 2.0 3.6 V AVDD = VDD

AVDD = VDD = 3.0V,
Operating current IDAC 2.20 mA DAC_VREF = AVDD
DAC conversion rate 500kHz
Resolution RADC 12 Bit
Reference voltage VREF 1.8 AVDD V
AVDD = VDD = 3.0V
Reference input current (Avg.) IREF 0.85 mA DAC_VREF=Ext_Vref
DAC conversion rate 500kHz
DAC output swin range 0.1 x 0.9 x
VOUT - V
VREF VREF
Conversion Rate (code to
adjacent code) FSPS 500 kHz VDD = 3V
Integral Non-Linearity Error VREF is external Vref pin

INL ±4 ±5 LSB
Not include offset and gain error
Differential Non-Linearity VREF is external Vref pin

DNL ±1 ±2 LSB
Not include offset and gain error
Gain error EG 290 LSB
Offset error EOFFSET 150 LSB

9.4.6 LCD
SPECIFICATIONS
MIN. TYP. MAX. UNIT
Operating voltage VDD 1.8 - 3.6 V

VLCD voltage VLCD34 - 3.4 - V CPUMP_VOL_SET=111, no loading
VDD = 3V, frame rate = 32Hz
Operating current ILCD - 10 - A
Without loading
9.4.7 Internal Voltage Reference
SPECIFICATIONS
MIN. TYP. MAX. UNIT

Operating voltage AVDD 1.8 - 3.6 V
1.8V voltage reference VREF1 1.69 1.8 1.87 V AVDD ≥ 2.0V (-40C ~85C)
2.5V voltage reference VREF2 2.35 2.5 2.60 V AVDD ≥ 2.8V (-40C ~85C)
Stable Time TREFTAB - 1 - ms
Operating current IVREF - 30 - A AVDD = 3V
9.4.8 USB PHY Specifications
9.4.8.1 USB PHY DC Electrical Characteristics
SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNIT
VIH Input high (driven) 2.0 - V
VIL Input low - 0.8 V
VDI Differential input sensitivity |PADP-PADM| 0.2 - V

Differential
VCM Includes VDI range 0.8 - 2.5 V
common-mode range
VSE Single-ended receiver threshold 0.8 - 2.0 V
Receiver hysteresis 200 mV
VOL Output low (driven) 0 - 0.3 V
VOH Output high (driven) 2.8 - 3.6 V
VCRS Output signal cross voltage 1.3 - 2.0 V
RPU Pull-up resistor 1.425 - 1.575 kΩ
RPD Pull-down resistor 14.25 - 15.75 kΩ
Termination Voltage for

VTRM 3.0 - 3.6 V
upstream port pull up (RPU)
ZDRV Driver output resistance Steady state drive* 10 Ω
CIN Transceiver capacitance Pin to GND - 20 pF
*Driver output resistance doesn’t include series resistor resistance.
9.4.8.2 USB PHY Full-Speed Driver Elevtrical Characteristics
TFR Rise Time CL=50p 4 - 20 ns
TFF Fall Time CL=50p 4 - 20 ns
TFRFF Rise and fall time matching TFRFF=TFR/TFF 90 - 111.11 %

9.4.8.3 USB PHY Power Dissipation
IVDDREG
VDDD and VDDREG Supply
(Full Standby 50 uA
Current (Steady State)
Speed)
9.4.8.4 USB LDO DC Electrical Characteristics
VBUS 5 V
V33 Output voltage VBUS = 5V, 25C 2.97 3.3 3.63 V
Iop Operation Current 100 uA

9.5 Flash DC Electrical Characteristics
Symbol Parameter Min Typ Max Unit Test Condition

[2]
VFLA Supply Voltage 1.62 1.8 1.98 V
[1]
NENDUR Endurance 20000 cycles
TRET Data Retention 100 year TA = 25℃
TERASE Page Erase Time - 20 - ms
TPROG Program Time - 40 - us
IDD1 Read Current 0.150 mA/MHz
IDD2 Program Current 7 mA
IDD3 Erase Current 7 mA
Notes:
1. Number of program/erase cycles.
2. VFLA is source from chip LDO output voltage.
3. Guaranteed by design, not test in production.

10 PACKAGE DIMENSIONS
10.1 LQFP128 (14x14x1.4 mm footprint 2.0 mm)








10.5 QFN48 (7x7x0.85 mm)

11 REVISION HISTORY
Date Revision Description
2012.10.11 1.00 Initial release

1. Added SmartCard UART mode description in Pin Description.
2. Unified the abbreviation (TMR) in the Timer Controller section.
3. Modified the specifications of external input clock.
4. Added LCD COM4 and COM5 description for each pin description and
2012.12.11 1.01 diagram.
5. Updated the ADC enabled by timer event description in the ADC
section.
6. Changed Timer0/1 Ch0/1 to Timer x (x=0, 1, 2, 3) in the Timer
Controller section.
2012.12.17 1.02 1. Added description of reading UCID in ISP mode.
1. Added R-type related description in LCD section.
2012.12.28 1.03 2. Updated the operating current data of Run mode and Idle mode at each
frequency and added related data at 42 MHz in section 9.2.
2013.01.02 1.04 1. Updated the table in Power Consumption section.
1. Updated the display modes from four to six in section 5.13.2.

2. Corrected the pin descriptions in section 3.4.
2013.03.05 1.05 3. Updated temperature sensor of analog characteristic in section 9.4.4.
4. Corrected Smart Card’s feature to be half duplex in UART mode in

section 5.16.2.
1. Updated the Nano110 LQFP128-pin diagram in section 3.3.2.

2. Updated “12 MHz OSC has 2 % deviation within all temperarure range”
2013.05.28 1.06 in sections 2.1 to 2.4.
3. Updated DAC analog characteristics in section 9.4.5.
4. Added Nano110RC2BN to the Nano110 LCD Line Selection Guide.
1. Updated Nano100 series selection code in section 3.1.
2. Added the Nano100 QFN48 package in section 3.2 and QFN48
package dimensions in chapter 10.
3. Fixed the typo of LCD characteristic in section 9.4.7.
2013.12.04 1.07
4. Added a note that “Output voltage for ADC/LCD shared pins cannot be
higher than VDD because these pins are without 5V tolerance.” for pin
description in section 3.4, LCD overview in section 5.13.1 and Absolute
Maximum Ratings in section 9.1.
5. Modified the schematic for ADC and DAC application circuit in section

7.2 and 7.3.
1. Added Flash DC Electrical Characteristics in section 9.5.

2. Fixed the typo of LCD Feature in section 5.13.2.
2016.05.31 1.08 3. Fixed the typo of Products Selection Guide in section 3.2
4. Modified the schematic for ADC, DAC and Whole Chip Application
Circuit in section 7.2, 7.3 and 7.4.

Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.

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NUMICRO® NANO100 (B) DATASHEET

NANO100 SERIES DATASHEET

For additional information or questions, please contact: Nuvoton Technology Corporation.

May 31, 2016 Page 1 of 160 Revision 1.08

5.4.2 Features ....................................................................................................................... 105

NANO100 SERIES DATASHEET

May 31, 2016 Page 3 of 160 Revision 1.08

5.19.1 Overview .................................................................................................................... 123

7.4 Whole Chip Application Circuit ................................................................................. 137

May 31, 2016 Page 4 of 160 Revision 1.08

9.4.8 USB PHY Specifications ............................................................................................... 149

NANO100 SERIES DATASHEET

May 31, 2016 Page 5 of 160 Revision 1.08

May 31, 2016 Page 6 of 160 Revision 1.08

NANO100 SERIES DATASHEET

May 31, 2016 Page 7 of 160 Revision 1.08

 Wireless RF4CE Remote Control

May 31, 2016 Page 8 of 160 Revision 1.08

Table 1‑1 Connectivity Support Table

NANO100 SERIES DATASHEET

May 31, 2016 Page 9 of 160 Revision 1.08

2.1 Nano100 Features – Base Line

 Supports DMA mode

May 31, 2016 Page 10 of 160 Revision 1.08

 Supports address direction: increment, fixed, and wrap around

NANO100 SERIES DATASHEET

May 31, 2016 Page 11 of 160 Revision 1.08

 Selectable time-out period from 1.6 ms ~ 26 sec (depending on clock source)

 Master up to 32 MHz, and Slave up to 16 MHz

NANO100 SERIES DATASHEET

 12-bit SAR ADC up to 2Msps conversion rate

 Supports up to three ISO-7816-3 ports

May 31, 2016 Page 14 of 160 Revision 1.08

 Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode

NANO100 SERIES DATASHEET

May 31, 2016 Page 15 of 160 Revision 1.08

2.2 Nano110 Features – LCD Line

May 31, 2016 Page 16 of 160 Revision 1.08

NANO100 SERIES DATASHEET

May 31, 2016 Page 17 of 160 Revision 1.08

 Wake system up from Power-down mode

rising/ falling/both capture inputs.

 Variable length of transfer data from 4 to 32 bits

NANO100 SERIES DATASHEET

Temperature sensor, AVDD, and AVSS

 Programmable receiver buffer trigger level

May 31, 2016 Page 20 of 160 Revision 1.08

 Selectable LCD frequency by frequency divider

NANO100 SERIES DATASHEET

May 31, 2016 Page 21 of 160 Revision 1.08

2.3 Nano120 Features – USB Connectivity Line

May 31, 2016 Page 22 of 160 Revision 1.08

NANO100 SERIES DATASHEET

 Window Watchdog Timer(WWDT)

 Supports one shot and continuous mode

 Variable length of transfer data from 4 to 32 bits

NANO100 SERIES DATASHEET

May 31, 2016 Page 25 of 160 Revision 1.08

 Programmable transmission clock frequency

Marked in the table (2+3) means 2 UART+ 3 ISO-7816 UART. LQFP64:7X7mm

Marked in the table (2+3) means 2 UART+ 3 ISO-7816 UART. LQFP64:7X7mm

Marked in the table (2+3) means 2 UART+ 3 ISO-7816 UART. LQFP64:7X7mm

Marked in the table (2+3) means 2 UART+ 3 ISO-7816 UART. LQFP64:7X7mm