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TC58NVG0S3ETA00
TC58NVG0S3ETA00
2
1 GBIT (128M × 8 BIT) CMOS NAND E PROM
DESCRIPTION
The TC58NVG0S3E is a single 3.3V 1 Gbit (1,107,296,256 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 1024blocks.
The device has two 2112-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block
unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages).
The TC58NVG0S3E is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
x8
Memory cell array 2112 × 64K × 8
Register 2112 × 8
Page size 2112 bytes
Block size (128K + 4K) bytes
• Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
• Mode control
Serial input/output
Command control
• Power supply
VCC = 2.7V to 3.6V
• Access time
Cell array to register 25 µs max
Serial Read Cycle 25 ns min (CL=100pF)
• Program/Erase time
Auto Page Program 300 µs/page typ.
Auto Block Erase 2.5 ms/block typ.
• Operating current
Read (25 ns cycle) 30 mA max.
Program (avg.) 30 mA max
Erase (avg.) 30 mA max
Standby 50 µA max
• Package
TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.)
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TC58NVG0S3ETA00
PIN ASSIGNMENT (TOP VIEW)
TC58NVG0S3ETA00
×8 ×8
NC 1 48 NC
NC 2 47 NC
NC 3 46 NC
NC 4 45 NC
NC 5 44 I/O8
NC 6 43 I/O7
RY / BY 7 42 I/O6
RE 8 41 I/O5
CE 9 40 NC
NC 10 39 NC
NC 11 38 NC
VCC 12 37 VCC
VSS 13 36 VSS
NC 14 35 NC
NC 15 34 NC
CLE 16 33 NC
ALE 17 32 I/O4
WE 18 31 I/O3
WP 19 30 I/O2
NC 20 29 I/O1
NC 21 28 NC
NC 22 27 NC
NC 23 26 NC
NC 24 25 NC
PIN NAMES
CE Chip enable
WE Write enable
RE Read enable
WP Write protect
RY/BY Ready/Busy
VSS Ground
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BLOCK DIAGRAM
VCC VSS
Status register
Sense amp
CE
decoder
ALE
Logic control Control circuit Memory cell array
WE
RE
WP
RY / BY
RY / BY HV generator
* This parameter is periodically sampled and is not tested for every device.
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VALID BLOCKS
SYMBOL PARAMETER MIN TYP. MAX UNIT
NOTE: The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime
The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane
operations.
VIH High Level input Voltage 2.7 V ≤ VCC ≤ 3.6 V Vcc x 0.8 ⎯ VCC + 0.3 V
VIL Low Level Input Voltage 2.7 V ≤ VCC ≤ 3.6 V −0.3* ⎯ Vcc x 0.2 V
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AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70℃, VCC = 2.7 to 3.6V)
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AC TEST CONDITIONS
CONDITION
PARAMETER
VCC: 2.7 to 3.6V
Note: Busy to ready time depends on the pull-up resistor tied to the RY / BY pin.
(Refer to Application Note (9) toward the end of this document.)
tDCBSYW2 Data Cache Busy Time in Write Cache (following 15h) ⎯ ⎯ 700 µs (2)
(1) Refer to Application Note (12) toward the end of this document.
(2) tDCBSYW2 depends on the timing between internal programming time and data in time.
Data Output
When tREH is long, output buffers are disabled by /RE=High, and the hold time of data output depend on tRHOH
(25ns MIN). On this condition, waveforms look like normal serial read mode.
When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depend on
tRLOH (5ns MIN). On this condition, output buffers are disabled by the rising edge of CLE,ALE,/CE or falling
edge of /WE, and waveforms look like Extended Data Output Mode.
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TIMING DIAGRAMS
CLE
ALE
CE
RE Setup Time Hold Time
WE
tDS tDH
I/O
: VIH or VIL
CLE
tCLS tCLH
tCS tCH
CE
tWP
WE
tALS tALH
ALE
tDS tDH
I/O
: VIH or VIL
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TC58NVG0S3ETA00
tCLS tCLH
CLE
CE
WE
tALS tALH
ALE
: VIH or VIL
tCLS tCLH
CLE
CE
tALS tALH
tWC
ALE
WE
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TC58NVG0S3ETA00
Serial Read Cycle Timing Diagram
tRC
CE
RE
tRHZ tRHZ tRHZ
tREA tRHOH tREA tRHOH tREA tRHOH
tCEA tCEA
I/O
tRR
RY / BY
: VIH or VIL
tCLR
CLE
tCLS tCLH
tCS
CE
WE tCHZ
tWHC
tWHR
RE
tRHOH
tDS tDH tIR
tREA tRHZ
Status
I/O 70h*
output
RY / BY
: VIH or VIL
*: 70h represents the hexadecimal number
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TC58NVG0S3ETA00
Read Cycle Timing Diagram
tCLR
CLE
tCLS tCLH tCLS tCLH
tCS tCH tCS tCH
CE
tWC
WE
tALH tALS tALH tALS
ALE
tR tRC
RE tWB
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tCEA
tRR
CLE
tCLS tCLH tCLS tCLH
CE
tWC tCSD
WE
tALH tALS tALH tALS
ALE
tR tRC tCHZ
RE tWB
tRHZ
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tCEA
tRR tRHOH
RY / BY
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Read Cycle with Data Cache Timing Diagram (1/2)
tCLR tCLR
CLE
tCLH tCLH tCLH tCLH
tCLS tCLS tCLS tCLS
tCH tCH tCH tCH
tCS tCS tCS tCS
CE
tWC
WE
tALH tALS tALH tALS tRW tCEA tCEA
ALE
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tRR tDS tDH tRR tREA
tREA
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Read Cycle with Data Cache Timing Diagram (2/2)
WE
tCEA tCEA
tCEA
ALE
tDCBSYR1 tRC tDCBSYR1 tRC tDCBSYR1 tRC
RY / BY
Col. Add. 0
Col. Add. 0 Col. Add. 0
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Column Address Change in Read Cycle Timing Diagram (1/2)
tCLR
CLE
tCLS tCLH tCLS tCLH
CE
tWC
tCEA
WE
ALE
tR tRC
tWB
RE
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tRR tREA
RY / BY
Column address
A
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Column Address Change in Read Cycle Timing Diagram (2/2)
tCLR
CLE
tCLS tCLH tCLS tCLH
CE
WE
tALH tALS tALH tALS
ALE
tWHR tRC
RE
tDS tDH tDS tDH tDS tDH tDS tDH tREA
tIR
DOUT CA0 CA8 DOUT DOUT DOUT
I/O 05h E0h
A+N to 7 to 11 B B+1 B + N’
Column address Page address
B P
RY / BY
Column address
B
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CLE
tCLS tCLH
tCS tCH
CE
WE
tALH
ALE
tRC tCHZ
tRP tREH tRP tRP tRHZ
RE
tREA tREA
tCEA tDS tDH
tREA tRLOH tRLOH
tRR
tRHOH tRHOH
RY / BY
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Auto-Program Operation Timing Diagram
tCLS
CLE
tCLS tCLH
tCS tCS
CE
tCH
WE
tALH tALH
tALS tPROG
tALS
tWB
ALE
RE tDS
tDS
tDS tDH tDS tDH tDH tDH
RY / BY
: VIH or VIL
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Auto-Program Operation with Data Cache Timing Diagram (1/3)
tCLS
CLE
tCLS tCLH
tCS tCS
CE
tCH
WE
tALH tALH
tALS tDCBSYW2
tALS tWB
ALE
RE
tDS tDS
tDS tDH tDS tDH tDH tDH
DIN2111
RY / BY
: Do not input data while data is being output.
: VIH or VIL
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TC58NVG0S3ETA00
Auto-Program Operation with Data Cache Timing Diagram (2/3)
tCLS
CLE
tCLS tCLH
tCS tCS
CE
tCH
WE
tALH tALH
tALS tALS tDCBSYW2
tWB
ALE
RE
tDS tDS
tDS tDH tDS tDH tDH tDH
DIN2111
RY / BY
: VIH or VIL
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Auto-Program Operation with Data Cache Timing Diagram (3/3)
tCLS
CLE
tCLS tCLH
tCS tCS
CE
tCH
WE
tALH tALH
tALS tALS tPROG (*1)
tWB
ALE
RE
tDS tDS
tDS tDH tDS tDH tDH tDH
DIN2111
RY / BY
: Do not input data while data is being output.
: VIH or VIL
2
(*1) tPROG: Since the last page programming by 10h command is initiated after the previous cache
Continued from 2 of last page program, the tPROG during cache programming is given by the following equation.
If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max.
(Note) Make sure to terminate the operation with 80h-10h- command sequence.
If the operation is terminated by 80h-15h command sequence, monitor I/O 6 (Ready / Busy) by
issuing Status Read command (70h) and make sure the previous page program operation is
completed. If the page program operation is completed issue FFh reset before next operation.
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Multi-Page Program Operation with Data Cache Timing Diagram (1/4)
tCLS
CLE
tCLS tCLH
tCS tCS
CE
tCH
WE
tALH tALH
tALS tALS tDCBSYW1
tWB
ALE
RE
tDS tDS
tDS tDH tDS tDH tDH tDH
RY / BY
: Do not input data while data is being output.
: VIH or VIL
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TC58NVG0S3ETA00
Multi-Page Program Operation with Data Cache Timing Diagram (2/4)
tCLS
CLE
tCLS tCLH
tCS tCS
CE
tCH
WE
tALH tALH
tALS tDCBSYW2
tALS tWB
ALE
RE
tDS tDS
tDS tDH tDS tDH tDH tDH
RY / BY
: VIH or VIL
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Multi-Page Program Operation with Data Cache Timing Diagram (3/4)
tCLS
CLE
tCLS tCLH
tCS tCS
CE
tCH
WE
tALH tALH
tALS tALS tDCBSYW1
tWB
ALE
RE
tDS tDS
tDS tDH tDS tDH tDH tDH
RY / BY
: Do not input data while data is being output.
: VIH or VIL
2 3
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TC58NVG0S3ETA00
Multi-Page Program Operation with Data Cache Timing Diagram (4/4)
tCLS
CLE
tCLS tCLH
tCS tCS
CE
tCH
WE
tALH tALH
tALS tALS tPROG (*1)
tWB
ALE
RE
tDS tDS
tDS tDH tDS tDH tDH tDH
RY / BY
: Do not input data while data is being output.
: VIH or VIL
(*1) tPROG: Since the last page programming by 10h command is initiated after the previous cache
program, the tPROG during cache programming is given by the following equation.
If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max.
(Note) Make sure to terminate the operation with 80h-10h- command sequence.
If the operation is terminated by 81h-15h command sequence, monitor I/O 6 (Ready / Busy) by issuing Status
Read command (70h) and make sure the previous page program operation is completed. If the page program
operation is completed issue FFh reset before next operation.
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Auto Block Erase Timing Diagram
CLE
tCLS
tCLH
tCS
tCLS
CE
WE
tALH
tALS tWB tBERASE
ALE
RE
tDS tDH
Busy
RY / BY Auto Block Erase Start Status Read
Erase Setup command command
command
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Multi Block Erase Timing Diagram
CLE
tCLS
tCLH
tCS
tCLS
CE
WE
ALE
RE
tDS tDH
: VIH or VIL
: Do not input data while data is being output.
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ID Read Operation Timing Diagram
tCLS
CLE
tCLS
tCS tCS tCH tCEA
CE
tCH
WE
tALS tALH
tALH tAR
ALE
RE
tDH
tDS
tREA tREA tREA tREA tREA
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PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information.
Chip Enable: CE
The device goes into a low-power Standby mode when CE goes High during the device is in Ready state. The
CE signal is ignored when device is in Busy state ( RY / BY = L), such as during a Program or Erase or Read
operation, and will not enter Standby mode even if the CE input goes High.
Write Enable: WE
The WE signal is used to control the acquisition of data from the I/O port.
Read Enable: RE
The RE signal controls serial data output. Data is available tREA after the falling edge of RE .
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
Write Protect: WP
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy: RY / BY
The RY / BY output signal is used to indicate the operating condition of the device. The RY / BY signal is
in Busy state ( RY / BY = L) during the Program, Erase and Read operations and will return to Ready state
( RY / BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be
pulled-up to Vccq with an appropriate resister.
If RY / BY signal is not pulled-up to Vccq( “Open” state ), device operation can not guarantee.
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Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
I/O1
64 Pages=1 block
65536
pages
1024 blocks
8I/O
2112
An address is read in via the I/O port over four
consecutive clock cycles, as shown in Table 1.
Table 1. Addressing
Second cycle L L L L CA11 CA10 CA9 CA8 PA6 to PA15: Block address
PA0 to PA5: NAND address in block
Third cycle PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Fourth cycle PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8
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Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by command operations shown
in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE , WE ,
RE and WP signals, as shown in Table 2.
Command Input H L L H *
Data Input L L L H H
Address input L H L H *
* * H * * *
During Read (Busy)
* * L H (*2) H (*2) *
Standby * * H * * 0 V/VCC
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Read 00 30
Read Start for Last Page in Read Cycle with Data Cache 3F ⎯
80 11
81 10
ID Read 90 ⎯
Status Read 70 ⎯ {
Reset FF ⎯ {
1 0 0 0 0 0 0 0
8 7 6 5 4 3 2 I/O1
H: VIH, L: VIL
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DEVICE OPERATION
Read Mode
Read mode is set when the "00h" and “30h” commands are issued to the Command register. Between the two
commands, a start address for the Read mode needs to be issued. Refer to the figures below for the sequence and
the block diagram (Refer to the detailed timing chart.).
CLE
CE
WE
ALE
RE
Page Address N
Start-address input
A data transfer operation from the cell array to the Data
M m
Data Cache Cache via Page Buffer starts on the rising edge of WE in the
30h command input cycle (after the address information has
Page Buffer been latched). The device will be in the Busy state during this
Select page transfer period.
N After the transfer period, the device returns to Ready state.
Cell array
Serial data can be output synchronously with the RE clock
from the start address designated in the address input cycle.
I/O1 to 8: m = 2111
CLE
CE
WE
ALE
RE
RY / BY
Busy
tR
Col. M
00h 30h M M+1 M+2 M+3 05h E0h M’ M’+1 M’+2 M’+3 M’+4
I/O
M M’ During the serial data output from the Data Cache, the column
address can be changed by inputting a new column address
using the 05h and E0h commands. The data is read out in serial
starting at the new column address. Random Column Address
Change operation can be done multiple times within the same
Select page page.
N
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Read Operation with Read Cache
The device has a Read operation with Data Cache that enables the high speed read operation shown below. When the block address changes, this sequence has to be
started from the beginning.
CLE
CE
WE
ALE
RE
RY / BY
tR tDCBSYR1 tDCBSYR1 tDCBSYR1
3 5 7
1 2 4 6
I/O 00h 30h 31h 0 1 2 3 2111 31h 0 1 2 3 2111 3Fh 0 1 2 3 2111
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Multi Page Read Operation
The device has a Multi Page Read operation and Multi Page Read with Data Cache operation.
Command
input (2 cycle) (2 cycle)
60 Address input 60 Address input 30 A
Page Address Page Address
PA0 to PA15 PA0 to PA15
(District 0) (District 1) tR
RY/BY A
Command
input (4 cycle) (2 cycle)
A 00 Address input 05 Address input E0 Data output B
Column + Page Address Column Address (District 0)
CA0 to CA11, PA0 to PA15 CA0 to CA11
(District 0) (District 0)
RY/BY A B
Command
input (2 cycle)
(4 cycle)
B 00 Address input 05 Address input E0 Data output
Column + Page Address Column Address (District 1)
CA0 to CA11, PA0 to PA15 CA0 to CA11
(District 1) (District 1)
RY/BY B
District 0 District 1
Reading
Selected
page Selected
page
The data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising
edge of WE in the 30h command input cycle (after the 2 Districts address information has been
latched). The device will be in the Busy state during this transfer period.
After the transfer period, the device returns to Ready state. Serial data can be output synchronously
with the RE clock from the start address designated in the address input cycle.
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(2) Multi Page Read with Data Cache
When the block address changes (increments) this sequenced has to be started from the beginning.
The sequence of command and address input is shown below.
Same page address (PA0 to PA5) within each district has to be selected.
Command
input
60 Address input 60 Address input 30 A
Page Address Page Address
PA0 to PA15 PA0 to PA15
(Page m0 ; District 0) (Page n0 ; District 1) tR
RY/BY A
Command
input
A 31 00 Address input 05 Address input E0 Data output B
Column + Page Address Column Address (District 0)
CA0 to CA11, PA0 to PA15 CA0 to CA11
tDCBSYR1 (Page m0 ; District 0) (District 0)
RY/BY A B
Command
input
B 00 Address input 05 Address input E0 Data output C
Column + Page Address Column Address (District 1)
CA0 to CA11, PA0 to PA15 CA0 to CA11
(Page n0 ; District 1) (District 1)
RY/BY B C
Return to A
Repeat a max of 63 times
Command
input
C 3F 00 Address input 05 Address input E0 Data output D
Column + Page Address Column Address (District 0)
CA0 to CA11, PA0 to PA15 CA0 to CA11
tDCBSYR1 (Page m63 ; District 0) (District 0)
RY/BY C D
Command
input
D 00 Address input 05 Address input E0 Data output
Column + Page Address Column Address (District 1)
CA0 to CA11, PA0 to PA15 CA0 to CA11
(Page n63 ; District 1) (District 1)
RY/BY D
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(3) Notes
(a) Internal addressing in relation with the Districts
To use Multi Page Read operation, the internal addressing should be considered in relation with the District.
• The device consists from 2 Districts.
• Each District consists from 512 erase blocks.
• The allocation rule is follows.
District 0: Block 0, Block 2, Block 4, Block 6,···, Block 1022
District 1: Block 1, Block 3, Block 5, Block 7,···, Block 1023
(b) Address input restriction for the Multi Page Read operation
There are following restrictions in using Multi Page Read;
(Restriction)
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two districts has to be selected.
For example;
(60) [District 0, Page Address 0x0000] (60) [District 1, Page Address 0x0040] (30)
(60) [District 0, Page Address 0x0001] (60) [District 1, Page Address 0x0041] (30)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 0] (60) [District 1] (30)
(60) [District 1] (60) [District 0] (30)
It requires no mutual address relation between the selected blocks from each District.
(c) WP signal
Make sure WP is held to High level when Multi Page Read operation is performed
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Auto Page Program Operation
The device carries out an Automatic Page Program operation when it receives a "10h" Program command
after the address and data have been input. The sequence of command, address and data input is shown below.
(Refer to the detailed timing chart.)
CLE
CE
WE
ALE
RE
RY/BY
Status
I/O 80h Din Din Din Din 10h 70h Out
Data input
The data is transferred (programmed) from the Data Cache via
the Page Buffer to the selected page on the rising edge of WE
Program Read& verification following input of the “10h” command. After programming, the
programmed data is transferred back to the Page Buffer to be
Selected
automatically verified by the device. If the programming does not
page
succeed, the Program/Verify operation is repeated by the device
until success is achieved or until the maximum loop number set in
the device is reached.
80h Din Din Din Din 85h Din Din Din Din 10h 70h Status
Data input
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Multi Page Program
The device has a Multi Page Program, which enables even higher speed program operation compared to Auto Page Program. The sequence of command, address and data
input is shown bellow. (Refer to the detailed timing chart.)
Although two planes are programmed simultaneously, pass/fail is not available for each page when the program operation completes. Status bit of I/O 0 is set to “1” when
any of the pages fails. Limitation in addressing with Multi Page Program is shown below.
tDCBSYW1 tPROG
R/ B
”0”
I/O0~7 80h Address & Data Input 11h 81h Address & Data Input 10h 70h I/O0 Pass
Note
CA0~CA11 : Valid CA0~CA11 : Valid ”1”
PA0~PA5 : Valid’ PA0~PA5 : Valid
PA6 : District0’ PA6 : District1 Fail
PA7~PA15 : Valid’ PA7~PA15 : Valid
NOTE: Any command between 11h and 81h is prohibited except 70h and FFh.
Block 0 Block 1
Block 2 Block 3
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Auto Page Program Operation with Data Cache
The device has an Auto Page Program with Data Cache operation enabling the high speed program operation shown below. When the block address changes this
sequenced has to be started from the beginning.
CLE
CE
WE
ALE
RE
RY / BY
tDCBSYW2 tDCBSYW2 tPROG (NOTE)
I/O 80h Add Add Add Din Din Din 15h 70h 80h Add Add Add Add Din Din Din 15h 70h 80h Add Add Add Add Din Din Din 10h 70h
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Pass/fail status for each page programmed by the Auto Page Programming with Data Cache operation can be detected by the Status Read operation.
z I/O1 : Pass/fail of the current page program operation.
z I/O2 : Pass/fail of the previous page program operation.
The Pass/Fail status on I/O1 and I/O2 are valid under the following conditions.
z Status on I/O1: Page Buffer Ready/Busy is Ready State.
The Page Buffer Ready/Busy is output on I/O6 by Status Read operation or RY / BY pin after the 10h command
z Status on I/O2: Data Cache Read/Busy is Ready State.
The Data Cache Ready/Busy is output on I/O7 by Status Read operation or RY / BY pin after the 15h command.
Example)
I/O2 => Invalid Page 1 Page 1 Page N − 2 invalid Page N − 1
I/O1 => Invalid Invalid Page 2 Invalid invalid Page N
RY/BY pin
Page 1
Page Buffer Busy
Page 2
Page N − 1
Page N
If the Page Buffer Busy returns to Ready before the next 80h command input, and if Status Read is done during
this Ready period, the Status Read provides pass/fail for Page 2 on I/O1 and pass/fail result for Page1 on I/O2
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Multi Page Program with Data Cache
The device has a Multi Page Program with Data Cache operation, which enables even higher speed program
operation compared to Auto Page Program with Data Cache as shown below. When the block address changes
(increments) this sequenced has to be started from the beginning.
The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.)
Address Data input Address Data input Address Data input Address Data input
input 0 to 2111 input 0 to 2111 input 0 to 2111 input 0 to 2111
(District 0) (District 1) (District 0) (District1)
RY/BY
After “15h” or “10h” Program command is input to device, physical programing starts as follows. For details
of Auto Program with Data Cache, refer to “Auto Page Program with Data Cache”.
District 0 District 1
Selected
page
The data is transferred (programmed) from the page buffer to the selected page on the rising edge of
/WE following input of the “15h” or “10h” command. After programming, the programmed data is
transferred back to the register to be automatically verified by the device. If the programming does not
succeed, the Program/Verify operation is repeated by the device until success is achieved or until the
maximum loop number set in the device is reached.
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Starting the above operation from 1st page of the selected erase blocks, and then repeating the operation
total 64 times with incrementing the page address in the blocks, and then input the last page data of the
blocks, “10h” command executes final programming. Make sure to terminate with 81h-10h- command
sequence.
In this full sequence, the command sequence is following.
1st 80 11 81 15
80 11 81 15
63th 80 11 81 15
64th 80 11 81 10
After the “15h” or “10h” command, the results of the above operation is shown through the “71h”Status Read
command.
Pass
10 or15 71 I/O
RY/BY
STATUS OUTPUT
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Internal addressing in relation with the Districts
To use Multi Page Program operation, the internal addressing should be considered in relation with the
District.
• The device consists from 2 Districts.
• Each District consists from 512 erase blocks.
• The allocation rule is follows.
District 0: Block 0, Block 2, Block 4, Block 6,···, Block 1022
District 1: Block 1, Block 3, Block 5, Block 7,···, Block 1023
Address input restriction for the Multi Page Program with Data Cache operation
There are following restrictions in using Multi Page Program with Data Cache;
(Restriction)
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two districts has to be selected.
For example;
(80) [District 0, Page Address 0x0000] (11) (81) [District 1, Page Address 0x0040] (15 or 10)
(80) [District 0, Page Address 0x0001] (11) (81) [District 1, Page Address 0x0041] (15 or 10)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(80) [District 0] (11) (81) [District 1] (15 or 10)
(80) [District 1] (11) (81) [District 0] (15 or 10)
It requires no mutual address relation between the selected blocks from each District.
Operating restriction during the Multi Page Program with Data Cache operation
(Restriction)
The operation has to be terminated with “10h” command.
Once the operation is started, no commands other than the commands shown in the timing diagram is allowed
to be input except for Status Read command and reset command.
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Page Copy (2)
By using Page Copy (2), data in a page can be copied to another page after the data has been read out.
When the block address changes (increments) this sequenced has to be started from the beginning.
Command 2 3
input
00 Address input 30 Data output 8C Address input Data input 15 00 Address input 3A Data output A
Address Col = 0 start Address When changing data,
Address Col = 0 start
CA0 to CA11, PA0 to PA15 CA0 to CA11, PA0 to PA15 changed data is input. CA0 to CA11, PA0 to PA15
(Page N) (Page M) (Page N+P1)
1 4 5
A
RY/BY tR tDCBSYW2 tDCBSYR2
1 Data for Page N 2 Data for Page N 3 Data for Page M 4 5 Data for Page N + P1
Data Cache
Page Buffer
Cell Array
Page M
Page N Page N + P1
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Command 6
input
A 8C Address input Data input 15 00 Address input 3A Data output 00 Address input 3A Data output B
Address When changing data,
Address Col = 0 start Address Col = 0 start
CA0 to CA11, PA0 to PA15 changed data is input. CA0 to CA11, PA0 to PA15 CA0 to CA11, PA0 to PA15
(Page M+R1) (Page N+P2) (Page N+Pn)
7 8 9
RY / BY A B
tDCBSYW2 tDCBSYR2 tDCBSYR2
6 7 8 9
Data for Page M + R1 Data for Page M + R1 Data for Page N + P2 Data for Page N + Pn
Data Cache
Page Buffer
Page M + Rn − 1 Page M + Rn − 1
Cell Array Page M + R1
Page M
Page N + Pn
Page N + P2
Page N + P1
6 Copy Page address (M + R1) is input and if the data needs to be changed, changed data is input.
7 After programming of page M is completed, Data Cache for Page M + R1 is transferred to the Page Buffer.
8 By the 15h command, the data in the Page Buffer is programmed to Page M + R1. Data for Page N + P2 is transferred to the Data cache.
9 The data in the Page Buffer is programmed to Page M + Rn − 1. Data for Page N + Pn is transferred to the Data Cache.
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Command 10
input
B 8C Address input Data input 10 70 Status output
Address
CA0 to CA11, PA0 to PA15
(Page M+Rn)
11
RY / BY B
tPROG (*1)
10 Copy Page address (M + Rn) is input and if the data needs to be changed, changed data is input.
11 By issuing the 10h command, the data in the Page Buffer is programmed to Page M + Rn.
(*1) Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG here will be expected as the following,
tPROG = tPROG of the last page + tPROG of the previous page − ( command input cycle + address input cycle + data output/input cycle time of the last page)
Make sure WP is held to High level when Page Copy (2) operation is performed.
Also make sure the Page Copy operation is terminated with 8Ch-10h command sequence
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Multi Page Copy (2)
By using Multi Page Copy (2), data in two pages can be copied to another pages after the data has been read out.
When the each block address changes (increments) this sequenced has to be started from the beginning.
Same page address (PA0 to PA5) within two districts has to be selected.
Command
input
60 Address input 60 Address input 30 00 Address input 05 Address input E0 Data output A
Address Address Address Address
PA0 to PA15 PA0 to PA15 CA0 to CA11, PA0 to PA15 CA0 to CA11
(Page m0 ; District 0) (Page n0 ; District 1) (Page m0) (Col = 0)
A
RY/BY tR
A 00 Address input 05 Address input E0 Data output 8C Address input Data input 11 B
Address Address Address
CA0 to CA11, PA0 to PA15 CA0 to CA11 CA0 to CA11, PA0 to PA15
(Page n0) (Col = 0) (Page M0 ; District 0)
A B
RY/BY tDCBSYW1
C 00 Address input 05 Address input E0 Data output 00 Address input 05 Address input E0 Data output D
Address Address Address Address
CA0 to CA11, PA0 to PA15 CA0 to CA11 CA0 to CA11, PA0 to PA15 CA0 to CA11
(Page m1) (Col = 0) (Page n1) (Col = 0)
C D
RY/BY
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E 60 Address input 60 Address input 3A 00 Address input 05 Address input E0 Data output F
Address Address Address Address
PA0 to PA15 PA0 to PA15 CA0 to CA11, PA0 to PA15 CA0 to CA11
(Page m63 ; District 0) (Page n63 ; District 1) (Page m63) (Col = 0)
E F
RY/BY tDCBSYR2
F 00 Address input 05 Address input E0 Data output 8C Address input Data input 11 G
Address Address Address
CA0 to CA11, PA0 to PA15 CA0 to CA11 CA0 to CA11, PA0 to PA15
(Page n63) (Col = 0) (Page M63 ; District 0)
F G
RY/BY tDCBSYW1
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Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which
follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an extra layer of
protection from accidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.
Pass
60 D0 70 I/O
Block Address Erase Start Status Read Fail
input: 2 cycles command command
RY / BY Busy
Pass
60 60 D0 71 I/O
Status Read Fail
Block Address Block Address Erase Start
command
input: 2 cycles input: 2 cycles command
District 0 District 1
RY / BY Busy
(Restriction)
Maximum one block should be selected from each District.
For example;
(60) [District 0] (60) [District 1] (D0)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 1] (60) [District 0] (D0)
It requires no mutual address relation between the selected blocks from each District.
Make sure to terminate the operation with D0h command. If the operation needs to be terminated before D0h
command input, input the FFh reset command to terminate the operation.
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ID Read
The device contains ID codes which can be used to identify the device type, the manufacturer, and features of
the device. The ID codes can be read out under the following timing conditions:
CLE
tCEA
CE
WE
tAR
ALE
RE
tREA
See See See
I/O 00h 98h D1h table 5 table 5 table 5
ID Read Address 00 Maker code Device code
command
Description I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Hex Data
3rd Data
1 0 0
2 0 1
Internal Chip Number
4 1 0
8 1 1
2 level cell 0 0
4 level cell 0 1
Cell Type
8 level cell 1 0
16 level cell 1 1
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4th Data
1 KB 0 0
Page Size 2 KB 0 1
(without redundant area) 4 KB 1 0
8 KB 1 1
64 KB 0 0
Block Size 128 KB 0 1
(without redundant area) 256 KB 1 0
512 KB 1 1
5th Data
1 Plane 0 0
2 Plane 0 1
Plane Number
4 Plane 1 0
8 Plane 1 1
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Status Read
The device automatically implements the execution and verification of the Program and Erase operations.
The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass
/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is
output via the I/O port using RE after a “70h” command input. The Status Read can also be used during a
Read operation to find out the Ready/Busy status.
The resulting information is outlined in Table 6.
Chip Status1
I/O1 Pass/Fail Pass/Fail Invalid
Pass: 0 Fail: 1
Chip Status 2
I/O2 Invalid Pass/Fail Invalid
Pass: 0 Fail: 1
Write Protect
I/O8 Write Protect Write Protect Write Protect
Not Protected :1 Protected: 0
The Pass/Fail status on I/O1 and I/O2 is only valid during a Program/Erase operation when the device is in the Ready state.
Chip Status 1:
During a Auto Page Program or Auto Block Erase operation this bit indicates the pass/fail result.
During a Auto Page Programming with Data Cache operation, this bit shows the pass/fail results of the
current page program operation, and therefore this bit is only valid when I/O6 shows the Ready state.
Chip Status 2:
This bit shows the pass/fail result of the previous page program operation during Auto Page Programming
with Data Cache. This status is valid when I/O7 shows the Ready State.
The status output on the I/O6 is the same as that of I/O7 if the command input just before the 70h is not
15h or 31h.
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An application example with multiple devices is shown in the figure below.
CLE
ALE Device Device Device Device Device
WE 1 2 3 N N+1
RE
I/O1
to I/O8
RY / BY
RY / BY Busy
CLE
ALE
WE
CE1
CEN
RE
System Design Note: If the RY / BY pin signals from multiple devices are wired together as shown in the
diagram, the Status Read function can be used to determine the status of each individual device.
Reset
The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally
generated voltage is discharged to 0 volt and the device enters the Wait state.
Reset during a Cache Program/Page Copy may not just stop the most recent page program but it may also
stop the previous program to a page depending on when the FF reset is input.
The response to a “FFh” Reset command input during the various device operations is as follows:
80 10 FF 00
Internal VPP
RY / BY
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When a Reset (FFh) command is input during erasing
D0 FF 00
Internal erase
voltage
RY / BY
00 30 FF 00
RY / BY
FF 00
RY / BY
tRST (max 6 µs)
FF 70
I/O status: Pass/Fail → Pass
: Ready/Busy → Ready
RY / BY
10 FF FF FF
RY / BY
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APPLICATION NOTES AND COMMENTS
2.7 V
2.5V
VCC
0 V
Don’t Don’t
care care
CE , WE , RE
CLE, ALE
VIH
VIL VIL
WP 1 ms max
100 µs max Operation
Invalid Don’t
care
Ready/Busy
Power on FF
Reset
The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
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(5) Acceptable commands after Serial Input command “80h”
Once the Serial Input command “80h” has been input, do not input any command other than the Column
Address Change in Serial Data Input command “85h”, Auto Program command “10h”, Multi Page Program
command “11h”, Auto Program with Data Cache Command “15h”, or the Reset command “FFh”.
80 FF
WE
Address input
RY / BY
If a command other than “85h” , “10h” , “11h” , “15h” or “FFh” is input, the Program operation is not
performed and the device operation is set to the mode which the input command specifies.
80 XX 10
Mode specified by the command. Programming cannot be executed.
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.
From the LSB page to MSB page Ex.) Random page program (Prohibition)
DATA IN: Data (1) Data (64) DATA IN: Data (1) Data (64)
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(7) Status Read during a Read operation
00
[A]
Command 00 30 70
CE
WE
RY/BY
RE
Address N Status Read
command input Status output
Status Read
.
The device status can be read out by inputting the Status Read command “70h” in Read mode. Once the
device has been set to Status Read mode by a “70h” command, the device will not return to Read mode
unless the Read command “00h” is inputted during [A]. If the Read command “00h” is inputted during [A],
Status Read mode is reset, and the device returns to Read mode. In this case, data output starts
automatically from address N and address input is unnecessary
Fail
80 10 70 I/O 80 10
Address Data Address Data
M input N input
80
If the programming result for page address M is Fail, do not try to program the
10 page to address N in another block without the data input sequence.
Because the previous input data has been lost, the same input sequence of 80h
M command, address and data is necessary.
A pull-up resistor needs to be used for termination because the RY / BY buffer consists of an open drain
circuit.
VCC
Ready
VCC
VCC
R
Busy
Device
RY / BY
CL tf tr
Enable Programming
WE
DIN 80 10
WP
RY / BY
Disable Programming
WE
DIN 80 10
WP
RY / BY
Enable Erasing
WE
DIN 60 D0
WP
RY / BY
Disable Erasing
WE
DIN 60 D0
WP
RY / BY
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(11) When five address cycles are input
Although the device may read in a fifth address, it is ignored inside the chip.
Read operation
CLE
CE
WE
ALE
RY / BY
Program operation
CLE
CE
WE
ALE
I/O 80h
Ignored
Address input Data input
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(12) Several programming cycles on the same page (Partial Page Program)
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(13) Invalid blocks (bad blocks)
The device occasionally contains unusable blocks. Therefore, the following issues must be recognized:
Read Check :
Read either column 0 or 2048 of the 1st page or the
2nd page of each block. If the data of the column is not
Start FF (Hex), define the block as a bad block.
Block No = 1
Fail
Read Check
Pass
Block No. = Block No. + 1 Bad Block *1
No
Last Block
Yes
End
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(14) Failure phenomena for Program and Erase operations
The device may fail during a Program or Erase operation.
The following possible failure modes should be considered when implementing a highly reliable system.
Programming Failure
Single Bit ECC
“1 to 0”
• ECC: Error Correction Code. 1 bit correction per 512 Bytes is necessary.
• Block Replacement
Program
Block B
Erase
When an error occurs during an Erase operation, prevent future accesses to this bad block
(again by creating a table within the system or by using another appropriate scheme).
(15) Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery
is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data
and/or damage to data.
(16) The number of valid blocks is on the basis of single plane operations, and this may be decreased with two
plane operations.
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(17) Reliability Guidance
This reliability guidance is intended to notify some guidance related to using NAND flash with
1 bit ECC for each 512 bytes. For detailed reliability data, please refer to TOSHIBA’s reliability note.
Although random bit errors may occur during use, it does not necessarily mean that a block is bad.
Generally, a block should be marked as bad when a program status failure or erase status failure is detected.
The other failure modes may be recovered by a block erase.
ECC treatment for read data is mandatory due to the following Data Retention and Read Disturb failures.
• Write/Erase Endurance
Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read
after either an auto program or auto block erase operation. The cumulative bad block count will increase
along with the number of write/erase cycles.
• Data Retention
The data in memory may change after a certain amount of storage time. This is due to charge loss or charge
gain. After block erasure and reprogramming, the block may become usable again.
Here is the combined characteristics image of Write/Erase Endurance and Data Retention.
Data
Retention
[Years]
• Read Disturb
A read operation may disturb the data in memory. The data may change due to charge gain. Usually, bit
errors occur on other pages in the block, not the page being read. After a large number of read cycles
(between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another
state. After block erasure and reprogramming, the block may become usable again.
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Package Dimensions
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Revision History
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• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA’s written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts,
diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating
parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR
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noncompliance with applicable laws and regulations.
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