TC58NVG1S3BFT00/TC58NVG1S8BFT00

TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

2
2 GBIT (256M × 8 BIT/128M × 16 BIT) CMOS NAND E PROM
DESCRIPTION
The TC58NVG1SxB is a single 3.3 V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes/(1024 + 32) words × 64 pages × 2048 blocks.
The device has a 2112-byte/1056-word static register which allow program and read data to be transferred between
the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single
block unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages).
The TC58NVG1SxB is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.

FEATURES
• Organization
TC58NVG1S3B TC58NVG1S8B
Memory cell array 2112 × 128K × 8 1056 × 128K × 16
Register 2112 × 8 1056 × 16
Page size 2112 bytes 1056 words
Block size (128K + 4K) bytes (64K + 2K) words

• Modes
Read, Reset, Auto Page Program, Auto Block Erase，Status Read

• Mode control
Serial input/output
Command control

• Number of valid blocks

Max 2048 blocks
Min 2008 blocks

• Power supply
VCC = 2.7 V to 3.6 V

• Program/Erase Cycles
100000 Cycles (With ECC)

• Access time
Cell array to register 25 µs max
Serial Read Cycle 50 ns min

• Program/Erase time
Auto Page Program 200 µs/page typ.
Auto Block Erase 1.5 ms/block typ.

• Operating current
Read (50 ns cycle) 10 mA typ.
Program (avg.) 10 mA typ.
Erase (avg.) 10 mA typ.
Standby 50 µA max

• Package
TC58NVG1S3BFT00 TSOP I 48-P-1220-0.50
TC58NVG1S8BFT00 TSOP I 48-P-1220-0.50
(Weight: 0.53 g typ.)

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PIN ASSIGNMENT (TOP VIEW)

TC58NVG1S8BFT00

TC58NVG1S3BFT00

×16 ×8 ×8 ×16

NC NC 1 48 NC VSS
NC NC 2 47 NC I/O16
NC NC 3 46 NC I/O8
NC NC 4 45 NC I/O15
NC NC 5 44 I/O8 I/O7
GND GND 6 43 I/O7 I/O14
RY / BY RY / BY 7 42 I/O6 I/O6
RE RE 8 41 I/O5 I/O13
CE CE 9 40 NC I/O5
NC NC 10 39 PSL PSL
NC NC 11 38 NC NC
VCC VCC 12 37 VCC VCC
VSS VSS 13 36 VSS NC
NC NC 14 35 NC NC
NC NC 15 34 NC NC
CLE CLE 16 33 NC I/O12
ALE ALE 17 32 I/O4 I/O4
WE WE 18 31 I/O3 I/O11
WP WP 19 30 I/O2 I/O3
NC NC 20 29 I/O1 I/O10
NC NC 21 28 NC I/O2
NC NC 22 27 NC I/O9
NC NC 23 26 NC I/O1
NC NC 24 25 NC VSS

PINNAMES

I/O1 to I/O8 I/O port

I/O9 to I/O16 I/O port (×16)

CE Chip enable

WE Write enable

RE Read enable

CLE Command latch enable

ALE Address latch enable

PSL Power on select

WP Write protect

RY/BY Ready/Busy

GND Ground

VCC Power supply

VSS Ground

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BLOCK DIAGRAM

VCC VSS
Status register

I/O1 Address register Column buffer

I/O
to Column decoder
Control circuit
I/O8 Command register Data register
or
I/O16 Sense amp

CE

Row address decoder

Row address buffer
CLE
ALE

decoder
WE Logic control Control circuit Memory cell array
RE
WP
PSL

RY / BY
RY / BY HV generator

ABSOLUTE MAXIMUM RATINGS

SYMBOL RATING VALUE UNIT

VCC Power Supply Voltage −0.6 to 4.6 V

VIN Input Voltage −0.6 to 4.6 V

VI/O Input /Output Voltage −0.6 V to VCC + 0.3 V (≤ 4.6 V) V

PD Power Dissipation 0.3 W

TSOLDER Soldering Temperature (10 s) 260 °C

TSTG Storage Temperature −55 to 150 °C

TOPR Operating Temperature 0 to 70 °C

CAPACITANCE *(Ta = 25°C, f = 1 MHz)

SYMB0L PARAMETER CONDITION MIN MAX UNIT

CIN Input VIN = 0 V  10 pF

COUT Output VOUT = 0 V  10 pF

* This parameter is periodically sampled and is not tested for every device.

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VALID BLOCKS
SYMBOL PARAMETER MIN TYP. MAX UNIT

NVB Number of Valid Blocks 2008  2048 Blocks

NOTE: The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The minimum number of valid blocks is guaranteed over the lifetime.

RECOMMENDED DC OPERATING CONDITIONS

SYMBOL PARAMETER MIN TYP. MAX UNIT

VCC Power Supply Voltage 2.7 V  3.6 V V

VIH High Level input Voltage 2.7 V ≤ VCC ≤ 3.6 V 2.0  VCC + 0.3 V

VIL Low Level Input Voltage 2.7 V ≤ VCC ≤ 3.6 V −0.3*  0.8 V

* −2 V (pulse width lower than 20 ns)

DC CHARACTERISTICS (Ta = 0 to 70℃, VCC = 2.7 V to 3.6 V)

SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT

IIL Input Leakage Current VIN = 0 V to VCC   ±10 µA

ILO Output Leakage Current VOUT = 0 V to VCC   ±10 µA

PSL = GND or NC  10 30
ICCO0* Power On Reset Current PSL = VCC, FFh command input after mA
 10 30
Power On

ICCO1 Serial Read Current CE = VIL, IOUT = 0 mA, tcycle = 50 ns  10 30 mA

ICCO2 Programming Current   10 30 mA

ICCO3 Erasing Current   10 30 mA

ICCS1 Standby Current CE = VIH, WP = 0 V/VCC   1 mA

ICCS2 Standby Current CE = VCC − 0.2 V, WP = 0 V/VCC  10 50 µA

VOH High Level Output Voltage IOH = −0.4 mA (2.7 V ≤ VCC ≤ 3.6 V) 2.4   V

VOL Low Level Output Voltage IOL = 2.1 mA (2.7 V ≤ VCC ≤ 3.6 V)   0.4 V

IOL Output current of RY / BY

VOL = 0.4 V (2.7 V ≤ VCC ≤ 3.6 V)  8  mA
( RY / BY ) pin

* Refer to application note (2) for detail

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AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70℃, VCC = 2.7 V to 3.6 V)

SYMBOL PARAMETER MIN MAX UNIT NOTES

tCLS CLE Setup Time 0  ns

tCLH CLE Hold Time 10  ns

tCS CE Setup Time 0  ns

tCH CE Hold Time 10  ns

tWP Write Pulse Width 25  ns

tALS ALE Setup Time 0  ns

tALH ALE Hold Time 10  ns

tDS Data Setup Time 20  ns

tDH Data Hold Time 10  ns

tWC Write Cycle Time 50  ns

tWH WE High Hold Time 15  ns

tWW WP High to WE Low 100  ns

tRR Ready to RE Falling Edge 20  ns

tRW Ready to WE Falling Edge 20  ns

tRP Read Pulse Width 35  ns

tRC Read Cycle Time 50  ns

tREA RE Access Time  35 ns

tCEA CE Access Time  45 ns

tCLEA CLE Access Time  45 ns

tALEA ALE Access Time  45 ns

tOH Data Output Hold Time 10  ns

tRHZ RE High to Output High Impedance  30 ns

tCHZ CE High to Output High Impedance  20 ns

tREH RE High Hold Time 15  ns

tIR Output-High-impedance-to- RE Falling Edge 0  ns

tRHW RE High to WE Low 30  ns

tWHC WE High to CE Low 30  ns

tWHR WE High to RE Low 30  ns

tR Memory Cell Array to Starting Address  25 µs

tWB WE High to Busy  200 ns

tRST Device Reset Time (Ready/Read/Program/Erase)  6/6/10/500 µs

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AC TEST CONDITIONS
CONDITION
PARAMETER
2.7 V ≤ VCC ≤ 3.6 V

Input level 2.4 V, 0.4 V

Input pulse rise and fall time 3ns

Input comparison level 1.5 V, 1.5 V

Output data comparison level 1.5 V, 1.5 V

Output load CL (100 pF) + 1 TTL

Note: Busy to ready time depends on the pull-up resistor tied to the RY / BY pin.
(Refer to Application Note (9) toward the end of this document.)

PROGRAMMING AND ERASING CHARACTERISTICS

(Ta = 0 to 70℃, VCC = 2.7 V to 3.6 V)

SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES

tPROG Average Programming Time  200 500 µs

N Number of Partial Program Cycles in the Same Page   8 (1)

tBERASE Block Erasing Time  1.5 3 ms

(1) Refer to Application Note (12) toward the end of this document.

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TIMING DIAGRAMS

Latch Timing Diagram for Command/Address/Data

CLE
ALE
CE
RE Setup Time Hold Time

WE

tDS tDH

I/O

: VIH or VIL

Command Input Cycle Timing Diagram

CLE
tCLS tCLH
tCS tCH

CE

tWP

WE

tALS tALH

ALE

tDS tDH

I/O

: VIH or VIL

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Address Input Cycle Timing Diagram

tCLS

CLE

tCS tWC tWC tWC tWC

CE

tWP tWH tWP tWH tWP tWH tWP tWH tWP

WE

tALS tALH

ALE

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH

I/O CA0 to 7 CA8 to 11 PA0 to 7 PA8 to 15 PA16

: VIH or VIL

Data Input Cycle Timing Diagram

tCLH

CLE

tCH

CE

tALS tWC

ALE

tWP tWH tWP tWP

WE

tDS tDH tDS tDH tDS tDH

I/O DIN0 DIN1 DIN2111*

*) ×16: 1055 : VIH or VIL

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Serial Read Cycle Timing Diagram

tRC tCEA

CE

tRP tREH tRP tRP tCHZ

RE
tOH tOH tOH
tREA tRHZ tREA tRHZ tREA tRHZ

I/O

tRR

RY / BY

Status Read Cycle Timing Diagram

tCLEA

CLE
tCLS tCLH

tCS

CE

tWP tCH

WE
tWHC tCEA tCHZ
tWHR

RE
tOH
tDS tDH tIR
tREA
tRHZ
Status
I/O 70h*
output

RY / BY

*: 70h represents the hexadecimal number : VIH or VIL

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Read Cycle Timing Diagram

tCLEA

CLE
tCLS tCLH tCLS tCLH

tCS tCH tCS tCH tCEA

CE

tWC

WE
tALH tALS tALH tALS

ALE

tR tRC

RE tWB

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tRR tREA

CA0 CA8 PA0 PA8 DOUT DOUT

I/O 00h PA16 30h
to 7 to 11 to 7 to 15 N N+1

Data out from

Col. Add. N Col. Add. N
RY / BY

Read Cycle Timing Diagram: When Interrupted by CE

tCLEA

CLE
tCLS tCLH tCLS tCLH

tCS tCH tCS tCH tCEA

CE

tWC

WE
tALH tALS tALH tALS tCHZ

ALE

tR tRC tRHZ

RE tWB

tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tRR tREA tOH

CA0 CA8 PA0 PA8 DOUT DOUT

I/O 00h PA16 30h
to 7 to 11 to 7 to 15 N N+1

Col. Add. N Col. Add. N

RY / BY

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Column Address Change in Read Cycle Timing Diagram (1/2)

tCLEA

CLE
tCLS tCLH tCLS tCLH

tCS tCH tCS tCH

CE
tWC
tCEA
WE

tALH tALS tALH tALS

ALE

tR tRC

tWB
RE
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tRR tREA

CA0 CA8 PA0 PA8 DOUT DOUT DOUT

I/O 00h PA16 30h
to 7 to 11 to 7 to 15 A A+1 A+N
Column address Page address Page address
A P P

RY / BY

Column address
A

Continues from 1 of next page

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Column Address Change in Read Cycle Timing Diagram (2/2)

tCLEA

CLE
tCLS tCLH tCLS tCLH

tCS tCH tCS tCH

CE

tRHW tWC tCEA

WE
tALH tALS tALH tALS

ALE

tRC

RE
tDS tDH tDS tDH tDS tDH tDS tDH tREA
tIR
DOUT CA0 CA8 DOUT DOUT DOUT
I/O 05h E0h
A+N to 7 to 11 B B+1 B + N’
Column address Page address
B P

RY / BY

Column address
B

Continues from 1 of next page

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Auto-Program Operation Timing Diagram

tCLS

CLE
tCLS tCLH
tCS tCS

CE

tCH

WE
tALH tALH
tALS tPRPG
tALS
tWB

ALE

RE tDS
tDS
tDS tDH tDS tDH tDH tDH

CA0 CA8 PA0 PA8 Status

I/O 80h PA16 DINN DIN DINM* 10h 70h
to 7 to 11 to 7 to 15 output
Column address
N

RY / BY
: Do not input data while data is being output.

: VIH or VIL

*) M: up to 2112 (byte input data for ×8 device).

M: up to 1056 (word input data for ×16 device).

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Auto Block Erase Timing Diagram

CLE
tCLS
tCLH
tCS
tCLS
CE

WE
tALH
tALS tWB tBERASE

ALE

RE

tDS tDH

PA0 PA8 Status

I/O 60h to 7 PA16 D0h 70h
to 15 output

Busy
RY / BY Auto Block Erase Start Status Read
Erase Setup command command
command

: VIH or VIL : Do not input data while data is being output.

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ID Read Operation Timing Diagram

tCLS

CLE
tCLS
tCS tCS tCH tCEA

CE

tCH

WE
tALS tALH
tALH tALEA

ALE

RE
tDH
tDH
tREA tREA tREA tREA tREA

See See See

I/O 90h 00h 98h DAh Table 5 Table 5 Table 5

ID Read Address Maker code Device code

command 00
: VIH or VIL

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PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information.

Command Latch Enable: CLE

The CLE input signal is used to control loading of the operation mode command into the internal command
register. The command is latched into the command register from the I/O port on the rising edge of the WE
signal while CLE is High.

Address Latch Enable: ALE

The ALE signal is used to control loading address information into the internal address register. Address
information is latched into the address register from the I/O port on the rising edge of WE while ALE is High.

Chip Enable: CE
The device goes into a low-power Standby mode when CE goes High during the device is in Ready state. The
CE signal is ignored when device is in Busy state ( RY / BY = L), such as during a Program or Erase or Read
operation, and will not enter Standby mode even if the CE input goes High.

Write Enable: WE
The WE signal is used to control the acquisition of data from the I/O port.

Read Enable: RE
The RE signal controls serial data output. Data is available tREA after the falling edge of RE .
The internal column address counter is also incremented (Address = Address + l) on this falling edge.

I/O Port: I/O1 to 8

The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
the device.

I/O Port: I/O9 to 16 (×16 device)

The I/O9 to 16 pins are used as a port for transferring input/output data to and from the device. I/O9 to 16
pins must be low level (VIL) when address and command are input.

Write Protect: WP
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.

Ready/Busy: RY / BY
The RY / BY output signal is used to indicate the operating condition of the device. The RY / BY signal is
in Busy state ( RY / BY = L) during the Program, Erase and Read operations and will return to Ready state
( RY / BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be
pulled-up to Vccq with an appropriate resister.

Power on Select: PSL

The PSL signal is used to select whether the device initialization should take place during the device power
on or during the first Reset. Please refer to the application note (2) for details.

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Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.

I/O1

Page Buffer 2048 64 I/O8

A page consists of 2112 bytes in which 2048 bytes are
used for main memory storage and 64 bytes are for
redundancy or for other uses.
64 Pages = 1 block
1 page = 2112 bytes
131072 1 block = 2112 bytes × 64 pages = (128K + 4K) bytes
pages Capacity = 2112 bytes × 64pages x 2048blocks
2048 blocks

8I/O

2112

I/O1

Page Buffer 1024 32 I/O16

A page consists of 1056 words in which 1024 words are
used for main memory storage and 32 words are for
redundancy or for other uses.
64 Pages = 1 block
1 page = 1056 words
131072 1 block = 1056 words × 64 pages = (64K + 2K) words
pages
2048 blocks Capacity = 1056 words × 64 pages × 2048 blocks

16I/O An address is read in via the I/O port over three

1056 consecutive clock cycles, as shown in Table 1.

Table 1. Addressing

I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1

CA0 to CA11: Column address
PA0 to PA16: Page address
First cycle CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

Second cycle L L L L CA11 CA10 CA9 CA8 PA6 to PA16: Block address
PA0 to PA5: NAND address in block
Third cycle PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Fourth cycle PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8

Fifth cycle L L L L L L L PA16

Note) I/O9 − 16 must be held low when address is input (×16 device).

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Operation Mode: Logic and Command Tables

The operation modes such as Program, Erase, Read and Reset are controlled by command operations shown
in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE , WE ,
RE and WP signals, as shown in Table 2.

Table 2. Logic Table

*1
CLE ALE CE WE RE WP

Command Input H L L H *

Data Input L L L H H

Address input L H L H *

Serial Data Output L L L H *

During Program (Busy) * * * * * H

During Erase (Busy) * * * * * H

* * H * * *
During Read (Busy)
* * L H (*2) H (*2) *

Program, Erase Inhibit * * * * * L

Standby * * H * * 0 V/VCC

H: VIH, L: VIL, *: VIH or VIL

*1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit
*2: If CE is low during read busy, WE and RE must be held High to avoid unintended command/address input to the device or
read to device. Reset or Status Read command can be input during Read Busy.

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Table 3. Command table (HEX)

First Cycle Second Cycle Acceptable while Busy

Serial Data Input 80 

Read 00 30

Column Address Change in Serial Data Output 05 E0

Auto Page Program 80 10

Column Address Change in Serial Data Input 85 

Auto Block Erase 60 D0

ID Read 90 

Status Read 70  {

Reset FF  {

Table 4 shows the operation states for Read mode.

Table 4. Read mode operation states

CLE ALE CE WE RE I/O1 to I/O8 (I/O16) Power

Output select L L L H L Data output Active

Output Deselect L L L H H High impedance Active

H: VIH, L: VIL, *: VIH or VIL

HEX data bit assignment

(Example) Serial Data Input: 80h

0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
I/O16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 I/O1

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DEVICE OPERATION
Read Mode
Read mode is set when the "00h" and “30h” commands are issued to the Command register. Between the two
commands, a start address for the Read mode needs to be issued. Refer to the figures below for the sequence and
the block diagram (Refer to the detailed timing chart.).

CLE

CE

WE

ALE

RE

RY / BY Column Address M Page Address N Busy tR

I/O 00h 30h M M+1 M+2

Page Address N
Start-address input
A data transfer operation from the cell array to the register
starts on the rising edge of WE in the 30h command input
M m cycle (after the address information has been latched). The
device will be in the Busy state during this transfer period.
Select page After the transfer period, the device returns to Ready state.
Serial data can be output synchronously with the RE clock
N Cell array
from the start address designated in the address input cycle.

I/O1 to 8: m = 2111
I/O1 to 16: m = 1055

Random Column Address Change in Read Cycle

CLE

CE

WE

ALE

RE

RY / BY
Busy
tR
Col. M
00h 30h M M+1 M+2 M+3 05h E0h M’ M’+1 M’+2 M’+3 M’+4
I/O

Col. M Page N Col. M’

Page N Page N
Start-address input Start from Col. M Start from Col. M’
During the serial data output from the register the column
M M’ address can be changed by inputting a new column address
using the 05h and E0h commands. The data is read out in serial
starting at the new column address. Random Column Address
Change operation can be done multiple times within the same
Select page
page.
N Cell array

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Auto Page Program Operation

The device carries out an Automatic Page Program operation when it receives a "10h" Program command
after the address and data have been input. The sequence of command, address and data input is shown below.
(Refer to the detailed timing chart.)

CLE

CE

WE

ALE

RE

RY/BY

I/O 80h Din Din Din Din 10h 70h

Col. M Page P Data

The data is transferred (programmed) from the register to the

Data input selected page on the rising edge of WE following input of the “10h”
Program Read& verification command. After programming, the programmed data is transferred
back to the register to be automatically verified by the device. If the
programming does not succeed, the Program/Verify operation is
repeated by the device until success is achieved or until the
maximum loop number set in the device is reached.

Random Column Address Change in Auto Page Program Operation

The column address can be changed by the 85h command during the data input sequence of the Auto Page
Program operation.
Two address input cycles after the 85h command are recognized as a new column address for the data input.
After the new data is input to the new column address, the 10h command initiates the actual data program into the
selected page automatically. The Random Column Address Change operation can be repeated multiple times within
the same page.

80h Din Din Din Din 85h Din Din 10h Status

Col. M Page N Col. M’ Busy

Col. M Col. M’

Data input

Program Reading & verification

Selected
page

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Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which
follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an extra layer of
protection from accidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.

Pass
60 D0 70 I/O
Block Address Erase Start Status Read Fail
input: 3 cycles command command

RY / BY Busy

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ID Read
The device contains ID codes which can be used to identify the device type, the manufacturer, and features of
the device. The ID codes can be read out under the following timing conditions:

CLE
tCEA
CE

WE
tALEA

ALE

RE
tREA
See See See
I/O 90h 00h 98h DAh
table 5 table 5 table 5
ID Read Address 00 Maker code Device code
command
For the specifications of the access times tREAI, tCEA and tALEA refer to the AC Characteristics.

Table 5. Code table

Description I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Hex Data

1st Data Maker Code 1 0 0 1 1 0 0 0 98h

2nd Data Device Code 1 1 0 1 1 0 1 0 DAh

Chip Number, Cell Type, PGM

3rd Data 0 or 1 0 0 0 0 0 0 0 00h or 80h
Page

Page Size, Block Size, ×8) 15h or 95h

4th Data 0 or 1 0 or 1 0 1 0 1 0 1
Redundant Size, Organization ×16) 55h or D5h

5th Data Plane Number, Plane Size 0 or 1 1 0 0 0 1 0 0 44h or C4h

3rd Data

Description I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1

1 0 0
2 0 1
Internal Chip Number
4 1 0
8 1 1

2 level cell 0 0
4 level cell 0 1
Cell Type
8 level cell 1 0
16 level cell 1 1

1 0 0
Number of simultaneously 2 0 1
programmed pages 4 1 0
8 1 1

0
Reserved
0 or 1

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4th Data

Description I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1

1 KB 0 0
Page Size 2 KB 0 1
(without redundant area) 4K KB 1 0
8 KB 1 1

64 KB 0 0
Block Size 128 KB 0 1
(without redundant area) 256 KB 1 0
512 KB 1 1

8 0 0
Redundant area size 16 0 1
(byte/512byte) Reserved 1 0
Reserved 1 1

×8 0
Organization
×16 1

Reserved 0 or 1

5th Data

Description I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1

1 0 0
2 0 1
Plane Number
4 1 0
8 1 1

64 Mbit 0 0 0
128 Mbit 0 0 1
256 Mbit 0 1 0
512 Mbit 0 1 1
Plane Size
1 Gbit 1 0 0
2 Gbit 1 0 1
4 Gbit 1 1 0
8 Gbit 1 1 1

3 V only 0
Power Supply
1.8 V & 3.3 V dual 1

Reserved 0 or 1 0

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Status Read
The device automatically implements the execution and verification of the Program and Erase operations.
The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass
/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is
output via the I/O port using RE after a “70h” command input. The Status Read can also be used during a
Read operation to find out the Ready/Busy status.
The resulting information is outlined in Table 6.

Table 6. Status output table

Page Program
Definition Read
Block Erase

Chip Status1
I/O1 Pass/Fail Invalid
Pass: 0 Fail: 1

I/O2 Not Used Invalid Invalid

I/O3 Not Used 0 0

I/O4 Not Used 0 0

I/O5 Not Used 0 0

Ready/Busy
I/O6 Ready/Busy Ready/Busy
Ready: 1 Busy: 0

Ready/Busy
I/O7 Ready/Busy Ready/Busy
Ready: 1 Busy: 0

Write Protect
I/O8 Write Protect Write Protect
Not Protected :0 Protected: 1

I/O9 to 16 Not used Not used Not used

The Pass/Fail status on I/O1 is only valid during a Program/Erase operation when the device is in the Ready state.

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An application example with multiple devices is shown in the figure below.

CE1 CE2 CE3 CEN CEN + 1

CLE
ALE Device Device Device Device Device
WE 1 2 3 N N+1
RE

I/O1
to I/O8
RY / BY

RY / BY Busy

CLE

ALE

WE

CE1

CEN

RE

I/O 70h 70h

Status on Device 1 Status on Device N

System Design Note: If the RY / BY pin signals from multiple devices are wired together as shown in the
diagram, the Status Read function can be used to determine the status of each individual device.

Reset

The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally
generated voltage is discharged to 0 volt and the device enters the Wait state.
The response to a “FFh” Reset command input during the various device operations is as follows:

When a Reset (FFh) command is input during programming

80 10 FF 00

Internal VPP

RY / BY

tRST (max 10 µs)

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When a Reset (FFh) command is input during erasing

D0 FF 00

Internal erase
voltage

RY / BY

tRST (max 500 µs)

When a Reset (FFh) command is input during Read operation

00 30 FF 00

RY / BY

tRST (max 6 µs)

When a Reset (FFh) command is input during Ready

FF 00

RY / BY
tRST (max 6 µs)

When a Status Read command (70h) is input after a Reset

FF 70
I/O status: Pass/Fail → Pass
: Ready/Busy → Ready
RY / BY

When two or more Reset commands are input in succession

(1) (2) (3)

10 FF FF FF

RY / BY

The second FF command is invalid, but the third FF command is valid.

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APPLICATION NOTES AND COMMENTS

(1) Power-on/off sequence:

The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power
on sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in the
figure below. In this time period, the acceptable commands are FFh or 70h.
The WP signal is useful for protecting against data corruption at power-on/off.

2.7 V
2.5 V

VCC
0 V
Don’t Don’t
care care
CE , WE , RE
CLE, ALE
VIH

VIL VIL
WP 1 ms max
100 µs max Operation

Invalid Don’t
care
Ready/Busy

(2) Power-on Reset

The device goes into automatic self initialization during power on if PSL is tied either to GND or NC.
During the initialization process, the device consumes a maximum current of 30 mA (ICCO0). If PSL is tied
to VCC, the device will not complete its self initialization during power on and will not consume ICCO0, and
completes the initialization process with the first Reset command input after power on. During the first FFh
reset Busy period, the device consumes a maximum current of 30 mA (ICCO0). In either case (PSL = GND/
NC or VCC), the following sequence is necessary because some input signals may not be stable at power-on.

Power on FF

Reset

(3) Prohibition of unspecified commands

The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.

(4) Restriction of commands while in the Busy state

During the Busy state, do not input any command except 70h and FFh.

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(5) Acceptable commands after Serial Input command “80h”
Once the Serial Input command “80h” has been input, do not input any command other than the Column
Address Change in Serial Data Input command “85h”, Auto Program command “10h”, or the Reset command
“FFh”.

80 FF

WE
Address input

RY / BY

If a command other than “85h”, “10h” or “FFh” is input, the Program operation is not performed and the
device operation is set to the mode which the input command specifies.

80 XX 10
Mode specified by the command. Programming cannot be executed.

Command other than

“85h”, “10h” or “FFh”

(6) Addressing for program operation

Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.

From the LSB page to MSB page Ex.) Random page program (Prohibition)

DATA IN: Data (1) Data (64) DATA IN: Data (1) Data (64)

Data register Data register

Page 0 (1) Page 0 (2)

Page 1 (2) Page 1 (32)
Page 2 (3) Page 2 (3)

Page 31 (32) Page 31 (1)

Page 63 (64) Page 63 (64)

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(7) Status Read during a Read operation

00

[A]
Command 00 30 70

CE

WE

RY/BY

RE
Address N Status Read
command input Status output
Status Read
.

The device status can be read out by inputting the Status Read command “70h” in Read mode. Once the
device has been set to Status Read mode by a “70h” command, the device will not return to Read mode
unless the Read command “00h” is input during [A]. In this case, data output starts automatically from
address N and address input is unnecessary

(8) Auto programming failure

Fail
80 10 70 I/O 80 10
Address Data Address Data
M input N input
80
If the programming result for page address M is Fail, do not try to program the
10 page to address N in another block without the data input sequence.
Because the previous input data has been lost, the same input sequence of 80h
M command, address and data is necessary.

(9) RY / BY : termination for the Ready/Busy pin ( RY / BY )

A pull-up resistor needs to be used for termination because the RY / BY buffer consists of an open drain
circuit.

VCC
Ready
VCC
VCC 3.0 V
R
1.0 V Busy 1.0 V
Device
RY / BY
CL tf tr

VSS VCC = 3.3 V

1.5 µs Ta = 25°C 15 ns
tf CL = 100 pF
tr 1.0 µs 10 ns tf
tr
This data may vary from device to device. 0.5 µs 5 ns
We recommend that you use this data as a
reference when selecting a resistor value. 0
1 KΩ 2 KΩ 3 KΩ 4 KΩ
R
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(10) Note regarding the WP signal
The Erase and Program operations are automatically reset when WP goes Low. The operations are
enabled and disabled as follows:

Enable Programming

WE

DIN 80 10

WP

RY / BY

tWW (100 ns MIN)

Disable Programming

WE

DIN 80 10

WP

RY / BY

tWW (100 ns MIN)

Enable Erasing

WE

DIN 60 D0

WP

RY / BY

tWW (100 ns MIN)

Disable Erasing

WE

DIN 60 D0

WP

RY / BY

tWW (100 ns MIN)

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(11) When six address cycles are input
Although the device may read in a sixth address, it is ignored inside the chip.

Read operation

CLE

CE

WE

ALE

I/O 00h 30h

Ignored
Address input

RY / BY

Program operation

CLE

CE

WE

ALE

I/O 80h

Ignored
Address input Data input

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(12) Several programming cycles on the same page (Partial Page Program)
A page can be divided into up to 8 segments as follows:

Data area (column address 0 to 2047) : 512 bytes × 4 segments

1st segment: column address 0 to 511
2nd segment: column address 512 to 1023
3rd segment: column address 1024 to 1535
4th segment: column address 1536 to 2047

Redundant area (column address 2048 to 2111) : 16 bytes × 4 segments

1st segment: column address 2048 to 2063
2nd segment: column address 2064 to 2079
3rd segment: column address 2080 to 2095
4th segment: column address 2096 to 2111

Each segment can be programmed individually as follows:

1st programming Data Pattern 1 All 1 s

2nd programming All 1 s Data Pattern 2 All 1 s

8th programming All 1 s Data Pattern 8

Result Data Pattern 1 Data Pattern 2 Data Pattern 8

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(13) Invalid blocks (bad blocks)
The device occasionally contains unusable blocks. Therefore, the following issues must be recognized:

At the time of shipment, all data bytes in a valid block are FFh. For bad
blocks, all bytes are not in the FFh state. Please do not perform an erase
operation to bad blocks. It may be impossible to recover the bad block
Bad Block information if the information is erased.
Check if the device has any bad blocks after installation into the system.
Refer to the test flow for bad block detection. Bad blocks which are
detected by the test flow must be managed as unusable blocks by the
system.
Bad Block
A bad block does not affect the performance of good blocks because it is
isolated from the bit lines by select gates.

The number of valid blocks at the time of shipment is as follows:

MIN TYP. MAX UNIT

Valid (Good) Block Number 2008  2048 Block

Bad Block Test Flow

Start Read Check: Read either column 0 or 2048 of the

1st page or the 2nd page of each
block. If the data of the column is
not FF (Hex), define the block as a
bad block.
Block No = 1

Fail
Read Check

Pass
Block No. = Block No. + 1 Bad Block *1

No
Block No. = 2048

Yes

End

*1: No erase operation is allowed to detected bad blocks

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(14) Failure phenomena for Program and Erase operations
The device may fail during a Program or Erase operation.
The following possible failure modes should be considered when implementing a highly reliable system.

FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE

Block Erase Failure Status Read after Erase → Block Replacement

Page Programming Failure Status Read after Program → Block Replacement

Programming Failure
Single Bit ECC
“1 to 0”

• ECC: Error Correction Code. 2 bits per page is necessary.

In case the 2 Kbyte page is divided into segments of 512 bytes, 1 bit correction per segment is
necessary.
• Block Replacement

Program

Error occurs When an error happens in Block A, try to reprogram the

Buffer data into another Block (Block B) by loading from an
memory external buffer. Then, prevent further system accesses
Block A
to Block A ( by creating a bad block table or by using
another appropriate scheme).

Block B

Erase

When an error occurs during an Erase operation, prevent future accesses to this bad block
(again by creating a table within the system or by using another appropriate scheme).

(15) Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery
is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data
and/or damage to data.

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Package Dimensions

Weight: 0.53 g (typ.)

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RESTRICTIONS ON PRODUCT USE 030619EBA

• The information contained herein is subject to change without notice.

• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced
and sold, under any law and regulations.

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