DASF0014495

TC58NC344CF
TC58NC344CF
1Chip Small Flash Disk Controller
OUTLINE
(*)
TC58NC344CF is a 1chip Small Flash Disk Controller which has PC Card ATA and IDE Interfaces. TC58NC344CF is
TM
1 chip small flash disk controller which can connect one 8M to 1G NAND Flash Memory and SmartMedia , and can
configure 1M to 128 Mbyte Flash Disk ATA, SmartMedia ATA Adapter and IDE Drives.
FEATURES
1. PC Card ’97 Standards compatibility
2. PC Card ATA/IDE Interfaces
3. Conforms 8M to 1 Gbit NAND type Flash Memory
TM
4. Conforms 1M to 128 Mbyte SmartMedia
TM
5. Conforms 4M to 128Mbyte Mask ROM SmartMedia
TM
6. Compatible with SSFDC Forum “SmartMedia Physical Format”
7. Write Protect Function
8. Conforms 8/16-bit Accesses
9. Embedded ECC Function
10. Automatic Power Down Function
11. 4 power modes (Sleep, Standby, Idle and Active)
12. Packaged Configuration which can generate PC Card Type I: 100-pin TQFP (Lead Pitch: 0.5 mm)
13. CMOS, Host Interface: 3.3/5 V, Flash Interface: 3.3/5 V, Internal: 3.3 V Power Source
NOTES
1. Confirm the comment in the box of bellow.
2. Be sure to refer to “Notes about SmartMedia Adapter” on page 13 of this document.
3. Recommend referring to an attached sheet “TC58NC344 reference design” ,when you design in.
TM
* SmartMedia is the registered trademark of TOSHIBA Corporation
• TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless,
semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and
vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to
observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA
product could cause loss of human life, bodily injury or damage to property. In developing your designs,
please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent products specifications. Also, please keep in mind the precautions and conditions set forth in the
TOSHIBA Semiconductor Reliability Handbook.
• Please do not use this device in the following applications
- special applications such as military related equipment, nuclear reactor control, and aerospace.
- control devices for automotive vehicles, train, ship and traffic equipment
- safety system for disaster prevention and crime prevention
- medical related equipment including medical measurement devices.
TOSHIBA do not guarantee any liability for loss or damage caused by the use in these applications.
• The products described in this document are subject to foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or
other rights of the third parties which may result from its use. No license is granted by implication or
otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
2001-03-25 1/91
TC58NC344CF
CONTENTS
Pin Assignment Table ･･･････････････････････････････････････････････････････････････････････････････････ 3

Pin Descriptions ････････････････････････････････････････････････････････････････････････････････････････ 7
Notes ･････････････････････････････････････････････････････････････････････････････････････････････ 13
Function Description ････････････････････････････････････････････････････････････････････････････････････ 14
1. Interface Outline ･････････････････････････････････････････････････････････････････････････････････ 14
2. System Configuration Example ･････････････････････････････････････････････････････････････････････ 14
3. Host Interfaces･･･････････････････････････････････････････････････････････････････････････････････ 15
4. PC Card Interfaces ･･･････････････････････････････････････････････････････････････････････････････ 15
5. IDE Interface ････････････････････････････････････････････････････････････････････････････････････ 22
ATA Commands ････････････････････････････････････････････････････････････････････････････････････････ 33
1. ATA Command Block ･････････････････････････････････････････････････････････････････････････････ 33
2. ATA Command Block Register Operation ････････････････････････････････････････････････････････････ 33
3. ATA Command Codes and Parameters ･･････････････････････････････････････････････････････････････ 34
4. ATA Command Error Message Table ････････････････････････････････････････････････････････････････ 35
5. ATA Command Description ････････････････････････････････････････････････････････････････････････ 36
Standard ATA Commands ･･････････････････････････････････････････････････････････････････････ 36
Vendor Unique ATA Commands ･････････････････････････････････････････････････････････････････ 67
Reset Operation････････････････････････････････････････････････････････････････････････････････････････ 68
Power Management ････････････････････････････････････････････････････････････････････････････････････ 69
EEPROM Interface ･････････････････････････････････････････････････････････････････････････････････････ 70
Drive Capacity ･････････････････････････････････････････････････････････････････････････････････････････ 71
Flash Memory Identification Method ･･･････････････････････････････････････････････････････････････････････ 71
Others ････････････････････････････････････････････････････････････････････････････････････････････････ 72
Absolute Maximum Ratings ･･････････････････････････････････････････････････････････････････････････････ 73
Operating Ranges ･･････････････････････････････････････････････････････････････････････････････････････ 73
DC Characteristics･･････････････････････････････････････････････････････････････････････････････････････ 74
Capacitance ･･･････････････････････････････････････････････････････････････････････････････････････････ 75
Switching Characteristics ････････････････････････････････････････････････････････････････････････････････ 76
1. PC Card Interface ････････････････････････････････････････････････････････････････････････････････ 76
2. IDE Interface ････････････････････････････････････････････････････････････････････････････････････ 80
3. Flash Interface ･･･････････････････････････････････････････････････････････････････････････････････ 82
4. Clock Input Timing････････････････････････････････････････････････････････････････････････････････ 84
5. Reset Input Condition ･････････････････････････････････････････････････････････････････････････････ 84
6. Reset Sequence ･････････････････････････････････････････････････････････････････････････････････ 85
Physical Dimensions ････････････････････････････････････････････････････････････････････････････････････ 86
[Notes]
1. This product is compatible with PC Card ’97 Standards.
TM
2. This product is standardized by SSFDC Forum and is compatible with the SmartMedia Physical Format
Specifications.
3. It is possible to use NAND Flash Memory compatible with Flash Interface.
4. The voltage level display depends on whether the signal is input or output.
5. “Hi-Z” used in this manual represents the high-impedance state.
6. This product is not supported 2-Drive Protocol.
Voltage Level Input Signal Output Signal
VDD 1 H
VSS 0 L
2001-03-25 2/91
TC58NC344CF
Pin Assignment Table
The numerals indicated in the column of NOTES correspond to the definitions listed at the end of this table.
SYMBOL
NO. I/O NOTES
PC Card ATA IDE
1  VDD3.3 ←
2  VDD ←
3 B EEPROMSD  1
4 I IDEDIS VSS 2
5 O IOIS16 IOCS16 3
6 B D10 DD10 4
7 B D2 DD2 4
8  VSS ←
9 B D9 DD9 4
10 B D1 DD1 4
11  VSS ←
12 B D8 DD8 4
13 B D0 DD0 4
14 B STSCHG PDIAG 5
15 I A0 DA0 6
16 B LOGICH ( SPKR ) DASP (LED) 7
17  VSS ←
18 I BSYSEL VSS 2
19 O EEPROMSC  8
20 I A1 DA1 6
21 I REG  9
22 I A2 DA2 6
23 O INPACK  3
24  VDD ←
25  VDD3.3 ←
26  VSS ←
27 I A3  10
28 O WAIT IORDY 3
29 I A4  10
30 I RESET RESET 6
I : Input
O : Output
B : Bi-directional
2001-03-25 3/91
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SYMBOL
NO. I/O NOTES
PC Card ATA IDE
31 I A5  10
32 I A6  10
33 I CSEL ← 9
34 I A7  10
35  VSS ←
36  VSS ←
37 O IREQ INTRQ 3
38 I WE  11
39 I A8  10
40 I IOWR DIOW 11
41 I A9  10
42 I IORD DIOR 11
43 I OE SELATA (VSS) 11
44 I CE2 CS1 9
45 I A10  10
46  VDD ←
47 B D15 DD15 4
48 I CE1 CS0 9
49 B D7 DD7 4
50  VSS ←
51  VDD3.3 ←
52  VDD ←
53 B D14 DD14 4
54 B D6 DD6 4
55  VSS ←
56 B D13 DD13 4
57 B D5 DD5 4
58  VSS ←
59 B D12 DD12 4
60 B D4 DD4 4
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TC58NC344CF
SYMBOL
NO. I/O NOTES
PC Card ATA IDE
61  VSS ←
62 B D11 DD11 4
63 B D3 DD3 4
64 I PONRST ← 12
65   
66   
67 I PWRDWN ← 13
68 I VSENSE ← 13
69 B FDB4 ← 14
70 B FDB5 ← 14
71 B FDB3 ← 14
72 B FDB6 ← 14
73   
74  VDD ←
75  VDD3.3 ←
76  VSS ←
77 B FDB2 ← 14
78 B FDB7 ← 14
79 B FDB1 ← 14
80 B FDB0 ← 14
81 O FWP ← 15
82 I FBSY ← 16
83 O FWE ← 15
84 O FRE ← 15
85 O FALE ← 15
86 O FCE ← 15
87 O FCLE ← 15
88 I WPIN ← 13
89 O VENO ← 15
90  VSS ←
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SYMBOL
NO. I/O NOTES
PC Card ATA IDE
91  VSS ←
92   
93   
94   
95 O VEN1 ← 15
96 O OCTL ← 15
97 O OUTCLK ← 15
98 I MCLK ← 16
99 I RMCLK ← 16
100  VSS ←
NOTES
1 LVTTL I/O Buffer (IOL = 3 mA) with Pull-Up Resister
2 LVTTL Input Buffer
3 5 V Full Swing 3-State Output Buffer (CMOS Output: IOL = 6 mA)
4 5 V Full Swing I/O Buffer (TTL Input: CMOS Output: IOL = 6 mA) with Pull-Down Resister
5 5 V Full Swing I/O Buffer (TTL Input: CMOS Output: IOL = 6 mA)
6 5 V Full Swing Input Buffer (TTL Input)
7 5 V Full Swing I/O Buffer (CMOS Schmitt Input: CMOS Output: Low Noise: IOL = 18 mA)
8 LVTTL Output Buffer (IOL = 3 mA)
9 5 V Full Swing Input Buffer (TTL Input) with Pull-Up Resister
10 5 V Full Swing Input Buffer (TTL Input) with Pull-Down Resister
11 5 V Full Swing Input Buffer (TTL Schmitt Input) with Pull-Up Resister
12 5 V Full Swing Input Buffer (CMOS Schmitt Input)
13 5 V Tolerant Input Buffer
14 5 V Tolerant I/O Buffer (IOL = 3 mA) with Pull-Down Resister
15 5 V Tolerant Output Buffer (IOL = 3 mA)
16 5 V Tolerant Input Buffer (Schmitt Input)
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TC58NC344CF
Pin Descriptions
Host Interface
Host pins which change the functions in the IDE Mode are described in brackets [ ].
SYMBOL No. I/O NAME DESCRIPTION
VDD 2, 24, 46, 52, 74  POWER SUPPLY This is a power supply. (All must be connected to the power
supply 3.3 V ± 0.3 V or 5.0 ± 0.5 V)
VDD3.3 1, 25, 51, 75  POWER SUPPLY This is a power supply. (All must be connected to the power
supply 3.3 V ± 0.3 V)
VSS 8, 11, 17, 26, 35,  GROUND This is a ground. (All must be connected to the ground)
36, 50, 55, 58, 61,
76, 90, 91, 100
RESET 30 I CARD RESET This is a reset. When this is set to 1, all the internal conditions
[ RESET ] [DRIVE RESET] including FCR are initialized. Note that, in IDE Mode, the
polarity is inverted and the initialization takes place when this
signal is 0.
In PC Card mode, it is in reset condition by detecting the edge

to transit in asserted condition, the reset is canceled by
detecting the negated condition.
Please refer “Reset Sequence”, Section 6 of Switching

Characteristics for more detail.
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TC58NC344CF
D15~D0 6, 7, 9, 10, 12, 13, B DATA BUS This is a 16-bit wide (2-byte) data bus. The MSB is D15; the
[DD15~DD0] 47, 49, 53, 54, 56, [DRIVE DATA LSB is D0. Normally, this bus is in input state and it becomes
57, 59, 60, 62, 63 BUS] in output state only when the host reads data.
(With the Pull-down Resister)
A10~A0 15, 20, 22, 27, 29, I ADDRESS BUS This is an address bus. The MSB is A10; the LSB is A0. In
[DA2~DA0] 31, 32, 34, 39, 41, [DRIVE TC58NC344, the maximum address lines are 11 and the
45 ADDRESS BUS] number of decodes vary with the mode. A0 is invalid in
accessing words. In IDE Mode, only the lower 3 bits are used
and the upper 8 bits are open.
(The upper 8 bits have the Pull-down Resister)
REG 21 I ATTRIBUTE When this is set to 1, the I/O space can be accessed with
MEMORY OE and WE in Memory Mapped Mode. When REG is set
SELECT to 0, CIS and FCR can be accessed with OE and WE . The
I/O space can be accessed with IORD and IOWR in
Independent I/O, Primary and Secondary Modes. In IDE
Mode, this signal is open.
(With the Pull-up Resister)
CE1 48 I CARD ENABLE 1 In PC Card Mode, this must be set to 0 when the host
[ CS0 ] [DRIVE CHIP accesses to TC58NC344 via D7~D0. In IDE Mode, this is
SELECT 0] the selection signal for the Command Block Register.(With the
Pull-up Resister)
CE2 44 I CARD ENABLE 2 In PC Card Mode, this must be set to 0 when the host
[ CS1 ] [DRIVE CHIP accesses to TC58NC344 via D15~D8. The host can only
SELECT 1] access odd addresses via D15~D8 regardless of A0. In IDE
Mode, this is the selection signal for the Control Block
Register.
OE 43 I OUTPUT This pin is used to read the I/O space in CIS, FCR and
[ SELATA ] ENABLE Memory Mapped Modes. This pin must not be active in the
[SELECT ATA] write operation. It changes to PC Card ATA Mode in case this
pin is set to 1 and to IDE Mode in case this pin is set to 0
during the PONRST star-up. In using only in IDE Mode,
please connect this signal to VSS.
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TC58NC344CF
WE 38 I WRITE ENABLE This pin is used to write into the I/O space in FCR and
Memory Mapped Modes. In IDE Mode, this signal is open.
IORD 42 I I/O READ This is used to read the I/O space in Independent I/O, Primary
[ DIOR ] [DRIVE I/O and Secondary Modes. This signal is invalid in any other
READ] modes.
IOWR 40 I I/O WRITE This is used to write into the I/O space in Independent I/O,
[ DIOW ] [DRIVE I/O Primary and Secondary Modes. This signal is invalid in any
WRITE] other modes.
IOIS16 5 O I/O IS 16 bits In Independent I/O Mode, In Primary and Secondary Modes, it
(WP) PORT outputs L when the data bus has the address which allows the
[ IOCS16 ] (WRITE 16-bit access. Normally, all the I/O registers are allowed of the
PROTECT) 16-bit access, however it outputs H only in case that 4-byte
[DRIVE 16-bit I/O] ECC is read out when the host reads continuously the data
register by using the Long Commands.
When the Memory Card Interface is used, this signal outputs
the input of WPIN pin with the logic unchanged in WP. In IDE
Mode, it normally outputs “Hi-Z”. It is an open-drain system
which outputs L only when the host accesses the data
register.
IREQ 37 O INTERRUPT This is an interrupt request when the I/O Card Interface is
(READY) REQUEST used and it outputs its signal in two ways. The setting can be
[INTRQ] (READY) changed by using the LevIREQ (D6) bit of the Configuration
[DRIVE Option Register in FCR. When this bit is 1, IREQ is in Level
INTERRUPT] Mode and when this bit is 0, it is in Pulse Mode. Right after the
reset, this bit is in Level Mode. When the Memory Card
Interface is used, this signal provides the RDY/BSY functions.
It outputs L when the BSY (D7) bit of the ATA Status Register
is 1 or by the PWRDWN bit of the Card Configuration and
Status Register in FCR. RDY/BSY is supplied in two ways.
These settings are changeable by using the BSYSEL signal.
1. It outputs L when the PWRDWN bit is set or reset, it returns
to H after the internal processing. However, it does not
output L since the internal processing is very short.
2. It outputs L when the PWRDWN bit is set. Note that in IDE
Mode, this signal becomes INTRQ and the polarity is
inverted so an interrupt occurs in H.
INPACK 23 O INPUT PORT It outputs L only when CE1 (or CE2 ) and IORD are 0 and
ACKNOWLEDGE the address on the address bus matches the I/O space. This
signal outputs “Hi-Z” when the Memory Card Interface is used.
In IDE Mode, this signal is open.
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TC58NC344CF
STSCHG 14 B STATUS Basically, this is an output signal when a change occurs in the
CHANGED status of the interior of the controller (RDY/BSY status, Write
Protect status and the status of the battery voltage).
However, it always outputs H because a change does not
occur in the flash memory device which uses TC58NC344 or
SmartMedia Adapter Card.
[ PDIAG ] [PASSED This is asserted to inform Drive 0 that the self diagnosis of
DIAGNOSTICS] Drive 1 has been completed in IDE Mode. Drive 1 negates
this signal within 1 msec after the Power-on Reset, Software
Reset or Hardware Reset. Then, Drive 1 performs the self
diagnosis, prepares the status information and asserts this
signal within 30 sec. When the valid Executive Drive
Diagnostic Command is received, the Drive1 negates within
1msec to inform the Drive0 that the self diagnosis of Drive1 is
being performed. The Drive0 waits for the Drive1 to assert
for 5sec. The drive1 asserts this pin after clearing BSY, then
informs the Drive0 that the diagnosis has been completed and
the status information is prepared.
* TC58NC344 does not supported 2-Drive protocol, therefore,

in case of making 2 drive system, it is not guaranteed by TED.
LOGICH 16 B LOGIC HIGH This signal is an output which is fixed to H because its
( SPKR ) (AUDIO DIGITAL function is not supported.
WAVE FORM)
[ DASP (LED) ] DRIVE ACTIVE This is a signal which indicates the existence of Drive1 or the
active status of Drive in IDE mode. This signal must be
asserted by the Drive1 within 400 msec to indicate that the
Drive1 exists after the initialization during the power-on or
cancellation of the RESET signal. Drive0 waits for the the
Drive1 to assert this signal for 450 msec and if the Drive1
does not perform the assertion, the Drive0 asserts to indicate
that the drive is active. Drive1 is negated, in case of no
access for 31 sec or in case a first valid command is recieved.
After that, a drive in an active state performs an assertion. If
the DASP signal is not asserted in initializing after the reset (if
Drive1 does not exist), Drive0 clears the Drive1 Status
Register to “00h” after completing its self diagnosis.
* TC58NC344 does not supported 2-Drive protocol, therefore,

in case of making 2 drive system, it is not guaranteed by TED.
WAIT 28 O EXTEND BUS It always outputs H because TC58NC344 never asserts the
[IORDY] CYCLE WAIT in PC Card mode. In IDE mode, it goes into “Hi-z”
[I/O CHANNEL state because it is always possible to respond.
READY]
CSEL 33 I CABLE SELECT This pin is a signal in IDE mode and a selection pin for the
drive number. When the PONRST signal, the RESET
signal or the SRESET “D7” bit of the FCR Configuration
Option Register is released, Drive 0 is selected when the input
is 0, Drive 1 is selected when it is H or “OPEN”.
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TC58NC344CF
Flash Memory Interface
FD7~FD0 69~72, 77~80 B FLASH This is the bus for both the addresses and data to the Flash
DATA BUS Memory. The addresses and data (including commands) are
distinguished by using FALE and FCLE. When the Flash
Memory is not accessed or during the reset period, this bus
outputs L in Output state in order to avoid “Hi-Z”.
(With the Pull-down Resister)
FCE 86 O FLASH This is a Flash Memory Chip Enable (L). It outputs H during
CHIP ENABLE the reset period.
FCLE 87 O FLASH This is a Command Latch Enable to the Flash Memory chips.
COMMAND It outputs H when the commands are output to the FD bus.
LATCH ENABLE It outputs L during the reset period.
FALE 85 O FLASH This is an Address Latch Enable to the Flash Memory chips.
ADDRESS It outputs H when the addresses are output to the FD bus.
LATCH ENABLE It outputs L during the reset period.
FRE 84 O FLASH This is a Read Enable to the Flash Memory chips. It outputs L
READ ENABLE in reading data from the FD bus. It outputs H during the reset
period.
FWE 83 O FLASH This is a Write Enable to the Flash Memory chips. It outputs L
WRITE ENABLE in writing into the FD bus. It outputs H during the reset period.
FBSY 82 I FLASH BUSY This is a Ready/Busy Input from the Flash Memory chips.
The input of 0 indicates Busy and the input of 1 indicates
Ready. Please connect the Ready/Busy Output from the Flash
Memory chips to this pin via the Pull-up Resister.
FWP 81 O FLASH This is a Write Protect for the Flash memory chips. The write
WRITE protect is performed when the Flash Memory is not accessed.
PROTECT It outputs L during the reset period.
EEPROM Interface
EEPROMSD 3 B EEPROM This is a Serial Data I/O pin for EEPROM.

SERIAL DATA In case EEPROM has not been used, please use it in open
condition. (With the Pull-up Resister)
EEPROMSC 19 O EEPROM This is a Serial Clock Output pin for EEPROM.

SERIAL CLOCK In case EEPROM has not been used, please use it in open
condition.
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TC58NC344CF
Others
WPIN 88 I WRITE This is a Write Protect Input. If the input is 1, the write
PROTECT INPUT commands from the host are aborted. The input state is
reflected in the IOIS16 (WP) pin and the RWProt “D0” bit of
FCR Pin Replacement Register and it outputs the input logic.
This pin does not change after power-on. Also, changing it is

not allowed. In Memory Card Interface, this pin outputs the
input from the IOIS16 (WP) pin with its logic unchanged.
PONRST 64 I POWER ON This is a power-on reset for TC58NC344. By making this

RESET signal 0, the inside of TC58NC344 becomes in reset status,
and by making it 1, the reset gets cancelled.
PWRDWN 67 I POWER DOWN This is a Self Power-down Setup pin in TC58NC344. If this
SELECTION signal is set to 0 and an oscillator with an oscillation control
INPUT function is used, the OCTL pin becomes active automatically 5
msec after the command is finished, the clock input becomes
invalid and it shifts to Power-down Mode. Commands can be
accepted during the power-down period. If this signal is 1, it
shifts to Power-down Mode only by the ATA commands of the
power-down system such as Standby and Idle.
MCLK 98 I MASTER CLOCK This is a Supply Master Clock to the interior logic of
INPUT TC58NC344CF. Please connect it to OUTCLK.
OCTL 96 O OSCILLATOR This is a Oscillation Control Signal. In using an oscillator with

CONTROL an oscillation control function, please connect it to the
oscillation control pin in the oscillator.
OUTCLK 97 O OUT CLOCK This is a Clock Output after the oscillation becomes stabilized.
Please connect it to MCLK.
RMCLK 99 I DEFERENCE This is a Master Clock Input of TC58NC344. This pin is a

MASTER CLOCK 16 MHz oscillator connection pin with a duty ratio of 45 to
INPUT 55%.
BSYSEL 18 I BUSY SELECT This is a RDY/BSY function selection signal in the Memory
INPUT Interface. When this signal is 1, the RDY/BSY signal outputs L
only when the PwrDwn bit is set or reset. It returns to H after
the internal processing. It does not output L since the internal
processing is very short. If this signal is 0, the RDY/BSY
signal outputs L while the PwrDwn bit is set. In IDE Mode,
please connect it to the ground.
VSENSE 68 I VOLTAGE This pin detects the SmartMedia voltage which is connected.
SENSE INPUT It receives the VSENSE input value right after the reset is
released and it outputs to VEN0, 1. Also, if the VSENSE input
value changes while it is active, the output value of VEN0, 1
changes as well.
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TC58NC344CF
VEN0 89 O VOLTAGE This pin reports the SmartMedia voltage which is connected
ENABLE 0 by the input of the VSENSE pin. Please refer to the following
OUTPUT table for details.
VEN1 95 O VOLTAGE This pin reports the SmartMedia voltage which is connected
ENABLE 1 by the input of the VSENSE pin. Please refer to the following
OUTPUT table for details.
IDEDIS 4 I IDE DISABLE This is an IDE Mode Mask Selection. If this signal is 1, IDE is
unusable. If it is 0, IDE is in usable state.
SmartMedia
PONRST RESET VEN0 VEN1 Comment
17 pin
0 * * 0 1 3.3 V
* 1 * 0 1 3.3 V
1 0 0 1 0 5V
1 0 1 0 1 3.3 V
Notes:
1. RESET: Please add 0.022 µF Capacitor between this pin and GND to keep the compatibility of PC Card Interface.
Please add 100 kΩ Pull-up Resistor to this pin.
*Notes concerning SmartMedia Adapter
In connecting SmartMedia into the connector, if SmartMedia is in moving state, a chattering might occur in the
part where the connector touches the SmartMedia. So, until the SmartMedia is inserted completely into the
connector and the connection becomes stable, please reset TC58NC344 and refrain from accessing to
SmartMedia. In this case, it is recommended to reset for at least 200 msec, if possible for 500 msec after the
11 pins of the SmartMedia touches the connector of SmartMedia.
It is not until either XPONRST or RESET pin is absolved and it takes 1024μs cycle that TC58NC344 should
send command to Flash Memory first, That's why you should keep stability of power supply for flash memory
during this term.
2. XCE1: In the case of occurring the noise on this pin by the cross talk of Data bus simultaneous switching, please add
100 pF Capacitor between this pin and GND.
3. XCE2: In the case of occurring the noise on this pin by the cross talk of Data bus simultaneous switching, please add
100 pF Capacitor between this pin and GND.
4. XPDIAG: Need to connect 10 KΩ pull-up resister to this pin due to keeping compatibility with IDE interface.
5. XDASP: Need to connect 10 KΩ pull-up resister to this pin due to keeping compatibility with IDE interface.
6. WPIN: Please pull down the connector of SmartMedia write protect output pin by using approximately 100 KΩ and
connect it to this pin.
7. RMCLK: Please pull up the oscillation output signal from the oscillator by using 100 KΩ and connect it to this input.
8. VSENSE: Please pull down the 17-pin of SmartMedia by using 100 KΩ and connect it to this pin.
9. XPONRST: Please use a 2.9V voltage detector with a delay circuit of 200 to 500 msec before the power-on reset
signal is sent to this pin.
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TC58NC344CF
Functional Description
1. Interface Outline
TC58NC344 has the following three kinds of interfaces.
* Host Interface
* Flash Interface
* EEPROM Interface
The System Configuration Examples are described in Clause 2, Detailed Host Interfaces are described in Clause 3.
2. System Configuration Examples
3.3 / 5V
[SmartMedia ATA Adapter]
3.3V
VCC from Host DC/DC DC/DC 5V
3.3/5 V→3.3 V 3.3 V→5 V
5V
3.3 V Voltage
Switch
VDD3.3 To VCC of SmartMedia
VDD
Voltage
Detector
PC Card ATA/IDE Interface SmartMedia Interface
TC58NC344
SmartMedia Connector
Crystal Oscillator
2
E PROM
Ceramic Resonator
(Option)
CD1 , CD2
PC Card Connector
[PC Card ATA]

VCC from Host DC/DC
3.3/5 V→3.3 V
3.3 V
VDD VDD3.3 To VCC of Flash

Voltage
Detector
PC Card ATA/IDE Interface Flash Interface
TC58NC344
Flash Bus
Crystal Oscillator
2
E PROM
Ceramic Resonator
PC Card Connector
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TC58NC344CF
3. Host Interfaces
TC58NC344 corresponds to the following three interfaces as host interfaces; PC Card (Memory and ATA) Interfaces
and IDE Interface. The PC Card ATA Interface supports four I/O modes (Memory Mapped I/O, Independent I/O, Primary
and Secondary). In addition, the PC Card Interfaces have a memory space called Attribute Memory which can configure
TC58NC344 by using a software.
(All the items marked by asterisks “*” in the table below mean “Do not Care”.)
4. PC Card Interfaces
Address Map
<Attribute Memory Space>
Attribute Memory contains CIS (Card Information Structure) which helps the host to recognize a kind of functions
connected to TC58NC344. It also contains FCR (Function Configuration Register) to perform the configurations. The
Attribute Memory can be accessed in Memory Interface state and also after it is configured as I/O Interface. The
procedures for accessing Attribute Memory Registers and their addresses are described below.
[Attribute Memory Reading Operation]

WE must be inactive (1), REG and OE must be active (0) during the Read Cycle of the Attribute Memory. CE2 , CE1 and A0
control both odd and even addresses, however, only the data in even addresses is valid in Attribute Memory Access.
Function Mode REG CE2 CE1 A0 OE WE D15~D8 D7~D0
Standby Mode * 1 1 * * * Hi-Z Hi-Z
0 1 0 0 0 1 Hi-Z Even byte

Byte Access (8 Bits)
0 1 0 1 0 1 Hi-Z Invalid
Word Access (16 Bits) 0 0 0 * 0 1 Invalid Even byte
Odd Byte Only Access 0 0 1 * 0 1 Invalid Hi-Z
[Attribute Memory Writing Operation]

OE must be inactive (1), REG and WE must be active (0) during the Write Cycle of the Attribute Memory.
Standby Mode * 1 1 * * * * *
0 1 0 0 1 0 * Even byte
0 1 0 1 1 0 * *
Word Access (16 Bits) 0 0 0 * 1 0 * Even byte
Odd Byte Only Access 0 0 1 * 1 0 * *
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TC58NC344CF
[Attribute Memory Address Map]
Address CE REG WE OE FCR Read/Write
* 1 * * * Standby Invalid
* 0 1 1 0 Common Memory Read R
* 0 1 0 1 Common Memory Write W
* 0 0 1 0 Card Information Structure Read R
* 0 0 * * Invalid Access Invalid
0 0 1 0
200h Configuration Option Register R/W
0 0 0 1
0 0 1 0
202h Card Configuration and Status Register R/W
0 0 0 1
0 0 1 0
204h Pin Replacement Register R
0 0 0 1
0 0 1 0
206h Socket and Copy Register R/W
0 0 0 1
0 0 1 0
208h Extended Status Register R/W
0 0 0 1
0 0 1 0
20Ah I/O Base 0 R/W
0 0 0 1
0 0 1 0
20Ch I/O Base 1 R/W
0 0 0 1
0 0 1 0
20Eh I/O Base 2 R/W
0 0 0 1
0 0 1 0
210h I/O Base 3 R/W
0 0 0 1
0 0 1 0
212h I/O Limit R/W
0 0 0 1
0 0 1 0
214h Power Management Register R/W
0 0 0 1
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TC58NC344CF
<Common Memory Space>
[Common Memory Reading Operation]

REG and WE must be inactive (1), OE must be active (0) during the Read Cycle of Common Memory.

1 1 0 1 0 1 Hi-Z Odd byte
Word Access (16 Bits) 1 0 0 * 0 1 Odd byte Even byte
Odd Byte Only Access 1 0 1 * 0 1 Odd byte Hi-Z
[Common Memory Writing Operation]

REG and OE must be inactive (1) and WE must be active (0) during the Write Cycle of Common Memory.
Standby Mode * 1 1 * * * * *
1 1 0 0 1 0 * Even byte
1 1 0 1 1 0 * Odd byte
Odd Byte Only Access 1 0 1 * 1 0 Odd byte *
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TC58NC344CF
<I/O Space>
[Reading Operation during I/O Addressing Mode]
Function Mode REG CE2 CE1 A0 IORD IOWR D15~D8 D7~D0

0 1 0 1 0 1 Hi-Z Odd byte
I/O Inhibit 1 * * * 0 1 Hi-Z Hi-Z
Odd Byte Only Access 0 0 1 * 0 1 Odd byte Hi-Z
[Writing Operation during I/O Addressing Mode]
Function Mode REG CE2 CE1 A0 IORD IOWR D15~D8 D7~D0
Standby Mode * 1 1 * * * * *
0 1 0 0 1 0 * Even byte
0 1 0 1 1 0 * Odd byte
I/O Inhibit 1 * * * 1 0 * *
Odd Byte Only Access 0 0 1 * 1 0 Odd byte *
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TC58NC344CF
<ATA Register Accessing Procedures>

TC58NC344 supports four types of I/O Addressing Modes of PC Card ATA in the host interfaces. The I/O
Addressing Modes are determined by the setup values of the D5 to D0 bits “Function Configuration Index” in FCR
Configuration Option Register. The procedures for accessing the registers in I/O Addressing Mode and their
addresses are shown below.
[Memory Mapped Mode for ATA]

The table below lists each Register Address in Memory Mapped Mode.
REG Offset A10 A9~A4 A3 A2 A1 A0 OE = 0 WE = 0
Even Read Even Write

1 0 0 * 0 0 0 0
Data Data
1 1 0 * 0 0 0 1 Error Feature
1 2 0 * 0 0 1 0 Sector Count Sector Count
Sector Sector
1 3 0 * 0 0 1 1
Number Number
1 4 0 * 0 1 0 0 Cylinder Low Cylinder Low
Cylinder Cylinder
1 5 0 * 0 1 0 1
High High
1 6 0 * 0 1 1 0 Drive/Head Drive/Head
1 7 0 * 0 1 1 1 Status Command
Duplicate Duplicate
1 8 0 * 1 0 0 0 Even Read Even Write
Data(*) Data(*)
Duplicate Duplicate
1 9 0 * 1 0 0 1 Odd Read Odd Write
Data(*) Data(*)
Duplicate Duplicate
1 D 0 * 1 1 0 1
Error Feature
Alternate Device
1 E 0 * 1 1 1 0
Status Control
Drive
1 F 0 * 1 1 1 1 Reserved
Address

1 * 1 * * * * 0
Data(*) Data(*)
Odd Read Odd Write

1 * 1 * * * * 1
Data(*) Data(*)
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TC58NC344CF
[Independent I/O Mode]

The table below lists each Register Address in Independent I/O Mode.
REG Offset A10 A9~A4 A3 A2 A1 A0 IORD = 0 IOWR = 0

0 0 * * 0 0 0 0
Data Data
0 1 * * 0 0 0 1 Error Feature
0 2 * * 0 0 1 0 Sector Count Sector Count
Sector Sector
0 3 * * 0 0 1 1
Number Number
0 4 * * 0 1 0 0 Cylinder Low Cylinder Low
Cylinder Cylinder
0 5 * * 0 1 0 1
High High
0 6 * * 0 1 1 0 Drive/Head Drive/Head
0 7 * * 0 1 1 1 Status Command
Duplicate Duplicate
0 8 * * 1 0 0 0 Even Read Even Write
Data(*) Data(*)
Duplicate Duplicate
0 9 * * 1 0 0 1 Odd Read Odd Write
Data(*) Data(*)
Duplicate Duplicate
0 D * * 1 1 0 1
Error Feature
Alternate Device
0 E * * 1 1 1 0
Status Control
Drive
0 F * * 1 1 1 1 Reserved
Address
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TC58NC344CF
[Primary and Secondary I/O Modes]

The table below lists each Register Address in Primary and Secondary I/O Modes.
A9~A4
REG A10 IORD = 0 IOWR = 0
Primary Secondary A3 A2 A1 A0

0 * 1Fxh 17xh 0 0 0 0
Data Data
0 * 1Fxh 17xh 0 0 0 1 Error Feature
0 * 1Fxh 17xh 0 0 1 0 Sector Count Sector Count
Sector Sector
0 * 1Fxh 17xh 0 0 1 1
Number Number
0 * 1Fxh 17xh 0 1 0 0 Cylinder Low Cylinder Low
Cylinder Cylinder
0 * 1Fxh 17xh 0 1 0 1
High High
0 * 1Fxh 17xh 0 1 1 0 Drive/Head Drive/Head
0 * 1Fxh 17xh 0 1 1 1 Status Command
Alternate Device
0 * 3Fxh 37xh 0 1 1 0
Status Control
Drive
0 * 3Fxh 37xh 0 1 1 1 Reserved
Address
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TC58NC344CF
5. IDE Interface
Address Map
IDE Interface has no Attribute Memory (CIS and FCRs) spaces unlike PC Card Interface and is controlled only by
ATA Registers.
<ATA Register Access Procedures>
CS0 CS1 DA02 DA01 DA00 DIOR = 0 DIOW = 0
1 1 * * * Hi-Z Not Used
1 0 0 * * Hi-Z Not Used
1 0 1 0 * Hi-Z Not Used
1 0 1 1 0 Alternate Status Device Control
1 0 1 1 1 Device Address Not Used
0 1 0 0 0 Data Data
0 1 0 0 1 Error Features
0 1 0 1 0 Sector Count Sector Count
0 1 0 1 1 Sector Number Sector Number
0 1 1 0 0 Cylinder Low Cylinder Low
0 1 1 0 1 Cylinder High Cylinder High
0 1 1 1 0 Drive/Head Drive/Head
0 1 1 1 1 Status Command
0 0 * * * Invalid Invalid
Note) 2-Drive Protocol is not guaranteed to work in this mode.
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TC58NC344CF
Register Details
Attribute Memory Space and I/O Space Registers are described below respectively.
<CIS (Card Information Structure) >

CIS is Read-only Register which indicates the attribute information of functions connected to TC58NC344. The
registers consist of 128 bytes of an address space which is allocated to even addresses in the range of 000h to 0FFh.
The address space is implemented by the internal RAM of TC58NC344, data is read from the Flash in reset. At this
time, TC58NC344 sets RDY/BSY to L notifying that accessing to the host interface is not allowed.
<FCRs (Function Configuration Registers) >

These registers are used by the host to set TC58NC344.
[Configuration Option Register]
Address D7 D6 D5 D4 D3 D2 D1 D0
Function Configuration Index

200h SRESET LevIREQ
Conf5 Conf4 Conf3 Conf2 Conf1 Conf0
Initial Value 0 1 0 0 0 0 0 0
Read/Write R/W
SRESET: This bit resets PC Card Software. It has the same functions as the Power-on Reset and Hardware Reset except for the
fact that this bit will not be reset.
1: Reset State 0: Reset Canceled
LevIREQ: This bit is the mode selection signal of the interrupt signal to the IREQ pin.
1: Level Mode (default) 0: Pulse Mode
Function Configuration Index:

This bit is an I/O Mode Selection Signal.
Conf5 Conf4 Conf3 Conf2 Conf1 Conf0 Mode
0 0 0 0 0 0 Memory Mapped I/O
0 0 0 0 0 1 Independent I/O
Primary I/O
0 0 0 0 1 0
1F0~1F7/3F0~3F7
Secondary I/O
0 0 0 0 1 1
170~177/370~377
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TC58NC344CF
[Card Configuration and Status Register]
202h Changed SigChg IOIs8 RFU Audio PwrDwn Intr IntrAck
Read/Write 0 Fixed R/W 0 Fixed R/W R 0 Fixed
Changed: This bit is fixed to “0” in TC58NC344, because the change defined by the PC Card Standard will not occur.
The case the D7 to D4 bits of the Pin Replacement Register change to “1”.
(In TC58NC344, the above bits are fixed to “0”.）
The case the bits of the Extended Status Register change to “1”.
Since the function is for the Modem Card, no change will occur in the Flash Memory Card which uses TC58NC344.
SigChg： This bit is fixed to “0” in TC58NC344 because there will be no change like the one Changed is subject to.
IOIs8: This bit indicates the data bus width of the host interface.
1: 8-bits width 0: 16-bits width (default)
This bit can not be changed by executing the ATA Set Feature command.
This bit is not interlocked with the IOIS16 pin.
PwrDwn: This bit indicates Power Down.

1: Power Down 0: Operating Status
When this bit is set to 0, the system is in the status specified by the prior ATA command. When this bit is set to 1 and
the BSYSEL signal is 1, the system is in ATA Standby Mode unless the ATA command gets accepted. When ATA
commands can not be accepted while the Power Down Mode is being released (during the state change), the D6
“DRDY” bit in the ATA Status Register is set to L (Not Ready). The host must not set it to Power Down status while
TC58NC344 is in BSY Mode. In case the oscillator with an oscillation control function is being used, the oscillation stops
when this bit is set.
Intr: This bit is interlocked with the operation of the IREQ pin. However, this bit operates in Level Mode even when in Pulse
Mode.
H: IREQ = L L: IREQ = H
IntrAck: This bit enables R/W Operations of the Intr bit. It is fixed to 0.
0: Intr = Read Only 1: Intr = Read/Write enabled
[Pin Replacement Register]
204h CBVD1 CBVD2 CREDY CWProt RBVD1 RBVD2 RREDY RWProt
Read/Write 0 Fixed 1 Fixed R
D7-D4： These bits are fixed to “0” in TC58NC344 because there will be no change like the one PC Card Standard is subject to
during operation.
RWProt: This bit outputs the input logic of the WPIN signal.
This pin does not change after the power-on. Please do not change it, either.
0: No Write Protect 1: Write Protect
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TC58NC344CF
[Socket and Copy Register]
206h RFU Copy Number Socket Number
Read/Write R/W
Copy Number: These bits indicate the number of drive. When the same functionable cards are connected to the host, the host
writes the data indicating card number into these bits. These bits are compared with D4 bit “DRV” of ATA Drive/Head Register, and if
the values do not match, TC58NC344 does not correspond to the access.
Drive 0: 000B = (D6, D5, D4) B
Drive 1: 001B = (D6, D5, D4) B
Socket Number: The data which indicates the controller is connected to what number of host socket are written into these bits.
There is no effect on the TC58NC344 operation.
[Extended Status Register]
ReqAttn
208h Event 3 Event 2 Event 1 ReqAttn Enable 3 Enable 2 Enable 1
Enable
Read/Write R/W
This register is a Read/Write Enable Register which exists to maintain the compatibility. There is no effect on the TC58NC344
operation.
[I/O Base 0 Register]
20Ah I/O Base 0
Read/Write R/W
operation.
20Ch I/O Base 1
Read/Write R/W
operation.
20Eh I/O Base 2
Read/Write R/W
operation.
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TC58NC344CF
210h I/O Base 3
Read/Write R/W
operation.
[I/O Limit Register]
212h I/O Limit
Read/Write R/W
operation.
[Power Management Register]
Begin/
Save/ Stored
Status Done
214h RFU (0) RFU (0) RFU (0) RFU (0) Restore State
Restored State
State Exists
Operation
Read/Write 0 Fixed R/W 0 Fixed
This register does not affect the TC58NC344 operation.
State Restored: If the Begin/Done State Operation bit is set when the Save/Restore State is set, this bit is set to 1.
After reading this register, it is cleared to 0.
Begin/Done State Operation: In reading, this is fixed to 0. Once this bit is set, the State Restored bit gets set.
Save/Restore State: This is a Read/Write Enable Register.
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TC58NC344CF
<ATA Registers>
[Data Register]
Address D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Data Word
Data byte
Initial Value Unidentified
Read/Write R/W
This 16-bits register is used to transfer data between ATA Data Buffer in TC58NC344 and the host. This enables both Word Access
and byte Access.
The data bus operates differently at 8-bits and 16-bits width. At 8-bit width, the bus allows an alternate output of odd and even data,
whereas it allows an output of only even data at 16-bits width.
[Error Register]
BBK UNC MC IDNF MCR ABRT TKN0F AMNF
Read/Write R
This register stores the additional data regarding the cause of errors occur in processing destination codes. The host must check
this register when the D0 bit “ERR” in ATA Status Register is set to H. A diagnostic code is set in this register after the Power On
Reset or the execution of the ATA Execute Drive Diagnostic command. BBK, TKNOF and AMNF were not designed for reporting the
information on errors, but for displaying error codes for the ATA Execute Drive Diagnostic command.
(See the following table for details.)
BBK (Bad Block Detected): Indicates that a bad block mark was detected in the sector ID.
It is fixed to L in TC58NC344.
UNC (Uncorrectable Data Error): Indicates that an uncorrectable error was detected.
MC (Media Changed): Indicates that there was a change in the status of a removable media.
IDNF (ID Not Found): Indicates that the requested ID could not be found.
MCR (Media Change Requested): Indicates that the release latch of a removable media drive was pressed.
It is fixed to L in TC58NC344.
ABRT (Aborted Command): Indicates that the requested command was aborted.
TKN0F (Track 0 Not Found): Indicates that the track 0 could not be found in the execution of the ATA Recalibrate command.
AMNF (Address Mark Not Found): Indicates that the data address could not be found after locating the correct ID.
Diagnostic Codes (See Execute Drive for details.)
Code Error Type
01h No Error Detected
02h Formatter Device Error
03h Sector Buffer Error
04h ECC Circuitry Error
05h Controlling Microprocessor Error
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TC58NC344CF
[Feature Register]
Feature byte
Read/Write W
This register adds special functions to ATA commands and is used to enable and disable the host interface. It exists just to maintain
the compatibility in TC58NC344 and does not affect the TC58NC344 operation.
[Sector Count Register]
Sector Count
Read/Write R/W
In this register, the host writes the sector count of data for which a transfer request has been made to perform Read and Write
operations by ATA command between the host and TC58NC344. The register value of 0h (All 0) indicates the sector count of 256.
The register value being 0h after the ATA command execution means the command has ended normally. If the command does not
end normally, the sector count that must be transferred to complete the request from the host is designated in this register. (The
remaining sector count that has not been transferred is designated.) Right after the Power-on Reset, this register is “00h”. It
becomes “01h” after the initialization process of TC58NC344.
[Sector Number Register]
Sector Number (CHS Addressing)
Logical Block Number bits A07~A00 (LBA Addressing)
Read/Write R/W
The host writes the first sector number which is to be used in CHS Mode in this register. After the ATA command execution, the host
can read the last sector number in this register. When LBA Mode is selected, the host designates the Logical Block Number bits A07
to A00. After the ATA command execution, the host can read the Logical Block Number from this register. Right after the Power-on
Reset, this register is “00h”. It becomes “01h” after the initialization process of TC58NC344.
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TC58NC344CF
[Cylinder Low Register]
Cylinder Number Low byte (CHS Addressing)
Read/Write R/W
The host writes the low byte of the first cylinder number which is to be used in CHS Mode in this register. After the ATA command
execution, the host can read the low byte of the last cylinder number from this register. When LBA Mode is selected, the host
designates the Logical Block Number bits A15 to A08. After the ATA command execution, the host can read the Logical Block
Number from this register.
[Cylinder High Register]
Cylinder Number High byte (CHS Addressing)
Read/Write R/W
The host writes the high byte of the first cylinder number which is to be used in CHS Mode in this register. After the ATA command
execution, the host can read the high byte of the last cylinder number. When LBA is selected, the host designates the Logical Block
Number bits A23 to A16. After the ATA command execution, the host can read the Logical Block Number from this register.
[Drive/Head Register]
LBA (0) HS3 HS2 HS1 HS0

1 1 DRV
LBA (1) LBA27 LBA26 LBA25 LBA24
Read/Write R/W
This register is used to designate a drive among one pair of drives sharing a pair of registers.
LBA (Logical Block Address): This bit is used to select between CHS Mode and LBA Mode.
0: CHS Addressing Mode 1: LBA Addressing Mode
DRV (Drive Address): The drive number selected by the host is written into this bit.
0: Drive0 (Card0) 1: Drive1(Card1)
This bit affects nDS1 and nDS0 of the ATA Drive Address Register.
HS3~HS0: Indicates the bits 3 to 0 of the head number in CHS Addressing Mode.
LBA27~LBA24: Indicates the Logical Block Number bits 27 to 24 in LBA Addressing Mode.
(Reference) LBA ↔ CHS Conversion Formula

CHS → LBA Conversion Formula LBA = (C × HpC + H) × SpH + S + 1
LBA → CHS Conversion Formula C = LBA/ (HpC × SpH)
H = (LBA/SpH) mod HpC
S = (LBA mod SpH) + 1
C: Cylinder Number HpC: Head Count per Cylinder
H: Head Number SpH: Sector Count per Head (Track)
S: Sector Number
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[Alternate Status Register]
BSY DRDY DWF DSC DRQ CORR IDX ERR
Read/Write R
This register reports the TC58NC344 status when it receives the read instructions from the host. An interrupt ( IREQ ) is not cleared
after the register has been read.
BSY (Busy): This bit indicates that TC58NC344 is in busy state. It is always set to H when an access is made to
the ATA Command Register.
DRDY (Drive Ready): When this bit is set to H, TC58NC344 is ready to respond to the ATA commands. If an error occurs,
this bit is latched and continues to be latched until the host reads this register. When this register is
read, this bit indicates the present TC58NC344 status. At Power-on, this bit is cleared to L and stays
in this state until it gets ready to receive the ATA commands again.
DWF (Drive Write Fault): This bit indicates the current Write Fault status. It is fixed to L.
DSC (Drive Seek Complete): This bit indicates that the head has been positioned on a track. However, since TC58NC344 does not
have a head, it is normally H. It is L during the initial startup.
DRQ (Data Request): This bit indicates either Word Data or byte Data is ready to be transferred between the host and
TC58NC344.
CORR (Corrected Data): This bit is fixed to L.
IDX (Index): This bit is fixed to L.
ERR (Error): This bit indicates that an error occurred in the execution of the previous ATA command. The
information regarding the cause of an error is showed in ATA Error Register.
Representative examples are shown as below.
80h RESET is not able to be canceled.

10h Physical Format for Flash Memory without being produced.
50h Physical Format for Flash Memory is completed.
D0h Under executing Command
51h Error completion of the command
[Status Register]
BSY DRDY DWF DSC DRQ CORR IDX ERR
Read/Write R
This register reports the TC58NC344 status when it receives the read instruction from the host. When this register is read, the
interrupt ( IREQ ) is cleared. Refer to ATA Alternate Status Register for details.
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TC58NC344CF
[Device Control Register]
    1 SRST nIEN 0
Read/Write W
This register is used to control the interrupt requests of TC58NC344 and indicate ATA Software Reset to TC58NC344.
SRST (Software Reset): This bit resets the ATA Software. When this bit is set to 1, the reset status is maintained. When it is cleared
to 0, the reset is canceled.
nIEN (Interrupt Enable): This bit can be ignored while TC58NC344 is set by the Memory Mapped I/O. While this bit is set to 1, the
interrupts of TC58NC344 are inhibited.
[Device Address Register]
 nWTG nHS3 nHS2 nHS1 nHS0 nDS1 nDS0
Read/Write R
This register is for maintaining the compatibility with the ATA Disk Drive Interface.
D7: This bit is always Hi-Z.
nWTG (Write Gate): This bit is cleared to L if the write process is in progress, otherwise it is set to H. If this bit is cleared to L,
the host must not change the voltage supplied to TC58NC344.
nHS3~nHS0: This bit selects the head. This is the highlight signal of the ATA Drive/Head Register D3 to D0 bits
“HS3~HS0”.
nDS1: This bit is the Drive 1 selection bit. When the DRV bit of Drive/Head Register is 1, this bit is 0.
nDS0: This bit is the Drive 0 selection bit. When the DRV bit of Drive/Head Register is 0, this bit is 0.
[Command Register]
Command
Read/Write W
When a command is written to this register, the drive number of the Socket and Copy Register and the DRV bit of the Drive/Head
Register are compared, and only when they match, the command gets executed.
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TC58NC344CF
[Duplicate Even Data Register]
Duplicate Even Data
Read/Write R/W
This register is identical to the ATA Data Register.
[Duplicate Odd Data Register]
Duplicate Odd Data
Read/Write R/W
This register only allows the access to odd data addresses regardless of whether a low-order (D7~D0) or high-order (D15~D8)
access is made.
[Duplicate Feature Register]
Duplicate Feature byte
Read/Write W
This register is identical to the ATA Feature Register.
[Duplicate Error Register]
BBK UNC MC IDNF MCR ABRT TKNOF AMNF
Read/Write R
This register is identical to the ATA Error Register.
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TC58NC344CF
ATA Commands
1. ATA Command Block

ATA Command Block is the general name of 7 registers which are used to transmit commands by using ATA
Command Protocols. By interpreting the contents of these registers, the addressing mode which is used to specify the
address of the medium in TC58NC344 is determined. TC58NC344 supports CHS Addressing Mode and LBA Addressing
Mode.
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) X
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
Drive Head (6) 1 LBA 1 Drive X
Command (7) X
2. ATA Command Block Register Operation

By writing the necessary parameter to the related register in the Command Block and writing the command code in the
Command Register, a command is issued to TC58NC344. There are three types of classes. To receive all the commands,
it is fundamental that BSY = 0 (L: negate).
When TC58NC344 receives the Class 1 command, it sets BSY to H within 400 nsec.
When TC58NC344 receives the Class 2 command, it sets BSY to H within 400 nsec, sets up the sector buffer for the
writing action, sets DRQ to H within 700 µsec and clears BSY to L within 400 nsec from the DRQ setting.
* In case it is in Power-down Mode, it is impossible to set DRQ to H within 700 µsec because the oscillator
connected to TC58NC344 has stopped.
When TC58NC344 receives the Class 3 command, it sets BSY to H within 400 nsec, sets up the sector buffer for the
writing action, sets DRQ to H within 20 msec and clears BSY to L within 400 nsec from the DRQ setting.
Note) About Class 2 and Class 3, the transition of BSY may be too short for the host to recognize BSY = 1 (H) because
DRQ is set to H so quickly.
TC58NC344 does not correspond to a New Command in case a New Command is issued when TC58NC344 is
processing an Old Command.
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TC58NC344CF
3. ATA Command Codes and Parameters
Command Parameters Used

Class Command Name
Code
FR SC SN CY DH LBA
1 Check Power Mode 0 98h, E5h Y D
1 Execute Drive Diagnostic M 90h D
2 Format Track M 50h Y Y Y Y Y
1 Identify Drive 0 ECh D
1 Idle 0 97h, E3h Y D
1 Idle Immediate 0 95h, E1h D
1 Initialize Drive Parameters M 91h Y Y
1 Media Eject 0 EDh D
1 Recalibrate M 1Xh D
1 Read Buffer 0 E4h D
1 Read Multiple 0 C4h Y Y Y Y Y
1 Read Sector (s) M 20h, 21h Y Y Y Y Y
1 Read Long Sector M 22h, 23h Y Y Y Y Y
1 Read Verify Sector (s) M 40h, 41h Y Y Y Y Y
1 Seek M 7Xh Y Y Y Y
1 Set Features 0 EFh Y D
1 Set Multiple Mode 0 C6h Y D
1 Set Sleep Mode 0 99h, E6h D
1 Standby 0 96h, E2h D
1 Standby Immediate 0 94h, E0h D
2 Write Buffer 0 E8h D
3 Write Multiple 0 C5h Y Y Y Y Y
2 Write Sector (s) M 30h, 31h Y Y Y Y Y
2 Write Long Sector M 32h, 33h Y Y Y Y Y
1 Erase Sector (s) V C0h Y Y Y Y Y
1 Request Sense V 03h D
1 Translate Sector V 87h Y Y Y Y Y
1 Wear Level V F5h Y
3 Write Multiple w/o Erase V CDh Y Y Y Y Y
2 Write Sector (s) w/o Erase V 38h Y Y Y Y Y
3 Write Verify V 3Ch Y Y Y Y Y
 NOP V FFh
CY = Cylinder Registers SC = Sector Count Register DH = Drive/Head Register

SN = Sector Number Register FR = Feature Register (See Command Description.)
LBA = Logical Block Address Mode Supported
Y: Valid Parameters for Respective Commands are Set into each Register.
“Y” in the “DH” Column Represents that both the Drive and Head Parameters are Applied.
D: Only the Drive Parameter is Valid, the Head Parameter is Invalid.
M: Mandatory O: Option V: Vendor
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TC58NC344CF
4. ATA Command Error Message Table
Error Register Status Register
Command Name
UNC IDNF ABRT TKON AMNF ERR
Check Power Mode V V
Execute Drive Diagnostic V V *2
Format Track V V V
Identify Drive V V
Idle V V
Idle Immediate V V
Initialize Drive Parameters V V
Media Eject V V
Recalibrate V V
Read Buffer V V
Read Multiple V V V V
Read Sector (s) V V V V
Read Long Sector V V V
Read Verify Sector V V V V
Seek V V V
Set Features V V
Set Multiple Mode V V
Set Sleep Mode V V
Standby V V
Standby Immediate V V
Write Buffer V V
Write Multiple V V V
Write Sector (s) V V V
Write Long Sector V V V
Erase Sector (s) V V V
Request Sense *1 V V
Translate Sector V V V
Wear Level V V
Write Multiple w/o Erase V V V
Write Sector (s) w/o Erase V V V
Write Verify V V V
NOP V V
V: Varies with Executing this Command *1: Please refer to Command Descriptions. *2: Valid only Zero
TC58NC344 supports 6 kinds of Vendor Unique ATA Commands besides the commands mentioned above.
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TC58NC344CF
5. ATA Commands Outline Description
Standard ATA Commands
<Check Power Mode  98h, E5h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) X
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
Drive Head (6) X X X Drive X
Command (7) 98h or E5h
This command checks the current power mode of TC58NC344. In case the oscillator is in operation when this command gets issued,
TC58NC344 sets BSY and sets Sector Count Register to “FFh”. Then it clears BSY and issues an interrupt. In case the oscillator is
in Stop State or the oscillation stop timer is set, TC58NC344 sets BSY and sets the Sector Count Register to “00h”. Then it clears
BSY and issues an interrupt.
Input Parameters
Commands only
Output Parameters in Normal Ending

Sector Count Register = 00h (In case the oscillator is in Stop State or the oscillation stop timer is set)
Sector Count Register = FFh (In case the oscillator is in operation)
Output Parameters in Illegal Ending

Status Register = 11h
Error Register = 04h (Aborted Command)
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TC58NC344CF
<Execute Drive Diagnostic  90h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) X
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
Command (7) 90h
This command only determines whether the reset processing was executed normally or not in TC58NC344. In case PDIAG is
not asserted within about 6 seconds from Drive 0 in IDE Mode, TC58NC344 sets the logical sum of the error contents and “80h” in
the Error Register. The diagnostic codes are shown below.
(Diagnostic Codes)
Code Error Type
02h Formatter Device Error
“01h” or “81h": Reset Processing ended normally.

“02h” or “82h”: Reset Processing ended Illegally or Flash is not initialized.
Input Parameters
Commands only

Error Register = 01h or 81h

Error Register = 02h or 82h
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TC58NC344CF
<Format Track  50h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) Sector Count
Sector Number (3) Sector Number (LBA7~LBA0)
Cylinder Low (4) Cylinder Low (LBA15~LBA8)
Cylinder High (5) Cylinder High (LBA23~LBA16)
Drive Head (6) 1 LBA 1 Drive Head Number (LBA27~LBA24)
Command (7) 50h
This command, originally, formats the Flash Memory connected to TC58NC344. However, this command is issued only to check the
validity of the addresses specified in the Command Block Register in the NOP processing in TC58NC344. If this command is issued
when the input of the WPIN signal is 1, it gets aborted.
Input Parameters
1. CHS Addressing Mode
Sector Count Register = The Sector Count to be formatted
Cylinder Register, Head Register = Track Address
2. LBA Addressing Mode
Sector Count Register = The Sector Count to be formatted (00h = 256 sectors)
Sector Number, Cylinder, Head Register = Sector Address

Sector Count Register = 00h
Sector Number, Cylinder, Head Register = The Last Format Address

1. DRDY = 0
2. The Sector Count is bigger than the Sector Count per Track in CHS Addressing Mode.
Error Register = 10h (ID Not Found)
Sector Number Register = 01h
3. Address Over
Sector Count Register = The Unformatted Sector Count
Sector Number, Cylinder, Head Register = Over-addressed Sector Address
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TC58NC344CF
<Identify Drive  ECh>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) X
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
Command (7) ECh
This command enables the host to receive the following parameter information from TC58NC344. When this command is issued,
TC58NC344 sets BSY, sets the requested parameter information in the sector buffer and sets DRQ, then issues an interrupt. After
that, the host can read the parameter information from the sector buffer.
Input Parameters
Commands only


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TC58NC344CF
<<Identify Drive Information>>
Word Address Default Bytes Data Information
0 848Ah 2 General Configuration bit Information
1 Variable 2 Cylinder Count
2 0000h 2 Reserved
3 Variable 2 Head Count
4 Variable 2 Unformatted byte Count per Track
5 0210h 2 Unformatted byte Count per Sector
6 Variable 2 Sector Count per Track
7 0000h 2 Vendor Unique
10~19 0000h 20 Serial Number
20 0001h 2 Buffer Type
21 0001h 2 Buffer Size in the unit of 512 bytes
22 0004h 2 ECC byte Count passes Read/Write Long Command
23~26 XXXXh 8 Firmware Revision (Ver.1.2)
27~46 XXXXh 40 Model Number (Vendor Unique)
Maximum Counts of Sectors that can be transferred at time of every

47 0001h 2
interrupt caused with a Read/Write Multiple Command
48 0000h 2 Double Word (32 bits) is not supportable
49 0200h 2 LBA is supportable, DMA is not able to transfer
50 0000h 2 Reserved
51 0200h 2 PIO Data Transfer Timing
52 0000h 2 DMA Data Transfer Timing
53 0000h 2 Validity of the area reported in Translation Mode
54 Variable 2 Counts of Current Cylinders after being formatted (*1)
55 Variable 2 Counts of Current Heads after being formatted (*2)
56 Variable 2 Counts of Current Sectors per Track after being formatted (*3)
57~58 Variable 4 Current Sector Capacity = (*1) × (*2) × (*3)
59 010Xh 2 Option about Multiple Sector Transfer can not be set
60~61 Variable 4 Total counts of user addressable sectors in LBA mode supported
62 0000h 2 Single-word DMA Data Transfer is not supportable
63 0000h 2 Multi-word DMA Data Transfer is not supportable
64~127 0000h 128 Reserved
128~159 0000h 64 Vendor Unique
160~255 0000h 192 Reserved
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TC58NC344CF
<Idle  97h, E3h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) Timer Count (5 msec × Timer Count)
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
When this command is issued, TC58NC344 sets BSY and moves to Idle Mode. Then it clears BSY and issues an interrupt. An
interrupt is issued even if TC58NC344 has not completely entered into the Idle Mode. If the Sector Count Register is something
other than “00h”, the Auto Power Down Sequence is permitted and the countdown starts immediately. In case the oscillator with an
oscillation control functions is used, the oscillation stops after the times set in the Sector Count Register. The command reception is
enabled even during the Power Down Period. When the Sector Count Register is “00h”, the Auto Power Down Sequence is
inhibited.
Input Parameters
Sector Count Register = Setting of Auto Power Down Sequence
“00h”: the Auto Power Down Sequence is inhibited
Except“00h”: the Auto Power Down Sequence is permitted


Note) If the input of the PWRDWN signal is 0, the setting of Auto Power Down Sequence is ignored, changes to Self Power
Down Mode after each command is completed.
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TC58NC344CF
<Idle Immediate  95h or E1h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) X
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
This command executes NOP Processing in TC58NC344. The command reception is enabled even during the Power Down Period.
Input Parameters
Commands only


Note) If the input of the PWRDWN signal is 0, the setting of Auto Power Down Sequence is ignored, changes to Self Power
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TC58NC344CF
<Initialize Drive Parameters  91h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) Sector Count (Number of Sectors)
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
Drive Head (6) X 0 X Drive Head Number (no. of heads-1)
Command (7) 91h
This command enables the host to designate the sector count per track and the head count per cylinder. When this command is
issued, TC58NC344 sets BSY and parameters. Then, it clears BSY and issues an interrupt. This command does not check the
validity of the values of the sectors and heads. If an invalid value is set, an error will be reported when another command attempts
an invalid access.
Input Parameters
Sector Count Register = Sector Count per Track
Head Register = Head Count per Cylinder - 1


Status Register = 51h or 11h
<Media Eject  EDh>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) X
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
Command (7) EDh
This command executes NOP Processing. This has a different specification from the one ATA Standards define.
Input Parameters
Command only


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TC58NC344CF
<Recalibrate  1Xh>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) X
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
Drive Head (6) 1 LBA 1 Drive X
Command (7) 1Xh
This command moves the head cylinder of TC58NC344 to “0h”. However, TC58NC344 performs only the interface timing and
register operations in NOP Processing. When this command is issued, TC58NC344 sets BSY, renews the status, clears BSY and
issues an interrupt. After this command ends normally, TC58NC344 initializes the Command Block Register.
Input Parameters
Commands only

1. CHS Addressing Mode
Cylinder Register = 0000h
Head Register = 0h
2. LBA Addressing Mode
Cylinder Register = 0000h
Head Register = 0h

2001-03-25 44/91
TC58NC344CF
<Read Buffer  E4h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) X
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
Command (7) E4h
This command enables the host to read the current contents of the sector buffer of TC58NC344. When this command is issued,
TC58NC344 sets BSY and sets up the sector buffer for a read operation. Then, it issues an interrupt after setting DRQ and clearing
BSY. After this, the host can read the most recent 512 bytes data written by the sector buffer just before the read operation.
Input Parameters
Commands only


2001-03-25 45/91
TC58NC344CF
<Read Multiple  C4h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Command (7) C4h
This command functions in the same way as the Read Sector(s) command. Please refer to that. However, the Sector Count is
capable of dealing with only 1.
Input Parameters
Sector Count Register = Sector Count to be read (It is possible to perform 01h only.)

Sector Number, Cylinder, Head Register = Last Sector Address to be read

1. DRDY = 0
2. Multiple Inhibited
3. Address Over
Status Register = 59h (is 51h after 512 bytes Data Transfer)
Sector Count Register = Remaining Count of Sectors to be transferred
4. Uncorrected Data
Error Register = 40h (Uncorrectable Data Error)
Sector Number, Cylinder, Head Register = Uncorrected Data Sector Address
2001-03-25 46/91
TC58NC344CF
<Read Sector (s)  20h, 21h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Command (7) 20h or 21h
This command enables the host to read the sectors 1 to 256 which are designated by the Sector Count Register of TC58NC344.
The sector count of 0 indicates the transfer request of 256 sectors. The transfer starts at the sector designated by the Sector
Number. DRQ is always set prior to the data transfer regardless of the error state. When this command is finished, the cylinder,
head and sector number of the last sector which was read are set in the task file. If an error occurs, the read operation aborts in the
sector with the error. The cylinder, head and sector number of the sector where an error occurred are set in the task file. The data
where an error occurred remains in the sector buffer.
Input Parameters
Sector Count Register = Sector Count to be read (00h is 256 sectors)

Sector Number, Cylinder, Head Register = Last Read Sector Address

1. DRDY = 0
2. Address Over
3. Uncorrected Data
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TC58NC344CF
<Read Long Sector  22h, 23h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
This command functions in the same way as the Read Sector (s) command except that it transfers the requested sector data and
the ECC bytes for Long Commands. The transfer of the ECC bytes for Long Commands is a byte transfer at a fixed length of 4
bytes. The transferable sector count is limited to 1.
Input Parameters
Sector Count Register = Sector Count to be read (01h fixed)

Sector Number, Cylinder, Head Register = Last Read Sector Address

1. DRDY = 0
2. Multiple Sectors’ Transfer Request
3. Address Over
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TC58NC344CF
<Read Verify Sector (s)  40h, 41h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
This command functions in the same way as the Read Sector (s) except that it does not set DRQ and does not transfer data to the
host. After verifying the requested sectors, TC58NC344 clears BSY and issues an interrupt. When this command is finished, the
cylinder or the sector number of the last sector which has been verified is set in the task file. If an error occurs, the verify operation
aborts in the sector where an error occurred. The cylinder or the sector number of the sector where an error occurred is set in the
task file. Also, the sector count which has not been verified is set in the Sector Count Register.
Input Parameters
Sector Count Register = Sector Count to be verified (00h is 256 sectors)

Sector Number, Cylinder, Head Register = Last Verify Sector Address

1. DRDY = 0
2. Address Over
Sector Count Register = Unverified Sector Count
3. Uncorrected Data
Sector Count Register = Unverified Sector Count
2001-03-25 49/91
TC58NC344CF
<Seek  7Xh>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) X
Command (7) 7Xh
This command seeks to the designated track in the task file and selects the head.
Actually, TC58NC344 performs the interface timing and register operations. When this command is issued, the Flash Memory
connected to TC58NC344 does not need to be formatted. The TC58NC344 sets the DSC.
Input Parameters
Sector Number, Cylinder, Head Register = Sector Address to be sought


1. DRDY = 0
2. Address Over
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TC58NC344CF
<Set Features  EFh>
Bit 7 6 5 4 3 2 1 0
Feature (1) Feature
Sector Count (2) X
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
Command (7) EFh
Originally, this command enables the host to change the contents of the execution of TC58NC344. In case of IDE mode, “01h” and
“81h” are valid. In case of PC Card mode, Iois8 bit of “Card Configuration and Status Register” is set by “01h”. And Iois8 bit of “Card
Configuration and Status Register” is reset by “81h”. It is processed as the NOP even a parameter of something other than ”01h”
or ”81h” is set.
<Features Supports>
Feature Operation
01h Enable 8 bits Data Transfer
55h Disable Read Look Ahead
66h Disable Power on Reset establishment of Defaults at Soft Reset
69h 
81h Disable 8 bits Transfer
96h 
97h 
9Ah Set the host current source capability. Allows trade off between current drawn and Read/Write speed.
BBh 4 bytes of data Apply on Read/Write Long Commands
CCh Enable Power on Reset establishment of Defaults at Soft Reset
The Default Mode is “81h” at a power-on or after a hardware reset.
Input Parameters
Feature Register = Parameters to Change Functions


1. DRDY = 0
2. Unsupported Parameters
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TC58NC344CF
<Set Multiple Mode  C6h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
Command (7) C6h
Originally, this command is used to enable TC58NC344 to perform the Read Multiple and Write Multiple operations. “00h” or “01h”
can be set in the Sector Count Register. When TC58NC344 issues this command, the Read Multiple and Write Multiple command
can be executed.
Input Parameters
Sector Count Register = Sector Count per Block
(00h = Multiple Command inhibited, 01h = Multiple Command allowed,
Other cases beside 00h and 01h = Multiple Command inhibited)


1. DRDY = 0
2. Unsupported Block Size (Sector Count Register = other cases beside 00h and 01h)
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TC58NC344CF
<Set Sleep Mode  99h, E6h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) X
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
This command is the only way to set TC58NC344 to Sleep mode. By performing a hardware reset or a software reset, or when an
ATA Command is accepted, TC58NC344 recovers from the Sleep mode. When in Sleep mode, the D6 bit “DRDY” of the ATA
Status Register is "H" (Ready). As soon as this command is issued, TC58NC344 moves to Power-down mode right away. In
case the oscillator with an oscillation control function is used, the oscillation stops.
Input Parameters
Commands only


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TC58NC344CF
<Standby  96h, E2h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) Timer Count (5 msec × Timer Count)
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
When this command issued, TC58NC344 sets BSY and moves itself to Standby Mode. Then it clears BSY and issues an interrupt.
An interrupt occurs even though TC58NC344 has not moved to Standby Mode completely. Whatever the Sector Count Register,
TC58NC344 gets converted immediately to Power Down Mode. In case an oscillator with an oscillation control function is used, the
oscillation stops. In case the Sector Count Register is “00h”, it does not get set beck to Power Down Mode if a command is received
after the Power Down. However, if the Sector Count Register is something other than “00h” and the command is received after
Power Down is done once, an Auto Power Down Sequence is permitted after the command execution and a countdown starts right
away. In case an oscillator with an oscillation control function is used, the oscillation stops after the time set in the Sector Count
Register. The command reception is enabled during the Power Down Period.
Input Parameters
Sector Count Register = Setting Auto Power Down Sequence
“00h”: the Auto Power Down Sequence is inhibited
Except“00h”: the Auto Power Down Sequence is permitted


Note) If the input of the PWRDWN signal is 0, the setting of Auto Power Down Sequence is ignored and it changes to Self Power
2001-03-25 54/91
TC58NC344CF
<Standby Immediate  94h, E0h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) X
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
When this command is issued, TC58NC344 sets BSY and moves itself to Standby Mode. Then it clears BSY and issues an interrupt.
An interrupt occurs even though TC58NC344 has not moved to Standby Mode completely. TC58NC344 gets converted immediately
to Power Down Mode after executing this command. In case an oscillator with an oscillation control function is used, the oscillation
stops. If the command is received after the Power Down is done once, it depends on the value set by the standby and idle
commands in the Sector Count Register and moves itself to Auto Power Down Sequence. The command reception is enabled
during the Power Down Period.
Input Parameters
Commands only


Note) If the input of the PWRDWN signal is 0, the setting of Auto Power Down Sequence is ignored and it changes to Self Power
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TC58NC344CF
<Write Buffer  E8h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) X
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
Command (7) E8h
This command enables the host to rewrite the contents of the data buffer of TC58NC344. This data buffer can be accessed by the
512 bytes Address Access in the same area as the read buffer.
Input Parameters
Commands only


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TC58NC344CF
<Write Multiple  C5h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Drive Head (6) X LBA X Drive Head Number (LBA27~LBA24)
Command (7) C5h
This command functions in the same way as the Write Sector(s) command. Please refer to that. However, the Sector Count is
capable of dealing with only 1. If the input of the WPIN signal is 1, this command gets aborted after its execution.
Input Parameters
Sector Count Register = Sector Count to be Written (It is possible to perform 01h only.)

Sector Number, Cylinder, Head Register = Last Write Sector Address

1. DRDY = 0
3. Address Over
4. No Blank Blocks
Sector Number, Cylinder, Head Register = Sector Address which failed to written
2001-03-25 57/91
TC58NC344CF
<Write Sector (s)  30h, 31h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
This command writes data from the host. It starts writing from the 1 to 256 sector counts (00h is 256) and the first sector address
set in a designated register. When this command is finished, the first sector address to be written is reflected in the register. If
an error occurs during the multiple sector write operation, the write operation is stopped and the sector address at the time is
reflected in the register.
If the input of the WPIN signal is 1, this command gets aborted after its execution.
Input Parameters
Sector Count Register = Sector Count to be Written (00h requires 256 sectors)


1. DRDY = 0
2. Address Over
3. No Blank Blocks
Sector Number, Cylinder, Head Register = Sector Address which failed to written
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TC58NC344CF
<Write Long Sector  32h, 33h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
This command functions in the same way as the Write Sector (s) command except that it writes data and the ECC bytes for Long
Commands directly from the sector buffer. The ECC bytes for Long Commands are write bytes that consist of 4-bytes fixed length
data. The write enable sector count is limited to 1. If the input of the WPIN signal is 1, this command gets aborted after its execution.
Input Parameters
Sector Count Register = Sector Count to be written (01h fixed)


1. DRDY = 0
2. Multiple Sectors’ Transfer Request
3. Address Over
4. No Blank Blocks
Sector Number, Cylinder, Head Register = Sector Address which failed to be written
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TC58NC344CF
<Erase Sector (s)  C0h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Command (7) C0h
This is basically an Erase command to erase sectors but it is used only to check the validity of addresses in TC58NC344. If the
input of the WPIN signal is 1, this command does not get aborted after its execution.
Input Parameters
Commands only


1. DRDY = 0
2. Address Over
Sector Count Register = Sector Count which has not been erased
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TC58NC344CF
<Request Sense  03h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) X
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
Drive Head (6) 1 X 1 Drive X
Command (7) 03h
This command reads the Extended Error Codes from the Error Register after the command execution with an error.
Extended Error Codes
Extended Error Codes Description
21h Invalid Address (Requested Head or Sector Invalid)
11h Uncorrectable ECC Error
1Fh Data Transfer Error/Aborted Command
Input Parameters
Commands only

Error Register = 00h

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TC58NC344CF
<Translate Sector  87h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) X
Command (7) 87h
This command reports the programming cycle of the designated sector to the host by using the 512 bytes data (Translate Sector
Information). It supports NOP Processing in TC58NC344. The Translate Sector Information also outputs the original contents of the
Buffer before the execution of this command.
In TC58NC344 it returns the following contents as data.
・ Address ・ Information
・ 00-01 ・ Cylinder MSB (00), Cylinder LSB (01)
・ 02 ・ Head
・ 03 ・ Sector
・ 04-06 ・ LBA MSB (04) - LSB (06)
・ 07-1FF ・ 00h
Input Parameters
Commands only


1.DRDY=0
2.Address Over
Error Register = 10h
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TC58NC344CF
<Wear Level  F5h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Sector Count (2) Completion Status
Sector Number (3) X
Cylinder Low (4) X
Cylinder High (5) X
Drive Head (6) X X X Drive Flag
Command (7) F5h
In TC58NC344, this command supports NOP Processing. When this command is executed, it returns “00h” to the Sector Count
Register.
Input Parameters
Commands only


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TC58NC344CF
<Write Multiple without Erase  CDh>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Drive Head (6) X LBA X Drive Head Number (LBA27~LBA24)
Command (7) CDh
This command functions in the same way as the Write Multiple command in TC58NC344. If the input of the WPIN signal is 1, this
command will be aborted after its execution.
Input Parameters
Sector Count Register = Sector Count to be written (00h requires 256 blocks)


1. DRDY = 0
3. Address Over
4. No Blank Blocks
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TC58NC344CF
<Write Sector (s) without Erase  38h>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Command (7) 38h
This command functions in the same way as the Write Sector (s) command in TC58NC344. If the input of the WPIN signal is 1, this
Input Parameters


1. DRDY = 0
2. Address Over
3. No Blank Blocks
2001-03-25 65/91
TC58NC344CF
<Write Verify  3Ch>
Bit 7 6 5 4 3 2 1 0
Feature (1) X
Command (7) 3Ch
This command functions in the same way as the Write Sector (s) command in TC58NC344. If the input of the WPIN signal is 1, this
Input Parameters


1. DRDY = 0
2. Address Over
3. No Blank Blocks
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TC58NC344CF
Vendor Unique ATA Commands
TC58NC344 supports 6 kinds of Vendor Unique ATA Commands beside the Standard ATA Commands.
Command Name Description
Vendor Test Enable Enable TC58NC344 to receive a Vendor Test Command
Flash Read Read 528-bytes data from Flash by Physical Addressing.
Flash Write Write 528-bytes data to Flash by Physical Addressing.
Block Erase Erase data in Flash by block. (Include Invalid blocks)
EEPROM Read Read 512-bytes data from EEPROM
EEPROM Writer Write 512-bytes data to EEPROM
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TC58NC344CF
Reset Operation
TC58NC344 has four kinds of reset processes as follows.
Hardware Reset by PONRST pin
(1) TC58NC344 performs a consecutive diagnosis and sets the default values into ATA Command Block.
(2) After canceling the reset, it returns to Memory-Mapped I/O Interface.
(3) The default values of the ATA Command Block are as follows.
Error Register: 01h, Cylinder Low Register: 00h, Feature Register: 81h, Cylinder High Register: 00h,
Sector Count Register: 01h, Drive/Head Register: A0h, Sector Number Register: 01h,
FCR Configuration Option Register SRESET (D7) bit: 0
Hardware Reset by RESET pin
(3) The default values of the ATA Command Block are the same as those of the hardware reset by PONRST pin.
Software Reset by SRESET (D7) bit in FCR Configuration Option Register
(3) The default values of the ATA Command Block are the same as those of the hardware reset by PONRST pin.
(4) This reset does not influence SRESET bit. (To cancel: SRESET = 0)
Software Reset by SRST (D2) bit in ATA Drive Control Register
(1) TC58NC344 resets the host interface circuit.
(2) This reset does not influence SRST bit. (To cancel: SRST = 0)
(3) TC58NC344 maintains all the parameters before the reset regardless of the status of the Set Feature command.
However, the ATA Command Block except for the Feature Register is initialized.
(4) TC58NC344 only supplies the ATA soft reset function. It does not reset PC Card Interface. The normal access is
ensured because each parameter is not canceled even if this reset is executed every time the command
execution is finished.
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TC58NC344CF
Power Management
Normal Mode
The host can reduce the power consumption needed for the operation by changing the status of TC58NC344 with
the Power Command.
There are three conditions to transit the power control modes.
(1) XPWRDWN
(2) Command
(3) Auto Power Down Permit/Inhibit
The following table is the description.
Command PWRDWN One Auto Power Down(*1) MODE Clock Oscillation
Operational Command Condition
Condition Before
In Operation - - - Active Run
Not Operate Yet 0 - - Standby Stop
Not Operated Yet 1 Set Sleep - Sleep Stop
Not Operated Yet 1 Standby(*3) - Standby Stop
Not Operated Yet 1 Idel(*4) Permit Standby Stop(*2)
Inhibit Idle Run
Not Operated Yet 1 Others Permit Standby Stop(*2)
Inhibit Active Run
(*1) Default Inhibited
(*2) It stops after the SectorCount value when the Auto Power Down Permit is set X 5ms.
(*3) It is the same about Standby Immediate.
(*4) It is the same about Idle Immediate
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TC58NC344CF
EEPROM Interface
The EEPROM connected this interface is used in the following occasions.
・ In case the capacity of the 128 byte CIS Information Area secured in the NAND memory is not enough
・ In case of wanting to change a part of the Identify Drive Information
・ In case of using the NAND Flash Memory of an unsupported device ID
In case of connecting EEPROM or in case of using it only in IDE Mode, right CIS information must be
written in the first good block in the connected NAND Flash Memory.
This is to confirm the connection condition of the Flash Memory because CIS information is being used.
EEPROM uses X24CO4 (Xicor company production). Outline specification of this product are as follows.
・ An Interface with two lines
・ Power Supply Voltage: 3.3V(EEPROM can connect with TC58NC344 directly)
・ Serial Clock : Possible to operate with 100KHz
・ Capacity : More than 4096 bits
・ EEPROM Interface : Write time 10ms or less
In case of not using EEPROM, please have the connection pins (EEPROMSD and EEPROMSC)open.
Please refer to “Process of programming/re-programming CIS/Identify Drive and Test Commands” for data
formatting and access procedures.
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TC58NC344CF
Drive Capacity
TC58NC344 can set the following capacities.
Drive Flash Chip Number of Number of Number of Sectors per Number of
Capacity Capacity Flash Chips Cylinders Heads Track Sectors
1 Mbytes 8 Mbits 1 125 4 4 2,000
2 Mbytes 16 Mbits 1 125 4 8 4,000
4 Mbytes 32 Mbits 1 250 4 8 8,000
8 Mbytes 64 Mbits 1 250 4 16 16,000
16 Mbytes 128 Mbits 1 500 4 16 32,000
32 Mbytes 256 Mbits 1 500 8 16 64,000
64 Mbytes 512 Mbits 1 500 8 32 128,000
128 Mbytes 1 Gbit 1 500 16 32 256,000
Flash Memory Identification Method

TC58NC344 recognizes the Flash Memory capacity by Reading the Flash Memory Device ID. After reading the normal
Device ID, the first 10 bytes of the first valid block “CIS/Identify Drive information Area” are checked in order to determine
whether the physical formatting has been performed or not. If unsupported Device ID or an illegal data is found from the
first 10 bytes, the status is determined to be disabled (BSY state).
If a disabled state (BSY state) is found, please perform the physical formatting in the Flash Memory by using the Vendor
Unique ATA Command.
The recognizable Device IDs are as follows.

Flash Memory Mask ROM 版
Device ID Device ID
(SmartMedia) SmartMedia
8 Mbits NAND
“6Eh” “E8h” “ECh”
(1 Mbytes)
16 Mbits NAND
“64h” “EAh”
(2 Mbytes)
32 Mbits NAND
“6Bh” “E3h” “E5h” 4 Mbytes “D5h”
(4 Mbytes)
64 Mbits NAND
“E6h” “EDh” 8 Mbytes “D6h”
(8 Mbytes)
128 Mbits NAND
“73h” 16 Mbytes “57h”
(16 Mbytes)
256 Mbits NAND
“75h” 32 Mbytes “58h”
(32 Mbytes)
512 Mbits NAND
“76h” 64 Mbytes “D9h”
(64 Mbytes)
1 Gbit NAND
“79h” 128 Mbytes “DAh”
(128 Mbytes)
Note) The timing of the first access to Flash Memory by TC58NC344 is 1024 µsec after canceling the PONRST pin or the RESET
pin. So, please perform the Flash Memory Power stabilization during this period.
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TC58NC344CF
Others
By using TC58NC344, it is possible to make a Flash Disk with the characteristics stated below.
The figure below is reference data based on either theoretical one or actual one.
System Performance
Media Transfer Rate

Read (Max) 1.2 Mbytes/sec
Write (Max) 1.0 Mbytes/sec
Interface Transfer Rate
Read/Write (Max) 8.0 Mbytes/sec
How to calculate Read and Write Performance

* The Value and Condition for the calculation
NAND Flash Memory
: TOSHIBA 512Mbit
The Reading Time of 1 Sector
: About 0.1msec
The Writing Time of 1 Sector
: About 0.3msec (Please refer to NAND Flash Memory Datasheet.)
The Erasing Time of 1 Block (32 Sectors)
: About 3msec (Please refer to NAND Flash Memory Datasheet.)
The Transaction Time of Controller for 1 to 32 Sectors New Write in the case of Address Hit
: About 2.1msec
The Transaction Time of Controller for 1 to 32 Sectors New Write in the case of Address Miss Hit
: About 14.8msec
The Transaction Time of Controller for 1 to 32 Sectors Overwrite in the case of Address Hit
: About 4.7msec
The Transaction Time of Controller for 1 to 32 Sectors Overwrite in the case of Address Miss Hit
: About 17.4msec
The Transaction Time of Controller for 1 Sector Read in the case of Address Hit
: About 0.2msec
The Transaction Time of Controller for 1 Sector Read in the case of Address Miss Hit
: About 12.9msec
Note)
This controller can have the lookup table, which is a table for address translation from host logical address to flash
physical address, of only 1 zone NAND Flash Memory. When host logical address exists in the lookup table (Address
Hit), the controller can operate quickly. But when host logical address does not exist in the lookup table (Address
Miss Hit), the controller cannot operate quickly because the controller must remake the lookup table.
* The Read Performance

The Read Performance can be calculated by the Reading Time of 1 Sector (0.1msec) x Sector Count + the
Transaction Time of Controller for 1 Sector read in the case of Address Hit or Address Miss Hit x Sector Count + Data
Transfer Time from Controller to Host.
* The Write Performance

The Write Performance must be changed by the Sector Count, the Sector Number that is the Writing Start Address
and how to write, such as New Write or Overwrite. So it is very difficult to specify the Write Performance to the fixed
value. The following descriptions are the examples of the Write Performance.
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TC58NC344CF
Example1:
*The Condition
Sector Count : 32
The Writing Start Address: The Top of Block
The Writing Mode: Overwrite in the case of Address Hit
*The Write Performance

The Erasing Time of 1 Block = 3msec
The Writing Time of 32 Sectors = 9.6msec (0.3msecx32)
The Transaction Time of Controller for 32 Sectors Write = 4.7msec
Therefore, 3 + 9.6 + 4.7 = about 17.3msec + Data Transfer Time from Host to Controller
Example2:
*The Condition
Sector Count : 32
The Writing Mode: Overwrite in the case of Address Miss Hit

Therefore, 3 + 9.6 + 17.4 = about 30msec + Data Transfer Time from Host to Controller
Example3:
*The Condition
Sector Count : 32
The Writing Start Address: The Second Page of Block

The Erasing Time of 2 Blocks = 6msec (3msecx2)
The Transaction Time of Controller for 64 Sectors Write =9.4msec (4.7msecx2)
Example4:
*The Condition
Sector Count : 32

The Erasing Time of 2 Blocks = 6msec (3msecx2)
Example5:
*The Condition
Sector Count : 32
The Writing Mode: New Write in the case of Address Hit

Therefore, 9.6+2.1 = about 11.7msec + Data Transfer Time from Host to Controller
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TC58NC344CF
Example6:
*The Condition
Sector Count : 32
The Writing Mode: New Write in the case of Address Miss Hit

Example7:
*The Condition
Sector Count : 32

Therefore, 19.2 + 4.2 = about 23.4msec + Data Transfer Time from Host to Controller
Example8:
*The Condition
Sector Count : 32

Therefore, 19.2 + 29.6 = about 48.8msec + Data Transfer Time from Host to Controller
Example9:
*The Condition
Sector Count : 1
(It is same result although the writing start address is the second page or the last page of block.)

Example10:
*The Condition
Sector Count : 1

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TC58NC344CF
Example11:
*The Condition
Sector Count : 1

Example12:
*The Condition
Sector Count : 32

Note)
The above values are calculated by using the typical write and erase performance specifications of NAND Flash Memory.
The calculations may be needed to use the worst write and erase performance specifications of NAND Flash Memory.
Setup Time
Standby/Power Down to Active (Typ.) 512 µsec

Power on to Ready (Typ.) 50 msec
Change zone to zone (Typ.) 50ms
PC Card ATA Power Consumption of TC58NC344
Read (Typ.) 23mA

Write (Typ.) 38mA
Power Down (Typ.) 1.1mA
* The Condition 1 : In 5V operation
The Condition 2 : 64MB SmartMedia (3.3V)
The Condition 3 : Power Consumption of charge pump circuit which converts from 3.3V to 5.0V include.
Static Current(Max.)
Only 344 : 0.3mA
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TC58NC344CF
MTBF
The MTBF Specification is the Logical MTBF calculated for restricting the reprogramming cycle and it is not
considered for the physical aspects. By the formula stated below, it is possible to obtain MTBF.
#of Flash Chips × #of Blocks × Re-programming Cycle × Re-programming Area Rate
MTBF =
Average Programming Sector per Hour (1 sector = 512 byte)
Notes) Since the Program Area has no possibility to be reprogrammed once it is programmed, the Re-programming
Area Rate means the area which excludes all the area that is not re-programmable. For example, if 32 Kbyte
(64 sectors) of writing in 5 minutes reprograms 30% of a 4 Mbyte (32 Mbit) disk, its MTBF can be calculated
as follows.
MTBF = (512 × 1,000,000 × 0.3) / (64 × 12)
= 200,000 hours
Even if it is supposed that the write access is increased 5 times, its MTBF is calculated up to 200,000 hours.
In case there is a problem by using the MTBF Specifications, it is possible to prolong the life time of your
system by reprogramming the area regularly which has no possibility of being reprogrammed. This is for the
Re-programming Area Rate to be 100%.
ECC
44 bits/sector (1 bit correction or 2 bit detection is possible.)
Reliability
15
1/10 bits Read
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TC58NC344CF
Absolute Maximum Ratings
The maximum rating is a critical value that should not be exceeded even for an instant. As long as the product is used
within the maximum rating as defined, no permanent damage will ever be occurred. However, this does not guarantee
the normal logical operation.
Parameter Symbol Rating Unit
VDD3.3 −0.5~4.6
Supply Voltage
VDD −0.5~6.0
LVTTL V = −0.5~4.6 and V < VDD3.3 + 0.5 V
Input Voltage 5 V Tolerant Buffer V V = −0.5~6.6 and V < VDD3.3 + 3.0
5 V Full Swing Buffer V = −0.5~6.0 and V < VDD + 0.5
IOL = 3 mA 10
Output Current IOL = 6 mA IO 20 mA
IOL = 18 mA 60
Storage Temperature TST −65~150 °C
Operating Ranges
The recommended operating condition are the recommended values which guarantee the normal logical operation of
the device. It is guaranteed that the electrical characteristics (direct current alternate current characteristics) are satisfied.
Parameter Symbol Rating Unit
VDD3.3 3.0~3.6
Supply Voltage V
3.0~3.6
VDD
4.5~5.5
Ambient Operating Temperature TA −20~70 °C
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TC58NC344CF
DC Characteristics
Rating
Parameter Symbol Condition Unit
MIN MAX
VIH1 LVTTL
2.0
Input VIH2 TTL 5 V Tolerant
1 V
Voltage VIH3 5 V Full Swing CMOS VDD × 0.7
VIH4 5 V Full Swing TTL 2.2
VIL1 LVTTL
0.8
Input VIL2 TTL 5 V Tolerant
0 V
Voltage VIL3 5 V Full Swing CMOS VDD × 0.3
VIL4 5 V Full Swing TTL 0.8
VP1 TTL 5 V Tolerant Schmitt 1.2 2.4

Input
Positive VP2 CMOS Schmitt 1.8 4.0 V
Trigger
VP3 TTL Schmitt 1.2 2.4
VN1 TTL 5 V Tolerant Schmitt 0.6 1.8

Input
Negative VN2 CMOS Schmitt 0.6 3.1 V
Trigger
VN3 TTL Schmitt 0.6 1.8
LVTTL IOH = −3 mA
Output 2.4
TTL 5 V Tolerant IOH = −1.5 mA
H VOH V
Voltage 5 V Full Swing IOL = −3 mA
VDD − 0.4
IOL = −12 mA
LVTTL IOL = 3 mA
Output
TTL 5 V Tolerant IOL = 3 mA
L VOL 0.4 V
Voltage 5 V Full Swing IOL = 6 mA
IOL = 18 mA
Pull-up 3.3 V 20 300

RPU
Resister 5V 20 125
KΩ
Pull-down 3.3 V 15 300
RPD
Resister 5V 15 100
The voltage conditions concerning the above are LVTTL : 3.0~3.6V

TTL 5 V Tolerant : 3.0~3.6V
5 V Full Swing CMOS / TTL : 4.5~5.5V
Parameter Symbol Condition TYP MAX Unit
II3.3 VI = VDD (3.3V) or GND +10 -5

+10
II3.3 VI = GND (with Pull-up Resistor) -50 -180

Input II3.3 VI = VDD (3.3V) (with Pull-down Resistor) 70 225
Leak µ
Current II5.0 VI = VDD (5.0V) or GND +10-5 +10
II5.0 VI = GND (with Pull-up Resistor) -100 -250
II5.0 VI = VDD (5.0) (with Pull-down Resistor) 100 350
Output
Leak IOZ VDD = VDD(5.0) or VDD (3.3V) or GND - +10 µ
Current
2001-03-25 78/91
TC58NC344CF
Capacitance
Parameter Symbol Rating (MAX) Unit
Input Capacitance CIN 20
Output Capacitance COUT 20 pF
Bi-directional Capacitance CI/O 20
2001-03-25 79/91
TC58NC344CF
Switching Characteristics
About Load Capacity
1.PC Card ATA / IDE Interface

PIN NAME Load Capacity
D15 – D0[DD15 – DD0] 100pF
/IOIS16 (WP)[/IOIS16] 50pF
/IREQ (READY)[INTRQ] 50pF
/INPACK[ - ] 50pF
/STSDHG[/PDIAG] 50pF
LOGICH(/SPKR)[/DASP (LED)] 50pF
/WAIT[IORDY] 50pF
2.Flash Memory Interface (TC58NC344)

PIN NAME Load Capacity
FD7 – FD0 90pF
/FCE 90pF
FCLE 90pF
FALE 90pF
/FRE 90pF
/FWE 90pF
/FWP 90pF
2001-03-25 80/91
TC58NC344CF
1. PC Card Interface
Attribute Memory and Common Memory Read Timing
T1
T2 T9
A[10:0], REG
T3 T7
T10
CE[2:1]
T8 T4 T11
OE
T6 T5
D[15:0]
Symbol Parameter Min Max Unit
T1 Read Cycle Time 250 
T2 Address Access Time  250
T3 Card Enable Access Time  250
T4 Output Enable Access Time  125
T5 Output Disable Time from OE  100
T6 Output Enable Time from OE 5  ns
T7 Data Valid from Add Change 0 
T8 Address Setup Time 30 
T9 Address Hold Time 20 
T10 Card Enable Setup Time 0 
T11 Card Enable Hold Time 20 
2001-03-25 81/91
TC58NC344CF
Attribute Memory and Common Memory Write Timing
T20
A[10:0], REG
T24
T33
CE[2:1]
T23 T34
OE
T22 T21 T26
WE
T31 T32
T25
D[15:0] (Din)
T27
T28 T30
T29
D[15:0] (Dout)
T20 Write Cycle Time 250 
T21 Write Pulse Width 150 
T22 Address Setup Time 30 
T23 Address Setup Time for WE 180 
T24 Card Enable Setup Time for WE 180 
T25 Data Hold Time 30 
T26 Write Recover Time 30 
T27 Output Disable Time from WE  100 ns
T28 Output Disable Time from OE  100
T29 Output Enable Time from WE 5 
T30 Output Enable Time from OE 5 
T31 Output Enable Setup from WE 10 
T32 Output Enable Hold from WE 10 
T33 Card Enable Setup Time 0 
T34 Card Enable Hold Time 20 
2001-03-25 82/91
TC58NC344CF
I/O Read Timing
A[10:0]
T44
T47 T48
REG
T45 T46
CE
T42
IORD
T43
INPACK
T49 T51
IOIS16
T50 T40 T41
D[15:0]
T40 Data Delay after IORD  100
T41 Data Hold following IORD 0 
T42 IORD Width Time 165 
T43 Address Setup before IORD 70 
T44 Address Hold following IORD 20 
T45 CE Setup before IORD 5 

ns
T46 CE Hold following IORD 20 
T47 REG Setup before IORD 5 
T48 REG Hold following IORD 0 
T49 INPACK Delay Falling from IORD 0 45
T50 IOIS16 Delay Falling from Address  35
T51 IOIS16 Delay Rising from Address  35
2001-03-25 83/91
TC58NC344CF
I/O Write Timing
A[10:0]
T63
T66 T67
REG
T64 T65
CE
T61
IOWR
T62 T69
IOIS16
T68 T60
D[15:0]
T60 Data Hold following IOWR 30 
T61 IOWR Width Time 165 
T62 Address Setup before IOWR 70 
T63 Address Hold following IOWR 20 
T64 CE Setup before IOWR 5 

ns
T65 CE Hold following IOWR 20 
T66 REG Setup before IOWR 5 
T67 REG Hold following IOWR 0 
T68 IOIS16 Delay Falling from Address  35
T69 IOIS16 Delay Rising from Address  35
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TC58NC344CF
2. IDE Interface
IDE Read Timing
Address
T74
T75
CE T76
T73 T72
DIOR
T78
IOCS16
T77
T70 T71
DD[15:00]
T70 Data Delay after DIOR  100
T71 Data Hold following DIOR 0 
T72 DIOR Width Time 165 
T73 Address Setup before DIOR 70 
T74 Address Hold following DIOR 20  ns
T75 CS Setup before DIOR 5 
T76 CS Hold following DIOR 20 
T77 IOCS16 Delay Falling from Address  35
T78 IOCS16 Delay Rising from Address  35
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TC58NC344CF
IDE Write Timing
Address
T84
T85
CE T86
T83 T82
DIOW
T88
IOCS16
T87
T80 T81
DD[15:00]
T80 Data Setup before DIOW 60 
T81 Data Hold following DIOW 30 
T82 DIOW Width Time 165 
T83 Address Setup before DIOW 70 
T84 Address Hold following DIOW 20  ns
T85 CS Setup before DIOW 5 
T86 CS Hold following DIOW 20 
T87 IOCS16 Delay Falling from Address  35
T88 IOCS16 Delay Rising from Address  35
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TC58NC344CF
3.Flash Writng Timing
Flash Write Timing
T92
FCE
FWP
FCLE
T90
T91
FALE
T95
T96
T9A T93
FWE
T99 T94
FD[07::00]
T97 T98
T9B
FBSY
T90 FCLE Setup Time 50 
T91 FCLE Hold Time 50 
T92 FCE Setup Time 50 
T93 FCE Hold Time 50 
T94 FWE Pulse Width 50 
T95 FALE Setup Time 50 

ns
T96 FALE Hold Time 50 
T97 Data Setup Time 50 
T98 Data Hold Time 50 
T99 Write Cycle Time 100 
T9A FWE High Hold Time 50 
T9B Last FWE High to FBSY  205
2001-03-25 87/91
TC58NC344CF
Flash Read Timing
FBSY
T106
FWE
T105 T102
T104
FRE
T100
T103 T101
FD[07::00]
T100 Ready to FRE Low 150 
T101 FRE Pulse Time 50 
T102 Read Cycle Time 100 
FRE Access Time (Read) 50 
T103 FRE Low Status Output (Status Read) 50  ns
FRE Access Time (ID Read) 120 
T104 FRE High Hold Time 25 
T105 FWE High to FRE Low 70 
T106 Last FRE High to FBSY  205
There is no timing restriction of NAND Flash Memory concerning below.

tR, tCRY, tBERASE, tPROG, tBERS
2001-03-25 88/91
TC58NC344CF
4. Clock Input Timing
TC58NC344 Clock Input Timing is as follows.
TC
TP TF TN TR
Symbol Parameter Min Typ. Max Unit
TP 1 Time 28  
TN 0 Time 28  
TR Rise Time   5 ns
TF Fall Time   5
TC Cycle Time 62.5  
5. Reset Input Condition

TC58NC344 Reset Input Condition is as follows.
RESET
TAW
TAW Reset Width 30  ns
TRP
0.9VDD
PONRST
0.1VDD
TRP Rise Time  12 ns
Please refer to Reset Sequence.
2001-03-25 89/91
TC58NC344CF
6. Reset Sequence
VCC
PONRST
1. PC Card ATA Mode (Normal)
RESET
TC58NC344
is initialized.
2. PC Card ATA Mode (RESET OPEN)
RESET OPEN
TC58NC344
is initialized.
3. PC Card ATA Mode (RESET)
RESET
TC58NC344
is initialized.
4. IDE Mode (When PONRST absolve RESET is "H")
RESET
TC58NC344
is initialized.
5. IDE Mode (When PONRST absolve RESET is "L")
RESET
TC58NC344
is initialized.
RESETtime
Note) RESET of TC58NC344 is absolved in the above(↑) part.
2001-03-25 90/91
TC58NC344CF
Physical Dimensions
• TQFP100-P-1414-0.50C
Unit: mm
2001-03-25 /91 91

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TC58NC344CF

Pin Assignment Table ･･･････････････････････････････････････････････････････････････････････････････････ 3

Voltage Level Input Signal Output Signal

16 B LOGICH ( SPKR ) DASP (LED) 7

1 LVTTL I/O Buffer (IOL = 3 mA) with Pull-Up Resister

2 LVTTL Input Buffer

3 5 V Full Swing 3-State Output Buffer (CMOS Output: IOL = 6 mA)

6 5 V Full Swing Input Buffer (TTL Input)

8 LVTTL Output Buffer (IOL = 3 mA)

9 5 V Full Swing Input Buffer (TTL Input) with Pull-Up Resister

10 5 V Full Swing Input Buffer (TTL Input) with Pull-Down Resister

12 5 V Full Swing Input Buffer (CMOS Schmitt Input)

13 5 V Tolerant Input Buffer

14 5 V Tolerant I/O Buffer (IOL = 3 mA) with Pull-Down Resister

15 5 V Tolerant Output Buffer (IOL = 3 mA)

16 5 V Tolerant Input Buffer (Schmitt Input)

SYMBOL No. I/O NAME DESCRIPTION

In PC Card mode, it is in reset condition by detecting the edge

Please refer “Reset Sequence”, Section 6 of Switching

SYMBOL No. I/O NAME DESCRIPTION

SYMBOL No. I/O NAME DESCRIPTION

SYMBOL No. I/O NAME DESCRIPTION

* TC58NC344 does not supported 2-Drive protocol, therefore,

* TC58NC344 does not supported 2-Drive protocol, therefore,

SYMBOL No. I/O NAME DESCRIPTION

SYMBOL No. I/O NAME DESCRIPTION

EEPROMSD 3 B EEPROM This is a Serial Data I/O pin for EEPROM.

EEPROMSC 19 O EEPROM This is a Serial Clock Output pin for EEPROM.

SYMBOL No. I/O NAME DESCRIPTION

This pin does not change after power-on. Also, changing it is

PONRST 64 I POWER ON This is a power-on reset for TC58NC344. By making this

OCTL 96 O OSCILLATOR This is a Oscillation Control Signal. In using an oscillator with

RMCLK 99 I DEFERENCE This is a Master Clock Input of TC58NC344. This pin is a

SYMBOL No. I/O NAME DESCRIPTION

2. System Configuration Examples

[PC Card ATA]

VDD VDD3.3 To VCC of Flash

[Attribute Memory Reading Operation]

Function Mode REG CE2 CE1 A0 OE WE D15~D8 D7~D0

Standby Mode * 1 1 * * * Hi-Z Hi-Z

0 1 0 0 0 1 Hi-Z Even byte

Word Access (16 Bits) 0 0 0 * 0 1 Invalid Even byte

Odd Byte Only Access 0 0 1 * 0 1 Invalid Hi-Z

[Attribute Memory Writing Operation]

Function Mode REG CE2 CE1 A0 OE WE D15~D8 D7~D0

Word Access (16 Bits) 0 0 0 * 1 0 * Even byte

Odd Byte Only Access 0 0 1 * 1 0 * *

[Attribute Memory Address Map]

Address CE REG WE OE FCR Read/Write

* 0 1 1 0 Common Memory Read R

* 0 1 0 1 Common Memory Write W

* 0 0 1 0 Card Information Structure Read R

* 0 0 * * Invalid Access Invalid

<Common Memory Space>

[Common Memory Reading Operation]

Function Mode REG CE2 CE1 A0 OE WE D15~D8 D7~D0

Standby Mode * 1 1 * * * Hi-Z Hi-Z

1 1 0 0 0 1 Hi-Z Even byte

Word Access (16 Bits) 1 0 0 * 0 1 Odd byte Even byte

Odd Byte Only Access 1 0 1 * 0 1 Odd byte Hi-Z