A CAPACITOR-LESS LOW DROP-OUT VOLTAGE REGULATOR

WITH FAST TRANSIENT RESPONSE

A Thesis

by

ROBERT JON MILLIKEN

Submitted to the Office of Graduate Studies of

Texas A&M University
in partial fulfillment of the requirements for the degree of

MASTER OF SCIENCE

December 2005

Major Subject: Electrical Engineering

 A CAPACITOR-LESS LOW DROP-OUT VOLTAGE REGULATOR

WITH FAST TRANSIENT RESPONSE

A Thesis

by

ROBERT JON MILLIKEN

Submitted to the Office of Graduate Studies of

Texas A&M University
in partial fulfillment of the requirements for the degree of

MASTER OF SCIENCE

Approved by:

Co-Chairs of Committee, Jose Silva-Martinez

Edgar Sanchez-Sinencio
Committee Members, Aydin Karsilayan
Prasad Enjeti
Michael Pilant
Head of Department, Costas Georghiades

December 2005

Major Subject: Electrical Engineering

 iii

ABSTRACT

A Capacitor-less Low Drop-out Voltage Regulator

with Fast Transient Response. (December 2005)
Robert Jon Milliken, B.S., Iowa State University
Co-Chairs of Advisory Committee: Dr. Jose Silva-Martinez
Dr. Edgar Sanchez-Sinencio

Power management has had an ever increasing role in the present electronic industry.
Battery powered and handheld applications require power management techniques to extend the
life of the battery and consequently the operation life of the device. Most systems incorporate
several voltage regulators which supply various subsystems and provide isolation among such
subsystems. Low dropout (LDO) voltage regulators are generally used to supply low voltage,
low noise analog circuitry. Each LDO regulator demands a large external capacitor, in the range
of a few microfarads, to perform. These external capacitors occupy valuable board space,
increase the IC pin count, and prohibit system-on-chip (SoC) solutions.
The presented research provides a solution to the present bulky external capacitor LDO
voltage regulators with a capacitor-less LDO architecture. The large external capacitor was
completely removed and replaced with a reasonable 100pF internal output capacitor, allowing
for greater power system integration for SoC applications. A new compensation scheme is
presented that provides both a fast transient response and full range ac stability from a 0mA to
50mA load current. A 50mA, 2.8V, capacitor-less LDO voltage regulator was fabricated in a
TSMC 0.35um CMOS technology, consuming only 65uA of ground current with a dropout
voltage of 200mV.
Experimental results show that the proposed capacitor-less LDO voltage regulator exceeds
the current published works in both transient response and ac stability. The architecture is also
less sensitive to process variation and loading conditions. Thus, the presented capacitor-less
LDO voltage regulator is suitable for SoC solutions.
 iv

To my parents for their encouragement, love, and support

 v

ACKNOWLEDGMENTS

I would like to first thank my advisors Dr. Jose Silva-Martinez and Dr. Edgar Sanchez-
Sinencio for their expert knowledge and guidance throughout my entire Master’s program at
Texas A&M University. I would also like to thank my peers, namely Abraham Islas-Olimar,
Julio Aaylas, Chad Marquart, Farmarz Bahmani, Artur Lewinski, Arun Ramachandran,
Chinmaya Mishra, Alberto Valdes-Garcia, Feyza Berber, and Burak Kelleci for their input and
moral support. I would also like to extend my thanks to Dr. Randall Geiger and Prof. Patterson
from Iowa State University to whom I owe my acceptance and preparation towards achieving a
Master of Science degree in electrical engineering. Finally, I would like to thank my family for
all their love and support along my arduous journey in the electrical engineering profession. To
my family, I owe them my current successes and the success that will follow in the future.
Thank you.
 vi

TABLE OF CONTENTS

Page

ABSTRACT ............................................................................................................................ iii

DEDICATION ........................................................................................................................ iv
ACKNOWLEDGMENTS ....................................................................................................... v
TABLE OF CONTENTS ........................................................................................................ vi
LIST OF FIGURES................................................................................................................. vii
LIST OF TABLES .................................................................................................................. x
I. INTRODUCTION................................................................................................................ 1
A. LDO Regulator Applications................................................................................. 1
B. Conventional Linear and LDO Regulator Architectures ....................................... 4
C. LDO Regulator Characterization ........................................................................... 7
D. Capacitor-less LDO Voltage Regulators ............................................................... 12
II. CAPACITOR-LESS LDO REGULATOR DESIGN ......................................................... 21
A. Uncompensated Device Characterization.............................................................. 22
B. Design Architecture Strategy................................................................................. 38
III. TRANSISTOR-LEVEL DESIGN AND SIMULATION ................................................. 58
A. Transistor-level Simulations.................................................................................. 61
B. Statistical Analysis................................................................................................. 74
C. Final LDO Layout.................................................................................................. 78
IV. EXPERIMENTAL RESULTS .......................................................................................... 80
A. Test Board Design ................................................................................................. 80
B. Transient Response ................................................................................................ 81
C. High-Frequency Response..................................................................................... 86
D. Comparison of Results........................................................................................... 89
V. CONCLUSION .................................................................................................................. 91
REFERENCES ........................................................................................................................ 92
APPENDIX A TEST BOARD FOIL PATTERN ................................................................... 94
APPENDIX B TEST BOARD SCHEMATIC ........................................................................ 95
VITA ....................................................................................................................................... 96
 vii

LIST OF FIGURES

Page
Fig. 1. Cell phone power management application.......................................................................... 2
Fig. 2. Cell phone battery characteristics......................................................................................... 3
Fig. 3. High efficiency linear regulation.......................................................................................... 4
Fig. 4. Linear voltage regulator topologies...................................................................................... 4
Fig. 5. AC pole locations without compensation............................................................................. 5
Fig. 6. Conventional LDO regulator compensation......................................................................... 6
Fig. 7. LDO regulator parameters.................................................................................................... 8
Fig. 8. Capacitor-less LDO voltage regulator................................................................................ 13
Fig. 9. Pole locations for uncompensated capacitor-less LDO voltage regulator.......................... 14
Fig. 10. Equivalent circuit for fast load transients. ........................................................................ 16
Fig. 11. Power efficiency tradeoff. ................................................................................................ 17
Fig. 12. Capacitor-free LDO voltage regulator.............................................................................. 18
Fig. 13. LDO compensation with CF1. ........................................................................................... 18
Fig. 14. LDO regulator with pole/zero tracking. ........................................................................... 19
Fig. 15. Basic capacitor-less LDO concept.................................................................................... 20
Fig. 16. Pass transistor design........................................................................................................ 23
Fig. 17. AC open-loop simulation circuit. ..................................................................................... 26
Fig. 18. AC open-loop block diagram test circuit.......................................................................... 27
Fig. 19. Feedback circuit with parasitic capacitor, CF1. ................................................................. 28
Fig. 20. Pass transistor small signal analysis. ................................................................................ 29
Fig. 21. Pass transistor output resistance models........................................................................... 31
Fig. 22. Pass transistor load-dependent DC operating points:
(a) transconductance (b) output resistance. ..................................................................... 32
Fig. 23. Uncompensated LDO AC response.................................................................................. 34
Fig. 24. Uncompensated LDO AC parameters verses Iout:
(a) output pole frequency (b) phase margin..................................................................... 34
Fig. 25. Uncompensated AC response simulated in CADENCE. ................................................. 35
Fig. 26. Close-loop uncompensated LDO load transient test circuit. ............................................ 36
Fig. 27. 0 to 50mA load transient response. .................................................................................. 37
Fig. 28. Pass transistor gate transient effect................................................................................... 38
 viii

Page
Fig. 29. Fast transient path general concept................................................................................... 39
Fig. 30. Basic capacitive differentiator.......................................................................................... 40
Fig. 31. Addition of differentiator fast path................................................................................... 41
Fig. 32. Differentiator voltage mode AC response. ....................................................................... 42
Fig. 33. Simplest coupling network............................................................................................... 43
Fig. 34. Proposed coupling network. ............................................................................................. 44
Fig. 35. Differentiator charge analysis........................................................................................... 45
Fig. 36. Proposed topology: simplified circuit diagram. ............................................................... 48
Fig. 37. Proposed capacitor-less LDO voltage regulator: Open-loop schematic........................... 49
Fig. 38. Differential equivalent circuit diagram. ........................................................................... 50
Fig. 39. (a) General differentiator pole movement with gmf1
(b) Differentiator open-loop AC response....................................................................... 51
Fig. 40. Differentiator closed-loop pole movement with changing load current........................... 53
Fig. 41. Modified block diagram. .................................................................................................. 53
Fig. 42. Complete root locus showing closed-loop pole movement
for both load current variations and feedback factor, β. .................................................. 54
Fig. 43. Stability constraint for the differentiator’s complex close-loop poles.............................. 56
Fig. 44. MATLAB simulation: Open-loop AC response for IOUT = 0mA. .................................... 57
Fig. 45. Proposed capacitor-less LDO transistor-level design....................................................... 58
Fig. 46. Spice simulation: Transistor-level open-loop AC response. ........................................... 60
Fig. 47. Low output current open-loop AC response for Iout = 0 ~ 4mA. ...................................... 62
Fig. 48. Full range open-loop AC response for Iout = 0 ~ 50mA. .................................................. 63
Fig. 49. Variation in compensation resistor, Rf. ............................................................................ 64
Fig. 50. Variation in compensation capacitor, Cf. ......................................................................... 65
Fig. 51. Line regulation for Iout = 0mA. ......................................................................................... 66
Fig. 52. Load regulation for Vin = 3V........................................................................................... 66
Fig. 53. Full load transient response (without Cf2 and Cf3)............................................................ 67
Fig. 54. Load transient response for zero to full load with Cf2 and Cf3.......................................... 68
Fig. 55. Line transient response for Iout set to 0mA (a) and 1mA (b). ........................................... 69
Fig. 56. Turn-on settling time for various output current conditions:
(a) full pulse and (b) expanded view. .............................................................................. 70
Fig. 57. Equivalent output noise for various loading conditions. .................................................. 71
 ix

Page
Fig. 58. PSRR measurement for various output current conditions. ............................................. 73
Fig. 59. Process variation for IOUT = 0mA: nominal GBW
(a) and phase margin (b), Cf and Rf +20% of nominal GBW
(c) and phase margin (d), and Cf and Rf -20% of nominal GBW
(e) and phase margin (f). ................................................................................................. 74
Fig. 60. Process variation on DC gain for IOUT = 0mA (a) and 1mA (b). ...................................... 75
Fig. 61. Process variations effects on dc quiescent current. .......................................................... 76
Fig. 62. Process variation on PSRR for Iout = 0mA at 1Hz
(a) and 100kHz (b) and for Iout = 50mA at 1Hz (c) and 100kHz (d) ............................... 76
Fig. 63. Process variation on DC steady-state output voltage for Iout set to
0mA (a), 1mA (b), 10mA (c) and 50mA (d). .................................................................. 77
Fig. 64. Final layout in TSMC 0.35µm CMOS technology. ......................................................... 78
Fig. 65. Final populated test board and setup. ............................................................................... 80
Fig. 66. Transient load current generator....................................................................................... 81
Fig. 67. Transient response for a 0mA to 50mA load transient with VIN = 3V. ............................ 82
Fig. 68. Experimental line transient response with Iout = 0mA. ..................................................... 83
Fig. 69. Turn-on settling time for IOUT = 0mA: full pulse (a) and expanded view (b)................... 84
Fig. 70. Turn-on settling time for IOUT = 10mA (a) and IOUT = 50mA (b). .................................... 85
Fig. 71. PSRR for various loading conditions. .............................................................................. 87
Fig. 72. Line ripple rejection at 100Hz.......................................................................................... 88
Fig. 73. Noise Spectrum for 50mA output current. ....................................................................... 89
Fig. 74. Top layer of PCB.............................................................................................................. 94
Fig. 75. Bottom layer of PCB from top view................................................................................. 94
Fig. 76. Test board schematic diagram. ......................................................................................... 95
 x

LIST OF TABLES

Page

TABLE I. Capacitor-less LDO Specification ....................................................................... 21

TABLE II. TSMC 0.35 Data: Run T4CU .............................................................................. 24
TABLE III. Pass Transistor Dimensions ................................................................................. 24
TABLE IV. Amplifier Block Small Signal Transfer Functions .............................................. 30
TABLE V. AC Response Test Circuit Parameters................................................................. 33
TABLE VI. Load Dependent Poles and Zeros ........................................................................ 36
TABLE VII. Differentiator Simplifications .............................................................................. 50
TABLE VIII. Design Guide ....................................................................................................... 59
TABLE IX. Fabricated Circuit Parameters.............................................................................. 61
TABLE X. Integrated Output Noise: 1Hz ~ 100kHz ............................................................. 72
TABLE XI. Simulated Worst Case Parameters....................................................................... 73
TABLE XII. Final LDO Comparison ....................................................................................... 90
 1

I. INTRODUCTION

Industry is pushing towards complete system-on-chip (SoC) design solutions including

power management. The study of power management techniques has increased dramatically
within the last few years corresponding to the vast increase in the use of portable, handheld
battery operated devices [1]. Power management seeks to improve the device power’s efficiency
resulting in prolonged battery life and operating time for the device. A power management
system contains several subsystems including linear regulators, switching regulators, and control
logic. The control logic changes the attributes of each subsystem; turning the outputs on and off
as well as changing the output voltage levels, to optimize the power consumption of the device.
The presented research focuses on low drop-out (LDO) voltage regulators. LDO
regulators are an essential part of the power management system that provides constant voltage
supply rails. They fall into a class of linear voltage regulators with improved power efficiency.
LDO voltage regulators have several inherent advantages over conventional linear voltage
regulators making them more suitable for on-chip power management systems [2].
A power management system usually contains several LDO regulators and switching
regulators. The conventional LDO voltage regulator requires a relatively large output capacitor
in the single microfarad range. Large microfarad capacitors can not be realized in current design
technologies, thus each LDO regulator needs an external pin for a board mounted output
capacitor. The presented research proposes to remove the large external capacitor, eliminating
the need for an external pin. Removing the large output capacitor also reduces the board real
estate and the overall cost of the design and makes it suitable for SoC applications.

A. LDO Regulator Applications

LDO voltage regulators compose a small subset of the power supply arena. LDO
voltage regulators are used in analog applications that generally require low noise, high accuracy
power rails. Voltage regulators provide a constant voltage supply rail under all loading
conditions.

This thesis follows the style of the IEEE Journal of Solid-State Circuits.
 2

These conditions include fast current transients and rapid changes in the load impedance. Most
hand-held, battery-powered electronics feature power-saving techniques to reduce power
consumption. Circuits that are not performing tasks are temporarily turned off lowering the
overall power consumption. The LDO voltage regulator, therefore, must respond quickly to
system demands and power up connected circuits within a few system clock cycles, typically 1
to 2 µs.

1. Cell Phones

A typical cell phone power management IC is shown in Fig. 1. The purposed LDO
regulator topology would be used for the RF/Analog power supplies. These require ultra low
noise and a linear output. The LDO regulators are usually placed after switching regulators to
improve their efficiency. The RF/analog blocks require LDO regulators with output currents up
to 50 mA. They also require turn-on settling times around 2 µs.

Fig. 1. Cell phone power management application.

Most cell phones use a 1 cell Li-ion battery supply. The maximum output voltage for a Li-ion
battery is typically 4.2V at full charge. At the onset of battery dropout, the battery supplies
2.92V. Thus, the circuits must operate below roughly 3V. Fig. 2 shows the typical voltage
 3

headroom at full battery discharge. To improve power efficiency, most system blocks are
optimally design to operate with 2.8V power rails.

Fig. 2. Cell phone battery characteristics.

The proposed capacitor-less LDO was design to replace current RF/analog LDO regulators that
require a large external output capacitor. These blocks operate at 2.8V and consume
approximately 32 mA of current. Dropout voltage is a defining characteristic of an LDO
regulator and defines the minimum voltage drop across the control element, usually a large
common-source output transistor or pass transistor. The dropout voltage of the regulator can not
exceed 200 mV to operate at the full battery discharge condition. The typical RF standby current
is 50 µA and the RF/analog needs 65dB of power-supply-rejection-ratio (PSRR) at 217Hz.

2. High-Efficiency Linear Regulation

Linear regulators suffer from poor efficiency. The efficiency is inversely proportional to
the voltage drop across the control element. Typically, linear regulators are cascaded after
switching regulators. Switching regulators have the ability to buck or boost the input voltage to
any desired output voltage with near 100% efficiency. Therefore, the voltage drop across the
control element can be reduced which in turn increases the power efficiency of the linear
regulator. Fig. 3 shows a linear regulator cascaded after a switching regulator.
 4

Fig. 3. High efficiency linear regulation.

Without the switching regulator, the voltage drop across the linear regulator (VIN – VOUT) would
drastically increase. The switching regulator is designed to minimize the voltage drop across the
linear regulator during loading conditions. Charge pumps can also be used to reduce the size and
cost of the switching regulator.

B. Conventional Linear and LDO Regulator Architectures

Linear voltage regulators come in two different topologies: conventional linear

regulators and LDO voltage regulators [3]. The only topological difference arises from the
orientation of the pass element. The conventional linear voltage regulator uses a source follower
in either a single transistor realization or a Darlington BJT configuration. The LDO regulator on
the other hand uses a single transistor in a common-source configuration operating in saturation.
The two configurations are shown in Fig. 4.

Fig. 4. Linear voltage regulator topologies.

1. 两个线性稳压器都使用相同的反馈机制工作。输出电压通过反馈电阻R1和R2进行感应。然后，误差放大器将缩
放后的输出电压与参考电压进行比较。误差信号被馈送到通过晶体管，形成负反馈路径。
2. 晶体管的方向在线性稳压器的运行和稳定中起着重要作用。传统的线性稳压器需要超过输入电压的栅极驱动
5
电压，这使得它在低电压应用中变得很麻烦。传统的线性稳压器正被用于一些低压应用，但必须使用电荷泵栅极
驱动。LDO电压调节器通过在共源配置中操作通过晶体管来克服必要的电压余量。通过晶体管的VDS饱和电压限
制了稳压器的工作。输出电压或VDSAT是最大输出电流和通过晶体管尺寸的一个函数。
Both linear regulators operate using the same feedback mechanism. The output voltage is sensed
through feedback resistors R1 and R2. An error amplifier then compares the scaled output
voltage to a reference voltage. The error signal is fed to the pass transistor and forms the
negative feedback path.
Transistor orientation plays a major role in the operation and the stabilization of the
linear voltage regulator. The conventional linear regulator requires gate drive voltages in excess
of the input voltage making it cumbersome for low voltage applications. Conventional linear
regulators are being used in some low-voltage applications but necessitate the use of charge
pump gate drives. LDO voltage regulators overcome the necessary voltage headroom by
operating the pass transistor in a common-source configuration. The VDS saturation voltage of
the pass transistor limits the regulator operation. The drop-out voltage or VDSAT is a function of
the maximum output current and the size of the pass transistor.
As mentioned earlier, the transistor orientation affects the stability of the regulator.
Typical small signal AC responses for both architectures are shown in Fig. 5. The conventional
linear regulator is inherently stable due to the low output impedance of the source follower. The
first pole, P1, acting as the dominant pole, is generated from the error amplifier output
impedance. The output pole, P2, moves with the load impedance but resides at much higher
frequency.
3. 如前所述，晶体管方向会影响稳压器的稳定性。图5显示了两种架构的典型小信号交流响应。由于源极跟随
器的输出阻抗较低，传统的线性调节器具有内在的稳定性。第一极，P1，作为主导极，是由误差放大器的输出
阻抗产生的。输出极，P2，随着负载阻抗移动，但停留在更高的频率。

Fig. 5. AC pole locations without compensation.

无补偿的交流极点位置。
1. LDO电压调节器可以在低电压应用中运行而不需要电荷泵，但它们本身是不稳定的。大的输出电容和高的输出
阻抗产生了主导极，P1。然而，这个主导极位于误差放大器输出极P2的附近。因此，LDO稳压器的稳定性不能得
到保证，很可能是不稳定的。LDO稳压器必须进行内部或外部补偿以保证稳定性。典型的LDO调节器使用输出电
6
容的静电电阻（ESR）来达到稳定。ESR创造了一个零点，当放在P2附近时，可以增加必要的相位以保持稳定性
。图6显示了电容器ESR的使用情况。

LDO voltage regulators can operate in low voltage applications without the need of charge
pumps, but they are inherently unstable. The large output capacitor and high output impedance
create the dominant pole, P1. This dominant pole, however, is located in close proximity to the
error amplifier output pole, P2. Thus, the LDO regulator’s stability can not be guaranteed and
will most likely be unstable. LDO regulators must be internally or externally compensated for
guaranteed stability. Typical LDO regulators use the electro-static resistance (ESR) of the
output capacitor to reach stability. The ESR creates a zero, that when placed in the vicinity of
P2, can add phase necessary to maintain stability. Fig. 6 shows the use of capacitor ESR.

Fig. 6. Conventional LDO regulator compensation.

The ESR also creates a pole, P3. The regulator stability depends heavily on the value of ESR.
As ESR is decreased, the location of Z1 moves to the right and consequently has no effect on
phase margin. On the other extreme, when ESR is increased significantly, the associated pole,
P3, moves below the gain-bandwidth, and the LDO regulator becomes unstable. A given LDO
regulator must be given a range of stable capacitor ESR, otherwise the LDO regulator will be
unstable.
Several recent publications have sought to eliminate the dependence on ESR. They
exploit the use of internal compensation, either by creating an internal zero or adaptively
modulating the location of the dominate pole. The presented research seeks to push one step
further by eliminating the large external output capacitor altogether. The research begins with
2. ESR也产生了一个极点，P3。稳压器的稳定性在很大程度上取决于ESR的值。随着ESR的降低，Z1的位置向右
移动，因此对相位差没有影响。在另一个极端，当ESR显著增加时，相关的极点P3移动到增益带宽以下，LDO稳
压器变得不稳定。一个给定的LDO调节器必须给定一个稳定的电容器ESR范围，否则LDO调节器将是不稳定的。

3. 最近的一些出版物试图消除对ESR的依赖。他们利用内部补偿，通过创建一个内部零点或自适应调节主导极的
位置。所提交的研究试图通过完全消除大型外部输出电容而更进一步。该研究从线性调节器的基本属性开始。这为
实现无电容的LDO电压调节器奠定了基础和方向。
 7

the basic fundamental properties of linear regulators. This forms the foundation and direction to
realize capacitor-less LDO voltage regulators. 无论电源电压或负载电流如何变化，LDO电压调节器
和所有其他电压调节器最好具有恒定的输出电压。电
LDO稳压器的特性 压调节器的规格一般分为三类：静态或稳态规格、动
C. LDO Regulator Characterization 态规格和高频规格[4]。所有提出的公式只考虑CMOS
LDO电压调节器，但同样的基本原则与大多数其他线
性电压调节器有关。
LDO voltage regulators and all other voltage regulators ideally have constant output
voltage regardless of supply voltage or load current variations. Voltage regulator specifications
generally fall into three categories: static-state or steady-state specifications, dynamic-state
specifications, and high-frequency specifications [4]. All the equations presented consider only
CMOS LDO voltage regulators, but the same basic principles relate to most other linear voltage
regulators. 静态参数包括线路调节、负载调节和温度
1. 静态规格 系数影响。线路和负载调节规格通常是为
给定的LDO调节器定义的，并衡量在给定
1. Static-state Specifications 线路和负载稳态值下调节稳态输出电压的
能力。温度系数定义了电压基准和误差放
大器偏移电压的综合性能。
The static-state parameters include the line regulation, the load regulation, and the
temperature coefficient effects. The line and load regulation specifications are usually defined
for a given LDO regulator and measure the ability to regulate the steady-state output voltage for
given line and load steady-state values. The temperature coefficient defines the combined
performance of the voltage reference and the error amplifier offset voltage.
Line Regulation defines the ratio of output voltage deviation to a given change in the
input voltage. The quantity reflects the deviation after the regulator has reached steady-state. A
general line regulation equation is given in equation 1.
线路调节定义了输出电压偏差与输入电压特定变化的比率。该数量反映了调节器达到稳定状态后
的偏差。公式1中给出了一个一般的线路调节方程。

∆VOUT g mp rop 1 ⎛ ∆V REF ⎞

≈ + ⎜⎜ ⎟⎟ (1)
∆V IN Aβ β ⎝ ∆V IN ⎠

Line regulation depends on the pass transistor transconductance, gmp, the LDO output resistance,
rop, the LDO loop gain, Aβ, and the feedback gain, β. Fig. 7 below illustrates the LDO
parameters.
线路调节取决于通过晶体管的跨导，gmp，LDO输出电阻，rop，LDO环路增益，Aβ，以及反馈
增益，β，下面的图7说明了LDO参数。
 8

Fig. 7. LDO regulator parameters.

对于输入电压的给定直流变化，较小的输出电压偏差对应于更好的电压调节器。为了增加线路调
节，LDO稳压器必须有一个足够大的环路增益。这些数量在LDO稳压器的设计讨论中变得清晰。
Smaller output voltage deviation for a given dc change in input voltage corresponds to a better
voltage regulator. To increase the line regulation, the LDO regulator must have a sufficiently
large loop gain. These quantities become clear in the LDO regulator design discussion.
Load regulation is a measure of output voltage deviation during no-load and full-load
current conditions. The load regulation is related to the loop gain, Aβ, and the pass transistor
output impedance, rop. This relation is given in equation 2.
负载调节是对空载和满载电流条件下输出电压偏差的测量。负载调节与环路增益Aβ和通过晶体管输
出阻抗rop有关。这个关系在公式2中给出。

∆VO rop
LRload = = (2)
∆I O 1 + Aβ
负载调节随着环路增益的增加和输出电阻的减少而改善。负载调节只适用于LDO调节器的稳态条件
，不包括负载瞬态效应。

The load regulation improves as the loop-gain increases and the output resistance decreases. The
load regulation only applies to the LDO regulator steady-state conditions and does not include
load transient effects.
The temperature coefficient defines the output voltage variation due to temperature drift
of the reference and the input offset voltage of the error amplifier. The temperature coefficient is
given in equation 3.
温度系数定义了由于基准的温度漂移和误差放大器的输入偏移电压引起的输出电压变化。温度系数在
公式3中给出。
 9

[∆VTC REF + ∆VTC VOS ]⋅ VOUT

1 ∂VOUT 1 ∆VTC V REF
TC = ⋅ ≈ ⋅ = (3)
VOUT ∂Temp VOUT ∆Temp VOUT ⋅ ∆Temp

随着误差放大器偏移电压的减少和参考电压温度依赖性的最小化，输出电压的精度也会提高。

The output voltage accuracy improves as the error amplifier offset voltage is reduced and the
reference voltage temperature dependence is minimized.
The LDO regulator’s dropout voltage determines the maximum allowable current and
the minimum supply voltage. These specifications, dropout voltage, maximum load current, and
minimum supply voltage, all depend on the pass transistor parameters. A particular LDO design
typically specifies the maximum load current and the minimum supply voltage it can tolerate
while maintaining pass transistor saturation. Equation 4 relates the LDO dropout voltage to
device parameters were ILOAD is the maximum sustainable output current.
LDO稳压器的压降电压决定了最大允许电流和最低电源电压。这些规格，压差电压、最大负载电流和最低电源电压
，都取决于通电晶体的参数。一个特定的LDO设计通常规定了最大负载电流和它能容忍的最低电源电压，同时保持
通电晶体的饱和。公式4将LDO压降与器件参数联系起来，ILOAD是最大可持续输出电流。
Vdropout = I LOAD ⋅ RON = V DSAT , PMOS (4)

通过晶体管的尺寸设计是为了在最大负载电流ILOAD时获得所需的VDSAT。
The pass transistor dimensions are designed to obtain the desired VDSAT at the maximum load
current, ILOAD.

2. 动态状态规格
2. Dynamic-state Specifications

The LDO regulator dynamic-state specifications specify the LDO regulator’s ability to
regulate the output voltage during load and line transient conditions. The LDO regulator must
respond quickly to transients to reduce variations in output voltage. Dynamic-state
specifications, unlike steady-state specifications, depend on the large signal LDO regulator
capabilities. The most significant capability is the charging and discharging of parasitic
capacitance and the parasitic capacitor feed-through.
Load transients define the LDO regulator’s ability to regulate the output voltage during
fast load transients. The largest variations in output voltage occur when the load-current steps
from zero to the maximum specified value. The ability of the LDO to regulate the output voltage
2.1 LDO稳压器的动态状态规格规定了LDO稳压器在负载和线路期间调节输出电压的能力。
在负载和线路瞬态条件下调节输出电压的能力。LDO稳压器必须对瞬态作出快速反应，以减少输出电压的变化。动
态状态规格与稳态规格不同，取决于大信号LDO稳压器的能力。最重要的能力是寄生电容的充电和放电以及寄生电
容的馈通。
2.2 负载瞬态定义了LDO稳压器在快速负载瞬态中调节输出电压的能力。当负载电流从零步进到最大规定值时，输
出电压的变化最大。LDO在大电流瞬变期间调节输出电压的能力，取决于闭环带宽、输出电容和负载电流。输出电
压变化的模型见公式5。
 10

during a large current transient depends on the closed-loop bandwidth, the output capacitance,
and the load-current. The output voltage variation is modeled in equation 5.

I max ⋅ ∆t
∆Vout = (5)
C out
Imax是规定的最大输出电流，Δt是LDO响应时间，Cout是LDO输出电容。t大约是LDO闭环带宽的倒数。大的输出
电容和大的闭环带宽可以改善负载调节。传统的LDO稳压器本来就有大的输出电容，因此与无电容的LDO稳压器相
比，有更好的负载调节。
Imax is the maximum specified output current, ∆t is the LDO response time, and Cout is
the LDO output capacitance. ∆t is approximately the reciprocal of the LDO closed-loop
bandwidth. A large output capacitor and large closed-loop bandwidth improve the load
regulation. Conventional LDO regulators inherently have large output capacitors and therefore
寄生电容也会导 will have better load regulation verses capacitor-less LDO regulators.
致回转效应，降
低LDO稳压器的 Parasitic capacitors also cause slewing effects that degrade LDO regulator’s load
负载瞬态响应。 transient response. The gate capacitance of the pass transistor can be significant and places
通路晶体管的栅
极电容可能很大 strain on the error amplifier. If the slew rate at the gate of the pass transistor is much slower than
，并对误差放大 the gain-bandwidth product, significant transient voltage spikes appear at the output voltage
器造成压力。如
果通过晶体管栅 node during fast load transients. This effect becomes more pronounced with capacitor-less LDO
极的回转速率比 regulators.
增益带宽乘积慢
得多，那么在快 Ripple-rejection-ratio specifies the ability for the regulator to rejected input signals from
速负载瞬态期间
，输出电压节点 the output node. This parameter measures the small-signal gain from the input voltage to the
会出现明显的瞬 output voltage. The ripple rejection ratio is given in equation 6.
态电压尖峰。这
种影响在无电容 纹波抑制比规定了稳压器从输出节点拒绝输入信号的能力。该参数衡量从输入电压到输出电压
的LDO稳压器中 的小信号增益。纹波抑制比在公式6中给出。
变得更加明显。
output ripple voltage
ripple rejection = 20 log10 (6)
input ripple

The ripple-rejection-ratio is typically determined for lower frequencies within the gain-
bandwidth product. Large input voltage transient spikes can cause larger output voltage
variations than predicted by the ripple-rejection-ratio. The deviation is due to large signal
effects, mainly capacitor slewing.

纹波抑制比通常是针对增益带宽产品中的较低频率确定的。大的输入电压瞬时尖峰会导致比纹波抑制
比所预测的更大的输出电压变化。这种偏差是由于大信号的影响，主要是电容的回转。
3.1 电源抑制比(PSRR)和稳压器输出噪声可归类为高频规格。这两个参数都是小信号参数，与频率有关。大多数
LDO调节器规定了某些频率下的PSRR以及大于增益带宽乘积的特定频率下的点噪声[5]。
11
3.2 PSRR定义了LDO调节器在输入线上拒绝高频噪声的能力。PSRR是通过晶体管寄生电容的一个函数，与环路
增益的倒数成正比。误差放大器在改善PSRR方面起着主要作用[5]。单个误差放大器的PSRR和单个通过晶体管的
PSRR希望在输出电压节点相加为零。文中稍后将研究使PSRR最小化的设计技术。

3. 高频规格
3. High-frequency Specifications

Power-supply-rejection-ratio (PSRR) and regulator output noise can be categorized as

high-frequency specifications. Both parameters are small signal parameters and are plotted
verses frequency. Most LDO regulators specify PSRR at certain frequencies as well as spot
noise at a particular frequency greater than the gain-bandwidth product [5].
PSRR defines the LDO regulator’s ability to reject high-frequency noise on the input
line. PSRR is a function of pass transistor parasitic capacitances and is proportional to the
reciprocal of the loop gain. The error amplifier plays a major role in improving PSRR [5]. The
combined individual error amplifier PSRR and the individual pass transistor PSRR is desired to
sum to zero at the output voltage node. The design techniques to minimize PSRR are studied
later on in the text.
Output noise is primarily defined by the input stage transconductance. The
subsequent stages do not add significant noise to the output. Maximizing the input
transistors’ size lowers the output noise. The optimal noise figure is dependent on each
particular design and a general analysis lacks sufficient information.
3.3 输出噪声主要由输入级的跨导决定。后续阶段不会给输出增加明显的噪声。最大化输入晶体管的尺寸可以降低
输出噪声。最佳噪声系数取决于每个特定的设计，一般的分析缺乏足够的信息。
4. LDO Regulator Efficiency
4. LDO稳压器的效率
The LDO regulator efficiency is determined by three parameters: ground current, load
current, and pass transistor voltage drop. The total no-load quiescent current consumption for
the entire LDO regulator circuitry is defined as the ground current. Equation 7 relates the LDO
regulator power efficiency.
LDO稳压器的效率由三个参数决定：接地电流、负载电流和通过晶体管压降。整个LDO稳压器电路的总空载静态
电流消耗被定义为接地电流。公式7与LDO调节器的功率效率有关。
Vout ⋅ I LOAD
Eff = (7)
Vin ⋅ ( I GND + I LOAD )

There are two cases for power efficiency, one for small load currents and one for large load
currents. The relation reduces to equation 8 for small load currents.
功率效率有两种情况，一种是小负载电流，一种是大负载电流。对于小负载电流，该关系简化为方程8。
 12

I LOAD
Eff ≈ (8)
I GND + I LOAD

因此，在非常低的负载电流下，接地电流对LDO稳压器效率的影响更大。通过减少静态接地电流，可以大大增加
低电流应用的电池寿命。在另一个极端，对于非常大的负载电流，电源效率完全取决于通过晶体管的压降，如公
式9所示。
Thus, ground current affects the LDO regulator efficiency much more at very low load currents.
The longevity of battery life for low current applications can be significantly increased by
reducing the quiescent ground current. At the other extreme, for very large load currents, the
power efficiency is solely dependent on the pass transistor voltage drop, shown in equation 9.

Vout
Eff ≈ (9)
Vin
当输出电压接近输入电压时，线性稳压器的效率接近100%。然而，这种情况需要一个无限大的通过晶体管，但会
导致一个无限的栅极电容。显然，在效率和LDO稳压器的速度之间存在着权衡。
The efficiency of the linear regulator approaches 100% as the output voltage approaches the
input voltage. This scenario, however, requires an infinitely large pass transistor but would
result in an infinite gate capacitance. Clearly, there is a trade-off between efficiency and the
speed of the LDO regulator.

5. 规格权衡
5. Specification Trade-offs
所有的LDO调节器规格都是相互关联的，并导致了重要的权衡。在所有其他规格中，最大的是效率、稳定性和瞬态
响应。优化，特别是在严格的约束条件下，变得非常复杂。在设计LDO调节器时，权衡的结果将更加明显。
All the LDO regulator specifications are interrelated and lead to important tradeoffs. The largest
among all other specifications is efficiency, stability, and transient response. The optimization,
especially with tight constraints, becomes very convoluted. The tradeoffs will be more apparent
when designing the LDO regulator.
D. 无电容的LDO电压调节器
D. Capacitor-Less LDO Voltage Regulators

The basic linear voltage regulator architectures and their properties have been discussed.
Research continues on conventional LDO regulators but recent research is focusing on capacitor-
less LDO voltage regulators [2]-[10]. As mentioned before, removing the output capacitor on
LDO regulators allows SoC designs to fully incorporate power management systems with
已经讨论了基本的线性电压调节器结构和它们的特性。对传统LDO稳压器的研究仍在继续，但最近的研究集中在无
电容LDO稳压器上[2]-[10]。如前所述，去除LDO稳压器上的输出电容后，SoC设计可以完全纳入具有多个LDO电
压调节器的电源管理系统。去除外部电容还可以减少电路板的面积和系统成本。基本的无电容LDO电压调节器如图
8所示。
 13

multiple LDO voltage regulators. Removing the external capacitor also reduces board real estate
and system costs. The basic capacitor-less LDO voltage regulator is shown in Fig. 8.

Fig. 8. Capacitor-less LDO voltage regulator.

无电容LDO稳压器仍然有一个内部输出电容，但它比传统LDO稳压器使用的电容小得多。目前的工业无电容LDO稳
压器将所需的外部电容减少了10倍左右，但它们仍然使用0.1微法拉的外部电容。本研究的目的是完全去除外部电容
，用一个小的内部电容代替。内部电容被尽可能地扩大，但受到芯片尺寸和当前CMOS技术的限制。典型的电容值
落在几百皮法拉的范围内。
The capacitor-less LDO regulator still has an internal output capacitor but it is much smaller than
those used by conventional LDO voltage regulators. Current industrial capacitor-free LDO
regulators decrease the required external capacitor by a factor of 10 or so, but they still use a 0.1
microfarad external capacitor. The presented research purposes the complete removal of the
external capacitor and its replacement with a small internal capacitor. The internal capacitor is
maximized as much as possible but is constrained by chip size dimensions and current CMOS
technology. Typical capacitor values fall in the range of a few hundred picofarads.

1. 最初的无电容LDO稳压器的极点位置
1. Initial Capacitor-less LDO Regulators Pole Locations

Most of the conventional LDO specifications are greatly affected when the external
capacitor is reduced by several orders of magnitude. The most significant side effect is stability
degradation. The uncompensated capacitor-less LDO has two major poles, the error amplifier
output pole, P1, and the load dependent output pole, P2. Fig. 9 shows the relative pole location.
当外部电容减少几个数量级时，大多数传统的LDO规格受到很大影响。最重要的副作用是稳定性下降。未补偿的
无电容LDO有两个主要极点，即误差放大器输出极P1和与负载有关的输出极P2。图9显示了相对的极点位置。
 14

Fig. 9. Pole locations for uncompensated capacitor-less LDO voltage regulator.

独立的误差放大器有一个位于相对高频率的极点。等效通过晶体管的输入电容为误差放大器的输出阻抗增加了大
量电容。P1的位置由公式10给出。
The standalone error amplifier has a pole located at relatively high frequency. The equivalent
pass transistor input capacitance adds significant capacitance to the error amplifier output
impedance. The location of P1 is given by equation 10.

1
ω P1 = (10)
R1 ⋅ (C1 + CGS + APass C GD )

The pass transistor is very large in order to reduce VDSAT. Therefore, CGS and CGD are extremely
large, in the tens of picrofarads. CGD also forms a Miller capacitor which increases the effective
input capacitance by the gain of the pass transistor. The pass transistor has a typical gain of
20dB or 10V/V at low load currents. The Miller capacitor can increase the effective pass
transistor input capacitor to a few hundred picofarads. Thus, the pole, P1, resides at low
frequencies of typically a few kilohertz. The gain of the pass transistor changes with varying
load current. P1 is therefore load dependent but less so than P2. The first tradeoff is between
efficiency and stability. The large output current efficiency is inversely proportional to the pass
transistor’s VDSAT. Smaller VDSAT increases the effective input gate capacitance and
consequently decreases the error amplifier pole frequency, increasing the burden on the error
amplifier.

为了降低VDSAT，通电晶体非常大。因此，CGS和CGD都非常大，有几十微法。CGD也形成了一个米勒电容，
通过通过晶体管的增益来增加有效的输入电容。在低负载电流下，通过晶体管的典型增益为20dB或10V/V。米勒
电容可以将通过晶体管的有效输入电容增加到几百皮法拉。因此，极点P1驻留在典型的几千赫兹的低频率上。通
过晶体管的增益随着负载电流的变化而变化。因此，P1与负载有关，但比P2要小。第一个权衡是在效率和稳定性
之间。大输出电流的效率与通过晶体管的VDSAT成反比。较小的VDSAT增加了有效的输入门电容，从而降低了
误差放大器的极点频率，增加了误差放大器的负担。
 15
第二极，P2，位于LDO的输出端。输出电阻随着负载电流的增加而减少。P2与负载电流成正比，并且与负载有关
。P2的位置由公式11给出。
The second pole, P2, is located at the LDO’s output. The output resistance decreases for
increasing load current. P2 is directly proportional to the load current and is load dependent.
The location of P2 is given by equation 11.

1
ω P2 = (11)
( ROUT // R LOAD ) ⋅ C INT
高负载电流将输出极P2推向更高的频率，无电容的LDO稳压器通常是稳定的。在低电流时，有效负载电阻明显增加
。P2被推到较低的频率，与误差放大器的极点接近。由于相位余量减少，稳定性不能得到保证。无补偿的无电容
LDO稳压器在低电流下不稳定，特别是在空载条件下。
High load current pushes the output pole, P2, to higher frequency, and the capacitor-less LDO
regulator is usually stable. At low currents, the effective load resistance increases significantly.
P2 is pushed to lower frequency in close proximity to the error amplifier pole. Stability cannot
be guaranteed due to the decreased phase margin. The uncompensated capacitor-less LDO
regulator is not stable at low currents, especially at the no-load condition.
2. 瞬态响应属性
2. Transient Response Attributes

The large external capacitor is used on conventional LDO regulators and linear regulators in
general to improve the transient load regulation [2],[6] and [8]. The output capacitor stores
potential energy equivalent to the output voltage. The ideal capacitor can deliver instantaneous
current and has infinite bandwidth, assuming its source resistance in zero. The transfer of charge
from the capacitor to the load corresponds to a drop in output voltage. Equation 12 gives a
relationship for this voltage difference.
在传统的LDO调节器和一般的线性调节器上使用大的外部电容，以改善瞬态负载调节[2],[6]和[8]。输出电容器储存
相当于输出电压的势能。假设其源电阻为零，理想的电容器可以提供瞬时电流，并具有无限的带宽。电荷从电容器
转移到负载，对应于输出电压的下降。公式12给出了这个电压差的关系。
∆Q
∆VOUT = (12)
C OUT

Thus, the change in output voltage is inversely proportional to the output capacitance. The
output voltage ripple for a given load transient is reduced by increasing the output capacitance.
This relationship becomes much more apparent when the load transients are much faster than the
因此，输出电压的变化与输出电容成反比。对于一个给定的负载瞬态，输出电压纹波会通过增加输出电容而减少。
当负载瞬态比增益-带宽乘积快得多时，这种关系就变得更加明显，而这通常是一种情况。图10说明了传统LDO电
压调节器的这种情况。
 16

gain-bandwidth product, which is usually the case. Fig. 10 illustrates this situation in a
conventional LDO voltage regulator.

Fig. 10. Equivalent circuit for fast load transients.

增益带宽比负载瞬态慢得多，而且在整个负载瞬态过程中，可以假定通过晶体管栅极电压是恒定的。图10右边的电
路图用一个恒定的电流源代替了通电晶体。那么输出电压只由公式12和公式5决定。无电容的LDO稳压器没有大的
外部电容的优点。相反，图10中的恒定电流源必须用高速自适应电流源代替。
The gain-bandwidth is much slower than the load transient and the pass transistor gate voltage
can be assumed constant throughout the load transient. The circuit diagram to the right of Fig.
10 has substituted a constant current source for the pass transistor. Then the output voltage is
only determined by equation 12 and equation 5. The capacitor-less LDO regulator does not have
the advantages of a large external capacitor. Instead, the constant current source in Fig. 10 must
be replaced with high speed adaptive current source.
The pass transistor has a very large transconductance, but the large effective input
capacitance limits its transient speed. The effective input gate capacitance is driven by the error
amplifier. In order for the error amplifier to drive large capacitive loads, the quiescent bias
current must be increased. Slewing occurs at the pass transistor gate given by equation 13.
通路晶体管具有非常大的跨导，但大的有效输入电容限制了其瞬态速度。有效输入门电容是由误差放大器驱动的。
为了使误差放大器能够驱动大电容负载，必须增加静态偏置电流。回旋发生在通过晶体管门，由公式13给出。
I bias ,error
SR = (13)
C GS ,eff

The error amplifier output stage bias current only effects the slew rate in equation 13, and the
CGS,eff is the total effective input gate capacitance of the pass transistor. Conventional LDO

误差放大器输出级偏置电流只影响方程13中的回转率，CGS,eff是通过晶体管的总有效输入栅极电容。传统的LDO
稳压器通常使用带有AB类输出级的误差放大器。这降低了输出阻抗，增加了误差放大器的驱动能力。基本问题仍然
存在；必须增加功率以驱动更大的通过晶体管。这就形成了第二个固有的权衡，功率效率与瞬态响应成正比。第三
种权衡存在于大电流功率效率和小电流效率之间。大电流效率通过降低VDSAT得到改善。然而，有效的通过晶体管
输入栅极电容增加了；接地电流或偏置电流必须增加，以获得可接受的负载瞬态响应。这方面的权衡见图11。
 17

regulators typically use an error amplifier with a class AB output stage. This lowers the output
impedance and increases the drive capability of the error amplifier. The fundamental problem
still exists; the power must be increased to drive larger pass transistors. This forms the second
inherent tradeoff, the power efficiency is directly proportional to the transient response. A third
tradeoff exists between large-current power efficiency and low-current efficiency. The large
current efficiency is improved by reducing VDSAT. The effective pass transistor input gate
capacitance is increased, however; the ground current or bias current must be increased for
acceptable load transient response. The tradeoff is shown in Fig. 11.

Low Current Tradeoff High Current

Efficiency Efficiency

Fig. 11. Power efficiency tradeoff.

无电容的LDO稳压器是为特定的应用而设计的，其额定工作点是已知的。显然，通过晶体管构成了LDO稳压器的主
干，因此定义了大部分的设计权衡。

The capacitor-less LDO regulator is design for a specific application where the nominal
operating point is known. Clearly, the pass transistor forms the backbone of the LDO regulator
and consequently defines most of the design tradeoffs.
3. 以前的学术著作
3. Previous Academic Works

Only a few works have been published in the IEEE regarding capacitor-less LDO
regulators [4], [11], and [12]. To date, there have been no works published in IEEE journals that
demonstrate a completely stable common-source LDO regulator with no external capacitor.
They all have problems either tracking the output pole variation or have problems with high
impedance loads. The first work used a DFC analog block to create a fix internal dominant pole
[4]. The circuit architecture is shown in Fig. 12.

关于无电容的LDO稳压器，只有少数作品发表在IEEE上[4]、[11]和[12]。到目前为止，还没有任何发表在IEEE期
刊上的作品展示了一个完全稳定的无外部电容的共源LDO稳压器。他们都有问题，要么是跟踪输出极的变化，要
么是对高阻抗负载有问题。第一项工作使用DFC模拟块来创建一个固定的内部主导极[4]。该电路结构如图12所示
。
 18

Fig. 12. Capacitor-free LDO voltage regulator.

一个零点和一个极点是由补偿电容CF1创建的。零点是用来消除输出极点的。寄生极，Pf，必须被放置在单增益频
率之后。该补偿技术如图13所示。

A zero and a pole are created with compensation capacitor CF1. The zero is used to cancel the
output pole. The parasitic pole, Pf, must be placed past the unity-gain frequency. The
compensation technique is shown in Fig. 13.

Fig. 13. LDO compensation with CF1.

Two problems arise with this architecture. First, the pole created with CF1 is limited by the
selection of feedback resistors and will most likely be relatively close to Zf. This greatly reduces
the effect of the cancellation zero. Second, the zero is fixed and does not move with the load
dependent output pole. This pole moves well over a decade, and the stability at no-load
这种结构出现了两个问题。首先，用CF1产生的极点受到反馈电阻选择的限制，很可能相对接近Zf。这大大降低
了取消零点的效果。第二，零点是固定的，不随负载相关的输出极点移动。这个极点移动了十几年，空载条件下
的稳定性很可能是不稳定的。使用这一概念的无电容LDO调节器对于小于5mA的负载是不稳定的。
 19

condition is most likely unstable. The capacitor-free LDO regulator using this concept was
unstable for loads smaller than 5mA.
The second work [10] moves in the right direction using pole-zero tracking frequency
compensation. The structure is shown in Fig. 14.
第二项工作[10]采用极点零点跟踪频率补偿的方式向正确的方向发展。其结构如图14所示。

Fig. 14. LDO regulator with pole/zero tracking.

他们使用一个由线性电阻创造的可变零点。这种结构在整个输出电流范围内也不完全稳定。由于电阻对负载电流的
功能很弱，所以它没有足够的可调谐范围。
They use a variable zero created by a linear resistor. This structure is also not completely stable
over the entire output current range. The resistance does not have enough tunable range due to
its weak function of the load current.
4. 无电容的LDO设计方向
4. Capacitor-less LDO Design Direction

A new structure was needed to compensate the capacitor-less LDO while maintaining
good load transient response and stability at low load currents. The transient response is
dependent on the speed of the pass transistor and not the output capacitor. A fast transient path
from the LDO output to the gate of the pass transistor was required since the system gain-
bandwidth was relatively low in frequency. The capacitor-less LDO stability at low load
currents was the second major problem. The initial idea sought to apply adaptive techniques to
compensate the output pole and possibly the error amplifier output pole. The basic concept is
shown in Fig. 15.
需要一种新的结构来补偿无电容的LDO，同时在低负载电流下保持良好的负载瞬态响应和稳定性。瞬态响应取决于
通过晶体管的速度，而不是输出电容。由于系统增益带宽的频率相对较低，所以需要一个从LDO输出到通电晶体栅
极的快速瞬态路径。无电容的LDO在低负载电流下的稳定性是第二个主要问题。最初的想法是寻求应用自适应技术
来补偿输出极点和可能的误差放大器输出极点。其基本概念如图15所示。
 20

Fig. 15. Basic capacitor-less LDO concept.

The concept in Fig. 15 uses a fast path to improve the transient response. A compensation
network is needed to stabilize the new fast transient system. The main feedback loop determines
the capacitor-less LDO’s gain-bandwidth product and is the main mechanism that replenishes the
energy in the output capacitor, restoring the output voltage to the correct steady-state level. The
fast path is an internal negative feedback loop with very high bandwidth, much greater than the
overall gain-bandwidth product. The fast path senses any load current variation and mirrors and
amplifies the signal directly into the gate of the pass transistor.
The concept in Fig. 15 formed the basis of research and design for the final capacitor-
less LDO voltage regulator. A specific application was selected for the design, and the
capacitor-less LDO was designed to approach most of the conventional LDO specifications.
This leads to the formal design analysis discusses in Section II.
图15中的概念使用快速路径来改善瞬态响应。需要一个补偿网络来稳定新的快速瞬态系统。主反馈回路决定了无电
容LDO的增益带宽乘积，是补充输出电容能量的主要机制，将输出电压恢复到正确的稳态水平。快速路径是一个内
部负反馈回路，具有非常高的带宽，远远大于整体增益带宽积。快速路径感应到任何负载电流的变化，并将信号直
接反射和放大到通过晶体管的栅极。

图15中的概念构成了最终无电容LDO电压调节器的研究和设计基础。为设计选择了一个特定的应用，无电容LDO
的设计接近大多数传统LDO的规格。这导致了第二节中讨论的正式设计分析。
 21

II. 无电容LDO调节器分析
II. CAPACITOR-LESS LDO REGULATOR ANALYSIS

The capacitor-less LDO regulator design targets the cell phone and handheld device
market. Each of these designs uses a power management IC to improve the battery life longevity
and usually contain several LDO voltage regulators, shown in Fig. 1 in Section I. The proposed
capacitor-less LDO voltage regulator would most likely replace the analog/RF and audio power
supplies. Based on the current specification for these LDO regulator applications, the proposed
capacitor-less LDO specification was developed as shown in Table I.
无电容LDO稳压器的设计目标是手机和手持设备市场。这些设计中的每一个都使用电源管理IC来提高电池的寿命，
通常包含几个LDO电压调节器，如第一节中的图1所示。提议的无电容LDO电压调节器很可能会取代模拟/射频和音
频电源。根据这些LDO稳压器应用的现行规范，制定了拟议的无电容LDO规范，如表I所示。
TABLE I
CAPACITOR-LESS LDO SPECIFICATION

PARAMETER VALUE
Gain Bandwidth 1 ~ 2 MHz
Settling Time < 2 µs
Loop Gain ~ 100 dB
GND Current < 150 µA
Dropout Voltage 200 mV
Output Current 0 ~ 50 mA
PSRR < -40dB @ 100kHz
Output Noise < 20 µV
Line Regulation 0.01%
Load Regulation 0.02%
Technology TSMC 0.35µ CMOS
所选择的无电容LDO规格与目前传统的LDO稳压器相比，除了瞬态响应和高频响应外，都具有竞争力，说明输出电
容减少。这构成了LDO设计的基础，而器件的特性分析也很快进行了。

The chosen capacitor-less LDO specification is competitive with current conventional LDO
voltage regulators with the exception of the transient response and high frequency response,
accounting for the reduced output capacitance. This formed the basis for the LDO design, and
the device characterization soon followed.
The capacitor-less LDO design must incorporate two important criteria: stability and fast
transient response. There were two possible angles of attack. The first method starts by
stabilizing the LDO regulator and then optimizing the stability for fast transient response. The
second method first optimizes the fast transient response and then stabilizes the fast transient

无电容的LDO设计必须包含两个重要标准：稳定性和快速瞬态响应。有两种可能的攻击角度。第一种方法是先稳定
LDO稳压器，然后优化快速瞬态响应的稳定性。第二种方法首先优化快速瞬态响应，然后稳定快速瞬态的LDO调节
器。人们发现应用第二种方法更容易，并从增加一个快速瞬态路径开始。
在开发任何新的拓扑结构之前，必须首先对未补偿的无电容LDO调节器进行表征。这包括对极点、直流增益和固定
器件参数的完整表征。此外，还需要未补偿的瞬态响应来确定回转问题和相对电路速度。无电容的LDO稳压器对于
低于约5mA的直流输出电流是固有的不稳定的。然而，我们构建了一个测试电路来测量回旋效应。通过晶体管的亚
22
阈值饱和区域也在LDO操作中发挥了重要作用。这些影响都在下面的 "非补偿器件特性分析 "一节中进行了总结。

LDO regulator. It was found easier to apply the second method and start by adding a fast
transient path.
The uncompensated capacitor-less LDO regulator had to be characterized first before
any new topologies were developed. This included the complete characterization of poles, DC
gains, and fixed device parameters. Also, the uncompensated transient response was needed to
determine slewing issues and relative circuit speed. The capacitor-less LDO regulator was
inherently unstable for DC output currents lower than approximately 5mA. However, a test
circuit was constructed to measure the slewing effects. The pass transistor’s subthreshold
saturation region also played a major role in the LDO operation. These effects are all
summarized in the following section, Uncompensated Device Characterization.

A. 非补偿器件特性分析
A. Uncompensated Device Characterization
通过晶体管决定了最大输出电流和压差电压。这些参数在整个LDO运行过程中基本上是固定的。在构建新的拓扑结
构之前，就可以设计出通过晶体管。因此，LDO补偿和快速瞬态路径已经到位，以补偿大型通过晶体管的影响。
The pass transistor determines the maximum output current and the dropout voltage.
These parameters are essentially fixed throughout the LDO operation. The pass transistor could
be designed before a new topology was constructed. Thus, the LDO compensation and the fast
transient path are in place to compensate the effects of the large pass transistor.
The first section discusses the pass transistor design process. Following the design of
the pass transistor, the LDO is characterized for both AC response and transient response. The
results from the uncompensated device characterization were directly applied to the final
proposed capacitor-less LDO topology.
第一节讨论了通过晶体管的设计过程。在通过晶体管的设计之后，LDO的交流响应和瞬态响应都得到了表征。未补
偿的器件表征结果直接应用于最终提出的无电容LDO拓扑结构。
1. Pass Transistor Design
1. 通路晶体管设计
The dropout voltage of the capacitor-less LDO was selected to be 200mV for a maximum load
current of 50mA based on current LDO regulator requirements. In device parameters, the pass
transistor is designed to deliver a drain current of 50mA while maintaining a saturation voltage,
VDS ≥ VGS – VT, of 200 mV or less. The pass transistor stage is shown in Fig. 16.

根据当前LDO调节器的要求，无电容LDO的压降电压被选定为200mV，最大负载电流为50mA。在器件参数中，通
过晶体管被设计为提供50mA的漏极电流，同时保持200mV或以下的饱和电压，VDS≥VGS-VT。图16中显示了通
过晶体管的阶段。
 23

Fig. 16. Pass transistor design.

一阶近似法被用来寻找粗略的器件尺寸。这种关系显示在公式14中。
First order approximations were used to find the rough device dimensions. This relationship is
shown in equation 14.

2 I MAX
Vdropout = V DSAT = (14)
µ p C OX W / L
IMAX定义了最大的输出电流，迫使通过晶体管的尺寸，W/L，以达到理想的最小VDROPOUT。变量μp（空穴迁移
率）和COX（单位面积的栅极电容）是器件技术参数，在表II中给出。表二中的器件参数被用来设计通电晶体。方
程14被重新排列，以找到方程15中所示的通过晶体管器件尺寸比W/L。
IMAX defines the maximum output current, forcing the dimensions of the pass transistor, W/L, for
a desired minimum VDROPOUT. The variables µp, hole mobility, and COX, the gate capacitance
per unit area, are device technology parameters and are given in Table II. The device parameters
in Table II were used to design the pass transistor. Equation 14 was rearranged to find the pass
transistor device dimensional ratio, W/L, shown in equation 15.

⎡W ⎤ 2 I MAX
⎢L⎥ = 2
= 37.8 × 10 3 (15)
⎣ ⎦ PASS µC oxV DSsat
 24

TABLE II
TSMC 0.35 DATA: RUN T4CU

PARAMETER VALUE
VTP 0.58 V
VTN -0.74 V
µpCOX 180.2 µA/V2
µnCOX 66.00 µA/V2
方程15中发现的比率非常大。通道长度被最小化以减少栅极电容CGS。最小长度为400纳米，由台积电0.35微米
CMOS工艺设定。这迫使通过晶体管的宽度达到15,000µm或15mm。　BSIM3计算机模拟被用来验证和微调通过晶体
管的尺寸。表三显示了在50mA负载电流下产生200mV压差电压的计算和模拟的通过晶体管参数。
The ratio found in equation 15 was very large. The channel length was minimized to reduce the
gate capacitance CGS. The minimum length is 400nm, set by the TSMC 0.35µm CMOS process.
This forces the pass transistor width to 15,000µm or 15mm. BSIM3 computer simulations were
used to verify and fine tune the pass transistor dimensions. Table III shows the calculated and
simulated pass transistor parameters to yield a 200mV dropout voltage at 50mA load current.

TABLE III
PASS TRANSISTOR DIMENSIONS

CALCULATED SIMULATED
W = 15mm W = 16mm
L = 400nm L = 400nm
CGS = 19.1 pF CGS = 20.18 pF
CGD = 5.0 pF CGD = 3.84 pF

CADENCE simulations show that the actual dimensional ratio of the pass transistor must be at
least 40,000. Unfortunately, this means that for a device of minimum length, the required width
must increase to 16mm instead of the calculated 15mm width. Such a large device introduces
significant parasitic capacitances into the network, notably the gate-source capacitance CGS. As
mentioned previously in this report, large gate capacitance along with variable low-frequency
load impedance makes stabilizing a capacitor-less LDO difficult. The gate-source capacitance of
this PMOS pass-transistor measured 20pF. The Miller effect with CGD further increases the
effective gate capacitance. Equation 16 relates the total effective gate capacitance.

CADENCE的模拟结果表明，通过晶体管的实际尺寸比必须至少为40,000。不幸的是，这意味着对于最小长度的器
件，所需的宽度必须增加到16毫米，而不是计算的15毫米宽度。如此大的器件会在网络中引入大量的寄生电容，特
别是门-源电容CGS。正如本报告前面提到的，大的栅极电容与可变的低频负载阻抗一起，使得稳定无电容的LDO变
得困难。这个PMOS通电晶体的栅极-源极电容测量为20pF。带有CGD的米勒效应进一步增加了有效栅极电容。公
式16涉及到总的有效栅极电容。
 25

C GS ,eff ≅ CGS + (1 + A pass ) ⋅ CGD = C GS + (1 + Gm, pass RO , pass ) ⋅ C GD (16)

有效通过晶体管的栅极电容接近100pF。因此，米勒电容贡献了大部分的有效栅极电容，同时随着负载条件的变化
而变化。
The effective pass transistor gate capacitance approaches 100pF. Thus, the Miller capacitor
contributes most of the effective gate capacitance while varying with load conditions.
Pass transistor subthreshold operation is another major concern. For large variations in
the load current, the PMOS transistor will undergo a transition from operating in the saturation
region to operating in the subthreshold saturation region. The pass transistor exhibits an
exponential relationship while operating in subthreshold in contrast to the nominal square law
relationship. The relationship is shown in the equation 17.
通过晶体管的亚阈值操作是另一个主要问题。对于负载电流的巨大变化，PMOS晶体管将经历一个从工作在饱和区
到工作在亚阈值饱和区的过渡。通路晶体管在亚阈值工作时表现出一种指数关系，与标称的平方律关系相反。该关
系显示在公式17中。
⎡W ⎤
I D ≅ I DO ⎢ ⎥ e (qVGS nkT )
(17)
⎣L⎦
亚阈值操作产生的响应速度明显较慢。对于负载电流在短时间内下降到低电流水平的应用，这可能导致电压调节的
显著下降。负载调节的这种退化只能通过向LDO提供更多电流来抵消，从而提高电路的速度。这在亚阈值工作期间
尤其如此。
Subthreshold operation produces a significantly slower response. This may cause significant
degradation in the voltage regulation for applications where the load current drops to low current
levels in a short span of time. This degradation in load regulation can only be counteracted by
providing more current to the LDO, improving the speed of the circuit. This is especially true
during subthreshold operation.
The pass transistor constitutes the only fixed predetermined capacitor-less LDO
component. The other components, including the error amplifier, feedback gain, fast transient
path, and the compensation network, are molded around the fixed pass transistor. Next, the
newly designed pass transistor was simulated using a generic control loop.
通过晶体管构成了唯一固定的无电容LDO元件。其他元件，包括误差放大器、反馈增益、快速瞬态路径和补偿网络
，都是围绕固定的通电晶体成型的。接下来，新设计的通电晶体使用通用控制回路进行模拟。
2. Uncompensated AC Response
2. 未补偿的交流响应
The pole locations were determined over the entire desired operating range of 0 to 50mA, using
the generic control loop. The pass transistor transconductance and output impedance were
simulated in CADENCE over the output current operating range. The simulated pass transistor

使用通用控制回路，在0至50mA的整个预期工作范围内确定了极点位置。在输出电流工作范围内，在CADENCE中
模拟了通电晶体的跨导和输出阻抗。然后可以在MATLAB中使用模拟的通过晶体管数据，进行更稳健的交流模拟。
控制回路如图17所示。
 26

data could then be used in MATLAB for a more robust AC simulation. The control loop is
shown in Fig. 17.

Fig. 17. AC open-loop simulation circuit.

超导、gm1和输出阻抗、R1和C1构成误差放大器。反馈电阻，RF1和RF2，被设计成产生2.8V的输出电压。等式
18将参考电压VREF与输出电压联系起来，并假定环路增益为无限。
The transconductance, gm1, and the output impedance, R1 and C1, form the error amplifier. The
feedback resistors, RF1 and RF2, were designed to yield an output voltage of 2.8V. Equation 18
relates the reference voltage, VREF, to the output voltage assuming infinite loop gain.

⎛ R ⎞
VOUT = V REF ⋅ ⎜⎜1 + F 1 ⎟⎟ (18)
⎝ RF 2 ⎠
输出电压是由反馈电阻率和输入参考电压决定的。绝对电阻决定了通过晶体管的静态电流，IQ。标准BiCMOS带
隙参考输出在-40°C至80°C范围内为1.24V。因此，在整个无电容LDO稳压器设计中，使用了1.24V的输入参考电
压。
The output voltage is defined by the feedback resistor ratio and the input reference voltage. The
absolute resistance determines the pass transistor quiescent current, IQ. Standard BiCMOS
bandgap reference output is 1.24V in a range of -40°C to 80°C. Thus, the input reference
voltage of 1.24V was used throughout the capacitor-less LDO regulator design.
LOPEN形成了一个直流反馈路径，阻断了大部分的交流成分。这允许在图17所示的测试点进行开环交流响应测量。
通过LOPEN的直流反馈回路为LDO设定了通常在闭环操作中出现的直流工作点。COPEN将交流测试信号耦合到放
大器回路中，而不影响LDO的直流工作点。LOPEN和COPEN都非常大，分别为100H和100F。这使得交流测量可以
低至非常低的频率。 27

LOPEN forms a DC feedback path, blocking most of the AC components. This allows for
an open-loop AC response measurement at the test point shown in Fig. 17. The DC feedback
loop through LOPEN sets the DC operating points for the LDO that would normally occur during
closed-loop operation. COPEN couples the AC test signal to the amplifier loop without affecting
the LDO’s DC operating points. Both LOPEN and COPEN are very large, 100H and 100F
respectively. This allows the AC measurement down to very low frequencies.
A block diagram was used to simulate the open-loop LDO AC response. The
uncompensated LDO was divided into separate amplifier blocks shown in Fig. 18.
一个框图被用来模拟开环LDO的交流响应。未补偿的LDO被划分为图18所示的独立的放大器块。

Fig. 18. AC open-loop block diagram test circuit.

H1、H2和H3分别代表误差放大器、通过晶体管和反馈增益。通过晶体管已经根据所需的压差电压和最大负载电流
进行了设计。这样就剩下误差放大器和反馈增益需要设计。反馈电阻RF1和RF2被设计为通过晶体管吸收5µA的电
流。通过串联的反馈电阻的电流完全由输出电压决定。公式19定义了RF1和RF2的串联关系。
H1, H2, and H3 represent the error amplifier, the pass transistor, and the feedback gain,
respectively. The pass transistor was already designed based on the desired dropout voltage and
the maximum load current. This left the error amplifier and the feedback gain to be designed.
Feedback resistors, RF1 and RF2, were designed to draw 5µA of current through the pass
transistor. The current through the series-connected feedback resistors is solely determined by
the output voltage. Equation 19 defines the series relationship of RF1 and RF2.

VOUT 2.8V
RF1 + RF 2 = = = 560kΩ (19)
I Q , pass 5µA

Equation 20 was then used to find the absolute resistor values, combining equation 18 and the
results from equation 19.
然后用公式20来寻找绝对电阻值，结合公式18和公式19的结果。
 28

RF 2 =
VREF
(RF1 + RF 2 ) = ⎛⎜ 1.24 ⎞⎟ ⋅ 560kΩ = 248kΩ (20)
VOUT ⎝ 2.8 ⎠
这迫使RF1的电阻达到312k。一个寄生电容也被纳入到反馈增益部分。这个电容被用来模拟误差放大器输入电容
和与电阻布局相关的任何寄生电容的影响。图19中显示了电容的加入。

This forces the resistance of RF1 to 312k. A parasitic capacitor was also incorporated into the
feedback gain section. This capacitor was used to simulate the effects of the error amplifier
input capacitance and any parasitic capacitance associated with resistor layout. The addition of
the capacitor is shown in Fig. 19.

Fig. 19. Feedback circuit with parasitic capacitor, CF1.

反馈增益传递函数被分为两部分，即直流增益和交流增益特性。公式21给出了增益块H3的小信号传递函数。
The feedback gain transfer function was divided into two components, the DC gain and the AC
gain characteristics. Equation 21 gives the small signal transfer function for gain block H3.

⎡ RF 2 ⎤ ⎡ 1 ⎤
H3 = ⎢ ⎥ ⋅⎢ ⎥ (21)
⎣ R F 1 + R F 2 ⎦ DC ⎣1 + s ( R F 1 // R F 2 ) ⋅ C F 1 ⎦ AC
因此，寄生电容CF1只贡献了一个极点。反馈极点的位置位于相对较高的频率。尽管如此，CF1会影响相位差和快
速瞬态响应。
Thus, the parasitic capacitor, CF1, only contributes a pole. The location of the feedback pole
resides at relatively high frequency. Nonetheless, CF1 can affect the phase margin and the fast
transient response.
 29
通过晶体管级，H3，形成一个共源放大器。图16显示了完整的通过晶体管电路，包括寄生电容，CGS和CGD。这
个电路被用来形成一个小信号模型，如图20所示。
The pass transistor stage, H3, forms a common source amplifier. Fig. 16 showed the
complete pass transistor circuit including the parasitic capacitors, CGS and CGD. This circuit was
used to form a small signal model, shown in Fig. 20.

Fig. 20. Pass transistor small signal analysis.

通过晶体管的输入阻抗与误差放大器合并。H3代表其余的通过晶体管电路元件。初步检查表明H3有一个极点和一
个零。方程22形成了以VGS为输入的通过晶体管输出处的节点分析。

The pass transistor input impedance was merged with the error amplifier. H3 represents the rest
of the pass transistor circuit elements. Preliminary inspection indicates H3 had one pole and one
zero. Equation 22 forms the nodal analysis at the pass transistor output with VGS as the input.

vout
+ sC OUT vout + (vout − v gs ) sC gd + vin g m = 0 (22)
Rout

方程22被重新排列，形成方程23中的输出传递函数。
Equation 22 was rearranged to form the output transfer function in equation 23.

⎛ C gd ⎞
− g m Rout ⎜⎜1 − s ⎟
vout ⎝ g m ⎟⎠
= (23)
v gs s (C out + C gd ) Rout + 1
 30
传递函数中出现了一个极点和一个零点，反映了初步检查的情况。H1的传递函数遵循与H2类似的结果，但没有
前馈零点。表四列出了其余的小信号表征以及图18中给出的放大器块的极点和零点。

Both a pole and a zero appeared in the transfer function reflecting the preliminary inspection.
The transfer function for H1 followed similar results as H2 but without the feed-forward zero.
Table IV lists the rest of the small signal characterization and the poles and zeros for the
amplifier blocks given in Fig. 18.

TABLE IV
AMPLIFIER BLOCK SMALL SIGNAL TRANSFER FUNCTIONS

BLOCK TRANSFER FUNCTION POLE/ZERO

g m1 R1 1
H1 TF = p1 =
1 + sR1C1 R1C1
1
⎛ C gd ⎞ p2 =
− g mp Rout ⎜1 − s ⎟ ROUT C OUT
H2 ⎜ g ⎟
TF = ⎝ mp ⎠ g mp
s (C out + C gd ) Rout + 1 z1 =
C gd
⎡ RF 2 ⎤ ⎡ 1 ⎤ 1
H3 TF = ⎢ ⎥ ⋅⎢ ⎥ p3 =
⎣ R F 1 + R F 2 ⎦ DC ⎣1 + s ( R F 1 // R F 2 ) ⋅ C F 1 ⎦ AC R F 1 // R F 2 ⋅ C OUT

放大器H1和H2的特征是一个简单的一阶跨导传递函数。H1构成误差放大器模块，其中C1构成误差放大器的输出电
容，与有效通过晶体管栅极电容并联。有效的通电晶体管栅极电容在方程16中得出。公式24构成完整的误差放大器
输出极。
Amplifiers H1 and H2 are characterized by a simple first order transconductance transfer
function. H1 forms the error amplifier module, where C1 constitutes the error amplifier output
capacitance in parallel with the effective pass transistor gate capacitance. The effective pass
transistor gate capacitance was derived in equation 16. Equation 24 forms the complete error
amplifier output pole.

1 1
ω P1 = = (24)
R1C1 R1 [C error + C GS + (1 + G m, pass RO , pass ) ⋅ C GD ]
H3形成了通式晶体管共源放大器，gmp等于通式晶体管的跨导值。通过晶体管放大器块中的ROUT，H3结合了几个
电路参数。基于负载条件，有两种不同的方法来模拟ROUT。负载可以被建模为一个电阻，也可以被建模为一个电
流源。图21显示了通过晶体管输出阻抗建模的两种不同方法。
H3 forms the pass transistor common source amplifier with gmp equaled to the pass transistor
transconductance. ROUT in pass transistor amplifier block, H3, combines several circuit
 31

parameters. There are two different methods of modeling ROUT based on loading conditions. The
load can either be modeled as a resistor or as a current source. Fig. 21 shows the two different
methods for modeling the pass transistor output impedance.

Fig. 21. Pass transistor output resistance models.

通过晶体管的输出电阻是由反馈电阻RF1和RF2、晶体管输出电阻和负载电阻的平行组合形成。使用电流源负载的
方程25和使用电阻负载的方程26对两种形式的通断器输出电阻进行建模。
The pass transistor output resistance is formed from the parallel combination of the feedback
resistors, RF1 and RF2, the transistor output resistance, and the load resistance. Equation 25,
using a current source load, and equation 26, using a resistor load, model the two forms of pass
transistor output resistance.

ROUT = ( RO , pass // R F 1 + R F 2 // RO ,current ) (25)

ROUT = ( RO , pass // R F 1 + R F 2 // R L ) (26)

Resistive loading decreases the output impedance with respect to a current source load, and
effectively pushes the output pole to higher frequencies. Resistive loading was used for the
simple uncompensated AC response but was later changed to a current source for the final
design. The error amplifier was design to yield an overall gain of 100dB. Simulations showed
相对于电流源负载而言，电阻性负载降低了输出阻抗，并有效地将输出极推到更高的频率。电阻性负载被用于简
单的无补偿交流响应，但后来在最终设计中被改为电流源。误差放大器被设计为产生100dB的整体增益。仿真显示
，在零负载电流条件下，通过晶体管提供大约20dB的增益。因此，误差放大器需要80dB的增益。误差放大器也被
设计成在100Hz左右产生主导的系统极点，对于一个单极系统来说，产生的增益-带宽乘积为1MHz。公式27举例说
明了确定R1和C1的程序。
 32

that the pass transistor provides roughly 20dB of gain at the zero load current condition. Thus,
the error amplifier requires 80 dB of gain. The error amplifier was also design to produce the
dominant system pole around 100Hz, yielding a gain-bandwidth product of 1MHz for a single
pole system. Equation 27 exemplifies the procedure for determining R1 and C1.

1 1
C1 = = = 0.159nF (27)
R1 p1 10MΩ ⋅ (100 Hz ⋅ 2π )

R1被任意设置为10MΩ，迫使有效误差放大器输出电容C1为1.59nF。误差放大器的跨电导，gm1，由公式28确定
。
R1 was arbitrarily set to 10MΩ, forcing the effective error amplifier output capacitance, C1, to
1.59nF. The error amplifier transconductance, gm1, was determined by equation 28.

ADC ,error 10,000V / V

gm1 = = = 1000µA / V (28)
R1 10MΩ

最后，通过晶体管放大器的参数从BSIM3仿真中提取。图22显示了仿真结果。所有的交流电路参数都列在表五中。
Finally, the pass transistor amplifier parameters were extracted from a BSIM3 simulation. Fig.
22 shows the simulation results. All the AC circuit parameters are tabulated in Table V.

Fig. 22. Pass transistor load-dependent DC operating points: (a) transconductance (b) output resistance.
 33

TABLE V
AC RESPONSE TEST CIRCUIT PARAMETERS

ERROR AMPLIFIER PASS TRANSISTOR

DC Gain 80 dB W/L 16mm/400nm
Gm1 1000µA/V Gm Variable
R1 10MΩ Rout Variable
C1 0.159nF IQ 5µA
Pole 100Hz COUT 100pF
FEEDBACK VOLTAGE LEVELS
Β 0.443 VREF 1.24V
RF1 312kΩ VIN 3.0V
RF2 248kΩ VOUT 2.8V
CF1 1pF IOUT 0 ~ 50mA

All the amplifier blocks were combined together to yield equation 29. A computer simulation
determined the system poles and the AC Bode plots for various loading conditions. Fig. 23
illustrates the pole movement for the uncompensated capacitor-less LDO regulator. The AC
bode diagram was simulated for both zero load current and a 50mA load current. The load
dependent pass transistor gain adjusts the overall DC gain by roughly 10dB.
所有的放大器模块被组合在一起，得到方程29。计算机模拟确定了系统的极点和各种负载条件下的交流Bode图。图
23说明了未补偿的无电容LDO调节器的极点移动。对零负载电流和50mA负载电流的交流波德图进行了模拟。与负
载有关的通过晶体管增益将整个直流增益调整了大约10dB。
⎛ ⎛ C ⎞⎞
⎜ − g R ⎜1 − s gd ⎟ ⎟
mp out ⎜
Vout ⎛ g R ⎞ ⎜ ⎝ g mp ⎟⎠ ⎟ ⎛ RF 2 /( R F 1 + R F 2 ) ⎞
= ⎜⎜ m1 1 ⎟⎟ ⋅ ⎜ ⎟ ⋅ ⎜⎜ ⎟⎟ (29)
Vin ⎝ 1 + R1C1 s ⎠ ⎜ s (C out + C gd ) Rout + 1 ⎟ ⎝ 1 + s ( R F 1 // R F 2 )C F 1 ⎠
⎜⎜ ⎟⎟
⎝ ⎠

In a single pole system, the DC gain adjustment changes the gain-bandwidth product. Very
small load currents push the gain-bandwidth to higher frequency, increasing the difficulty in
stabilizing the LDO regulator. Secondly, the output pole movement is very large. Thus, a pole-
zero cancellation scheme becomes very tedious and cumbersome. Fig. 24 displays the pass
transistor output pole and phase margin verses the LDO load current. The pass transistor output
pole varies over several decades from 51kHz to 420MHz. This large variation in pole movement

在一个单极系统中，直流增益调整改变了增益-带宽乘积。非常小的负载电流将增益-带宽推向更高的频率，增加了
稳定LDO稳压器的难度。其次，输出极点的移动非常大。因此，极零消除方案变得非常繁琐和麻烦。图24显示了通
过晶体管输出磁极和相位差与LDO负载电流的关系。通过晶体管的输出极点在51kHz到420MHz之间变化了数十年。
这种极点移动的巨大变化导致相位差的巨大波动。大部分的变化在零负载电流和大约1mA的负载电流之间被吸收。
 34

causes large fluctuations in phase margin. Most of the variations are absorbed between zero load
current and approximately 1mA of load current.

Fig. 23. Uncompensated LDO AC response.

Fig. 24. Uncompensated LDO AC parameters verses Iout: (a) output pole frequency (b) phase margin.
 35

Fig. 25. Uncompensated AC response simulated in CADENCE.

The capacitor-less LDO regulator is inherently stable in the 1mA to 50mA range. The stability
of the final capacitor-less LDO regulator took these facts into account. CADENCE simulations
verify the mathematical models. Fig. 25 shows the uncompensated AC response simulated in
CADENCE. Mathematical models and CADENCE simulations revealed three important load
dependent AC characteristics. First, the LDO output pole moves with changing load conditions.
Second, the DC loop gain decreases with increasing load current. Finally, a right-half plane zero
created from the pass transistor parasitic capacitor, CGD, increases in frequency with a
corresponding increase in pass transistor transconductance. The variations are tabulated in Table
VI. These properties were taken into account during the final capacitor-less LDO regulator
design. Perhaps the most interesting discovery was the effects of the feed-forward zero.
Conventional LDO regulator analysis ignores this feed-forward zero. The reason is related to the
relative conventional LDO gain-bandwidth product, which typically ranges between 1kHz and
100kHz.
无电容的LDO稳压器在1mA至50mA范围内具有内在的稳定性。最终的无电容LDO调节器的稳定性考虑到了这些事
实。CADENCE的模拟验证了数学模型。图25显示了在CADENCE中模拟的未经补偿的交流响应。数学模型和
CADENCE模拟显示了三个重要的负载相关交流特性。首先，LDO输出极随负载条件的变化而移动。第二，直流环
路增益随着负载电流的增加而减少。最后，通过晶体管寄生电容CGD产生的右半平面零点，随着通过晶体管跨导的
相应增加而频率增加。这些变化列于表六。这些特性在最后的无电容LDO调节器设计中被考虑到了。也许最有趣的
发现是前馈零点的影响。传统的LDO调节器分析忽略了这个前馈零点。原因是与相对传统的LDO增益-带宽产品有
关，其范围通常在1kHz和100kHz之间。
 36

TABLE VI
LOAD DEPENDENT POLES AND ZEROS

EFFECT OF
RANGE
PARAMETER VARIANT INCREASED LOAD
(0 ~ 50mA)
CURRENT
p2 (output) ROUT Increase 10kHz ~ 420MHz
z1 gmp Increase 3.4MHz ~ 10GHz
ADC gmp, ROUT Decrease 100dB ~ 92dB
表六显示，前馈零点在典型的LDO增益带宽产品的十年之后，因此，在传统的LDO调节器分析中通常不会出现。所
提出的无电容LDO调节器需要一个1MHz的增益带宽积。在这个频率下，前馈零点在低负载电流下有明显的影响。
Table VI shows that the feed-forward zero falls a decade past the typical LDO gain-bandwidth
product, and therefore, does not typically surface during conventional LDO regulator analysis.
The presented capacitor-less LDO regulator requires a gain-bandwidth product of 1MHz. At this
frequency, the feed-forward zero has noticeable affects at low load currents.
3. 未补偿的瞬态响应
3. Uncompensated Transient Response

The uncompensated capacitor-less LDO transient response showed the limitations of

removing the large external output capacitor. The open-loop circuit shown in Fig. 17 was
modified to a closed-loop circuit by removing the large inductor. A load current transient was
introduced with an active load current mirror, shown in Fig. 26 with the transient response
shown in Fig. 27.
无补偿的无电容LDO瞬态响应显示了去除大型外部输出电容的局限性。图17所示的开环电路通过移除大电感被修改
为闭环电路。用一个有源负载电流镜引入负载电流瞬态，如图26所示，瞬态响应如图27所示。

Fig. 26. Close-loop uncompensated LDO load transient test circuit.

不幸的是，无补偿的无电容LDO调节器在负载电流低于约1mA时是内在不稳定的。超过1mA时，无电容LDO是稳定
的，需要进行瞬态响应调查。图27说明了与这种类型的LDO电压调节器有关的问题。响应是在0至50mA方波负载电
流瞬态下进行的，上升和下降时间为1µs。显然，输出电压，即图27的底部部分，是不可接受的。大的电压尖峰不
37
是由于稳定性问题，而完全是由于通电晶体栅极的电容回转所致。在负载电流从0mA到50mA的快速瞬变期间，
LDO输出电压实际上可以接近零伏。通过晶体管栅极电容的回转需要一个快速瞬态路径。由于控制环路包含误差放
大器输出端的主导低频极点，大信号瞬态响应受到很大影响。本节的结果导致了最初的无电容LDO调节器的研究和
开发。
Unfortunately, the uncompensated capacitor-less LDO regulator is inherently unstable at load
currents below approximately 1mA. Above 1mA the capacitor-less LDO is stable and warrants
a transient response investigation. Fig. 27 illustrates the problems associated with this type of
LDO voltage regulator. The response was carried out with a 0 to 50mA square wave load
current transient with 1µs rise and fall time. Clearly, the output voltage, bottom portion ofFig.
27, is unacceptable. The large voltage spikes are not due to a stability issue but are solely due to
capacitor slewing at the gate of the pass transistor. The LDO output voltage can actually
approach zero volts during a fast transient from 0mA to 50mA of load current. Pass transistor
gate capacitor slewing requires the need of a fast transient path. Since the control loop contains
the dominant low frequency pole at the output of the error amplifier, the large signal transient
response suffers significantly. Results from this section lead to the initial capacitor-less LDO
regulator research and development.

Fig. 27. 0 to 50mA load transient response.

无电容LDO调节器的研究和开发始于初步分析的结果。有两个主要的设计考虑：瞬态响应和稳压器的交流稳定性。
如果只完成了其中一个设计标准，无电容LDO就没有有益的价值。这就提出了一个问题：设计过程应该从哪里开始
。直观地说，人们会认为稳定性是最重要的LDO调节器属性，设计应首先稳定电路。然而，这一假设是大多数已发
38
表的专业论文中的主要设计缺陷，大多数设计都有较差的瞬态响应。所提出的研究偏离了这种方法，并在设计时考
虑到了瞬态响应。
B. 设计结构策略
B. Design Architecture Strategy

Capacitor-less LDO regulator research and development started with the results from the
preliminary analysis. There were two major design considerations: transient response and
regulator ac stability. The capacitor-less LDO has no beneficial value if only one of the design
criteria was accomplished. This raised the question, were should the design process start.
Intuitively, one would assume that stability is the foremost important LDO regulator attribute
and that the design should first stabilize the circuit. This assumption, however, is the leading
design flaw in most of the published professional papers with most designs having poor transient
responses. The presented research strayed away from this approach and initiated the design with
transient response in mind.
1. 瞬态响应补偿
1. Transient Response Compensation

The pass transistor comprises the most important element in the LDO transient response.
It supplies current to the load impedance and as a result develops the desired output voltage.
Transistor gate capacitance acts as a current to voltage converter, and thus, has an equivalent
propagation delay. The larger the gate capacitance is, the larger the propagation delay will be.
In the case of the pass transistor, the effective input gate capacitance is extremely large. Fig. 28
illustrates the current to voltage conversion at the gate of the pass transistor.
通过晶体管是LDO瞬态响应中最重要的元素。它向负载阻抗提供电流，从而产生所需的输出电压。晶体管的栅极电
容作为一个电流到电压的转换器，因此，有一个等效的传播延迟。栅极电容越大，传播延迟就越大。在通过晶体管
的情况下，有效的输入栅极电容是非常大的。图28说明了在通过晶体管栅极的电流到电压的转换情况。

Fig. 28. Pass transistor gate transient effect.

LDO电压调节器中的每个晶体管都有传播延迟。由于通式晶体管栅极电容的回转，通式晶体管贡献了最具破坏性
39
的传播延迟。只有当栅极电压Vg在一定的时间延迟tp后达到稳态时，通式晶体管才能向负载提供所需的电流。无
电容LDO电压调节器的速度主要由通过晶体管传播延迟tp决定，而不是控制回路的增益带宽乘积。

Each transistor in the LDO voltage regulator had a propagation delay. The pass transistor
contributes the most devastating propagation delay owing to the pass transistor gate capacitor
slewing. The pass transistor can only supply the desired current to the load when the gate
voltage, Vg, reaches steady-state after some time delay, tp. The speed of the capacitor-less LDO
voltage regulator is mainly determined by the pass transistor propagation delay, tp, and not the
gain-bandwidth product of the control loop.
Most LDO regulator designs attempt to reduce the source impedance, RS, to increase the
speed of pass transistor. Typically, a low output impedance buffer is used to drive the pass
transistor [7]. This approach greatly improves the transient response in conventional LDO
regulators were the external capacitor creates the dominant pole. The capacitor-less LDO
voltage regulator does not have this luxury. The small internal output capacitor can not be used
to create the dominant pole since the output pole resides at much higher frequencies. Thus, the
dominant pole must be placed within the error amplifier control loop. The transient control
signal must therefore propagate through a dominant pole before or at the gate of the pass
transistor.
大多数LDO稳压器设计试图降低源阻抗RS，以提高通电晶体的速度。通常，一个低输出阻抗的缓冲器被用来驱动通
过晶体管[7]。这种方法大大改善了传统LDO稳压器的瞬态响应，因为外部电容产生了主导极。无电容的LDO电压调
节器没有这种奢侈。小的内部输出电容不能用来创建主导极，因为输出极位于更高的频率。因此，主导极必须放在
误差放大器控制环路内。因此，瞬态控制信号必须在通过晶体管的栅极之前或栅极处通过主导极传播。

Fig. 29. Fast transient path general concept.

需要一种新的技术来提高通过晶体管门的速度。注入通过晶体管栅极电容的信号最好是一个电压。如图28所示，栅
极电压实际上是一个次要效应。电流必须首先流进栅极电容。然后，栅极电容器将电容器的电流整合起来，形成栅
极电压。快速路径必须以最小的延迟感知输出电流的变化，并将该信息转发回通断器门电容。这一信息必须以电流
的形式注入栅极电容器，与输出电压的变化成比例。图29显示了这个基本概念。 40

A new technique was needed to increase the speed of the pass transistor gate. The signal
injected into the pass transistor gate capacitor is ideally a voltage. As shown in Fig. 28, the gate
voltage is actually a secondary effect. Current must first flow into the gate capacitor. The gate
capacitor then integrates the capacitor current to form the gate voltage. The fast path had to
sense the change in output current with minimal delay and relay that information back to the pass
transistor gate capacitor. This information had to be injected in the form of current, at the gate
capacitor, in proportion to the change in output voltage. Fig. 29 shows the basic concept.
The ideal sensing network would relay the output voltage information to the gate
capacitor without consuming any power or changing the DC operating points of the pass
transistor. Several different topologies were developed for the sensing network. A differentiator
sensing network, however, produced the best results. A basic capacitor differentiator is shown in
Fig. 30.
理想的传感网络将把输出电压信息传递给栅极电容器，而不消耗任何功率或改变通过晶体管的直流工作点。为传感
网络开发了几种不同的拓扑结构。然而，一个微分器传感网络产生了最好的结果。图30中显示了一个基本的电容微
分器。

Fig. 30. Basic capacitive differentiator.

微分器感应到V1和V2之间电压差的任何变化。等式30将电容器电流等同于这两个电压。
The differentiator senses any change in voltage difference between V1 and V2. Equation 30
equates the capacitor current to the two voltages.

⎛v −v ⎞
iC = C f ⋅ ⎜ 1 2 ⎟ (30)
⎝ dt ⎠

Fig. 27 showed that the worst case scenario is a large increase in load current, especially during
fast load current transitions. The capacitor-less LDO output voltage sags due to the slow
response of the control circuit and the pass transistor gate capacitance. The load demands a large

图27显示，最坏的情况是负载电流大幅增加，特别是在快速负载电流转换期间。由于控制电路和通电晶体栅极电容
的缓慢响应，无电容的LDO输出电压下垂。负载在短时间内需要大量的电流，但通过晶体管基本上是作为一个恒定
的电流源，如图25所示。如果微分器电容的一端连接到输出电压节点上，输出电压的变化将引起与电容电压变化成
比例的电容电流。图31显示了添加微分电容器Cf后，典型的未补偿输出电压和输出电流的波形。当输出电压从标称
的2.8V变化时，会产生一个电容电流If。通过Cf的电流是双向的，对正负电压的偏移都有反应。然后设计了一个耦
合网络，将这一电流镜像到通过晶体管的栅极电容。
 41

amount of current in short amount of time, but the pass transistor essentially acts as a constant
current source shown in Fig. 25. If one end of the differentiator capacitor is attached to the
output voltage node, the change in output voltage would induce a capacitor current proportional
to the change in capacitor voltage. Fig. 31 shows the addition of the differentiating capacitor, Cf,
and the typical uncompensated output voltage and output current waveforms. A capacitor
current, If, is generated when the output voltage changes from the nominal 2.8V. The current
through Cf is bi-directional, responding to both positive and negative voltage deflections. A
coupling network was then designed to mirror this current into the pass transistor gate capacitor.

Fig. 31. Addition of differentiator fast path.

The speed of the differentiator is of particular interest. The instant the load demands
current, both Cf and CINT instantly respond by supplying current to the load. The output voltage
is a secondary effect and does not change until charge is stripped away from Cf and CINT. Thus,
the capacitor current transient leads the output voltage transient. In essence, the differentiator
capacitor predicts variations in the output voltage at the same time they exist, and the
differentiator represents the fastest type of detector possible. The only limitation is the amount
of current that can be supplied to differentiator capacitor. Ideally, the differentiator has an
infinite bandwidth assuming that the voltage at the other capacitor terminal, V1, remains constant
微分器的速度是特别值得关注的。在负载需要电流的瞬间，Cf和CINT都会立即作出反应，向负载提供电流。输出电
压是次要的，直到电荷从Cf和CINT中剥离出来才会发生变化。因此，电容器的电流瞬变导致了输出电压的瞬变。从
本质上讲，微分器电容器在输出电压存在的同时预测其变化，微分器代表了可能的最快类型的检测器。唯一的限制
是可以提供给微分器电容的电流量。理想情况下，微分器有一个无限的带宽，假设另一个电容终端V1的电压在整个
负载电流瞬态中保持不变。如果电压V1下垂到输出电压瞬态，快速瞬态路径的效果就会降低。
 42
接下来分析一下微分器的交流响应。有两种不同的工作模式，电流模式和电压模式。电压模式下的微分器被称为 "
交流耦合 "连接，在0Hz有一个零点。图32显示了从输出电压到耦合网络的电压模式交流响应，如图31所示。

throughout the load current transient. If the voltage V1 sags to an output voltage transient, the
effect of the fast transient path is reduced.
The AC response of the differentiator is analyzed next. There were two different modes
of operation, current mode and voltage mode. The differentiator in the voltage mode is referred
to as an “AC coupled” connection and has a zero at 0Hz. Fig. 32 shows the voltage mode AC
response from the output voltage to the coupling network, shown in Fig. 31.

Fig. 32. Differentiator voltage mode AC response.

为了更真实地描述微分器的特性，我们添加了一个寄生极。一个理想的微分器有一个不断增加的幅值响应，因为只
有直流的零点应该存在。然而，耦合网络将有一些非零输入阻抗，在系统中引入一个极点。公式31表达了微分器的
电压传递函数。
A parasitic pole was added to more realistic characterize the differentiator. An ideal
differentiator has an ever increasing magnitude response since only a zero at dc should exist.
The coupling network however will have some non-zero input impedance, introducing a pole
into the system. Equation 31 expresses the voltage transfer function for the differentiator.

v2 sC f R IN
= (31)
v out sC f R IN + 1

The coupling network input impedance drastically affects the speed and fast transient response
of the differentiator. The correct selection of Cf and the coupling network input impedance was
耦合网络的输入阻抗极大地影响了微分器的速度和快速瞬态响应。正确选择Cf和耦合网络的输入阻抗是经过深思熟
虑后设计的，将寄生极点置于增益带宽乘积之上。
 43

designed with careful consideration, placing the parasitic pole well passed the gain-bandwidth
product.
Cf formed the load sensing mechanism, but the method to couple the sensed load
variations posed the most difficult task. The coupling network forms a feedback loop, and the
feedback loop gain must be negative. The most basic negative feedback coupling network is a
straight wire, attaching the 2nd Cf node directly to the gate of the pass transistor, shown in Fig.
33. This method would work if Cf were made very large with respect to the pass transistor gate
capacitance. There is one major problem with this approach, the pass transistor’s RHP zero
frequency is reduced.
Cf形成了负载传感机制，但如何将传感到的负载变化进行耦合是最困难的任务。
变化构成了最困难的任务。耦合网络形成一个反馈回路，反馈回路的增益必须是负的。最基本的负反馈耦合网络是
一条直导线，将第2个Cf节点直接连接到通电晶体的栅极，如图33所示。如果Cf相对于通过晶体管的栅极电容来说
变得非常大，这种方法就会起作用。这种方法有一个主要问题，即通口晶体管的RHP零点频率会降低。

Fig. 33. Simplest coupling network.

方程32反映了在方程23中给出的通过晶体管的右半平面零点上增加了Cf。
Equation 32 reflects the addition of Cf to the pass transistor’s right-half plane zero given in
equation 23.

gmp
ω z pass = (32)
C gd + C f
 44

零点将移动到比最初的3MHz低得多的频率，并将位于整个控制环路的增益-带宽乘积之内。这将使无电容LDO调节
器极难稳定，如果不是几乎不可能的话。
The zero would move to much lower frequencies than the initial 3MHz, and would reside well
within the gain-bandwidth product of the overall control loop. This would make the capacitor-
less LDO regulator extremely hard to stabilize, if not almost impossible.
The previous analysis revealed an important design constraint; the coupling network
must provide negative feedback only. The direct connection of Cf not only created a feedback
path but also created an undesirable feed-forward path. Fig. 34 shows the proposed coupling
architecture.
之前的分析揭示了一个重要的设计限制；耦合网络必须只提供负反馈。Cf的直接连接不仅创造了一个反馈路径，而
且还创造了一个不受欢迎的前馈路径。图34显示了拟议的耦合结构。

Fig. 34. Proposed coupling network.

理想情况下，应该使用一个电流放大器将输出耦合到通过晶体管栅极。在充分的电流增益和静态偏置电流之间的权
衡方面出现了问题。一个电流放大器被替换成了一个跨导放大器。跨导放大器需要一个电压输入，因此，需要进行
电流到电压的转换，从而减慢了微分器的响应速度。尽管如此，跨导放大器gmf提供了一个负反馈路径，同时阻止
了原来的前馈路径。RIN为微分器电容提供电流，同时也提供必要的电流到电压的转换。
Ideally, a current amplifier should be used to couple the output back to the pass transistor gate.
Problems arise with the tradeoff between sufficient current gain and quiescent bias current. A
current amplifier was replaced with a transconductance amplifier. The transconductance
amplifier requires a voltage input, thus, a current to voltage conversion is needed, slowing down
the response of differentiator. Nonetheless, the transconductance amplifier, gmf, provided a
negative feedback path while blocking the original feed-forward path. RIN supplies the current
for the differentiator capacitor and also provides the necessary current to voltage conversion.
The topology in Fig. 34 was analyzed to provide the appropriate level of feedback
current gain. Fig. 35 shows the large signal capacitor and load charge analysis circuit. The goal
of the pass transistor during a fast load current transient is to supply the load demanded

对图34中的拓扑结构进行了分析，以提供适当水平的反馈电流增益。图35显示了大信号电容和负载电荷分析电路。
在快速的负载电流瞬变期间，通过晶体管的目标是提供负载所需的差分电荷。等式33将负载需求电荷与所需的通过
晶体管电荷联系起来。
 45

differential charge. Equation 33 relates the load demanded charge to the required pass transistor
charge.

∆Q LOAD = ∆I LOAD ⋅ t R / F = gm pass ⋅ ∆V g , pass ⋅ t R / F (33)

负载要求的电荷变化是非常明显的，其中tR/F是电流瞬态的上升或下降时间，　ΔILOAD是零负载到满负
载状态。
The change in charge demanded by the load is quite obvious where tR/F is the rise or fall time of
the current transient and ∆ILOAD is the zero-load to full-load condition.

Fig. 35. Differentiator charge analysis.

通路晶体管所需的电荷量等于其跨导产生的电流量和调节低电流和高电流转换的输出电压所需的稳态栅极电压之差
。现在可以根据差分栅极电压来计算通断晶体管中的电荷差，如公式34所示。
The amount of charge required by the pass transistor is equal to the amount of current generated
by its transconductance and the difference between the steady-state gate voltage required to
regulate the output voltage for the low and high current transitions. The charge difference in the
pass transistor could now be calculated based on the differential gate voltage, shown in Equation
34.

∆Q gs = ∆V g , pass ⋅ C gs = ∆I gs ⋅ t R / F (34)
 46

将Igs的值与耦合电容器Cf的特性替换，得到公式35。
The value of Igs was substituted with the properties of coupling capacitor Cf yielding equation 35.

C f ⋅ ∆VOUT
∆Q gs = ∆V g , pass ⋅ C gs = ⋅ tR / F (35)
tR / F

偏转电压Vg在方程35中得到解决，并代入方程34。最后，方程36求解Cf，以确定使输出电压瞬变最小所需的
有效电容。
The deflection voltage, Vg, was solved for in equation 35 and substituted into equation 34.
Finally, equation 36 solves for Cf to determine the effective capacitance needed to minimize the
output voltage transients.

⎛ ∆I ⎞ ⎛ C gs ⎞ ⎛ 50mA ⎞ ⎛ 26 pF ⎞
C f = ⎜⎜ LOAD ⎟⎟ ⋅ ⎜ ⎟=⎜ ⎟⋅⎜ ⎟ = 35nF (36)
⎜ ⎟ ⎝ 100mV
⎝ ∆VOUT ⎠ ⎝ gm pass ⎠ ⎠ ⎝ 365e − 6 ⎠
具有讽刺意味的是，方程36并不包含任何过渡时间。这是由于电容器的理想带宽是无限的。然而，微分器中引入的
极点将产生一个有限带宽的系统，输出电压偏移将增加。公式36显示，所需的Cf大小与负载电流变化和通过晶体管
栅极电容的有效大小成正比。另一方面，Cf与所需的输出偏转电压和通过晶体管的固有跨导成反比。
Ironically, equation 36 does not contain any transition times. This is due to the ideally infinite
bandwidth of a capacitor. An introduced pole in the differentiator will however produce a finite
bandwidth system, and the output voltage deflections will increase. Equation 36 shows that the
required size of Cf is proportional to the load current variations and the effective size of the pass
transistor gate capacitance. On the other hand, Cf is inversely proportional to the desired output
deflection voltage and the inherent transconductance of the pass transistor.
Cf was calculated based on the proposed design specifications. The output voltage
deflection was set to 100mV for a load current variation of 50mA. The pass transistor
transconductance was set to the lowest value, for a zero-load current condition, and Cf was found
to be 35nF. The required 35nF is too large to integrate on chip if the capacitor, Cf, was directly
connected between the output and the pass transistor gate. The proposed topology alleviates the
requirement of a large internal compensation capacitor by introducing a transconductance gain
amplifier, gmf. The gmf amplifier increases the effective size of Cf by the voltage gain of the
amplifier or Miller effect. Thus, Cf can be made much smaller than the required single 35nF
value. Equation 37 shows the affect of the added gmf amplifier shown in Fig. 34.

Cf是根据拟议的设计规格计算的。负载电流变化为50mA时，输出电压偏转被设定为100mV。在零负载电流条件下
，将通过晶体管的跨导设置为最低值，发现Cf为35nF。如果电容Cf直接连接在输出和通电晶体栅极之间，所需的
35nF太大了，无法在芯片上集成。拟议的拓扑结构通过引入一个跨导增益放大器gmf来缓解对大的内部补偿电容的
要求。gmf放大器通过放大器的电压增益或米勒效应增加Cf的有效尺寸。因此，Cf可以变得比所需的单个35nF值小
得多。公式37显示了图34所示的添加gmf放大器的影响。
 47

vg s ⋅ R IN ⋅ (C f gm f Rerr )
= (37)
v out ( sR IN C f + 1)( sRerr C gs + 1)

然后，有效的耦合电容，Cf，在方程38中定义。此时，方程37中的极点被忽略了；等效电容的计算方法是：。
The effective coupling capacitance, Cf, is then defined in equation 38. The poles in equation 37
were ignored at this point; the equivalent capacitor is computed as:

C f .eff = C f gm f Rerr = C f ⋅ Av , gmf (38)

因此，gmf放大器的电压增益被设计为产生所需的35nF有效耦合电容，但与[9]中使用的技术不同。通常增益值在
40dB到80dB之间，耦合电容在2pF到15pF之间，这取决于所需的最大输出电压瞬态。一个值得注意的特性是所需
的耦合电容随通电晶体跨导的变化而变化；由于通电晶体直流操作点引起的跨导非常小，因此零负载条件下需要更
多的耦合电容。 Thus, the voltage gain of the gmf amplifier was designed to yield the desired 35nF effective
coupling capacitance but differ from the technique used in [9]. Typically gain values range
between 40dB to 80dB with coupling capacitors in the range of 2pF to 15pF depending on the
maximum desired output voltage transient. A noteworthy property is the variation in required
coupling capacitance with respect to the change in pass transistor transconductance; the zero-
load condition requires much more coupling capacitance due to the very small transconductance
induced by the pass transistor dc operation point.
2. 交流稳定性补偿
2. AC Stability Compensation

The fast transient path was created using a differentiator. Stabilizing the new capacitor-
less LDO architecture is the next design stage. Components of the feedback network were
analyzed, but the complete AC transfer function was overlooked when designing the large signal
compensation. The overall control loop stability was the major concern, and the transfer
function was synthesized for basic circuit shown in Fig. 36. Equation 39 represents a simplified
version of the overall open-loop transfer function; the differentiator’s parasitic poles are removed
to simplify the analysis.
快速瞬态路径是用一个微分器创建的。稳定新的无电容LDO结构是下一个设计阶段。对反馈网络的组件进行了分析
，但在设计大信号补偿时忽略了完整的交流传递函数。整体控制环路的稳定性是主要的关注点，传递函数是为图36
所示的基本电路而合成的。方程39代表了整体开环传递函数的简化版本；为了简化分析，微分器的寄生极被移除。
 48

Fig. 36. Proposed topology: simplified circuit diagram.

在这个表达式中，1/RzCf的寄生极被忽略了，因为它应该被放置在环路的单一增益频率之上。
The parasitic pole at 1/RzCf is ignored in this expression since it should be placed well above the
loop’s unity gain frequency.

⎛ Cgd ⎞⎟
(Gm1 R1 ) ⋅ (Gm P ROUT )⎜ 1 − s
⎜ Gm ⎟
v
out = ⎝ p⎠
(39)
v ⎛ Cgd ⎞⎟
( sC GS R1 + 1)( sC INT ROUT + 1) + ( sC f R z Gm f 1 R1Gm P ROUT )⎜ 1 − s
in
⎜ Gm ⎟
⎝ p⎠

公式39揭示了微分器的理想影响和准米勒补偿的使用。假设CfRfAdiff 》 CINTROUTCgsR1，可以简化极点位置
，在公式40-42中给出。
Equation 39 sheds light on the ideal affect of the differentiator and the use of a quasi-Miller
compensation. The pole locations can be simplified by assuming the CfRfAdiff » CINTROUTCgsR1
and are given in Equation 40 – 42.

1
ω P1 = ω P dom ≈ (40)
C f R f Adiff

C f R f Gm f 1Gm p
ω P2 ≈ (41)
C INT C gs

Gm p
ω Z1 = − (42)
Cgd
1. 其
　 中Adiff = Gmf1R1GmpRout。微分器将位于通过晶体管的输入和输出的两极分开。高的微分器增益确保两个
极点之间有足够的距离，以产生稳定的交流响应。
49

where Adiff = Gmf1R1GmpRout. The differentiator splits the poles located at the input and output of
the pass transistor. High differentiator gain ensures sufficient distance between the two poles to
yield a stable AC response.
The macromodel of the final proposed solution is shown in Fig. 37 and adds additional
circuitry from that of Fig. 36. The compensating differentiator is composed by the integrator and
an additional amplifier Gmf2 to boost the feedback gain, resulting in higher equivalent
capacitance. The input resistance is also modified from Fig. 36, reflecting the final transistor-
level implementation, where RZ is replaced with Rf. Unfortunately, the differentiator contains
parasitic poles arising from the parasitic devices C2 and Rf that affect the overall behavior of the
AC stability, but they do not compromise the basic properties of the Miller pole splitting
technique. Fig. 37 also adds a second error amplifier stage to emulate the final circuit
implementation.

Fig. 37. Proposed capacitor-less LDO voltage regulator: Open-loop schematic.

The differentiator’s parasitic poles have an important influence on the loop stability. Nodal
analysis took all parasitic impedances into account to accurately model the final transistor-level
design. Fig. 38 shows the circuit used to model the differentiator.

2. 最终提出的解决方案的宏观模型如图37所示，在图36的基础上增加了额外的电路。补偿性微分器由积分器和一
个额外的放大器Gmf2组成，以提高反馈增益，从而产生更高的等效电容。输入电阻也从图36中进行了修改，反映
了最终的晶体管级实现，其中RZ被替换为Rf。不幸的是，微分器包含了由寄生器件C2和Rf产生的寄生极，影响了
交流稳定性的整体行为，但它们并没有损害米勒分极技术的基本特性。图37还增加了第二个误差放大器级来模拟最
终的电路实现。

3. 微分器的寄生极对环路稳定性有重要影响。节点分析考虑了所有的寄生阻抗，以准确模拟最终的晶体管级设计
。图38显示了用于为微分器建模的电路。
 50

Fig. 38. Differential equivalent circuit diagram.

该电路的电压传递函数已经确定。方程43显示了准确的传递函数，没有进行任何简化。
The voltage transfer function was determined for the circuit. Equation 43 shows the exact
transfer function with out any simplifications.

vout , f 1 sC f ( g mf 1 R f − 1) R2
= 2
(43)
vout s R f R2 C f C 2 + s ⋅ [C f ( R f + R2 ) + C 2 R2 ] + g m R2 + 1

为了降低传递函数的复杂性并暴露出关键的电路元件，我们使用了一些简化方法。简化结果见表七。
Several simplifications were used to reduce the transfer function complexity and expose the
critical circuit elements. The simplifications are shown in Table VII.

TABLE VII
DIFFERENTIATOR SIMPLIFICATIONS

STEP SIMPLIFICATION
1 Cf >> C2
2 [C f ( R f + R2 ) + C 2 R2 ] 2 >> 4 ⋅ R f R2 C f C 2 ⋅ [ g m R2 + 1]

重要的极点可以从方程44中提取出来，使用表七中的近似值可以找到近似的位置。
The significant poles can be extracted from equation 44 and approximate locations can be found
using the approximation in Table VII.
 51

[C f ( R f + R2 ) + C 2 R2 ] 2 − 4 ⋅ R f R2 C f C 2 ⋅ [ g m R2 + 1]
s = [C f ( R f + R2 ) + C 2 R2 ] ± (44)
2 ⋅ R f R2 C f C 2
高频瞬态响应完全由微分器寄生极点的位置决定。两个极点都被推到了可能的最高频率；但是，其他的限制因素限
制了极点频率的大小。图39所示的第一个寄生极，即PD1，是最关键的极点，为确保良好的瞬态响应，其位置刚好
超过增益带宽积。寄生极点在整个无电容LDO的稳定性中也起着重要作用。
The high frequency transient response is solely determined by the location of the differentiator
parasitic poles. Both poles were pushed out to the highest possible frequencies; however, other
constraints limit the magnitude of the pole frequencies. The first parasitic pole, PD1, shown in
Fig. 39, was the most critical pole and to ensure good transient response, was located just past
the gain bandwidth product. The parasitic poles also play an important role in the overall
capacitor-less LDO stability.

Fig. 39. (a) General differentiator pole movement with gmf1 (b) Differentiator open-loop AC response.

微分器的开环寄生极位置，ωPD1和ωPD2，显示在公式45和46中。当包含微分器和通过晶体管级的环路关闭时，
微分器的寄生极有不利影响。
The differentiator’s open-loop parasitic pole locations, ωPD1 and ωPD2, are shown in equation 45
and 46. The differentiator’s parasitic poles have an adverse effect when the loop containing both
the differentiator and the pass transistor stage is closed.
 52

1 + Gm f 1 R2
ω PD1 ≈ (45)
C f ⋅ ( R f + R2 )
1
ω PD 2 ≈ (46)
C 2 ( R2 // R f )

卡达诺方法[13]被用来将方程47中的三阶函数分解成它的根，显示出一个实极和一对复极，给定方程48中的判别值
。
Cardano’s method [13] is used to decompose the 3rd order function in equation 47 into its roots,
revealing one real pole and a complex pair given the value of its discriminant in equation 48.

( sRout C INT + 1) ⋅ ( s 2 R f R2 C f C 2 + s ⋅ [C f ( R f + R2 ) + C 2 R2 ] + g m R2 + 1) + Adiff (47)

( )
∆ ≈ 4 ⋅ Adiff ⋅ ω pD1 ⋅ ω pD 2 ⋅ ω POUT >> 1 (48)

This discriminant moves closer to 1 as the load current increases, indicating that complex pole
pair has a growing real component with larger load currents. The loop analysis does not contain
ωPdom since this pole location is virtually unaffected by the differentiators parasitic poles, ωPD1
and ωPD2. Fig. 40 shows the complex pole movement verses load current and the adverse effects
ωPD1 and ωz1 which push or pull the complex pole pair into the right-half plane where the AC
response becomes unstable. The root locus of Fig. 40 and ones hereafter represent the negative
or 0˚ root locus [14], reflecting the special case when having a RHP zero. Thus, the normal rules
for the root locus are reversed. The locations of the complex poles, ωP5, and ωP6 are given in
equation 49 – 51.

ω Complex ≈ ω P 2 (49)

ω P 5 ≈ ω PD 2 (50)

1
ω P6 = (51)
C E RE

这个判别式随着负载电流的增加而向1靠近，表明复数极对的实数分量随着负载电流的增加而增加。环路分析不
包含ωPdom，因为这个极点位置几乎不受微分器寄生极点ωPD1和ωPD2的影响。图40显示了复数极移动与负载
电流的关系，以及不利影响ωPD1和ωz1，它们将复数极对推到或拉到右半平面，在那里交流响应变得不稳定。
图40和以下的根位置代表负的或0的根位置[14]，反映了RHP为零时的特殊情况。因此，根基位置的正常规则是
相反的。复数极点、ωP5和ωP6的位置在公式49-51中给出。
 53

Fig. 40. Differentiator closed-loop pole movement with changing load current.

Fig. 41 shows the block diagram equivalent of the overall open-loop transfer function, where H1
and H2 represent the two-stage error amplifier, H3’ contains the closed-loop differentiator poles,
and β represents the feedback gain factor formed from RF1 and RF2. The closed-loop
differentiator poles, P5 and PCOMPLEX, represent the start of the open-loop poles for main control
loop open-loop transfer function, shown in Fig. 42. The block diagram in Fig. 41 can be used to
plot the all closed-loop pole locations and their movement verses load current and overall
feedback gain for the capacitor-less LDO regulator.
图41显示了整体开环传递函数的等效框图，其中H1和H2代表两级误差放大器，H3'包含闭环微分器极点，β代表由
RF1和RF2形成的反馈增益因子。闭环微分器极点，P5和PCOMPLEX，代表主控制环开环传递函数的开环极点的开
始，如图42。图41中的框图可用于绘制所有闭环极点的位置，以及它们与负载电流和无电容LDO调节器的整体反馈
增益的关系。

Fig. 41. Modified block diagram.

 54
对于每一个新的负载电流水平，必须为整体反馈增益的变化生成一个新的根基位置。因此，图42代表了一个二维根
基点，它产生于整个系统中的两个反馈回路，一个用于微分器回路，一个用于整体稳态控制回路。
For each new load current level, a new root locus must be generated for the changes in overall
feedback gain. Thus, Fig. 42 represents a two-dimensional root locus which arises from having
two feedback loops in the entire system, one for the differentiator loop and one for the overall
steady-state control loop.

Fig. 42. Complete root locus showing closed-loop pole movement for both load current variations and
feedback factor, β.

Fig. 42 shows that the imaginary axis forms a stability boundary for the differentiator’s closed-
loop complex poles. If the complex poles start in RHP as in Fig. 43, they will never leave the
RHP in full closed-loop operation. Thus, the complex poles in Fig. 40 should never cross the
imaginary axis. The condition for which there will be no RHP complex poles can be derived
from equation 52 showing the differentiator’s closed-loop transfer function in terms of poles and
zeros. The zero, ωp,gate, is not shown in Fig. 40 since it is mathematically canceled by the error
amplifier pole.
图42显示，虚轴形成了微分器闭环复极的稳定边界。如果复数极点像图43中那样从RHP开始，它们在全闭环运行中
永远不会离开RHP。因此，图40中的复数极点不应跨越虚轴。没有RHP复数极点的条件可以从方程52中得出，该方
程显示了微分器在极点和零点方面的闭环传递函数。图40中没有显示零点，ωp,gate，因为它在数学上被误差放大
器的极点抵消了。
 55

VOUT Agmp (1 − s / ω Z 1 )( s / ω PD1 + 1)( s / ω PD1 + 1)( s / ω P , gate + 1)

= (52)
V IN ( s / ω PD1 + 1)( s / ω PD 2 + 1)( s / ω P ,OUT + 1)( s / ω P , gate + 1) + ( s / ω Z , diff )(1 − s / ω Z 1 ) Aloop

RHP零点，ωZ1，给无电容LDO的特性方程增加了一个负s2项，允许形成两个RHP极点。在这种情况下，这两个
RHP极点将是复杂的。方程53表示在LHP中保持复数极点的条件。
The RHP zero, ωZ1, adds a negative s2 term to the capacitor-less LDO’s characteristic equation,
allowing for the formation of two RHP poles. In this case, the two RHP poles will be complex.
Equation 53 represents the condition to keep the complex poles in the LHP.

⎛ ω PD1 (ω PD 2 + ω P ,OUT + ω p , gate ) + ω PD 2 (ω P ,OUT + ω p , gate ) + ω P ,OUT ω p , gate ⎞ ⎛ω A ⎞

⎜ ⎟ > ⎜ Z , diff loop ⎟ (53)
⎜ ω P ,OUT ω p , gateω PD1ω PD 2 ⎟ ⎜ ω Z1 ⎟
⎝ ⎠ ⎝ ⎠

方程53表明，微分器回路的极点必须尽可能地增加，否则RHP的零点ωZ1就会增加很多。由于ωZ1、ωP,OUT和ωp
,gate受制于通过晶体管的尺寸，ωPD1和ωPD2必须被推到尽可能高的频率。
Equation 53 shows that the poles of the differentiator loop must be increased as much as possible
or that the RHP zero, ωZ1, much be increased. Since ωZ1, ωP,OUT, and ωp,gate, are constrained by
the size of the pass transistor, ωPD1 and ωPD2 must be pushed out to the highest possible
frequencies.
Fig. 40 and Fig. 42 show that the differentiator feedback path also creates additional left-
half plane zeros, located at the nodes that do not touch the feed-forward path. The most critical
zero, ωz2, is created by the differentiator’s lowest frequency open-loop pole, ωPD1, and typically
resides around the LDO’s unity gain frequency. Cf2 was added outside the differentiator loop,
creating an additional pole to cancel ωz2. Equation 54 shows the desired selection of Cf2.
图40和图42显示，微分器反馈路径还产生了额外的左半平面零点，位于不接触前馈路径的节点处。最关键的零点，
ωz2，是由微分器的最低频率开环极点ωPD1产生的，通常位于LDO的统一增益频率附近。Cf2被添加到微分器环路
之外，创造了一个额外的极点来抵消ωz2。公式54显示了Cf2的理想选择。
1 + Gm f 1 R2 1
ωZ2 ≈ = ω P4 = (54)
C f ⋅ ( R f + R2 ) C f 2 ⋅ ( R F 1 // R F 2 )

The second closed-loop differentiator LPH zero, ωz3, is not critical and rests well above the
capacitor-less LDO’s unity gain frequency with the second error amplifier pole, ωp6, canceling
its effect.

第二个闭环微分器LPH零点ωz3并不关键，它远远高于无电容LDO的统一增益频率，第二个误差放大器极点ωp6抵
消了它的影响。
 56

Fig. 43. Stability constraint for the differentiator’s complex close-loop poles

交流补偿的无电容LDO调节器有一个Bode图，类似于一阶传递函数，直到复共轭极点对，如图44所示。近似的相位
裕度由公式55给出。随着ROUT的增加，相位余量减少，表明最差的相位余量出现在空载条件下。
The AC compensated capacitor-less LDO regulator has a Bode plot that resembles a
first-order transfer function up to the complex conjugate pole pair, shown in Fig. 44. The
approximate phase margin is given by equation 55. As ROUT increases, the phase margin
decreases, indicating that the worst phase margin occurs at the no-load condition.

⎛ A C R C GS R1 ⎞
PM ≈ 90 + tan −1 ⎜ DC INT OUT ⎟ (55)
⎜ 2 2
(C f R f ) Adiff ⎟
⎝ ⎠

交流稳定性要求复数极对不跨越s平面的虚轴，或者复数共轭极对的幅度峰值不超过0dB阈值。
AC stability requires that the complex pole pair does not cross the s-plane’s imaginary axis, or
the magnitude peaking of the complex conjugate pair does not peak over the 0dB threshold.
 57

这两个问题都可以通过将ωP5放置在尽可能高的频率上得到解决。下一节将介绍ωP5的放置和其他方法，
以达到优化的无电容LDO稳压器设计。
Both these problems are remedied by placing ωP5 at the highest possible frequency. The next
section describes ωP5 placement and other methods to reach an optimized capacitor-less LDO
regulator design.

Fig. 44. MATLAB simulation: Open-loop AC response for IOUT = 0mA.

 58

III. 晶体管级设计和仿真
III. TRANSISTOR-LEVEL DESIGN AND SIMULATION

The final transistor-level design is shown in Fig. 45 with a step-by-step design procedure
illustrated in Table VIII. The design starts with the required dropout voltage, VDROP, and the
maximum current at dropout, IMAX, which define the parameters of the pass transistor. The
design then defines the differentiator parameters, followed by the error amplifier parameters, and
ends with the selection of compensation capacitors, Cf2 and Cf3.
最终的晶体管级设计如图45所示，表八中说明了分步设计程序。设计从所需的压降电压VDROP和压降时的最大电流
IMAX开始，它们定义了通过晶体管的参数。然后，设计定义了微分器参数，接着是误差放大器参数，最后是补偿电
容Cf2和Cf3的选择。

Fig. 45. Proposed capacitor-less LDO transistor-level design.

The differentiator is designed to yield the desired transient response while stabilizing the
overall system transfer function. The input and output nodes of Mgmf1, forming the first stage
amplifier in the inverting differentiator, are the most critical nodes. Enough gain must be
developed to provide a sufficient transient response while generating very small parasitic
capacitors to push the generated poles, ωPD1 and ωPD2, to high frequency. Thus, the tradeoff
between stability and transient response remains the most difficult design problem, and several
iterations of the design procedure in Table VIII may be required.
微分器的设计是为了获得理想的瞬态响应，同时稳定整个系统的传递函数。Mgmf1的输入和输出节点构成了反相微
分器的第一级放大器，是最关键的节点。必须开发足够的增益，以提供足够的瞬态响应，同时产生非常小的寄生电
容，将产生的极点ωPD1和ωPD2推至高频。因此，稳定性和瞬态响应之间的权衡仍然是最困难的设计问题，可能
需要对表八中的设计程序进行多次反复。
 1. 　然后反相微分器通过晶体管Mgmf2和M8相加进入误差放大器输出。电阻器Rf执行三项主要任务：在负载电流瞬
变期间将电容器Cf提供的电流转化为电压，为Mgmf1和Mgmf2提供直流偏压，并帮助降低微分器的输入阻抗，将相
关的极点ωPD1推到环路单增益频率之外。 59
2. 三个电流镜像运算跨导放
大器，M1-M7，ME和Mgm1
，构成了误差放大器。三电
流镜像OTA的低阻抗内部节 TABLE VIII
点将寄生极点驱动到高频率 DESIGN GUIDE
；很好地通过了所需的增益-
带宽产品。误差放大器的寄 STEP PARAMETER CONSTRAINT FINAL VALUE
生极点只要至少比增益带宽 CGS = 26pF,
积大2到3倍，就不会对调节 1 Pass transistor VDROP, IMAX CGD = 26pF
器的性能产生明显影响，因 Gmp = 320uA/V
此，误差放大器可以被设计 2 CINT Area 100pF
成满足任何所需的参数，如
输出噪声、功耗和直流增益 3 R OUT Area, power 280kΩ
[2],[3],[5],[6],[8]和[9] 。直流 4 Adiff Equation 53, 55 ~ 60dB
增益是误差放大器唯一的稳 5 C f Equation 36, 38 2pF
定性约束，由所需的增益余 6 Rf ωPD1 > GBW 200kΩ
量或最坏情况下复数极点幅 7 Gmf2·R2 Adiff-Apass-Agmf1 ~ 30dB
度峰值和统一增益之间的幅 8 ADC Gain margin ≤ 68dB
度差所迫使。这个增益余量 9 GmE, Gm1 ADC-Apass ~ 40dB
是负载电流的函数，并在 10 Cf2 Equation 54 1pF
0mA至5mA的负载电流范围 11 Cf3 Trial and error 2pF
内保持最低值。增益是通过
改变GmE和Gm1来调整的，
典型的范围在40dB和60dB
之间。 The inverting differentiator then sums into the error amplifier output through transistors
Mgmf2 and M8. Resistor, Rf, performs three main tasks: transforms the current supplied by the
capacitor, Cf, into a voltage during load current transients, provides the dc bias for both Mgmf1
and Mgmf2, and helps to lower the differentiator’s input impedance pushing the associated pole,
ωPD1, beyond the loops unity gain frequency.
A three-current mirror operational transconductance amplifier, M1-M7, ME, and Mgm1,
forms the error amplifier. The low impedance internal nodes of the three-current mirror OTA
drive the parasitic poles out to high frequencies; well pass the desired gain-bandwidth product.
The error amplifier’s parasitic poles do not significantly affect the performance of the regulator
as long as they are at least 2 to 3 times greater than the gain bandwidth product, and error
amplifier can therefore be designed to meet any desired parameter such as the output noise,
power consumption, and dc gain [2],[3],[5],[6],[8], and [9]. DC gain is the only stability
constraint on the error amplifier, forced by the desired gain margin or the magnitude difference
between the worst case complex pole magnitude peak and unity gain. This gain margin is a
function of load current, and retains it lowest value in the load current range of 0mA to 5mA.
The gain is adjusted by changing GmE and Gm1, and typical ranges between 40dB and 60dB.
Each stage of the capacitor-less LDO regulator is biased from a current mirror: any
inaccuracies and mismatches will cause large DC offsets at the output. M4, M5, M8, and M9 are
added to reduce the systematic offsets due to the drain-source voltage on M1-M3, Mgm1, Mgmf1,
无电容LDO稳压器的每一级都是由电流镜偏置的：任何不准确和不匹配都会在输出端造成大的直流偏移。添加M4
、M5、M8和M9是为了减少由于M1-M3、Mgm1、Mgmf1和Mgmf2的漏源电压造成的系统偏移，并随着VIN的增加
而增加电流镜的精度。IB1和IB2的电流是由精确的内部基准产生的。
补偿电容Cf3，范围为1至2皮法拉，仅用于提高交流稳定性。Cf3利用米勒效应将最低频率的极点推向更高的频率，
并置于正反馈中，如图45所示，将微分器ωPD1的输入极点推向更高的频率。Cf3确实阻碍了微分器的瞬时响应，引
入了回转和放电假象，只应在输入极点导致复数极点进入右半平面时使用。表九中给出了最终的电路参数，图46中
60
显示了香料模拟的开环交流响应。最终的无电容LDO设计具有全范围的稳定性，其增益-带宽积大约为260kHz，相
位余量大于80度。

and Mgmf2 and increase the current mirror accuracy as VIN is increased. IB1 and IB2 currents are
generated from an accurate internal reference.
Compensation capacitor, Cf3, in the range of 1 to 2 picofarads, is only used to improve
the AC stability. Cf3 uses the Miller effect to push the lowest frequency pole out to higher
frequencies, and placed in positive feedback, shown in Fig. 45, pushes the pole at the input of the
differentiator, ωPD1, out to higher frequencies. Cf3 does hinders the transient response of the
differentiator, introducing slewing and discharging artifacts, and should only be used when the
input pole causes the complex poles to enter the right-half plane. The final circuit parameters are
given in Table IX with a spice simulated open-loop AC response shown in Fig. 46. The final
capacitor-less LDO design had full range stability with a gain-bandwidth product of roughly
260kHz and phase margin greater than 80 degrees.

Fig. 46. Spice simulation: Transistor-level open-loop AC response.

 61

TABLE IX
FABRICATED CIRCUIT PARAMETERS

TRANSISTOR W(µm) L(µm) ID(µA) VREF 1.24V

ME 20 2 7.5 Cf 2pF
M1 , M2 1 2 7.5 Cf2 1pF
M3, Mgm1 2 2 5 Cf3 2pF
M4 , M5 5 2 5 Rf 200kΩ
M6 2.9 2 5 RF1 156kΩ
M7 20.3 2 35 RF2 124kΩ
M9,Mgmf1 3 0.4 30 CINT 100pF
M8,Mgmf2 1 0.4 10 IB1 5µA
PASS 16000 0.4 10 IB2 10µA

A. 晶体管级模拟
A. Transistor-level Simulations
无电容的LDO电压调节器的设计寻求满足几个初始参数。由于提出了大量的模拟，LDO稳压器的每个引脚都影响了
几个设计约束。仿真按参数的类型划分，即开环交流响应、稳态参数、动态状态参数和高频参数。
The design of the capacitor-less LDO voltage regulator sought to meet several initial
parameters. Each pin of the LDO regulator affected several design constraints owing to the large
number of simulations presented. The simulations are divided by the type of parameter, namely
open-loop AC response, steady-state parameters, dynamic state parameters, and high frequency
parameters.
1. 开环交流响应
1. Open-loop AC Response

The open-loop capacitor-less LDO voltage regulator’s AC response was simulated at the
transistor-level. The results are shown in Fig. 47 for 5 low output current conditions.

开环无电容LDO电压调节器的交流响应在晶体管水平上进行了仿真。结果显示在图47中，有5个低输出电流条件
。
基本特性用标签说明。首先，直流增益在低输出电流下大约为60dB。接下来，相位差在零负载电流条件下下降。这
是由于输出极点移动到其最低频率以及右半平面零点。需要更多的微分器增益来将复数极点推向更高的频率，重新
获得相位裕度的损失。增益-带宽乘积被设定为大约900MHz，但可以更低，因为GBW不会对建议的LDO瞬态响应产
62
生很大影响；瞬态响应是由快速瞬态路径决定。峰值确实在1mA左右开始出现。我们希望并满足至少10dB的增益余
量，这是由Cf2的值或反馈电阻节点上增加的补偿电容设定的。

Fig. 47. Low output current open-loop AC response for Iout = 0 ~ 4mA.

The basic properties are illustrated with labels. First, the DC gain resides at roughly 60dB at low
output currents. Next, the phase margin drops off at the zero-load current condition. This is due
to the output pole moving to its lowest frequency as well as the right-half plane zero. More
differentiator gain was required to push the complex poles out to higher frequency, regaining the
loss in phase margin. The gain-bandwidth product was set at roughly around 900 MHz, but
could have been lower since the GBW does not greatly affect the proposed LDO transient
response; the transient response is determined by the fast transient path. Peaking did start to
occur around 1mA. The gain margin of at least 10dB was desired and met, set by the value of
Cf2 or the added compensation capacitor at the feedback resistor node.
The ac response was also simulated over the entire range to verify that the capacitor-less
LDO was indeed stable over the entire range. Fig. 48 shows the results.

也对整个范围内的交流响应进行了模拟，以验证无电容的LDO在整个范围内确实是稳定的。图48显
示了结果。
 63

Fig. 48. Full range open-loop AC response for Iout = 0 ~ 50mA.

在较高的电流下，超过1mA，无电容LDO作为一个一阶系统，大约有90度的相位差。而且，在整个电流范围内，
增益带宽保持相对稳定。这种现象是由于增益相对于主导极的增加而相应减少。
At higher currents, above 1mA, the capacitor-less LDO acts as a first order system with roughly
90 degrees of phase margin. Also, the gain-bandwidth remains relatively constant over the entire
current range. This phenomenon is due to the corresponding reduction of gain verses the
increasing dominant pole.
Both Fig. 47 and Fig. 48 represent the nominal ac response, excluding process variation
and component mismatch. AC simulations were also used to find the range of compensation
capacitance, Cf, and compensation resistance, Rf, that yields stable operation.

图47和图48都代表了额定的交流响应，不包括工艺变化和元件失配。交流模拟也被用来寻找能产生稳定操作的补偿
电容Cf和补偿电阻Rf的范围。
 64

Fig. 49. Variation in compensation resistor, Rf.

图49显示了增加和减少补偿电阻Rf的一般趋势。显然，在低电流条件下增加相位余量和中段输出电流的复杂峰值
之间存在着一种权衡。我们采用了一种摇摆不定的方法来确定最佳的补偿电阻。
Fig. 49 shows the general trend for increased and decreased compensation resistance, Rf.
Clearly, there was a tradeoff between increased phase margin at low current conditions and
complex peaking at the mid-range output currents. A teeter-totter approach was used to zero in
on the best compensation resistance.
Likewise, the compensation capacitance, Cf, was tested for its general affects. Fig. 50
illustrates the general trends. The magnitude response has more peaking as the compensation
capacitance is increased. However, if the peaking was to be reduced, the compensation
capacitance was reduced but at the cost of decreased phase margin at low currents. The
compensation capacitance in conjunction with the compensation resistance was selected based
on a balancing act between the complex pole peaking in the mid-range output currents and the
phase margin at the no-load current condition. These AC simulations only considered
component mismatch and not temperature variations. The temperature variations were simulated
in the statistical analysis section.

同样地，也测试了补偿电容Cf的一般影响。图50说明了一般趋势。随着补偿电容的增加，幅值响应有更多的峰值。
然而，如果要减少峰值，就要减少补偿电容，但代价是在低电流时减少相位差。补偿电容和补偿电阻的选择是基于
中段输出电流的复极峰值和空载电流条件下的相位裕度之间的平衡行为。这些交流模拟只考虑了元件失配，而没有
考虑温度变化。温度变化在统计分析部分进行了模拟。
 65

Fig. 50. Variation in compensation capacitor, Cf.

2. 稳态参数
2. Steady-state Parameters

The steady-state parameters define the capacitor-less LDO’s static state conditions.
There were two important characteristics that defined the steady-state LDO parameters, the line
regulation and the load regulation. The line regulation was simulated for 3 different loading
conditions, 0mA, 1mA, and 50mA output current. The input voltage was varied from 3V to
4.8V and the corresponding steady-state output voltage was measured. The results are shown in
Fig. 51. Like the line regulation simulation, the load regulation measured the steady-state output
voltage. This time, however, the input voltage was fixed to 3V and the output current was varied
from 0mA to 50mA or the full load condition. Fig. 52 shows the simulation results.

稳态参数定义了无电容LDO的静态状态条件。有两个重要的特性定义了稳态LDO参数，即线路调节和负载调节。
线路调节是针对3种不同的负载条件进行模拟的，0mA、1mA和50mA输出电流。输入电压从3V到4.8V变化，测量
相应的稳态输出电压。结果显示在图51中。与线路调节模拟一样，负载调节测量了稳态输出电压。然而，这一次
，输入电压被固定为3V，输出电流从0mA到50mA或满负荷状态变化。图52显示了仿真结果。
 66

Fig. 51. Line regulation for Iout = 0mA.

Fig. 52. Load regulation for Vin = 3V.

随着负载电流的变化，输出电压从额定的2.8V输出偏移。这种偏移是由于控制回路中直流电压增益的下降，因为通
过晶体管的跨导和输出电阻都随着负载电流的变化而变化。在零负载条件下，较高的直流电压增益改善了线路和负
载的调节，但却牺牲了交流的稳定性。 67

The output voltage deflects from the nominal 2.8V output as the load current changes. The
deflection was due to the drop in DC voltage gain in the control-loop as both the pass transistor
transconductance and output resistance change with load current. A higher DC voltage gain at
the zero load condition improves the line and load regulation but at the expense of AC stability.

3. 动态状态参数
3. Dynamic-state Parameters

The capacitor-less LDO dynamic response was simulated for both load regulation and
line regulation as well as the turn-on settling time. As the dynamic-state implies, the capacitor-
less LDO is subjected to both line and load transients. The transistor-level design was first
simulated without compensation capacitors, Cf2 and Cf3. Fig. 53 shows the zero to full load
response with these conditions.
对无电容LDO的动态响应进行了模拟，包括负载调节和线路调节，以及开启的稳定时间。正如动态状态所暗示的
，无电容LDO同时受到线路和负载瞬变的影响。首先对晶体管级设计进行了模拟，没有补偿电容Cf2和Cf3。图53
显示了这些条件下的零到满载响应。

Fig. 53. Full load transient response (without Cf2 and Cf3).
输出电流回转率被设定为50mA/µs，VIN设定为3V。无电容LDO稳压器的响应主要由快速瞬态路径或微分器决定。
最坏的情况是，从低电流到高电流的快速过渡，特别是零到满负荷的条件。输出电压在电流正向变化开始时有一个
快速的负电压尖峰。快速路径在几纳秒内迅速作出反应，并迫使通过的晶体管用力打开。不幸的是，在高输出电流
68
下，微分器有太多的补偿，见公式36，因为通过晶体管的跨导率显著增加。因此，在输出电压波形中也出现了一个
大的过冲现象。

The output current slew rate was set to 50mA/µs with VIN set to 3V. The capacitor-less LDO
regulator’s response is mainly determined by the fast transient path or the differentiator. The
worst case scenario is a fast transition from low to high current, especially zero to full load
conditions. The output voltage has a fast negative voltage spike at the onset of the positive
change in current. The fast path responds quickly within few nanoseconds and forces the pass
transistor to turn on hard. Unfortunately, the differentiator has too much compensation at high
output currents, see Equation 36, as the pass transistor transconductance increases significantly.
Thus, a large overshoot also appears in the output voltage waveform.
The transistor-level design was then simulated with the added compensation capacitors.
These added compensation capacitors, Cf2 and Cf3, degrade the capacitor-less LDO’s transient
response, but improve the LDO stability and sensitivity to process variations. The results are
shown in Fig. 54.
然后对晶体管级设计进行了模拟，增加了补偿电容。这些添加的补偿电容Cf2和Cf3降低了无电容LDO的瞬态响应，
但改善了LDO的稳定性和对工艺变化的敏感性。结果显示在图54中。

Fig. 54. Load transient response for zero to full load with Cf2 and Cf3.
 69
在零负载条件和1mA负载条件下都进行了线路调节模拟。输入电压从3V到3.5V变化，上升和下降时间为1µs。图
55显示了零负载条件和1mA负载条件下的结果。
Line regulation simulations were carried out at both the zero load condition and at 1mA
load condition. The input voltage was varied from 3V to 3.5V with a 1µs rise and fall time. The
results for both the zero load condition and 1mA load condition are shown in Fig. 55.

Fig. 55. Line transient response for Iout set to 0mA (a) and 1mA (b).
由于从输入线到输出电压的增益减少，线路瞬态响应随着较大的输出电流而改善。在零负载条件下，从输入到输出
的传递函数增益是最大的，相当于最坏情况下的线路瞬态响应。

The line transient response improves with larger output currents, due to the decreased gain from
the input line to the output voltage. At the zero load condition, the transfer function gain from
input to output is at its maximum and corresponds to the worst case line transient response.
The final transient simulation measured the turn-on settling time. This measurement
determines the maximum turn-on time required for the capacitor-less LDO to reach a steady-
state output voltage. Thus, the input voltage is taken from 0V, turned off, to 3V, turned on, and
the time is measured from the point at which the VIN line reaches 3V to the time the output
voltage reaches 1% of the nominal output voltage. The results are shown in Fig. 56.

最后的瞬态模拟测量了开启的稳定时间。该测量确定了无电容LDO达到稳态输出电压所需的最大开启时间。因此，
输入电压从0V（关闭）到3V（开启），测量从VIN线达到3V到输出电压达到额定输出电压的1%的时间。结果显示
在图56中。
 70

Fig. 56. Turn-on settling time for various output current conditions: (a) full pulse and (b) expanded view.

The worst case scenario occurs at high output current demands during turn on conditions. The
initial turn-on condition is relative fast since the pass transistors gate is held to zero, turning the
output device completely on. The output voltage begins to slew after tens of nanoseconds as the
error amplifier comes online and pulls the pass transistor’s gate voltage close to VIN. The
differentiator was the main limiting factor for the turn-on settling. The gates of the differential
amplifier are tied to the compensation capacitor, Cf, through the compensation resistor, Rf and
the turn-on time is related to the charge rate of the Cf through the differentiator’s feedback
resistor and the current source that feeds the differentiator circuit. The output voltage is solely
determined by the rate or charge injected into the output capacitance. Higher output current
demand reduces that rate at which the output capacitor can be charge and the maximum output
level reached before the error amplifier turns on. Thus, the slope of the output voltage does not
change and is entirely dependent on the slewing in the differentiator. However, the reduced
initial charge level is lower for the high current conditions resulting in a longer turn-on settling
time.
最坏的情况发生在开启条件下的高输出电流需求。最初的开启条件相对较快，因为通过晶体管的栅极被保持为零
，使输出设备完全开启。在几十纳秒后，输出电压开始回转，因为误差放大器上线并将通过晶体管的栅极电压拉
到VIN附近。微分器是接通后沉降的主要限制因素。差分放大器的栅极通过补偿电阻Rf与补偿电容Cf相连，开启时
间与通过差分器的反馈电阻和供给差分器电路的电流源的Cf的充电率有关。输出电压完全由注入输出电容的速率
或电荷决定。较高的输出电流需求降低了输出电容的充电速度，以及在误差放大器开启前达到的最大输出水平。
因此，输出电压的斜率不会改变，完全取决于微分器的回转。然而，在高电流条件下，减少的初始电荷水平较低
，导致开启的稳定时间较长。
 71

4. 高频参数
4. High Frequency Parameters

The final set of measurements included the capacitor-less LDO’s output referred noise
and the PSRR. The output referred noise was measured in closed-loop for different static output
current conditions. Fig. 57 shows the output referred noise for various loading conditions.

最后一组测量包括无电容LDO的输出参考噪声和PSRR。输出参考噪声是在不同的静态输出电流条件下以闭环方
式测量的。图57显示了不同负载条件下的输出参考噪声。

Fig. 57. Equivalent output noise for various loading conditions.

The low-frequency noise component is influenced by the DC loop gain and the output
impedance of the output stage. As the output stage impedance decreases, the output referred
noise is reduced. The noise is then filtered at high frequencies by the output pole. Most LDO
regulators are characterized by the integrated noise over a 1Hz to 100 kHz bandwidth. The
corresponding integrated noise is shown in Table X.

低频噪声成分受直流环路增益和输出级的输出阻抗的影响。随着输出级阻抗的降低，输出参考噪声也随之降低。然
后，噪声在高频率下被输出极过滤掉。大多数LDO稳压器的特点是在1Hz至100kHz带宽上的综合噪声。表十显示
了相应的综合噪声。
1. 在1Hz至100kHz的噪声带宽内，平均综合输出噪声大约为50µV。误差放大器贡献了大部分的噪声，尽管微分器
增加了明显的效果。拟议的无电容LDO稳压器的噪声规格与大多数标准LDO稳压器竞争。低噪声LDO稳压器在测量
带宽中通常有大约20µV或更低。噪声可以通过减少误差放大器的噪声电流来降低。 72

TABLE X
INTEGRATED OUPUT NOISE: 1Hz ~ 100kHz

LOAD CURRENT NOISE

IOUT = 0mA 51.7 µV
IOUT = 25mA 50.6 µV
IOUT = 50mA 50.3 µV

The average integrated output noise is roughly 50µV in the 1Hz to 100 kHz noise bandwidth.
The error amplifier contributes to most of the noise although the differentiator adds noticeable
effects. The noise specifications for the proposed capacitor-less LDO regulator compete with
most standard LDO voltage regulators. Low noise LDO regulators typically have approximately
20µV or less in the measured bandwidth. The noise can be reduced by reduction of noise current
in the error amplifier.
Power-supply-rejection-ratio defines the LDO regulator’s ability to reject small-signal,
high-frequency noise from the input line to the output voltage node. The capacitor-less LDO
voltage regulator’s PSRR was measured in closed-loop for various static state current conditions.
The results are shown in Fig. 58. The proposed topology improves with increased load current.
This is mainly due to the chosen structure for the error amplifier. The PSRR is improved by
applying VIN as a common-mode signal to both the pass transistors gate node and its source
node. The PMOS differential input pair coupled by its NMOS active current mirror load
decouples the VIN rail from its output. Thus, better PSRR can come from a PMOS active current
mirror where the output of the differential amplifier directly drives the pass transistor. The
PMOS differential pair was chosen due to their lower flicker noise and output circuit protection
to large transients.
The first knee in the PSRR plot is due primarily to the dominant pole at the gate of the
pass transistor. The PSRR at higher frequencies is caused by the relative impedance at the
output node. At the highest frequencies, the PSRR is a function of the output node impedance.

2. 电源拒绝率定义了LDO稳压器拒绝从输入线到输出电压节点的小信号、高频噪声的能力。无电容的LDO稳压器
的PSRR是在闭环中对各种静态电流条件进行测量的。结果显示在图58中。拟议的拓扑结构随着负载电流的增加而
改善。这主要是由于为误差放大器选择的结构。通过将VIN作为共模信号施加到通电晶体的栅极节点和其源极节点
，PSRR得到了改善。PMOS差分输入对由其NMOS有源电流镜像负载耦合，将VIN轨与输出解耦。因此，更好的
PSRR可以来自于PMOS有源电流镜，其中差分放大器的输出直接驱动通过晶体管。选择PMOS差分对是由于其较
低的闪烁噪声和输出电路对大瞬态的保护。

3. PSRR图中的第一个膝盖主要是由于通过晶体管栅极处的主导极。更高频率下的PSRR是由输出节点的相对阻抗
造成的。在最高频率下，PSRR是输出节点阻抗的一个函数。
 73

Fig. 58. PSRR measurement for various output current conditions.

5. 最终的LDO规格
5. Final LDO Specifications

The final capacitor-less LDO regulator simulated parameters are given in Table XI. The
parameters indicate the worst case scenario assuming nominal values for both the threshold
voltage and mobility. The capacitor-less LDO regulator was then tested for process variation.

表十一中给出了最终的无电容LDO调节器的仿真参数。这些参数表示最坏的情况，假设阈值电压和移动性都是标
称值。然后对无电容LDO调节器进行了工艺变化的测试。
TABLE XI
SIMULATED WORST CASE PARAMETERS

PARAMETERS SPECIFICATION PARAMETER SPECIFICATION

GBW 704 kHz Line transient +64mV
Phase Margin 72° Load transient -211mV
Line regulation 2 mV/V Settling time 4.7 µs
Load regulation 10mV (full load) PSRR 47dB (at 0mA)
Power 65 µA Noise 51.7 µV
为了研究无电容LDO对载流子迁移率和MOSFET阈值电压等工艺变化的敏感性，进行了蒙特卡洛分析。所有的
蒙特卡洛模拟都采用了阈值电压和迁移率每西格玛10%的变化。因此，99.7%的制造的IC将落入标称设计值的±
30%的范围。图59显示了工艺变化对空载条件下的增益-带宽积和相位差的影响。 74

B. 统计分析
B. Statistical Analysis

Monte Carlo analysis was performed to study the capacitor-less LDO’s sensitivity to
process variation such as carrier mobility and MOSFET threshold voltage. All the Monte Carlo
simulations used a 10% variation in both threshold voltage and mobility per sigma. Thus, 99.7%
of the fabricated IC would fall into the range of ± 30% of the nominal designed values. Fig. 59
shows process variation effects on the gain-bandwidth product and phase margin at the no-load
condition.

Fig. 59. Process variation for IOUT = 0mA: nominal GBW (a) and phase margin (b), Cf and Rf +20% of
nominal GBW (c) and phase margin (d), and Cf and Rf -20% of nominal GBW (e) and phase margin (f).
图59显示，即使补偿电容Cf和补偿电阻Rf有很大的变化，也能获得足够的相位差。接下来，对工艺变化的直流增益
和接地电流进行了模拟，如图60所示。
75

Fig. 59 shows that plenty of phase margin is obtained even with large variation in the
compensation capacitor, Cf, and compensation resistor, Rf. Next, the dc gain and the ground
current were simulated for process variation, shown in Fig. 60.

Fig. 60. Process variation on DC gain for IOUT = 0mA (a) and 1mA (b).

The simulation showed that the low current dc gain was more susceptible to process variation
with a standard deviation of 3.5dB compared to 1.0dB for the 1mA load condition. This was the
main reason the gain margin was increased as much as possible. Fig. 61 shows process variation
effects on the dc quiescent current. Since all the current branches within the capacitor-less LDO
regulator were all generated from current mirrors, the overall quiescent ground current was
virtually unaffected by process variation. The standard deviation was only 317nA. Finally, the
PSRR was simulated for process variation. The results are shown in Fig. 62.

仿真结果显示，低电流直流增益更容易受到工艺变化的影响，标准偏差为3.5dB，而1mA负载条件下的标准偏差为
1.0dB。这就是尽可能增加增益余量的主要原因。图61显示了工艺变化对直流静态电流的影响。由于无电容LDO调
节器内的所有电流分支都是由电流镜产生的，整体静态接地电流几乎不受工艺变化的影响。标准偏差只有317nA。
最后，对工艺变化的PSRR进行了模拟。结果显示在图62中。
 76

Fig. 61. Process variations effects on dc quiescent current.

Fig. 62. Process variation on PSRR for Iout = 0mA at 1Hz (a) and 100kHz (b) and for Iout = 50mA at 1Hz
(c) and 100kHz (d)
 77
最后，模拟了直流稳态输出电压的工艺变化影响。对四种不同的输出电流条件，即0mA、1mA、10mA和50mA的
变化进行了验证。结果显示在图63中。

Finally, the dc steady-state output voltage was simulated for process variation effects. The
variation was verified for four different output current conditions, 0mA, 1mA, 10mA, and
50mA. The results are shown in Fig. 63.

Fig. 63. Process variation on DC steady-state output voltage for Iout set to 0mA (a), 1mA (b), 10mA (c)
and 50mA (d).
最终的无电容LDO电压调节器是通过MOSIS教育服务在TSMC 0.35um CMOS技术中进行布局的。所有的电流镜
都使用了普通的中心布局技术，其中包括除大型通电晶体外的所有晶体管。16毫米的通过晶体管被分割成16个
20x50微米的晶体管块。这允许额外的nwell衬底接触，以防止由诱导体电流引起的潜在闩锁问题。在两个反馈电
78
阻RF1和RF2之间也进行了仔细的匹配，通过交织单元电阻来满足所需的比率。图64显示了最终的无电容LDO电
压调节器布局。
C. 最终的LDO布局
C. Final LDO Layout

The final capacitor-less LDO voltage regulator was laid out in a TSMC 0.35um CMOS
technology through the MOSIS educational service. Common centriod layout techniques were
used for all current mirrors which included all the transistors except for the large pass transistor.
The 16mm pass transistor was split into 16 20x50µm transistor blocks. This allowed for extra n-
well substrate contacts to prevent potential latch-up issues caused by induced bulk current.
Careful matching was also used to between the two feedback resistors RF1 and RF2 by
interweaving unit resistors to meet the desired ratio. Fig. 64 shows the final capacitor-less LDO
voltage regulator layout.

Fig. 64. Final layout in TSMC 0.35µm CMOS technology.

无电容LDO本身尺寸为538µm x 538µm，而焊盘框架尺寸为1.5mm x 1.5mm。通路晶体管和100pF的内部输出电容
占据了总有效面积的大约3/4。无电容LDO周围的区域由各种层构成，以满足密度限制。
79

The capacitor-less LDO itself measures 538µm x 538µm while the pad frame measures 1.5mm x
1.5mm. The pass transistor and the 100pF internal output capacitor occupy approximately ¾ of
the total effective area. The area surrounding the capacitor-less LDO is constructed of various
layers to meet density constraints.
The control circuit contains the error amplifier, the differentiator, the feedback resistors,
and extra compensation circuitry. The feedback resistors, RF1 and RF2, and the compensation
resistor, Rf, accounted for most of the control circuitry area. The feedback resistors were
constructed using the second polysilicon layer or poly2. Vertical orientation was used so that the
average temperature gradient due to the pass transistor radial heat dissipation pattern was felt
equally across the two feedback resistors. The compensation resistor, Rf, was constructed with a
n-well diffusion resistor. This allowed for lower parasitic capacitance per resistance and a better
absolute accuracy.
Finally, the input and output nodes were connected to 5 external pins each. The pin
inductance was reduced from roughly 30nH to 6nH and produced better fast current transients.
The external pin capacitance did not hinder the capacitor-less LDO’s transient response but
actually improved the performance. Extra capacitance was added from VIN to ground and helped
to filter out higher frequency noise and ripple. The capacitor-less LDO voltage regulator was
finally packaged in a 40 pin ceramic dual-inline package.

控制电路包含误差放大器、微分器、反馈电阻和额外的补偿电路。反馈电阻RF1和RF2，以及补偿电阻Rf，占了控
制电路的大部分面积。反馈电阻是用第二个多晶硅层或多晶硅2构建的。使用垂直方向，以便通过晶体管径向散热
模式引起的平均温度梯度在两个反馈电阻上平均感受到。补偿电阻Rf是用n型孔扩散电阻构成的。这使得每个电阻
的寄生电容更低，绝对精度更高。

最后，输入和输出节点分别与5个外部引脚相连。引脚电感从大约30nH减少到6nH，产生了更好的快速电流瞬变
。外部引脚的电容没有阻碍无电容LDO的瞬态响应，实际上提高了性能。从VIN到地增加了额外的电容，有助于
滤除更高频率的噪声和纹波。无电容LDO电压调节器最终被封装在一个40针的陶瓷双列封装中。
物理无电容LDO电压调节器在实验室里对所有的模拟参数进行了测试，除了开环交流响应。设计和制作了一块测
试板，以方便实验中收集各种测试。每个实验都有明确的测试仪器，以及其他实验和环境参数，实验是在这些参数
下进行的。 80

IV. 实验结果

IV. EXPERIMENTAL RESULTS

The physical capacitor-less LDO voltage regulator was tested in the laboratory for all the
simulated parameters except for the open-loop AC response. A test board was designed and
fabricated to facilitate the experimental gathering for various tests. Each experiment has the
testing apparatus clearly defined as well as other experimental and environmental parameters
under which the experiment was carried out.

A. 测试板设计
A. Test Board Design

The test board was fabricated on FR-4 glass epoxy double sided boards with tinned
copper traces and plated trough holes. External circuitry was included to generate the desired
reference voltage, VREF, and the desired bias current, IBIAS. These components were not included
on chip, reducing the potential of circuit failure. A foil pattern and schematic are provided in
Appendix I and II. Fig. 65 shows the finished and populated test board and setup.
测试板是在FR-4玻璃环氧树脂双面板上制作的，有镀锡的铜线和电镀的槽孔。外部电路包括产生所需参考电压
VREF和所需偏置电流IBIAS。这些元件不包括在芯片上，减少了电路故障的可能性。附录一和附录二中提供了箔片
图案和原理图。图65显示了完成的和填充的测试板和设置。

Fig. 65. Final populated test board and setup.

电路板包含有源和无源负载元件。有源电流镜像负载使用松下XNO2501硅NPN外延刨花晶体管对，通过波形发生器
提供负载电流瞬变。该测试板还包含一个表面贴装的100mA LDO稳压器，为VREF和IBIAS电路供电。LDO可以直
接从无电容LDO电压调节器的VIN供电，也可以用单独的电源供电。一个电位器和几个不同的无源元件可以被调入
81
和调出以测试静态负载条件。最后，高频信号可以通过一个大的双极电容和50欧姆的直流电源电阻耦合到VIN轨上
。

The circuit board contains both active and passive load elements. The active current mirror load
used the Panasonic XNO2501 silicon NPN epitaxial planer transistor pair to provide load current
transients via a waveform generator. The test board also contains a surface mount 100mA LDO
voltage regulator that supplies the VREF and IBIAS circuits. The LDO can be either supplied
directly from the VIN of the capacitor-less LDO voltage regulator or a separate power supply. A
potentiometer and several different passive elements can be switched in and out to test static load
conditions. Finally, high-frequency signals can be coupled onto the VIN rail via a large bipolar
capacitor and 50 ohm DC supply resistor.
B. 瞬态响应
B. Transient Response
瞬态响应是针对负载和线路瞬态以及开机稳定时间进行的测试。实验只需要一个波形发生器、一个示波器和一个直
流电源。瞬态响应的结果将在接下来的三个小节中给出。
The transient response was tested for load and line transients and for the turn-on settling
time. The experiments only require a waveform generator, an oscilloscope, and a dc power
supply. The transient response results are given the next three subsections.

1. 负载瞬态响应
1. Load Transient Response

The load transient response was tested for the load current transient from 0mA to 50mA
with a 1us rise and fall time. The load current was generated with a BJT NPN current mirror and
a signal generator. The test circuit is shown in Fig. 66.
负载瞬态响应测试了从0mA到50mA的负载电流瞬态，上升和下降时间为1us。负载电流是由一个BJT NPN电流镜和
一个信号发生器产生的。测试电路如图66所示。

Fig. 66. Transient load current generator.

 82
对电流发生器的输入电压波形的最小和最大电压水平进行了微调，以产生0mA至50mA的负载电流。然后使用
500MHz示波器测试无电容LDO电压调节器的零到满载响应。结果显示在图67中。

The input voltage waveform’s minimum and maximum voltage levels for the current generator
were finely tuned to yield a 0mA to 50mA load current. The capacitor-less LDO voltage
regulator was then tested for its zero to full load response using a 500 MHz oscilloscope. The
results are shown in Fig. 67.

Fig. 67. Transient response for a 0mA to 50mA load transient with VIN = 3V.

The capacitor-less LDO voltage regulator gave expected results that resemble the transistor-level
circuit simulations. A little extra ringing was experienced for the positive load current transition
and was sensitive to test cable movement. The ringing quickly subsided and a stable response
was reached. Thus, the capacitor-less LDO internal compensation had produced stable operation
from zero to full load.

无电容的LDO电压调节器给出了与晶体管级电路模拟相似的预期结果。在正负载电流转换时出现了一点额外的振铃
，对测试电缆的移动很敏感。振铃很快就消退了，并达到了稳定的响应。因此，无电容的LDO内部补偿产生了从零
到满负荷的稳定运行。
 83

2. 线路瞬态响应
2. Line Transient Response

The Line transient response was measured for a 3V to 4V step waveform with 1µs
transition times. The IBIAS and VREF circuits were operated from a separate power supply through
out the operation. An Agilent waveform generator was used to supply the transient step. Fig. 68
shows the capacitor-less LDO line transient response.
线路瞬态响应是针对3V到4V的阶梯波形测量的，过渡时间为1µs。在整个操作过程中，IBIAS和VREF电路由一个
单独的电源操作。一个安捷伦的波形发生器被用来提供瞬态阶跃。图68显示了无电容的LDO线路瞬态响应。

Fig. 68. Experimental line transient response with Iout = 0mA.

Fig. 68 illustrates the worst case line transient condition with capacitor-less LDO operating at the
zero load condition. The output waveform, top trace, was ac coupled to the oscilloscope and
does not reflect the dc component while the input rail waveform was directly coupled to the
oscilloscope. The input voltage waveform was measured directly at the test board input voltage
rail. All cables were BNC 50ohm assemblies. The experimental results closely matched the
图68说明了无电容LDO在零负载条件下运行的最坏情况下的线路瞬态状况。输出波形，顶部痕迹，是交流耦合到
示波器，不反映直流成分，而输入轨道波形是直接耦合到示波器。输入电压波形是直接在测试板的输入电压轨上
测量的。所有电缆都是BNC 50欧姆组件。实验结果与预测的线路瞬态行为密切相关，大约有50mV的输出电压尖
峰。这比模拟预测的要小，因为模拟没有包括从VIN到地的寄生电容和其他寄生电容。
 84

predicted line transient behavior with approximately a 50mV output voltage spike. This was less
than the simulation predicted since the simulation did not include the parasitic capacitance from
VIN to ground and other parasitic capacitances.
3. 开机沉降时间
3. Turn-on Settling Time

The measurements for turn-on settling time are shown in Fig. 69 for no load current and
Fig. 70 for IOUT equaled to 10mA and 50mA.

图69显示了无负载电流时的开启稳定时间，图70显示了IOUT等于10mA和50mA时的测量结果。

Fig. 69. Turn-on settling time for IOUT = 0mA: full pulse (a) and expanded view (b).
对电路板进行了修改，以测量无电容的LDO调节器的开启稳定时间。主动调节的偏置电流发生器使用滤波电容来消
除注入IC的任何噪声或纹波。大的滤波电容通过引入回转效应大大减少了开启的稳定时间。有源电流发生器被一个
简单的电阻器所取代，该电阻器被修整为提供7.5µA。 85

The circuit board was modified to measure the capacitor-less LDO regulator’s turn-on settling
time. The actively regulated bias current generator used filter capacitors to remove any noise or
ripple injected into the IC. The large filter capacitors drastically decreased the turn-on settling
time by introducing slewing effects. The active current generator was replaced by a simple
resistor trimmed to supply 7.5µA.

Fig. 70. Turn-on settling time for IOUT = 10mA (a) and IOUT = 50mA (b).
沉淀时间是从输入电压脉冲边缘到输出电压达到其稳态值的0.2%时测量的。空载条件下的开启稳定时间最短，为6.
7µs，而10mA负载条件下为7.5µs，50mA负载条件为8.7µs。输出电压有一个很大的初始过冲量。这是由于在电路
测试条件下，参考电压没有与输入电压同步。这迫使通过晶体管的栅极接地，而电路的其他部分充电，导致输出电 86
压与输入电压成轨。

The settling time was measured from the input voltage pulse edge to the time the output voltage
reached 0.2% of its steady-state value. The no-load condition had the shortest turn-on settling
time at 6.7µs while the 10mA load condition had 7.5µs and the 50mA load condition had 8.7µs.
The output voltage had a large initial overshoot. This was due to the circuit testing condition
where the reference voltage was not stepped with the input voltage. This forced the pass
transistor’s gate to ground while the rest of the circuit charged up, causing the output voltage to
rail out to the input voltage.
C. 高频响应
C. High-Frequency Response
对无电容LDO稳压器的高频特性进行了测试。这些测量包括PSRR、纹波抑制比和等效输出噪声。对不同的负载电
流条件进行了测量，包括零、1mA和50mA负载电流条件。
The capacitor-less LDO regulator was tested for its high frequency characteristics.
These measurements included the PSRR, ripple rejection ratio and the equivalent output noise.
Measurements were taken for different load current conditions which included the zero, 1mA,
and 50mA load current conditions.
1. 电源抑制比
1. Power-supply-rejection-ratio

The power-supply-rejection-ratio (PSRR) measured the transfer function from the

capacitor-less LDO regulator’s input voltage to its output voltage. A network analyzer was used
to calculate the transfer function based on a known frequency swept input signal and the
measured regulators output voltage. The PSRR tests used only small signals such that large
signal effects did not influence the measurements, and the input signal was ac coupled through a
large capacitor and small resistor. The zero created by the coupling network set below the
frequencies of interest, roughly 5Hz. The results are shown in Fig. 71. The test results
correspond closely to the predicted transistor-level simulations and shows that the PSRR
improves with increased load current. The first knee or the effective dominant zero resides at
approximately 100kHz. The low frequency PSRR for three different load currents were -71dB
for a 50mA load, -48dB for a 1mA load, and -71dB for a no load condition. A few interesting
artifacts surfaced that were not predicted by the simulations. First, the PSRR plots rolled off at
very low frequencies. This was due to the coupling of the input signal superimposed on the dc
power supply through a coupling capacitor and resistor, and a low frequency zero was created.
电源抑制比（PSRR）测量了从无电容LDO稳压器的输入电压到输出电压的传递函数。
Second, the PSRR for a 50mA load increased drastically.
无电容的LDO稳压器的输入电压到其输出电压的传递函数。一个网络分析仪被用来计算基于已知频率扫频输入信号
和测量的稳压器输出电压的传递函数。PSRR测试只使用小信号，这样大信号的影响就不会影响测量结果，输入信
号通过一个大电容和小电阻进行交流耦合。耦合网络产生的零点设置在感兴趣的频率以下，大约是5Hz。结果显示
在图71中。测试结果与预测的晶体管级模拟结果密切对应，显示出PSRR随着负载电流的增加而改善。第一个拐点
或有效的主导零点位于大约100kHz处。三种不同负载电流的低频PSRR为：50mA负载为-71dB，1mA负载为-48dB
，无负载条件为-71dB。一些有趣的现象浮出水面，这不是模拟所能预测的。首先，PSRR图在非常低的频率下滚落
。这是由于输入信号通过耦合电容和电阻叠加在直流电源上的耦合，并产生了一个低频零点。第二，50mA负载的
PSRR急剧增加。
 87

Fig. 71. PSRR for various loading conditions.

这是由于前向路径中的阻抗与频率有关，从而使一个近乎完美的公共信号出现在通过晶体管的栅极和源极。
This was due to the frequency dependant impedance in the forward path such that a near perfect
common signal appeared to the gate and source of the pass transistor.
2. 纹波抑制率
2. Ripple Rejection Ratio

The ripple rejection ratio was measured at low frequency. The rise and fall times were
reduced such that slewing did not occur. The line regulation could also be determined from such
a measurement since the time period was much greater that the settling time of the capacitor-less
LDO regulator. Fig. 72 shows the measurement.

纹波抑制比是在低频下测量的。上升和下降的时间被减少，从而不会发生回转。线路调节也可以从这样的测量中确
定，因为该时间段远远大于无电容LDO调节器的沉降时间。图72显示了测量结果。
 88

Fig. 72. Line ripple rejection at 100Hz.

输入电压和输出电压的幅度标度不同。纹波抑制 在100Hz时大约是43dB。该测量是在零负载条件下进行的。纹波
抑制 纹波抑制与PSRR直接相关，图72中的测量结果与图71中的结果一致。图71中所示。
The magnitude scales differ between the input voltage and output voltage. The ripple rejection
at 100Hz is roughly 43dB. The measurement was taken for the zero load condition. The ripple
rejection is directly related to the PSRR and the measurement in Fig. 72 matches the results
shown in Fig. 71.

3. 等效输出噪声
3. Equivalent Output Noise

The equivalent output noise was measured at 50mA of load current, and was measured
from 1kHz to 1MHz, shown in Fig. 73. The results show that flicker noise dominates most of
the usable bandwidth. The spot noise at 100kHz was roughly 720 nV/sqrt(Hz). This value was
higher than the predicted model, suggesting that the model parameters for flicker noise were
perhaps too conservative. This concluded the experimental results.

等效输出噪声是在50mA的负载电流下测量的，测量范围是1kHz到1MHz。从1kHz到1MHz，如图73所示。结果显
示，闪烁噪声主导了大部分的 可用的带宽。100kHz时的斑点噪声大约为720 nV/sqrt(Hz)。这个值 高于模型预测
值，表明闪烁噪声的模型参数可能过于保守。也许太保守了。实验结果到此结束。
在无电容器 LDO 稳压器领域有三项重要的工作 [4]、[11] 和 [12]；然而，每件作品都使用不同的器件作为传输
晶体管。工作 [4] 与提议的设计最相似，在共源配置中使用 MOSFET，但它没有全范围稳定性，在低电流负载
下失去了可控性。工作 [11] 在与经典线性稳压器非常相似的共漏极配置中使用 MOSFET，但 [4]89需要更大的电
压余量和偏置电流。最新的工作 [12] 使用复合晶体管来降低电压裕量，但代价是显着的偏置电流。

Fig. 73. Noise Spectrum for 50mA output current.

D. 结果的比较
D. Comparison of Results

There have been three significant works in the area of capacitor-less LDO voltage
regulators [4],[11], and [12]; however, each work uses a different device for the pass transistor.
Work [4] most closely resembles the proposed design, using a MOSFET in the common-source
configuration, but it does not have full range stability, losing controllability at low current loads.
Work [11] uses a MOSFET in the common-drain configuration which closely resembles classic
linear regulators, but [4] requires a much larger voltage headroom and bias current. The latest
work, [12], uses a composite transistor to reduce the voltage headroom but at the cost of
significant bias current.
Experimental results show that the proposed capacitor-less LDO voltage regulator
exceeds current work in the area of capacitor-less LDO regulators in both transient response and
AC stability while consuming only 65µA of quiescent current. A comparison is made among the
other output capacitor-less designs [4], [11], and [12], shown in Table XII, illustrating the
significance of the proposed capacitor-less LDO regulator. Not only does the proposed

实验结果表明，所提出的无电容器 LDO 稳压器在瞬态响应和交流稳定性方面都超过了无电容器 LDO 稳压器领域

的电流工作，同时仅消耗 65µA 的静态电流。对其他无输出电容设计 [4]、[11] 和 [12] 进行了比较，如表 XII 所示
，说明了所提出的无电容 LDO 稳压器的重要性。所提出的稳压器不仅功耗低，而且提供低压差和快速建立时间。
SoC 设计将受益于所提议的无电容器 LDO 稳压器可减少的电路板空间、引脚数和成本。
 90

regulator consume low power, but it provides a low dropout voltage and fast settling time. SoC
designs would benefit from the reduced board real estate, pin count, and cost achievable with the
proposed capacitor-less LDO regulator.

TABLE XII
FINAL LDO COMPARISON

THIS
PARAMETER [4] [11] [12]
WORK
Process (µm) CMOS 0.6 CMOS 0.5 CMOS 0.09 CMOS 0.35
Pass Element CS CD Composite CS
IMAX (mA) 100 300 100 50
VOUT 1.3 3.3 0.9 2.8
VDROP (V) 0.20 1.7 0.30 0.20
IQ(mA) 0.038 0.75 6 0.065
CINT(pF) 0 180 600 100
2
Area (mm ) 0.307 1 0.098 0.289
∆vout (Full Unstable at
400mV 90mV 183mV
load transient) low currents
Settling (µs) 1.6 300 N/A 7.8
PSRR (1kHz) 60 dB N/A N/A 57 dB
Loop gain
90 ~ 110 N/A >43 55 ~ 62
(dB)
Noise 60 µV N/A N/A 250 µV
已经提出了一种新颖的设计，该设计允许移除通常在 LDO 稳压器上发现的大型外部电容器。新的无电容器 LDO 只
需三个小型内部电容器即可实现良好的瞬态响应和交流稳定性。第 II 节对未补偿的无电容器 LDO 以及建议的补偿
技术进行了全面分析。未经补偿的分析表明，无电容器 LDO 的大部分特性会随着负载电流的变化而变化，因此难
91
以在 0mA 至 50mA 的整个输出电流范围内保证稳定性和良好的瞬态响应。

V. CONCLUSION

A novel design has been presented that allows for the removal of the large external
capacitor normally found on LDO voltage regulators. The new capacitor-less LDO only requires
three small internal capacitors for good transient response and AC stability. A thorough analysis
was preformed in Section II on the uncompensated capacitor-less LDO as well as the proposed
compensation technique. The uncompensated analysis showed that most of the properties of the
capacitor-less LDO change with varying load current, making it difficult to guarantee stability
and good transient response over the entire output current range of 0mA to 50mA.
The proposed topology uses a differentiator to sense changes is the output voltage and
provides a fast negative feedback path for load transients. The differentiator loop also doubles as
the AC stability compensation network, using the properties of the Miller capacitor pole splitting
technique. Farther analysis showed the bounds of stability for the proposed capacitor-less LDO
compensation technique. The differentiator’s parasitic poles play a major role in the design, and
for a stable system, they must be placed at the highest possible frequencies. A properly designed
capacitor-less LDO using the proposed technique resembles a 1st order system up to the gain
bandwidth product and remains as such throughout the entire output current range.
The proposed capacitor-less LDO voltage regulator was designed and fabricated in the
TSMC 0.35um CMOS technology through the MOSIS educational service. Experimental results
showed that the proposed technique can be used to make a fully stable capacitor-less LDO
voltage regulator. A comparison was made in Section IV with other works [4], [11], and [12]
where the proposed design clearly had the best balanced specification. It only consumed 65µA
of ground current while providing a 50mA output with a dropout voltage of 200mV. The
transient response came in second to [12] but with a little more the 1/100th of the ground current
required by [12]. With these specifications, the proposed capacitor-less LDO voltage regulator
provides a viable solution for low-voltage, power-efficient, SoC applications, while reducing
board real estate, pin count, and overall cost.

建议的拓扑使用微分器来检测输出电压的变化，并为负载瞬态提供快速负反馈路径。微分器回路还兼作交流稳定性
补偿网络，利用米勒电容器极分裂技术的特性。进一步的分析显示了所提出的无电容器 LDO 补偿技术的稳定性范
围。微分器的寄生极点在设计中起着重要作用，对于稳定的系统，它们必须放置在尽可能高的频率上。使用所提出
技术的正确设计的无电容器 LDO 类似于增益带宽积的一阶系统，并在整个输出电流范围内保持不变。

所提出的无电容器 LDO 稳压器是通过 MOSIS 教育服务采用 TSMC 0.35um CMOS 技术设计和制造的。实验结果

表明，所提出的技术可用于制作完全稳定的无电容LDO稳压器。在第 IV 节中与其他作品 [4]、[11] 和 [12] 进行了比
较，其中提出的设计显然具有最佳平衡规范。它仅消耗 65µA 接地电流，同时提供 50mA 输出和 200mV 压差电压
。瞬态响应排在 [12] 之后，但比 [12] 所需的接地电流略多一点。凭借这些规范，所提议的无电容器 LDO 稳压器为
低电压、高能效 SoC 应用提供了可行的解决方案，同时减少了电路板空间、引脚数和总体成本。
 92

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 93

[13] R. W. D. Nickalls, “A new approach to solving the cubic: Cardan’s solution revealed,” The
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 94

APPENDIX A
TEST BOARD FOIL PATTERN

Fig. 74. Top layer of PCB.

Fig. 75. Bottom layer of PCB from top view.

 APPENDIX B
TEST BOARD SCHEMATIC

Fig. 76. Test board schematic diagram.

95
 96

VITA

Name: Robert Jon Milliken

Address: Texas A&M Department of Electrical Engineering, 214 Zachry, TAMU 3128,
College Station, TX 77843.

Email Address: rmilliken@linear.com

Education: B.S., Electrical Engineering, Iowa State University, Ames, IA, Dec. 2002