Lab 02
Lab 02
Lab 02
Parts: -
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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture
G1
out_G3
G3
G4
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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture
module mux_tb;
reg s, d0, d1;
wire y;
mux_2_1 mux_dut(s,d0,d1,y);
initial
begin
s= 0; d0 = 0; d1 =0;
#10 s=0; d0=0; d1=1; // select d0=1
#10 s=0; d0=1; d1=0; // select d0=0
#10 s=1; d0=0; d1=1; // select d1=1
#10 s=1; d0=1; d1=0; // select d1=0
end
endmodule
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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture
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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture
• Bitwise operators
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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture
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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture
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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture
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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture
Step 6: If You want to add any files here. Add the seven-
segment decoder Verilog file And Click Next.
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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture
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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture
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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture
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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture
Step 11: Compile all project after pin assignment, like step 9.
Program the FPGA.
Step 12: load the program to the FPGA.
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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture
Press “Start”
Hint: you may have a problem with the FPGA driver. Check the
“device manager” and update the USB driver.
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