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Elements of Cache Design

The document discusses key elements of cache design including logical vs physical addresses, cache size, mapping functions, replacement algorithms, write policies, line size, and number of caches. Logical addresses are generated by the CPU while physical addresses map to actual memory locations. Cache size must be large enough to improve access time but small enough to be cost-effective. Mapping determines how main memory blocks map to cache lines, and algorithms like direct, associative, and set associative are used. Replacement algorithms like LRU and FIFO determine which block to replace when the cache is full. Write policies impact when data is written to main memory.

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Tran Manh Tuan (K18 HCM)
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3K views

Elements of Cache Design

The document discusses key elements of cache design including logical vs physical addresses, cache size, mapping functions, replacement algorithms, write policies, line size, and number of caches. Logical addresses are generated by the CPU while physical addresses map to actual memory locations. Cache size must be large enough to improve access time but small enough to be cost-effective. Mapping determines how main memory blocks map to cache lines, and algorithms like direct, associative, and set associative are used. Replacement algorithms like LRU and FIFO determine which block to replace when the cache is full. Write policies impact when data is written to main memory.

Uploaded by

Tran Manh Tuan (K18 HCM)
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Elements of cache design

1. Cache adress (Logical and physical address)


Logical address is generated by CPU while a program is running. It is a
virtual address as it does not exist physically. It is used as a refenrence to
access the physical memory location by CPU. The hardware device called
Memory – manangement unit is used for mapping logical address to its
corresponding physical address.

Physical address identifies a physical location of required data in memory.


The user never directly deals with the physical address but can access by
its corresponding logical address, therefor, the logical address must be
mapped to the physical address by MMU before they are used.

Parameter LOGICAL ADDRESS PHYSICAL ADDRESS

Basic generated by CPU location in a memory unit

Address Logical Address Space is set of Physical Address is set of all


Space all logical addresses generated physical addresses mapped to the
Parameter LOGICAL ADDRESS PHYSICAL ADDRESS

by CPU in reference to a
program. corresponding logical addresses.

User can view the logical address User can never view physical
Visibility of a program. address of program.

Generation generated by the CPU Computed by MMU

The user can use the logical


address to access the physical The user can indirectly access
Access address. physical address but not directly.

Editable Logical address can be change. Physical address will not change.

Also called virtual address. real address.

2. Cache size
The size of the cache should be small enough so that the overall average
cost per bit is close to that of main memory alone and large enough so that
the overall average access time is close to that of the cache alone.
3. Mapping function
As there are fewer cache lines than main memory blocks, an algorithm is
needed for mapping main memory blocks into cache lines. Further, a
means is needed for determining which main memory block currently
occupies a cache line. The choice of the mapping function dictates how the
cache is organized. Three techniques can be used: direct, associative, and
set associative.
DIRECT MAPPING: The simplest technique, known as direct mapping,
maps each block of main memory into only one possible cache line.
The direct mapping technique is simple and inexpensive to
implement.
ASSOCIATIVE MAPPING: Associative mapping overcomes the
disadvantage of direct mapping by permitting each main memory
block to be loaded into any line of the cache
SET-ASSOCIATIVE MAPPING: Set-associative mapping is a
compromise that exhibits the strengths of both the direct and
associative approaches. With set-associative mapping, block can be
mapped into any of the lines of set j.
4. Replacement algorithm
Once the cache has been filled, when a new block is brought into the
cache, one of the existing blocks must be replaced. For direct mapping,
there is only one possible line for any particular block, and no choice is
possible. For the associative and set associative techniques, a replacement
algorithm is needed. To achieve high speed, such an algorithm must be
implemented in hardware. Least Recently Used (LRU), Least Frequently
Used(LFU), First In First Out (FIFO) are some replacement algorithms.\
- FIFO (first-in-first-out) is also used as a cache replacement algorithm
and behaves exactly as you would expect. Objects are added to the
queue and are evicted with the same order. Even though it provides a
simple and low-cost method to manage the cache but even the most
used objects are eventually evicted when they're old enough.

- The least recently used (LRU) algorithm is one of the most famous
cache replacement algorithms and for good reason! As the name
suggests, LRU keeps the least recently used objects at the top and
evicts objects that haven't been used in a while if the list reaches the
maximum capacity.So it's simply an ordered list where objects are
moved to the top every time they're accessed; pushing other objects
down. LRU is simple and providers a nice cache-hit rate for lots of
use-cases.

- the least frequently used (LFU) algorithm works similarly to LRU


except it keeps track of how many times an object was accessed
instead of how recently it was accessed. Each object has a counter
that counts how many times it was accessed. When the list reaches
the maximum capacity, objects with the lowest counters are evicted.

5. Write policy
when a block that is resident in the cache is to be replaced, there are
two cases to consider. If the old block in the cache has not been
altered, then it may be overwritten with a new block without first
writing out the old block. If at least one write operation has been
performed on a word in that line of the cache, then main memory
must be updated by writing the line of cache out to the block of
memory before bringing in the new block.
Write through- Ghi thẳng
 Simplest technique
 All write operations are made to main memory as well as to the
cache
 The main disadvantage of this technique is that it generates substantial
(heavy) memory traffic and may create a bottleneck.

 Write back-Ghi ngầm


 Minimizes memory writes
 Updates are made only in the cache
 Portions of main memory are invalid and hence accesses by I/O
modules can be allowed only through the cache
 This makes for complex circuitry and a potential bottleneck

6. Line size
Basically, as the block size increases, more useful data are brought into
the cache. The hit ratio will begin to decrease, however, as the block
becomes even bigger and the probability of using the newly fetched
information becomes less than the probability of reusing the information
that has to be replaced.
Larger line size  More data  Cache hit increases, but expensive and
more data in cache but not used (Normal: 64-128 bytes)

7. Number of cache
When caches were originally introduced, the typical system had a single cache.
More recently, the use of multiple caches has become an important aspect.
There are two design issues surrounding number of caches.

MULTILEVEL CACHES: Most contemporary designs include both on-chip and


external caches. The simplest such organization is known as a two-level cache,
with the internal cache designated as level 1 (L1) and the external cache
designated as level 2 (L2). There can also be 3 or more levels of cache. This
helps in reducing main memory accesses.
UNIFIED VERSUS SPLIT CACHES: Earlier on-chip cache designs consisted of
a single cache used to store references to both data and instructions. This is the
unified approach. More recently, it has become common to split the cache into
two: one dedicated to instructions and one dedicated to data. These two caches
both exist at the same level. This is the split cache. Using a unified cache or a
split cache is another design issue.

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