TL16C550CIPT

TL16C550C
SLLS177I – MARCH 1994 – REVISED MARCH 2021
TL16C550C Asynchronous Communications Element with Autoflow Control
1 Features 2 Description
• Programmable Auto-RTS and Auto-CTS The TL16C550C and the TL16C550CI are
• In Auto-CTSMode, CTS Controls Transmitter functional upgrades of the TL16C550B asynchronous
• In Auto-RTS Mode, RCV FIFO Contents and communications element (ACE), which in turn is a
Threshold Control RTS functional upgrade of the TL16C450. Functionally
• Serial and Modem Control Outputs Drive a RJ11 equivalent to the TL16C450 on power up (character
Cable Directly When Equipment Is on the Same or TL16C450 mode), the TL16C550C and the
Power Drop TL16C550CI, like the TL16C550B, can be placed
in an alternate FIFO mode. This relieves the
• Capable of Running With All Existing TL16C450
CPU of excessive software overhead by buffering
Software
received and transmitted characters. The receiver
• After Reset, All Registers Are Identical to the and transmitter FIFOs store up to 16 bytes including
TL16C450 Register Set three additional bits of error status per byte for the
• Up to 16-MHz Clock Rate for up to 1-Mbaud receiver FIFO. In the FIFO mode, there is a selectable
Operation autoflow control feature that can significantly reduce
• In the TL16C450 Mode, Hold and Shift Registers software overload and increase system efficiency by
Eliminate the Need for Precise Synchronization automatically controlling serial data flow using RTS
Between the CPU and Serial Data output and CTS input signals.
• Programmable Baud Rate Generator Allows
The TL16C550C and TL16C550CI perform serial-
Division of Any Input Reference Clock by 1 to (216
to-parallel conversions on data received from a
−1) and Generates an Internal 16×Clock
peripheral device or modem and parallel-to-serial
• Standard Asynchronous Communication Bits conversion on data received from its CPU. The
(Start, Stop, and Parity) Added to or Deleted From CPU can read the ACE status at any time. The
the Serial Data Stream ACE includes complete modem control capability
• 5-V and 3.3-V Operation and a processor interrupt system that can be
• Independent Receiver Clock Input tailored to minimize software management of the
• Transmit, Receive, Line Status, and Data Set communications link.
Interrupts Independently Controlled
Both the TL16C550C and the TL16C550CI ACE
• Fully Programmable Serial Interface include a programmable baud rate generator capable
Characteristics: of dividing a reference clock by divisors from 1 to
– 5-, 6-, 7-, or 8-Bit Characters 65535 and producing a 16× reference clock for the
– Even-, Odd-, or No-Parity Bit Generation and internal transmitter logic. Provisions are included to
Detection use this 16× clock for the receiver logic. The ACE
– 1-, 1 1/2-, or 2-Stop Bit Generation accommodates a 1-Mbaud serial rate (16-MHz input
– Baud Generation (dc to 1 Mbit/s) clock) so that a bit time is 1 μs and a typical character
• False-Start Bit Detection time is 10 μs (start bit, 8 data bits, stop bit).
• Complete Status Reporting Capabilities Two of the TL16C450 terminal functions on the
• 3-State Output TTL Drive Capabilities for TL16C550C and the TL16C550CI have been changed
Bidirectional Data Bus and Control Bus to TXRDY and RXRDY, which provide signaling to a
• Line Break Generation and Detection DMA controller.
• Internal Diagnostic Capabilities:
– Loopback Controls for Communications Link
Fault Isolation
– Break, Parity, Overrun, and Framing Error
Simulation
• Fully Prioritized Interrupt System Controls
• Modem Control Functions (CTS, RTS, DSR, DTR,
RI, and DCD)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL16C550C
SLLS177I – MARCH 1994 – REVISED MARCH 2021 www.ti.com
Table of Contents
1 Features............................................................................1 5.11 Transmitter Switching Characteristics..................... 11
2 Description.......................................................................1 5.12 Modem Control Switching Characteristics.............. 11
3 Revision History.............................................................. 2 6 Parameter Measurement Information.......................... 12
4 Pin Configuration and Functions...................................3 7 Detailed Description......................................................19
5 Specifications.................................................................. 6 7.1 Autoflow Control (see Figure 7-1) ............................ 19
5.1 Absolute Maximum Ratings........................................ 6 7.2 Auto-RTS (see Figure 7-1) .......................................19
5.2 Recommended Operating Conditions (Low 7.3 Auto-CTS (see Figure 7-1) .......................................19
Voltage - 3.3 nominal)................................................... 6 7.4 Enabling Autoflow Control and Auto-CTS ................19
5.3 Recommended Operating Conditions (Standard 7.5 Auto-CTS and Auto-RTS Functional Timing............. 20
Voltage - 5 V nominal)................................................... 7 7.6 Functional Block Diagram......................................... 21
5.4 Thermal Information....................................................7 7.7 Principles of Operation..............................................21
5.5 Electrical Characteristics (Low Voltage - 3.3 V 8 Application Information................................................ 33
nominal).........................................................................8 9 Device and Documentation Support............................35
5.6 Electrical Characteristics (Standard Voltage - 5 9.1 Receiving Notification of Documentation Updates....35
V nominal)..................................................................... 8 9.2 Support Resources................................................... 35
5.7 System Timing Requirements..................................... 9 9.4 Electrostatic Discharge Caution................................35
5.8 System Switching Characteristics.............................10 9.5 Glossary....................................................................35
5.9 Baud Generator Switching Characteristics............... 10 10 Mechanical, Packaging, and Orderable
5.10 Receiver Switching Characteristics.........................10 Information.................................................................... 36
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (January 2006) to Revision I (March 2021) Page

• Updated the data sheet format........................................................................................................................... 1
• Added the Pin Configuration and Functions section...........................................................................................3
• Added the Thermal Information table. ............................................................................................................... 7
2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TL16C550C

TL16C550C
www.ti.com SLLS177I – MARCH 1994 – REVISED MARCH 2021
4 Pin Configuration and Functions
Figure 4-2. FN Package (Top View)
Figure 4-1. N Package (Top View)
Figure 4-3. PT/PFB Package (Top View)
NC - No internal connection
Table 4-1. Pin Functions
TERMINAL
I/O DESCRIPTION
NAME NO.N(1) NO.FN NO.PT
A0 28 31 28 I Register select. A0 −A2 are used during read and write operations to select the
ACE register to read from or write to. Refer to Table 1 for register addresses
A1 27 30 27
and refer to ADS description.
A2 26 29 26
ADS 25 28 24 I Address strobe. When ADS is active (low), A0, A1, and A2 and CS0, CS1,
and CS2 drive the internal select logic directly; when ADS is high, the register
select and chip select signals are held at the logic levels they were in when the
low-to-high transition of ADS occurred
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3

TL16C550C
Table 4-1. Pin Functions (continued)

TERMINAL
I/O DESCRIPTION
BAUDOUT 15 17 12 O Baud out. BAUDOUT is a 16 x clock signal for the transmitter section of the
ACE. The clock rate is established by the reference oscillator frequency divided
by a divisor specified by the baud generator divisor latches. BAUDOUT may
also be used for the receiver section by tying this output to RCLK.
CS0 12 14 9 I Chip select. When CS0 and CS1 are high and CS2 is low, these three inputs
select the ACE. When any of these inputs are inactive, the ACE remains
CS1 13 15 10
inactive (refer to ADS description).
CS2 14 16 11
CTS 36 40 38 I Clear to send. CTS is a modem status signal. Its condition can be checked
by reading bit 4 (CTS) of the modem status register. Bit 0 (ΔCTS) of the
modem status register indicates that CTS has changed states since the last
read from the modem status register. If the modem status interrupt is enabled
when CTS changes levels and the auto-CTS mode is not enabled, an interrupt
is generated. CTS is also used in the auto-CTS mode to control the transmitter
D0 1 2 43 I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for
D1 2 3 44 data, control, and status information between the ACE and the CPU.
D2 3 4 45
D3 4 5 46
D4 5 6 47
D5 6 7 2
D6 7 8 3
D7 8 9 4
DCD 38 42 40 I Data carrier detect. DCD is a modem status signal. Its condition can be checked
by reading bit 7 (DCD) of the modem status register. Bit 3 (ΔDCD) of the
modem status register indicates that DCD has changed states since the last
read from the modem status register. If the modem status interrupt is enabled
when DCD changes levels, an interrupt is generated
DDIS 23 26 22 O Driver disable. DDIS is active (high) when the CPU is not reading data. When
active, DDIS can disable an external transceiver.
DSR 37 41 39 I Data set ready. DSR is a modem status signal. Its condition can be checked by
reading bit 5 (DSR) of the modem status register. Bit 1 (ΔDSR) of the modem
status register indicates DSR has changed levels since the last read from the
modem status register. If the modem status interrupt is enabled when DSR
changes levels, an interrupt is generated.
DTR 33 37 33 O Data terminal ready. When active (low), DTR informs a modem or data set that
the ACE is ready to establish comunication. DTR is placed in the active level
by setting the DTR bit of the modem control register. DTR is placed in the
inactive level either as a result of a master reset, during loop mode operation, or
clearing the DTR bit.
INTRPT 30 33 30 O Interrupt.When active (high), INTRPT informs the CPU that the ACE has an
interrupt to be serviced. Four conditions that cause an interrupt to be issued
are: a receiver error, received data that is available or timed out (FIFO mode
only), an empty transmitter holding register, or an enabled modem status
interrupt. INTRPT is reset (deactivated) either when the interrupt is serviced
or as a result of a master reset.
MR 35 39 35 I Master reset. When active (high), MR clears most ACE registers and sets the
levels of various output signals (refer to Table 2).
OUT1 34 38 34 O Outputs 1 and 2. These are user-designated output terminals that are set to
the active (low) level by setting respective modem control register (MCR) bits
OUT2 31 35 31
(OUT1 and OUT2). OUT1 and OUT2 are set to inactive the (high) level as a
result of master reset, during loop mode operations, or by clearing bit 2 (OUT1)
or bit 3 (OUT2) of the MCR.
RCLK 9 10 5 I Receiver clock. RCLK is the 16 x baud rate clock for the receiver section of the
ACE.

TL16C550C
Table 4-1. Pin Functions (continued)

TERMINAL
I/O DESCRIPTION
RD1 21 24 19 I Read inputs. When either RD1 or RD2 is active (low or high respectively) while
the ACE is selected, the CPU is allowed to read status information or data from
RD2 22 25 20
a selected ACE register. Only one of these inputs is required for the transfer of
data during a read operation; the other input should be tied to its inactive level
(i.e., RD2 tied low or RD1 tied high
RI 39 43 41 I Ring indicator. RI is a modem status signal. Its condition can be checked by
reading bit 6 (RI) of the modem status register. Bit 2 (TERI) of the modem
status register indicates that RI has transitioned from a low to a high level since
the last read from the modem status register. If the modem status interrupt is
enabled when this transition occurs, an interrupt is generated
RTS 32 36 32 O Request to send. When active, RTS informs the modem or data set that the
ACE is ready to receive data. RTS is set to the active level by setting the RTS
modem control register bit and is set to the inactive (high) level either as a
result of a master reset or during loop mode operations or by clearing bit 1
(RTS) ofthe MCR. In the auto-RTS mode, RTS is set to the inactive level by the
receiver threshold control logic
RXRDY 29 32 29 O Receiver ready. Receiver direct memory access (DMA) signalling is available
with RXRDY. When operating in the FIFO mode, one of two types of DMA
signalling can be selected using the FIFO control register bit 3 (FCR3). When
operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0
supports single-transfer DMA in which a transfer is made between CPU bus
cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made
continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0
= 0 or FCR0 =1, FCR3 = 0), when there is at least one character in the receiver
FIFO or receiver holding register, RXRDY is active (low). When RXRDY has
been active but there are no characters in the FIFO or holding register, RXRDY
goes inactive (high).In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger
level or the time-out has been reached, RXRDY goes active (low); when it has
been active but there are no more characters in the FIFO or holding register, it
goes inactive (high).
SIN 10 11 7 I Serial data input. SIN is serial data input from a connected communications
device.
SOUT 11 13 8 O Serial data output. SOUT is composite serial data output to a connected
communication device. SOUT is set to the marking (high) level as a result of
master reset.
TXRDY 24 27 23 O Transmitter ready. Transmitter DMA signalling is available with TXRDY. When
operating in the FIFO mode, one of two types of DMA signalling can be selected
using FCR3. When operating in the TL16C450 mode, only DMA mode 0 is
allowed. Mode 0 supports single-transfer DMA in which a transfer is made
between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple
transfers are made continuously until the transmit FIFO has been filled.
VCC 40 44 42 5-V supply voltage
VSS 20 22 18 Supply common
WR1 18 20 16 I Write inputs. When either WR1 or WR2 is active (low or high respectively) and
while the ACE is selected,the CPU is allowed to write control words or data into
WR2 19 21 17
a selected ACE register. Only one of these inputs is required to transfer data
during a write operation; the other input should be tied to its inactive level (i.e.,
WR2 tied low or WR1 tied high).
XIN 16 18 14 I/O External clock. XIN and XOUT connect the ACE to the main timing reference
(clock or crystal).
XOUT 17 19 15
(1) The N package is Not Recommended for New Designs.

TL16C550C
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range(3) –0.5 7 V
VI Input voltage range at any input –0.5 7 V
VO Output voltage range –0.5 7 V
TL16C550C 0 70 °C
TA Operating free-air temperature range
TL16C550CI –40 85 °C
Tstg Storage temperature –65 150 °C
TC Case temperature for 10 seconds FN package 260 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds N(1) (2) or PT package 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The N package is Not Recommended for New Designs.
(3) All voltage values are with respect to VSS.
5.2 Recommended Operating Conditions (Low Voltage - 3.3 nominal)

MIN NOM MAX UNIT
Supply voltage, VCC 3 3.3 3.6 V
Input voltage, VI 0 VCC V
High-level input voltage, VIH (1) 0.7 VCC V
Low-level input voltage, VIL (1) 0.3 VCC V
Output voltage, VO (2) 0 VCC V
High-level output current, IOH (all outputs) 1.8 mA
Low-level output current, IOL (all outputs) 3.2 mA
Input capacitance 1 pF
Operating free-air temperature, TA 0 25 70 °C
Junction temperature range, TJ (3) 0 25 115 °C
Oscillator/clock speed 14.9 MHz
(1) Meets TTL levels, VIHmin = 2 V and VILmax = 0.8 V on nonhysteresis inputs.
(2) Applies for external output buffers.
(3) These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is
responsible for verifying junction temperature.

TL16C550C
5.3 Recommended Operating Conditions (Standard Voltage - 5 V nominal)

MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
Input voltage, VI 0 VCC V
Except XIN 2
High-level input voltage, VIH V
XIN 0.7 VCC
Except XIN 0.8
Low-level input voltage, VIL V
XIN 0.3 VCC
Output voltage, VO (1) 0 VCC V
High-level output current, IOH (all outputs) 4 mA
Low-level output current, IOL (all outputs) 4 mA
Input capacitance 1 pF
Operating free-air temperature, TA 0 25 70 °C
Junction temperature range, TJ (2) 0 25 115 °C
Oscillator/clock speed 16 MHz
(1) Applies for external output buffers.

(2) These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is
responsible for verifying junction temperature.
5.4 Thermal Information

TL16C550C TL16C550C TL16C550C
THERMAL METRIC(1) PT PFB FN UNIT

48 PINS 48 PINS 44 PINS
RθJA Junction-to-ambient thermal resistance 72.5 73.6 62.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 31.0 26.3 37.2 °C/W
RθJB Junction-to-board thermal resistance 36.2 37.2 39.1 °C/W
ψJT Junction-to-top characterization parameter 4.4 1.9 19.4 °C/W
ψJB Junction-to-board characterization parameter 36.0 37.0 38.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

TL16C550C
5.5 Electrical Characteristics (Low Voltage - 3.3 V nominal)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VOH (2) High-level output voltage IOH = − 1 mA 2.4 V
VOL (2) Low-level output voltage IOL = 1.6 mA 0.5 V
VCC = 3.6 V, VSS = 0,
II Input current 10 μA
VI = 0 to 3.6 V, All other terminals floating
VCC = 3.6 V,
High-impedance-state output VSS = 0,
IOZ VO = 0 to 3.6 V ± 20 μA
current
Chip selected in write mode or chip deselect
VCC = 3.6 V, TA = 25°C
SIN, DSR, DCD, CTS, and XTAL1 at 4 MHz,
ICC Supply current RI at 2V, Baud rate = 50 kbit/s 8 mA
All other inputs at 0.8 V,
No load on outputs,
Ci(CLK) Clock input capacitance VCC= 0, VSS = 0, 15 20 pF
Co(CLK) Clock output capacitance f =1 MHz, TA = 25°C 20 30 pF
Ci Input capacitance All other terminals grounded 6 10 pF
Co Output capacitance 10 20 pF
(1) All typical values are at VCC = 3.3 V and TA = 25°C.

(2) These parameters apply for all outputs except XOUT.
5.6 Electrical Characteristics (Standard Voltage - 5 V nominal)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VOH (2) High-level output voltage IOH = − 1 mA 2.4 V
VOL (2) Low-level output voltage IOL = 1.6 mA 0.4 V
VCC = 5.25 V, VSS = 0,
II Input current 10 μA
VI = 0 to 5.25 V, All other terminals floating
VCC = 5.25 V, VSS = 0,

High-impedance-state output
IOZ VO = 0 to 5.25 V, ± 20 μA
current
Chip selected in write mode or chip deselect
VCC = 5.25 V, TA = 25°C
SIN, DSR, DCD, CTS, and XTAL1 at 4 MHz,
ICC Supply current RI at 2V, Baud rate = 50 kbit/s 10 mA
All other inputs at0.8 V,
No load on outputs,
Ci(CLK) Clock input capacitance VCC= 0, 15 20 pF
Co(CLK) Clock output capacitance f =1 MHz, VSS = 0, 20 30 pF
Ci Input capacitance All other terminals TA = 25°C, 6 10 pF
Co Output capacitance grounded 10 20 pF
(1) All typical values are at VCC = 5 V and TA = 25°C.

(2) These parameters apply for all outputs except XOUT.

TL16C550C
5.7 System Timing Requirements

over recommended ranges of supply voltage and operating free-air temperature
ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
tcR Cycle time, read (tw7 + td8 + td9) RC 87 ns
tcW Cycle time, write (tw6 + td5 + td6) WC 87 ns
tw1 Pulse duration, clock high tXH f = 16 MHz Max,
5 25 ns
tw2 Pulse duration, clock low tXL VCC = 5 V
tw5 Pulse duration, ADS low tADS 6.7 9 ns

tw6 Pulse duration, WR tWR 6 40 ns
tw7 Pulse duration, RD tRD 7 40 ns
tw8 Pulse duration, MR tMR 1 ns
tsu1 Setup time, address valid before ADS↑ tAS
6.7 8 ns
tsu2 Setup time, CS valid before ADS↑ tCS
tsu3 Setup time, data valid before WR1↑ or WR2↓ tDS 6 15 ns
tsu4 Setup time, CTS↑ before midpoint of stop bit 17 10 ns
th1 Hold time, address low after ADS↑ tAH
6.7 0 ns
th2 Hold time, CS valid after ADS↑ tCH
th3 Hold time, CS valid after WR1↑ or WR2↓ tWCS
6 10 ns
th4 Hold time, address valid after WR1↑ or WR2↓ tWA
th5 Hold time, data valid after WR1↑ or WR2↓ tDH 6 5 ns
th6 Hold time, chip select valid after RD1↑or RD2↓ tRCS 7 10 ns
th7 Hold time, address valid after RD1↑ or RD2↓ tRA 7 20 ns
td4 (1) Delay time, CS valid before WR1↓ or WR2↑ tCSW
6 7 ns
td5 (1) Delay time, address valid before WR1↓ or WR2↑ tAW
td6 (1) Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ tWC 6 40 ns
td7 (1) Delay time, CS valid to RD1↓ or RD2↑ tCSR
7 7 ns
td8 (1) Delay time, address valid to RD1↓ or RD2↑ tAR
td9 Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ tRC 7 40 ns
td10 Delay time, RD1↓ or RD2↑ to data valid tRVD 7 CL = 75 pF 45 ns
td11 Delay time, RD1↑ or RD2↓ to floating data tHZ 7 CL = 75 pF 20 ns
(1) Only applies when ADS is low.

TL16C550C
5.8 System Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature(1)
PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
tdis(R) Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ tRDD 7 CL = 75 pF 20 ns
(1) Charge and discharge times are determined by VOL, VOH, and external loading.
5.9 Baud Generator Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature, CL = 75 pF
tw3 Pulse duration, BAUDOUT low tLW 5 f = 16 MHz, CLK ÷ 2,
50 ns
tw4 Pulse duration, BAUDOUT high tHW 5 VCC = 5 V
td1 Delay time, XIN↑ to BAUDOUT↑ tBLD 5 45 ns

td2 Delay time, XIN↑↓ to BAUDOUT↓ tBHD 5 45 ns
5.10 Receiver Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature(1)
td12 Delay time, RCLK to sample tSCD 8 10 ns
Delay time, stop to set INTRPT or read RBR to RCLK
td13 tSINT 8, 9, 10, 11, 12 1
LSI interrupt or stop to RXRDY↓ cycle
td14 Delay time, read RBR/LSR to reset INTRPT tRINT 8, 9, 10, 11, 12 CL = 75 pF 70 ns
(1) In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register).

TL16C550C
5.11 Transmitter Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature
baudout
td15 Delay time, initial write to transmit start tIRS 13 8 24
cycles
baudout
td16 Delay time, start to INTRPT tSTI 13 8 10
cycles
td17 Delay time, WR (WR THR) to reset INTRPT tHR 13 CL = 75 pF 50 ns
baudout
td18 Delay time, initial write to INTRPT (THRE(1)) tSI 13 16 34
cycles
Delay time, read IIR(1) to reset INTRPT
td19 tIR 13 CL = 75 pF 35 ns
(THRE(1))
td20 Delay time, write to TXRDY inactive tWXI 14, 15 CL = 75 pF 35 ns
baudout
t21 Delay time, start to TXRDY active tSXA 14, 15 CL = 75 pF 9
cycles
(1) THRE = transmitter holding register empty; IIR = interrupt identification register.
5.12 Modem Control Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature, CL = 75 pF
PARAMETER ALT. SYMBOL FIGURE MIN MAX UNIT
td22 Delay time, WR MCR to output tMDO 16 50 ns
td23 Delay time, modem interrupt to set INTRPT tSIM 16 35 ns
td24 Delay time, RD MSR to reset INTRPT tRIM 16 40 ns
baudout
td25 Delay time, CTS low to SOUT↓ 17 24
cycles
baudout
td26 Delay time, RCV threshold byte to RTS↑ 18 2
cycles
baudout
td27 Delay time, read of last byte in receive FIFO to RTS↓ 18 2
cycles
baudout
td28 Delay time, first data bit of 16th character to RTS↑ 19 2
cycles
baudout
td29 Delay time, RBRRD low to RTS↓ 19 2
cycles

TL16C550C
6 Parameter Measurement Information
Figure 6-1. Baud Generator Timing Waveforms

TL16C550C
Figure 6-2. Write Cycle Timing Waveforms

TL16C550C
Figure 6-3. Read Cycle Timing Waveforms

TL16C550C
Figure 6-4. Receiver Timing Waveforms
Figure 6-5. Receive FIFO First Byte (Sets DR Bit) Waveforms

TL16C550C
Figure 6-6. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms
Figure 6-7. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
Figure 6-8. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)

TL16C550C
Figure 6-9. Transmitter Timing Waveforms
Figure 6-10. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
Figure 6-11. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)

TL16C550C
Figure 6-12. Modem Control Timing Waveforms
Figure 6-13. CTS and SOUT Autoflow Control Timing (Start and Stop) Waveforms
Figure 6-14. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms
Figure 6-15. Auto-RTS Timing for RCV Threshold of 14 Waveforms

TL16C550C
7 Detailed Description
7.1 Autoflow Control (see Figure 7-1)
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before
the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data
and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless
the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a
TLC16C550C with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds
the receiver FIFO read latency.
Figure 7-1. Autoflow Control (Auto-RTS and Auto-CTS) Example
7.2 Auto-RTS (see Figure 7-1)

Auto-RTS data flow control originates in the receiver timing and control block (see Section 7.6) and is linked to
the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of 1, 4, or 8
(see Figure 7-3), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an additional
byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it may
not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is automatically
reasserted once the RCV FIFO is emptied by reading the receiver buffer register.
When the trigger level is 14 (see Figure 4), RTS is deasserted after the first data bit of the 16th character is
present on the SIN line. RTS is reasserted when the RCV FIFO has at least one available byte space.
7.3 Auto-CTS (see Figure 7-1)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the
next byte. To stop the transmitter from sending the following byte, CTS must be released before the middle
of the last stop bit that is currently being sent (see Figure 7-2). The auto-CTS function reduces interrupts to
the host system. When flow control is enabled, CTS level changes do not trigger host interrupts because the
device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in
the transmit FIFO and a receiver overrun error may result
7.4 Enabling Autoflow Control and Auto-CTS
Autoflowcontrol is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to a 1.
Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem control
register should be cleared (this assumes that a control signal is driving CTS).

TL16C550C
7.5 Auto-CTS and Auto-RTS Functional Timing
Figure 7-2. CTS Functional Timing Waveforms
NOTES:
1. When CTS is low, the transmitter keeps sending serial data out.
2. If CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the
current byte but it does not send the next byte.
3. When CTS goes from high to low, the transmitter begins sending data again.
The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figure 7-3 and Figure
7-4.
Figure 7-3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes
NOTES:
1. N = RCV FIFO trigger level (1, 4, or 8 bytes)
2. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding
auto-RTS section.
Figure 7-4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes
NOTES:
1. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full
after finishing the sixteenth byte.
2. RTS is asserted again when there is at least one byte of space available and no incoming byte is in
processing or there is more than one byte of space available.
3. When the receive FIFO is full, the first receive buffer register read reasserts RTS.

TL16C550C
7.6 Functional Block Diagram
7.7 Principles of Operation

Table 7-1. Register Selection
DLAB(1) A2 A1 A0 REGISTER
0 L L L Receiver buffer (read), transmitter holding register (write)
0 L L H Interrupt enable register
X L H L Interrupt identification register (read only)
X L H L FIFO control register (write)
X L H H Line control register
X H L L Modem control register
X H L H Line status register

TL16C550C
Table 7-1. Register Selection (continued)

DLAB(1) A2 A1 A0 REGISTER
X H H L Modem status register
X H H H Scratch register
1 L L L Divisor latch (LSB)
1 L L H Divisor latch (MSB)
(1) The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled by writing to this
bit location (see Table 4).
Table 7-2. ACE Reset Functions

REGISTER/SIGNAL RESET CONTROL RESET STATE
Interrupt enable register Master reset All bits cleared (0 − 3 forced and 4 − 7 permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and
Interrupt identification register Master reset
bits 4 − 5 are permanently cleared
FIFO control register Master reset All bits cleared
Line control register Master reset All bits cleared
Modem control register Master reset All bits cleared (6 − 7 permanent)
Line status register Master reset Bits 5 and 6 are set; all other bits are cleared
Modem status register Master reset Bits 0 − 3 are cleared; bits 4 − 7 are input signals
SOUT Master reset High
INTRPT (receiver error flag) Read LSR/MR Low
INTRPT (received data available) Read RBR/MR Low
INTRPT (transmitter holding register empty) Read IR/write THR/MR Low
INTRPT (modem status changes) Read MSR/MR Low
OUT2 Master reset High
RTS Master reset High
DTR Master reset High
OUT1 Master reset High
Scratch register Master reset No effect
Divisor latch (LSB and MSB) registers Master reset No effect
Receiver buffer register Master reset No effect
Transmitter holding register Master reset No effect
RCVR FIFO MR/FCR1 −FCR0/ΔFCR0 All bits cleared
XMIT FIFO MR/FCR2 −FCR0/ΔFCR0 All bits cleared

TL16C550C
7.7.1 Accessible Registers

The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 7-2. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 7-3.
Table 7-3. Summary of Accessible Registers
REGISTER ADDRESS
0 DLAB = 0 0 DLAB = 0 1 DLAB = 0 2 2 3 4 5 6 7 0 DLAB = 1 1 DLAB = 1
Receiver Transmitter Interrupt FIFO
BIT Buffer Holding Interrupt Ident. Control Line Modem Line Modem Divisor
NO. Scratch Latch
Register Register Enable Register Register Control Control Status Status Latch
Register (MSB)
(Read (Write Register (Read (Write Register Register Register Register (LSB)
Only) Only) Only) Only)
RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM
Enable
Word
Received Data Delta
0 if Length Data
Data FIFO Terminal Clear to
0 Data Bit 0(1) Data Bit 0 Interrupt Select Ready Bit 0 Bit 0 Bit 8
Available Enable Ready Send
Pending Bit 0 (DR)
Interrupt (DTR) (ΔCTS)
(WLS0)
(ERBI)
Enable
Transmitter Word
Delta
Holding Receiver Length Request Overrun
Interrupt Data Set
1 Data Bit 1 Data Bit 1 Register FIFO Select to Send Error Bit 1 Bit 1 Bit 9
ID Bit 1 Ready
Empty Reset Bit 1 (RTS) (OE)
(ΔDSR)
Interrupt (WLS1)
(ETBEI)
Enable Trailing
Number
Receiver Transmitt Parity Edge
Interrupt of Stop
2 Data Bit 2 Data Bit 2 Line Status er FIFO OUT1 Error Ring Bit 2 Bit 2 Bit 10
ID Bit 2 Bits
Interrupt Reset (PE) Indicator
(STB)
(ELSI) (TERI)
Enable Delta
Modem DMA Parity Framing Data
Interrupt
3 Data Bit 3 Data Bit 3 Status Mode Enable OUT2 Error Carrier Bit 3 Bit 3 Bit 11
ID Bit 3(2)
Interrupt Select (PEN) (FE) Detect
(EDSSI) (ΔDCD)
Even
Break Clear to
Parity
4 Data Bit 4 Data Bit 4 0 0 Reserved Loop Interrupt Send Bit 4 Bit 4 Bit 12
Select
(BI) (CTS)
(EPS)
Autoflow Transmitt
Control er Data Set
Stick
5 Data Bit 5 Data Bit 5 0 0 Reserved Enable Holding Ready Bit 5 Bit 5 Bit 13
Parity
(AFE) Register (DSR)
(THRE)
FIFOs Receiver Transmitt Ring
Break
6 Data Bit 6 Data Bit 6 0 Enabled Trigger 0 er Empty Indicator Bit 6 Bit 6 Bit 14
(2) Control
(LSB) (TEMT) (RI)
Divisor
Data
FIFOs Receiver Latch Error in
Carrier
7 Data Bit 7 Data Bit 7 0 Enabled Trigger Access 0 RCVR Bit 7 Bit 7 Bit 15
(2) Detect
(MSB) Bit FIFO(2)
(DCD)
(DLAB)
(1) Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
(2) These bits are always 0 in the TL16C450 mode.

TL16C550C
7.7.2 FIFO Control Register (FCR)

The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.
• Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits
are written to or they are not programmed. Changing this bit clears the FIFOs.
• Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self clearing.
• Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self clearing.
• Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.
• Bits 4 and 5: These two bits are reserved for future use.
• Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 7-4).
Table 7-4. Receiver FIFO Trigger
Level
RECEIVER FIFO
BIT 7 BIT 6 TRIGGER LEVEL
(BYTES)
0 0 01
0 1 04
1 0 08
1 1 14
7.7.3 FIFO Interrupt Mode Operation

When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt
occurs as follows:
1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the
interrupt, it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04)
interrupt.
4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO.
It is cleared when the FIFO is empty.
When the receiver FIFO and receiver interrupts are enabled:
1. • At least one character is in the FIFO.
• The most recent serial character was received more than four continuous character times ago (if two stop
bits are programmed, the second one is included in this time delay).
• The most recent microprocessor read of the FIFO has occurred more than four continuous character
times before. This causes a maximum character received command to interrupt an issued delay of 160
ms at a 300 baud rate with a 12-bit character.
2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional to
the baud rate).
3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor reads
one character from the receiver FIFO.
4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received or
after the microprocessor reads the receiver FIFO.
When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as
follows:

TL16C550C
1. The transmitter holding register empty interrupt [IIR (3 −0) = 2] occurs when the transmit FIFO is empty. It is
cleared [IIR (3 −0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit FIFO
while servicing this interrupt) or the IIR is read.
2. The transmitter holding register empty interrupt is delayed one character time minus the last stop bit time
when there have not been at least two bytes in the transmitter FIFO at the same time since the last time that
the FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled.
7.7.4 FIFO Polled Mode Operation
With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts
the ACE in the FIFO polled mode of operation. Since the receiver and transmitter are controlled separately,
either one or both can be in the polled mode of operation.
In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously:
• LSR0 is set as long as there is one byte in the receiver FIFO.
• LSR1 − LSR 4 specify which error(s) have occurred. Character error status is handled the same way as when
in the interrupt mode; the IIR is not affected since IER2 = 0.
• LSR5 indicates when the THR is empty.
• LSR6 indicates that both the THR and TSR are empty.
• LSR7 indicates whether there are any errors in the receiver FIFO.
There is no trigger level reached or time-out condition indicated in the FIFO polled mode. However, the receiver
and transmitter FIFOs are still fully capable of holding characters.
7.7.5 Interrupt Enable Register (IER)
The IER enables each of the five types of interrupts (refer to Table 7-5) and enables INTRPT in response to an
interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of
this register are summarized in Table 7-3 and are described in the following bullets.
• Bit 0: When set, this bit enables the received data available interrupt.
• Bit 1: When set, this bit enables the THRE interrupt.
• Bit 2: When set, this bit enables the receiver line status interrupt.
• Bit 3: When set, this bit enables the modem status interrupt.
• Bits 4 through 7: These bits are not used (always cleared).
7.7.6 Interrupt Identification Register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most popular microprocessors.
The ACE provides four prioritized levels of interrupts:
• Priority 1 − Receiver line status (highest priority).
• Priority 2 − Receiver data ready or receiver character time-out.
• Priority 3 − Transmitter holding register empty.
• Priority 4 − Modem status (lowest priority).
When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt
in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 7-3 and
described in Table 7-5. Detail on each bit is as follows:
• Bit 0: This bit is used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared, an
interrupt is pending If bit 0 is set, no interrupt is pending.
• Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 3.
• Bit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a
time-out interrupt is pending.
• Bits 4 and 5: These two bits are not used (always cleared).

TL16C550C
• Bits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO control
register is set.
Table 7-5. Interrupt Control Functions
INTERRUPT IDENTIFICATION
REGISTER PRIORITY
INTERRUPT TYPE INTERRUPT SOURCE INTERRUPT RESET METHOD
LEVEL
BIT 3 BIT 2 BIT 1 BIT 0
0 0 0 1 None None None None
Overrun error, parity error,
0 1 1 0 1 Receiver line status Read the line status register
framing error, or break interrupt
Receiver data available in the
Received data
0 1 0 0 2 TL16C450 mode or trigger level Read the receiver buffer register
available
reached in the FIFO mode
No characters have been
removed from or input to the
Character time-out receiver FIFO during the last four
1 1 0 0 2 Read the receiver buffer register
indication character times, and there is at
least one character in it during
this time
Read the interrupt identification
Transmitter holding Transmitter holding register register(if source of interrupt)
0 0 1 0 3
register empty empty or writing into the transmitter
holding register
Clear to send, data set ready,
0 0 0 0 4 Modem status ring indicator, or data carrier Read the modem status register
detect

TL16C550C
7.7.7 Line Control Register (LCR)

The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 7-3 and described in the following bulleted list.
• Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. These
bits are encoded as shown in Table 7-6.
Table 7-6. Serial Character Word
Length
BIT 1 BIT 0 WORD LENGTH
0 0 5 bits
0 1 6 bits
1 0 7 bits
1 1 8 bits
• Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When bit
2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated is
dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit regardless
of the number of stop bits selected. The number of stop bits generated in relation to word length and bit 2 are
shown in Table 7-7.
Table 7-7. Number of Stop Bits Generated
WORD LENGTH
NUMBER OF STOP
BIT 2 SELECTED BY BITS
BITS GENERATED
1 AND 2
0 Any word length 1
1 5 bits 1 1/2
1 6 bits 2
1 7 bits 2
1 8 bits 2
• Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is
cleared, no parity is generated or checked.
• Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set even parity (an
even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is cleared,
odd parity (an odd number of logic 1s) is selected.
• Bit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. If bit 5
is cleared, stick parity is disabled.
• Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT is
forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no affect
on the transmitter logic; it only effects SOUT.
• Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the baud
generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver buffer, the
THR, or the IER.

TL16C550C
7.7.8 Line Status Register (LSR)

1The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are summarized in Table 7-3 and described in the following bulleted list.
• Bit 0: This bit is the data ready (DR) indicator for the receiver. DR is set whenever a complete incoming
character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the
data in the RBR or the FIFO.
• Bit 12:This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in the
RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every time
the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the trigger
level, an overrun error occurs only after the FIFO is full and the next character has been completely received
in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character in the shift
register is overwritten, but it is not transferred to the FIFO.
• Bit 2 (see Footnote 2): This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity
of the received data character does not match the parity selected in the LCR (bit 4). PE is cleared every
time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular
character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at
the top of the FIFO.
• Bit 3 (see Footnote 2): This bit is the framing error (FE) indicator. When FE is set, it indicates that the
received character didnot have a valid (set) stop bit. FE is cleared every time the CPU reads the contents
of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it
applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. The ACE
tries to resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to
the next start bit. The ACE samples this start bit twice and then accepts the input data.
• Bit 4 (see Footnote 2): This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the
received data input was held low for longer than a full-word transmission time. A full-word transmission time
is defined as the total time to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU
reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the
FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the
FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character transfer is
enabled after SIN goes to the marking state for at least two RCLK samples and then receives the next valid
start bit.
• Bit 5: This bit is the THRE indicator. THRE is set when the THR is empty, indicating that the ACE is ready to
accept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated. THRE
is set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the loading
of the THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared when
at least one byte is written to the transmit FIFO.
• Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are
bothempty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode,
TEMT is set when the transmitter FIFO and shift register are both empty.
• Bit 7: In the TL16C550C mode, this bit is always cleared. In the TL16C450 mode, this bit is always cleared. In
the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is cleared
when the microprocessor reads the LSR and there are no subsequent errors in the FIFO.
1 The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing
environment.
2 Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.

TL16C550C
7.7.9 Modem Control Register (MCR)

The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 7-3 and are described in the following
bulleted list.
• Bit 0: This bit (DTR) controls the DTR output
• Bit 1: This bit (RTS) controls the RTS output
• Bit 2: This bit (OUT1) controls OUT1, a user-designated output signal.
• Bit 3: This bit (OUT2) controls OUT2, a user-designated output signal.
When any of bits 0 through 3 are set, the associated output is forced low. When any of these bits are cleared,
the associated output is forced high.
• Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP is set,
the following occurs:
• – The transmitter SOUT is set high.
– The receiver SIN is disconnected.
– The output of the TSR is looped back into the receiver shift register input.
– The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.
– The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
– The four modem control outputs are forced to the inactive (high) levels.
• Bit 5: This bit (AFE) is the autoflow control enable. When set, the autoflow control as described in the detailed
description is enabled.
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify the
transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational. The
modem control interrupts are also operational, but the modem control interrupt’s sources are now the lower four
bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the IER.
The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 7-8.
Table 7-8. ACE Flow Configuration
MCR BIT 5 (AFE) MCR BIT 1 (RTS) ACE FLOW CONFIGURATION
1 1 Auto-RTS and auto-CTS enabled (autoflow control enabled)
1 0 Auto-CTS only enabled
0 X Auto-RTS and auto-CTS disabled

TL16C550C
7.7.10 Modem Status Register (MSR)

The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information; when a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 7-3 and are
described in the following bulleted list.
• Bit 0: This bit is the change in clear-to-send (ΔCTS) indicator. ΔCTS indicates that the CTS input has
changed state since the last time it was read by the CPU. When ΔCTS is set (autoflow control is not enabled
and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is
enabled (ΔCTS is cleared), no interrupt is generated.
• Bit 1: This bit is the change in data set ready (ΔDSR) indicator. ΔDSR indicates that the DSR input has
changed state since the last time it was read by the CPU. When ΔDSR isset and the modem status interrupt
is enabled, a modem status interrupt is generated.
• Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that the RI input to the
chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, a
modem status interrupt is generated.
• Bit 3: This bit is the change in data carrier detect (ΔDCD) indicator. ΔDCD indicates that the DCD input to the
chip has changed state since the last time it was read by the CPU. When ΔDCD is set and the modem status
interrupt is enabled, a modem status interrupt is generated.
• Bit 4: This bit is the complement of the clear-to-send (CTS) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1 (RTS).
• Bit 5: This bit is the complement of the data set ready (DSR) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR).
• Bit 6: This bit is the complement of the ring indicator (RI) input. When the ACE is in the diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1).
• Bit 7: This bit is the complement of the data carrier detect (DCD) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).

TL16C550C
7.7.11 Programming Baud Generator

The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHz
and divides it by a divisor in the range between 1 and (216−1).The output frequency of the baud generator is
sixteen times (16 x) the baud rate. The formula for the divisor is:
divisor = XIN frequency input ÷ (desired baud rate x 16) (1)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Table 7-9 and Table 7-10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and
3.072 MHz respectively. For baud rates of 38.4 kbits/s and below, the error obtained is very small. The accuracy
of the selected baud rate is dependent on the selected crystal frequency (refer to Figure 7-5 for examples of
typical clock circuits).
Table 7-9. Baud Rates Using a 1.8432-MHz Crystal
PERCENT ERROR DIFFERENCE BETWEEN
DESIRED BAUD RATE DIVISOR USED TO GENERATE 16 x CLOCK
DESIRED AND ACTUAL
50 2304
75 1536
110 1047 0.026
134.5 857 0.058
150 768
300 384
600 192
1200 96
1800 64
2000 58 0.69
2400 48
3600 32
4800 24
7200 16
9600 12
19200 6
38400 3
56000 2 2.86
Table 7-10. Baud Rates Using a 3.072-MHz Crystal

DESIRED AND ACTUAL
50 3840
75 2560
110 1745 0.026
134.5 1428 0.034
150 1280
300 640
600 320
1200 160
1800 107 0.312
2000 96
2400 80
3600 53 0.628
4800 40

TL16C550C
Table 7-10. Baud Rates Using a 3.072-MHz Crystal (continued)

DESIRED AND ACTUAL
7200 27 1.23
9600 20
19200 10
38400 5
Figure 7-5. Typical Clock Circuits
Table 7-11. TYPICAL CRYSTAL OSCILLATOR

NETWORK
CRYSTAL RP RX2 C1 C2
3.072 MHz 1 MW 1.5 kW 10 − 30 pF 40 − 60 pF
1.8432 MHz 1 MW 1.5 kW 10 − 30 pF 40 − 60 pF
7.7.12 Receiver Buffet Register (RBR)

The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is supplied by the 16 x receiver clock (RCLK). Receiver section control is a function of the ACE line
control register.
The ACE RSR receives serial data from SIN. The RSR then concatenates the data and moves it into the RBR
FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt is
enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR. In
the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
7.7.13 Scratch Register
The scratch register is an 8-bit register that is intended for the programmer’s use as a scratchpad in the sense
that it temporarily holds the programmer’s data without affecting any other ACE operation.
7.7.14 Transmitter Holding Register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is supplied by BAUDOUT. Transmitter section control is a function of the ACE line control
register.
The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the
TSR. The TSR serializes the data and outputs it at SOUT. In the TL16C450 mode, if the THR is empty and
the transmitter holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO control register.

TL16C550C
8 Application Information
Figure 8-1. Basic TL16C550C Configuration
Figure 8-2. Typical Interface for a High Capacity Data Bus

TL16C550C
Figure 8-3. Typical TL16C550C Connection to a CPU
(2)

TL16C550C
9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

TL16C550C
10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 27-Apr-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TL16C550CFNR ACTIVE PLCC FN 44 500 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TL16C550CFN
TL16C550CFNRG4 ACTIVE PLCC FN 44 500 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TL16C550CFN
TL16C550CIFNR ACTIVE PLCC FN 44 500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TL16C550CIFN
TL16C550CIFNRG4 ACTIVE PLCC FN 44 500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TL16C550CIFN
TL16C550CIPTR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TA550CI
TL16C550CIPTRG4 ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TA550CI
TL16C550CPFBR ACTIVE TQFP PFB 48 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 TA550CPFB
TL16C550CPTR ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TA550C
TL16C550CPTRG4 ACTIVE LQFP PT 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TA550C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL16C550CIPTR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
TL16C550CPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TL16C550CPTR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL16C550CIPTR LQFP PT 48 1000 350.0 350.0 43.0
TL16C550CPFBR TQFP PFB 48 1000 350.0 350.0 43.0
TL16C550CPTR LQFP PT 48 1000 350.0 350.0 43.0
Pack Materials-Page 2
PACKAGE OUTLINE
FN0044A SCALE 0.800
PLCC - 4.57 mm max height
PLASTIC CHIP CARRIER
B .650-.656 .180 MAX

[16.51-16.66] [4.57]
.020 MIN
NOTE 3 [0.51]
A (.008)
6 1 44 40 [0.2]
7 39
PIN 1 ID
.650-.656 (OPTIONAL)
[16.51-16.66] .582-.638
NOTE 3 [14.79-16.20]
17 29
18 28
.090-.120 TYP
[2.29-3.04]
44X .026-.032
[0.66-0.81]
SEATING PLANE
44X .013-.021 .004 [0.1] C
[0.33-0.53] 40X .050
[1.27]
.007 [0.18] C A B
.685-.695
[17.40-17.65]
TYP
4215154/A 04/2017
NOTES:
1. All linear dimensions are in inches. Any dimensions in brackets are in millimeters. Any dimensions in parenthesis are for reference only.
Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension does not include mold protrusion. Maximum allowable mold protrusion .01 in [0.25 mm] per side.
4. Reference JEDEC registration MS-018.
www.ti.com
EXAMPLE BOARD LAYOUT
FN0044A PLCC - 4.57 mm max height
SYMM
44X (.093 )
[2.35] 6 1 44 40
7
39
44X (.030 )
[0.75]
SYMM
(.64 )
[16.2]
40X (.050 )
[1.27]
17 29
(R.002 ) TYP
[0.05]
18 28
(.64 )
[16.2]
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:4X
.002 MAX EXPOSED METAL .002 MIN EXPOSED METAL

[0.05] [0.05]
ALL AROUND ALL AROUND
METAL SOLDER MASK SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4215154/A 04/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
FN0044A PLCC - 4.57 mm max height
SYMM
44X (.093 ) 6 40
1 44
[2.35]
7
39
44X (.030 )
[0.75]
SYMM
(.64 )
[16.2]
40X (.050 )
[1.27]
17 29
(R.002 ) TYP
[0.05]
18 28
(.64 )
[16.2]
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4215154/A 04/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
0,27
0,50 0,08 M
0,17
36 25
37 24
48 13
0,13 NOM
1 12
5,50 TYP
7,20
SQ Gage Plane
6,80
9,20
SQ
8,80 0,25
0,05 MIN 0°– 7°
1,05
0,95
0,75
Seating Plane 0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OUTLINE
PT0048A SCALE 2.000
LQFP - 1.6 mm max height
LOW PROFILE QUAD FLATPACK
9.2
8.8
7.2
B
6.8
9.2 7.2
8.8 6.8
0.27
48X
0.17
0.08 C A B
44X 0.5
SEE DETAIL A 4X 5.5
1.6 MAX C
SEATING PLANE
0.1 C
1.45
0.25 1.35
GAGE PLANE
0.75 0.5 MIN

0 -7 0.45
DETAIL A
A15.000
4215159/A 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.
4. This may also be a thermally enhanced plastic package with leads conected to the die pads.
www.ti.com
EXAMPLE BOARD LAYOUT
PT0048A LQFP - 1.6 mm max height
PKG
SYMM
48 37
SEE SOLDER MASK
DETAILS
48X (1.6)
1
36
48X (0.3)
44X (0.5)
PKG SYMM (8.2)
(R0.05) TYP
12 25
13 24
(8.2)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE 10.000
0.05 MAX 0.05 MIN

ALLAROUND ALL AROUND
EXPOSED METAL EXPOSED METAL
METAL EDGE SOLDER MASK METAL UNDER

SOLDER MASK
OPENING OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
SOLDER MASK DETAILS 4215159/A 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PT0048A LQFP - 1.6 mm max height
PKG
SYMM
48 37
48X (1.6)
1
36
48X (0.3)
44X (0.5)
PKG SYMM (8.2)
(R0.05) TYP
12 25
13 24
(8.2)
SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE: 10X
4215159/A 12/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated

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TL16C550C

SLLS177I – MARCH 1994 – REVISED MARCH 2021

TL16C550C Asynchronous Communications Element with Autoflow Control

Changes from Revision H (January 2006) to Revision I (March 2021) Page

2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TL16C550C

4 Pin Configuration and Functions

Figure 4-2. FN Package (Top View)

Figure 4-1. N Package (Top View)

Figure 4-3. PT/PFB Package (Top View)

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3

Table 4-1. Pin Functions (continued)

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Product Folder Links: TL16C550C

Table 4-1. Pin Functions (continued)

(1) The N package is Not Recommended for New Designs.

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5

5.2 Recommended Operating Conditions (Low Voltage - 3.3 nominal)

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Product Folder Links: TL16C550C

5.3 Recommended Operating Conditions (Standard Voltage - 5 V nominal)

(1) Applies for external output buffers.

5.4 Thermal Information

THERMAL METRIC(1) PT PFB FN UNIT

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7

5.5 Electrical Characteristics (Low Voltage - 3.3 V nominal)

(1) All typical values are at VCC = 3.3 V and TA = 25°C.

5.6 Electrical Characteristics (Standard Voltage - 5 V nominal)

VCC = 5.25 V, VSS = 0,

(1) All typical values are at VCC = 5 V and TA = 25°C.

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Product Folder Links: TL16C550C

5.7 System Timing Requirements

tw5 Pulse duration, ADS low tADS 6.7 9 ns

(1) Only applies when ADS is low.

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9

5.8 System Switching Characteristics

5.9 Baud Generator Switching Characteristics

td1 Delay time, XIN↑ to BAUDOUT↑ tBLD 5 45 ns

5.10 Receiver Switching Characteristics

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Product Folder Links: TL16C550C

5.11 Transmitter Switching Characteristics

5.12 Modem Control Switching Characteristics

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11

6 Parameter Measurement Information

Figure 6-1. Baud Generator Timing Waveforms

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Figure 6-2. Write Cycle Timing Waveforms

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13

Figure 6-3. Read Cycle Timing Waveforms

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Product Folder Links: TL16C550C

Figure 6-4. Receiver Timing Waveforms

Figure 6-5. Receive FIFO First Byte (Sets DR Bit) Waveforms

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15

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Product Folder Links: TL16C550C

Figure 6-9. Transmitter Timing Waveforms