LM1882 • 54ACT715 • LM1882-R • 54ACT715-R Programmable Video Sync Generator

December 1998

LM1882 • 54ACT715
LM1882-R • 54ACT715-R Programmable Video Sync
Generator
General Description LM1882-R is mask programmed to default to a Clock En-
abled state. Bit 10 of the Status Register defaults to a logic
The ’ACT715/LM1882 and ’ACT715-R/LM1882-R are 20-pin “1”. Although completely (re)programmable, the ’ACT715-R/
TTL-input compatible devices capable of generating Hori- LM1882-R version is better suited for applications using the
zontal, Vertical and Composite Sync and Blank signals for default 14.31818 MHz RS-170 register values. This feature
televisions and monitors. All pulse widths are completely de- allows power-up directly into operation, following a single
finable by the user. The devices are capable of generating CLEAR pulse.
signals for both interlaced and noninterlaced modes of op-
eration. Equalization and serration pulses can be introduced
into the Composite Sync signal when needed. Features
Four additional signals can also be made available when n Maximum Input Clock Frequency > 130 MHz
Composite Sync or Blank are used. These signals can be n Interlaced and non-interlaced formats available
used to generate horizontal or vertical gating pulses, cursor n Separate or composite horizontal and vertical Sync and
position or vertical Interrupt signal. Blank signals available
These devices make no assumptions concerning the system n Complete control of pulse width via register
architecture. Line rate and field/frame rate are all a function programming
of the values programmed into the data registers, the status n All inputs are TTL compatible
register, and the input clock frequency. n 8 mA drive on all outputs
The ’ACT715/LM1882 is mask programmed to default to a n Default RS170/NTSC values mask programmed into
Clock Disable state. Bit 10 of the Status Register, Register 0, registers
defaults to a logic “0”. This facilitates (re)programming be- n 4 KV minimum ESD immunity
fore operation. n ’ACT715-R/LM1882-R is mask programmed to default to
The ’ACT715-R/LM1882-R is the same as the ’ACT715/ a Clock Enable state for easier start-up into
LM1882 in all respects except that the ’ACT715-R/ 14.31818 MHz RS170 timing

Connection Diagrams

Pin Assignment for

Pin Assignment
DIP and SOIC
for LCC

DS100232-1
DS100232-2
Order Number LM1882CN or LM1882CM
For Default RS-170, Order Number
LM1882-RCN or LM1882-RCM

TRI-STATE ® is a registered trademark of National Semiconductor Corporation.

FACT™ is a trademark of Fairchild Semiconductor Corporation.

© 1998 National Semiconductor Corporation DS100232 www.national.com

 Logic Block Diagram

DS100232-3

Pin Description
There are a Total of 13 inputs and 5 outputs on the ’ACT715/ ODD/EVEN: Output that identifies if display is in odd (HIGH)
LM1882. or even (LOW) field of interlace when device is in interlaced
Data Inputs D0–D7: The Data Input pins connect to the Ad- mode of operation. In noninterlaced mode of operation this
dress Register and the Data Input Register. output is always HIGH. Data can be serially scanned out on
this pin during Scan Mode.
ADDR/DATA: The ADDR/DATA signal is latched into the de-
vice on the falling edge of the LOAD signal. The signal deter- VCSYNC: Outputs Vertical or Composite Sync signal based
mines if an address (0) or data (1) is present on the data bus. on value of the Status Register. Equalization and Serration
pulses will (if enabled) be output on the VCSYNC signal in
L/HBYTE: The L/HBYTE signal is latched into the device on
composite mode only.
the falling edge of the LOAD signal. The signal determines if
data will be read into the 8 LSB’s (0) or the 4 MSB’s (1) of the VCBLANK: Outputs Vertical or Composite Blanking signal
Data Registers. A 1 on this pin when an ADDR/DATA is a 0 based on value of the Status Register.
enables Auto-Load Mode. HBLHDR: Outputs Horizontal Blanking signal, Horizontal
LOAD: The LOAD control pin loads data into the Address or Gating signal or Cursor Position based on value of the Sta-
Data Registers on the rising edge. ADDR/DATA and tus Register.
L/HBYTE data is loaded into the device on the falling edge of HSYNVDR: Outputs Horizontal Sync signal, Vertical Gating
the LOAD. The LOAD pin has been implemented as a signal or Vertical Interrupt signal based on value of Status
Schmitt trigger input for better noise immunity. Register.
CLOCK: System CLOCK input from which all timing is de-
rived. The clock pin has been implemented as a Schmitt trig- Register Description
ger for better noise immunity. The CLOCK and the LOAD
All of the data registers are 12 bits wide. Width’s of all pulses
signal are asynchronous and independent. Output state
are defined by specifying the start count and end count of all
changes occur on the falling edge of CLOCK.
pulses. Horizontal pulses are specified with-respect-to the
CLR: The CLEAR pin is an asynchronous input that initial- number of clock pulses per line and vertical pulses are speci-
izes the device when it is HIGH. Initialization consists of set- fied with-respect-to the number of lines per frame.
ting all registers to their mask programmed values, and ini-
tializing all counters, comparators and registers. The CLEAR REG0 — STATUS REGISTER
pin has been implemented as a Schmitt trigger for better The Status Register controls the mode of operation, the sig-
noise immunity. A CLEAR pulse should be asserted by the nals that are output and the polarity of these outputs. The de-
user immediately after power-up to ensure proper initializa- fault value for the Status Register is 0 (000 Hex) for the
tion of the registers — even if the user plans to (re)program ’ACT715/LM1882 and is “1024” (400 Hex) for the
the device. ’ACT715-R/LM1882-R.
Note: A CLEAR pulse will disable the CLOCK on the ’ACT715/LM1882 and
will enable the CLOCK on the ’ACT715-R/LM1882-R.

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Register Description (Continued) HORIZONTAL INTERVAL REGISTERS
The Horizontal Interval Registers determine the number of
Bits 0–2 clock cycles per line and the characteristics of the Horizontal
Sync and Blank pulses.
B2 B1 B0 VCBLANK VCSYNC HBLHDR HSYNVDR
REG1 — Horizontal Front Porch
0 0 0 CBLANK CSYNC HGATE VGATE
REG2 — Horizontal Sync Pulse End Time
(DEFAULT)
REG3 — Horizontal Blanking Width
0 0 1 VBLANK CSYNC HBLANK VGATE
REG4 — Horizontal Interval Width # of Clocks per
0 1 0 CBLANK VSYNC HGATE HSYNC
Line
0 1 1 VBLANK VSYNC HBLANK HSYNC
1 0 0 CBLANK CSYNC CURSOR VINT VERTICAL INTERVAL REGISTERS
1 0 1 VBLANK CSYNC HBLANK VINT The Vertical Interval Registers determine the number of lines
1 1 0 CBLANK VSYNC CURSOR HSYNC per frame, and the characteristics of the Vertical Blank and
1 1 1 VBLANK VSYNC HBLANK HSYNC Sync Pulses.
REG5 — Vertical Front Porch
REG6 — Vertical Sync Pulse End Time
Bits 3–4
REG7 — Vertical Blanking Width
B4 B3 Mode of Operation REG8 — Vertical Interval Width # of Lines per Frame
0 0 Interlaced Double Serration and
EQUALIZATION AND SERRATION PULSE
(DEFAULT) Equalization
SPECIFICATION REGISTERS
0 1 Non Interlaced Double Serration
These registers determine the width of equalization and ser-
1 0 Illegal State ration pulses and the vertical interval over which they occur.
1 1 Non Interlaced Single Serration and REG 9 — Equalization Pulse Width End Time
Equalization REG10 — Serration Pulse Width End Time
Double Equalization and Serration mode will output equal- REG11 — Equalization/Serration Pulse Vertical
ization and serration pulses at twice the HSYNC frequency
Interval Start Time
(i.e., 2 equalization or serration pulses for every HSYNC
pulse). Single Equalization and Serration mode will output REG12 — Equalization/Serration Pulse Vertical
an equalization or serration pulse for every HSYNC pulse. In Interval End Time
Interlaced mode equalization and serration pulses will be
output during the VBLANK period of every odd and even VERTICAL INTERRUPT SPECIFICATION REGISTERS
field. Interlaced Single Equalization and Serration mode is These Registers determine the width of the Vertical Interrupt
not possible with this part. signal if used.
REG13 — Vertical Interrupt Activate Time
Bits 5–8
REG14 — Vertical Interrupt Deactivate Time
Bits 5 through 8 control the polarity of the outputs. A value of
zero in these bit locations indicates an output pulse active CURSOR LOCATION REGISTERS
LOW. A value of 1 indicates an active HIGH pulse.
These 4 registers determine the cursor position location, or
B5 — VCBLANK Polarity they generate separate Horizontal and Vertical Gating sig-
B6 — VCSYNC Polarity nals.
B7 — HBLHDR Polarity REG15 — Horizontal Cursor Position Start Time
B8 — HSYNVDR Polarity REG16 — Horizontal Cursor Position End Time
REG17 — Vertical Cursor Position Start Time
Bits 9–11
REG18 — Vertical Cursor Position End Time
Bits 9 through 11 enable several different features of the de-
vice.
B9 — Enable Equalization/Serration Pulses (0)
Signal Specification
Disable Equalization/Serration Pulses (1) HORIZONTAL SYNC AND BLANK
B10 — Disable System Clock (0) SPECIFICATIONS
Enable System Clock (1) All horizontal signals are defined by a start and end time.
Default values for B10 are “0” in the ’ACT715/ The start and end times are specified in number of clock
LM1882 and “1” in the ’ACT715-R/LM1882-R. cycles per line. The start of the horizontal line is considered
B11 — Disable Counter Test Mode (0) pulse 1 not 0. All values of the horizontal timing registers are
referenced to the falling edge of the Horizontal Blank signal
Enable Counter Test Mode (1) (see Figure 1). Since the first CLOCK edge, CLOCK #1,
This bit is not intended for the user but is for internal causes the first falling edge of the Horizontal Blank reference
testing only. pulse, edges referenced to this first Horizontal edge are n +
1 CLOCKs away, where “n” is the width of the timing in ques-
tion. Registers 1, 2, and 3 are programmed in this manner.
The horizontal counters start at 1 and count until HMAX. The
value of HMAX must be divisible by 2. This limitation is im-

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 Signal Specification (Continued) ization pulses at 2 x the horizontal frequency. Horizontal
signals will change on the falling edge of the CLOCK signal.
posed because during interlace operation this value is inter- Signal specifications are shown below.
nally divided by 2 in order to generate serration and equal-

DS100232-4

FIGURE 1. Horizontal Waveform Specification

Horizontal Period (HPER) = REG(4) x ckper Vertical Syncing Width = [REG(6) − REG(5)] x hper/n
Horizontal Blanking Width: = [REG(3) − 1] x ckper Vertical Front Porch = [REG(5) − 1] x hper/n
Horizontal Sync Width: = [REG(2) − REG(1)] x ckper where n = 1 for noninterlaced
Horizontal Front Porch: = [REG(1) − 1] x ckper n = 2 for interlaced

VERTICAL SYNC AND BLANK SPECIFICATION COMPOSITE SYNC AND BLANK SPECIFICATION
All vertical signals are defined in terms of number of lines per Composite Sync and Blank signals are created by logically
frame. This is true in both interlaced and noninterlaced ANDing (ORing) the active LOW (HIGH) signals of the corre-
modes of operation. Care must be taken to not specify the sponding vertical and horizontal components of these sig-
Vertical Registers in terms of lines per field. Since the first nals. The Composite Sync signal may also include serration
CLOCK edge, CLOCK #1, causes the first falling edge of the and/or equalization pulses. The Serration pulse interval oc-
Vertical Blank (first Horizontal Blank) reference pulse, edges curs in place of the Vertical Sync interval. Equalization
referenced to this first edge are n + 1 lines away, where “n” pulses occur preceding and/or following the Serration
is the width of the timing in question. Registers 5, 6, and 7 pulses. The width and location of these pulses can be pro-
are programmed in this manner. Also, in the interlaced grammed through the registers shown below. (See Figure 3.)
mode, vertical timing is based on half-lines. Therefore regis- Horizontal Equalization PW = [REG(9) − REG(1)] x ckper
ters 5, 6, and 7 must contain a value twice the total horizontal
REG 9 = (HFP) + (HEQP) + 1
(odd and even) plus 1 (as described above). In
non-interlaced mode, all vertical timing is based on Horizontal Serration PW: = [REG(4)/n + REG(1) −
whole-lines. Register 8 is always based on whole-lines and REG(10)] x ckper
does not add 1 for the first clock. The vertical counter starts REG 10 = (HFP) +
at the value of 1 and counts until the value of VMAX. No re- (HPER/2) − (HSERR) + 1
strictions exist on the values placed in the vertical registers. Where n = 1 for noninterlaced single serration/
Vertical Blank will change on the leading edge of HBLANK. equalization
Vertical Sync will change on the leading edge of HSYNC.
n = 2 for noninterlaced double serration/
(See Figure 2.)
equalization
Vertical Frame Period (VPER) = REG(8) x hper n = 2 for interlaced operation
Vertical Field Period (VPER/n) = REG(8) x hper/n
Vertical Blanking Width = [REG(7) − 1] x hper/n

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Signal Specification (Continued)

DS100232-5

FIGURE 2. Vertical Waveform Specification

DS100232-12

FIGURE 3. Equalization/Serration Interval Programming

HORIZONTAL AND VERTICAL GATING SIGNALS Addressing Logic

Horizontal Drive and Vertical Drive outputs can be utilized as
The register addressing logic is composed of two blocks of
general purpose Gating Signals. Horizontal and Vertical Gat-
logic. The first is the address register and counter (AD-
ing Signals are available for use when Composite Sync and
DRCNTR), and the second is the address decode (AD-
Blank signals are selected and the value of Bit 2 of the Sta-
DRDEC).
tus Register is 0. The Vertical Gating signal will change in the
same manner as that specified for the Vertical Blank. ADDRCNTR LOGIC
Horizontal Gating Signal Width = [REG(16) − REG(15)] x Addresses for the data registers can be generated by one of
ckper two methods. Manual addressing requires that each byte of
Vertical Gating Signal Width: = [REG(18) − REG(17)] x each register that needs to be loaded needs to be ad-
hper dressed. To load both bytes of all 19 registers would require
a total of 57 load cycles (19 address and 38 data cycles).
CURSOR POSITION AND VERTICAL INTERRUPT Auto Addressing requires that only the initial register value
The Cursor Position and Vertical Interrupt signal are avail- be specified. The Auto Load sequence would require only 39
able when Composite Sync and Blank signals are selected load cycles to completely program all registers (1 address
and Bit 2 of the Status Register is set to the value of 1. The and 38 data cycles). In the auto load sequence the low order
Cursor Position generates a single pulse of n clocks wide byte of the data register will be written first followed by the
during every line that the cursor is specified. The signals are high order byte on the next load cycle. At the time the High
generated by logically ORing (ANDing) the active LOW Byte is written the address counter is incremented by 1. The
(HIGH) signals specified by the registers used for generating counter has been implemented to loop on the initial value
Horizontal and Vertical Gating signals. The Vertical Interrupt loaded into the address register. For example: If a value of 0
signal generates a pulse during the vertical interval speci- was written into the address register then the counter would
fied. The Vertical Interrupt signal will change in the same count from 0 to 18 before resetting back to 0. If a value of 15
manner as that specified for the Vertical Blanking signal. was written into the address register then the counter would
Horizontal Cursor Width = [REG(16) − REG(15)] x ckper count from 15 to 18 before looping back to 15. If a value
greater than or equal to 18 is placed into the address register
Vertical Cursor Width = [REG(18) − REG(17)] x hper
the counter will continuously loop on this value. Auto ad-
Vertical Interrupt Width = [REG(14) − REG(13)] x hper dressing is initiated on the falling edge of LOAD when AD-
DRDATA is 0 and LHBYTE is 1. Incrementing and loading of
data registers will not commence until the falling edge of
LOAD after ADDRDATA goes to 1. The next rising edge of

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 Addressing Logic (Continued)

LOAD will load the first byte of data. Auto Incrementing is

disabled on the falling edge of LOAD after ADDRDATA and
LHBYTE goes low.

Manual Addressing Mode

Cycle # Load Falling Edge Load Rising Edge
1 Enable Manual Addressing Load Address m
2 Enable Lbyte Data Load Load Lbyte m
3 Enable Hbyte Data Load Load Hbyte m
4 Enable Manual Addressing Load Address n
5 Enable Lbyte Data Load Load Lbyte n
6 Enable Hbyte Data Load Load Hbyte n

DS100232-7

Auto Addressing Mode

Cycle # Load Falling Edge Load Rising Edge
1 Enable Auto Addressing Load Start Address n
2 Enable Lbyte Data Load Load Lbyte (n)
3 Enable Hbyte Data Load Load Hbyte (n); Inc Counter
4 Enable Lbyte Data Load Load Lbyte (n+1)
5 Enable Hbyte Data Load Load Hbyte (n+1); Inc Counter
6 Enable Manual Addressing Load Address

DS100232-8

ADDRDEC LOGIC CLOCK is disabled. Clocking the part during a Vectored Re-
The ADDRDEC logic decodes the current address and gen- start or Vectored Clear state will have no effect on the part.
erates the enable signal for the appropriate register. The en- To resume operation in the new state, or disable the Vec-
able values for the registers and counters change on the fall- tored Restart or Vectored Clear state, another
ing edge of LOAD. Two types of ADDRDEC logic is enabled non-ADDRDEC address must be loaded. Operation will be-
by 2 pair of addresses, Addresses 22 or 54 (Vectored Re- gin in the new state on the rising edge of the non-ADDRDEC
start logic) and Addresses 23 or 55 (Vectored Clear logic). load pulse. It is recommended that an unused address be
Loading these addresses will enable the appropriate logic loaded following an ADDRDEC operation to prevent data
and put the part into either a Restart (all counter registers are registers from accidentally being corrupted. The following
reinitialized with preprogrammed data) or Clear (all registers Addresses are used by the device.
are cleared to zero) state. Reloading the same ADDRDEC Address 0 Status Register REG0
address will not cause any change in the state of the part. Address 1–18Data Registers REG1–REG18
The outputs during these states are frozen and the internal

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Addressing Logic (Continued) is possible without interruption or data and performance cor-
ruption. If the defaulted 14.31818 MHz RS-170 values are
Address 19–21Unused being used, preconditioning and restarting can be minimized
Address 22/54Restart Vector (Restarts Device) by using the CLEAR pulse instead of the Vectored Restart
operation. The ’ACT715-R/LM1882-R is better suited for this
Address 23/55Clear Vector (Zeros All Registers)
application because it eliminates the need to program a 1
Address 24–31Unused into Bit 10 of the Status Register to enable the CLOCK. Gen
Address 32–50Register Scan Addresses Locking to another count location other than the very begin-
Address 51–53Counter Scan Addresses ning or separate horizontal/vertical resetting is not possible
Address 56–63Unused with the ’ACT715/LM1882 nor the ’ACT715-R/LM1882-R.
At any given time only one register at most is selected. It is SCAN MODE LOGIC
possible to have no registers selected.
A scan mode is available in the ACT715/LM1882 that allows
VECTORED RESTART ADDRESS the user to non-destructively verify the contents of the regis-
ters. Scan mode is invoked through reading a scan address
The function of addresses 22 (16H) or 54 (36H) are similar to into the address register. The scan address of a given regis-
that of the CLR pin except that the preprogramming of the ter is defined by the Data register address + 32. The internal
registers is not affected. It is recommended but not required Clocking signal is disabled when a scan address is read.
that this address is read after the initial device configuration Disabling the clock freezes the device in it’s present state.
load sequence. A 1 on the ADDRDATA pin (Auto Addressing Data can then be serially scanned out of the data registers
Mode) will not cause this address to automatically incre- through the ODD/EVEN Pin. The LSB will be scanned out
ment. The address will loop back onto itself regardless of the first. Since each register is 12 bits wide, completely scanning
state of ADDRDATA unless the address on the Data inputs out data of the addressed register will require 12 CLOCK
has been changed with ADDRDATA at 0. pulses. More than 12 CLOCK pulses on the same register
will only cause the MSB to repeat on the output.
VECTORED CLEAR ADDRESS
Re-scanning the same register will require that register to be
Addresses 23 (17H) or 55 (37H) is used to clear all registers reloaded. The value of the two horizontal counters and 1 ver-
to zero simultaneously. This function may be desirable to use tical counter can also be scanned out by using address num-
prior to loading new data into the Data or Status Registers. bers 51–53. Note that before the part will scan out the data,
This address is read into the device in a similar fashion as all the LOAD signal must be brought back HIGH.
of the other registers. A 1 on the ADDRDATA pin (Auto Ad-
Normal device operation can be resumed by loading in a
dressing Mode) will not cause this address to automatically
non-scan address. As the scanning of the registers is a
increment. The address will loop back onto itself regardless
non-destructive scan, the device will resume correct opera-
of the state of ADDRDATA unless the address on the Data
tion from the point at which it was halted.
inputs has been changed with ADDRDATA at 0.

RS170 Default Register Values

The tables below show the values programmed for the
RS170 Format (using a 14.31818 MHz clock signal) and
how they compare against the actual EIA RS170 Specifica-
tions. The default signals that will be output are CSYNC,
CBLANK, HDRIVE and VDRIVE. The device initially starts at
the beginning of the odd field of interlace. All signals have
active low pulses and the clock is disabled at power up. Reg-
isters 13 and 14 are not involved in the actual signal informa-
tion. If the Vertical Interrupt was selected so that a pulse in-
dicating the active lines would be output.

DS100232-9

FIGURE 4. ADDRDEC Timing

GEN LOCKING
The ’ACT715/LM1882 and ’ACT715-R/LM1882-R is de-
signed for master SYNC and BLANK signal generation.
However, the devices can be synchronized (slaved) to an ex-
ternal timing signal in a limited sense. Using Vectored Re-
start, the user can reset the counting sequence to a given lo-
cation, the beginning, at a given time, the rising edge of the
LOAD that removes Vector Restart. At this time the next
CLOCK pulse will be CLOCK 1 and the count will restart at
the beginning of the first odd line.
Preconditioning the part during normal operation, before the
desired synchronizing pulse, is necesasry. However, since
LOAD and CLOCK are asynchronous and independent, this

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 RS170 Default Register Values (Continued)

Reg D Value H Register Description

REG0 0 000 Status Register (715/LM1882)
REG0 1024 400 Status Register
(715-R/LM1882-R)
REG1 23 017 HFP End Time
REG2 91 05B HSYNC Pulse End Time
REG3 157 09D HBLANK Pulse End Time
REG4 910 38E Total Horizontal Clocks
REG5 7 007 VFP End Time
REG6 13 00D VSYNC Pulse End Time
REG7 41 029 VBLANK Pulse End Time
REG8 525 20D Total Vertical Lines
REG9 57 039 Equalization Pulse End Time
REG10 410 19A Serration Pulse Start Time
REG11 1 001 Pulse Interval Start Time
REG12 19 013 Pulse Interval End Time
REG13 41 029 Vertical Interrupt Activate Time
REG14 526 20E Vertical Interrupt Deactivate Time
REG15 911 38F Horizontal Drive Start Time
REG16 92 05C Horizontal Drive End Time
REG17 1 001 Vertical Drive Start Time
REG18 21 015 Vertical Drive End Time
Rate Period
Input Clock 14.31818 MHz 69.841 ns
Line Rate 15.73426 kHz 63.556 µs
Field Rate 59.94 Hz 16.683 ms
Frame Rate 29.97 Hz 33.367 ms

RS170 Horizontal Data

Signal Width µs %H Specification (µs)
HFP 22 Clocks 1.536 1.5 ± 0.1
HSYNC Width 68 Clocks 4.749 7.47 4.7 ± 0.1
HBLANK Width 156 Clocks 10.895 17.15 10.9 ± 0.2
HDRIVE Width 91 Clocks 6.356 10.00 0.1H ± 0.005H
HEQP Width 34 Clocks 2.375 3.74 2.3 ± 0.1
HSERR Width 68 Clocks 4.749 7.47 4.7 ± 0.1
HPER iod 910 Clocks 63.556 100
RS170 Vertical Data
VFP 3 Lines 190.67 6 EQP Pulses
VSYNC Width 3 Lines 190.67 6 Serration Pulses
VBLANK Width 20 Lines 1271.12 7.62 0.075V ± 0.005V
VDRIVE Width 11.0 Lines 699.12 4.20 0.04V ± 0.006V
VEQP Intrvl 9 Lines 3.63 9 Lines/Field
VPERiod (field) 262.5 Lines 16.683 ms 16.683 ms/Field
VPERiod (frame) 525 Lines 33.367 ms 33.367 ms/Frame

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 Absolute Maximum Ratings (Note 1) Junction Temperature (TJ)
If Military/Aerospace specified devices are required, Ceramic 175˚C
please contact the National Semiconductor Sales Office/ Plastic 140˚C
Distributors for availability and specifications.
Supply Voltage (VCC) −0.5V to +7.0V Recommended Operating
DC Input Diode Current (IIK) Conditions
VI = −0.5V −20 mA
Supply Voltage (VCC) 4.5V to 5.5V
VI = VCC +0.5V +20 mA
Input Voltage (VI) 0V to VCC
DC Input Voltage (VI) −0.5V to VCC +0.5V
Output Voltage (VO) 0V to VCC
DC Output Diode Current (IOK)
Operating Temperature (TA)
VO = −0.5V −20 mA
54ACT −55˚C to +125˚C
VO = VCC +0.5V +20 mA
Minimum Input Edge Rate (∆V/∆t)
DC Output Voltage (VO) −0.5V to VCC +0.5V
VIN from 0.8V to 2.0V
DC Output Source
VCC @ 4.5V, 5.5V 125 mV/ns
or Sink Current (IO) ± 15 mA Note 1: Absolute maximum ratings are those values beyond which damage
DC VCC or Ground Current to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
per Output Pin (ICC or IGND) ± 20 mA temperature and output/input loading variables. National does not recom-
Storage Temperature (TSTG) −65˚C to +150˚C mend operation of FACT ® circuits outside databook specifications.

DC Characteristics
For ’ACT Family Devices over Operating Temperature Range (unless otherwise specified)
LM1882 54ACT/LM1882 LM1882
VCC TA = +25˚C TA = −55˚C TA = −40˚C
Symbol Parameter (V) CL = 50 pF to +125˚C to +85˚C Units Conditions
CL = 50 pF
Typ Guaranteed Limits
VOH Minimum High Level 4.5 4.49 4.4 4.4 4.4 V IOUT = −50 µA
Output Voltage 5.5 5.49 5.4 5.4 5.4 V
(Note 2)
4.5 3.86 3.7 3.76 V VIN = VIL/VIH
5.5 4.86 4.7 4.76 V IOH = −8 mA
VOL Maximum Low Level 4.5 0.001 0.1 0.1 0.1 V IOUT = 50 µA
Output Voltage 5.5 0.001 0.1 0.1 0.1 V
(Note 2)
4.5 0.36 0.5 0.44 V VIN = VIL/VIH
5.5 0.36 0.5 0.44 V IOH = +8 mA
IOLD Minimum Dynamic 5.5 32.0 32.0 mA VOLD = 1.65V
Output Current
IOHD Minimum Dynamic 5.5 −32.0 −32.0 mA VOHD = 3.85V
Output Current
IIN Maximum Input 5.5 ± 0.1 ± 1.0 ± 1.0 µA VI = VCC, GND
Leakage Current
ICC Supply Current 5.5 8.0 160 80 µA VIN = VCC, GND
Quiescent
ICCT Maximum ICC/Input 5.5 0.6 1.6 1.5 mA VIN = VCC − 2.1V
Note 2: All outputs loaded; thresholds on input associated with input under test.
Note 3: Test Load 50 pF, 500Ω to Ground.

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 AC Electrical Characteristics
LM1882 54ACT/LM1882 LM1882
VCC TA = +25˚C TA = −55˚C TA = −40˚C
Symbol Parameter (V) CL = 50 pF to +125˚C to +85˚C Units
CL = 50 pF CL = 50 pF
Min Typ Max Min Max Min Max
fMAXI Interlaced fMAX 5.0 170 190 130 150 MHz
(HMAX/2 is ODD)
fMAX Non-Interlaced fMAX 5.0 190 220 145 175 MHz
(HMAX/2 is EVEN)
tPLH1 Clock to Any Output 5.0 4.0 13.0 15.5 3.5 19.5 3.5 18.5 ns
tPHL1
tPLH2 Clock to ODDEVEN 5.0 4.5 15.0 17.0 3.5 22.0 3.5 20.5 ns
tPHL2 (Scan Mode)
tPLH3 Load to Outputs 5.0 4.0 11.5 16.0 3.0 20.0 3.0 19.5 ns

AC Operating Requirements
LM1882 54ACT/LM1882 LM1882
Symbol Parameter VCC TA = +25˚C TA = −55˚C TA = −40˚C Units
(V) to +125˚C to +85˚C
Typ Guaranteed Minimums
Control Setup Time
tsc ADDR/DATA to LOAD− 5.0 3.0 4.0 4.5 4.5 ns
tsc L/HBYTE to LOAD− 3.0 4.0 4.5 4.5 ns
Data Setup Time
tsd D7–D0 to LOAD+ 5.0 2.0 4.0 4.5 4.5 ns
Control Hold Time
thc LOAD− to ADDR/DATA 5.0 0 1.0 1.0 1.0 ns
LOAD− to L/HBYTE 0 1.0 1.0 1.0 ns
Data Hold Time
thd LOAD+ to D7–D0 5.0 1.0 2.0 2.0 2.0 ns
trec LOAD+ to CLK (Note 4) 5.0 5.5 7.0 8.0 8.0 ns
Load Pulse Width
twld− LOW 5.0 3.0 5.5 5.5 5.5 ns
twld+ HIGH 5.0 3.0 5.0 7.5 7.5 ns
twclr CLR Pulse Width HIGH 5.0 5.5 6.5 9.5 9.5 ns
twck CLOCK Pulse Width 5.0 2.5 3.0 4.0 3.5 ns
(HIGH or LOW)
Note 4: Removal of Vectored Reset or Restart to Clock.

Capacitance
Symbol Parameter Typ Units Conditions
CIN Input Capacitance 7.0 pF VCC = 5.0V
CPD Power Dissipation 17.0 pF VCC = 5.0V
Capacitance

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Capacitance (Continued)

DS100232-6

FIGURE 5. AC Specifications

Additional Applications Information

POWERING UP PREPROGRAMMING “ON-THE-FLY”
The ’ACT715/LM1882 default value for Bit 10 of the Status Although the ’ACT715/LM1882 and ’ACT715-R/LM1882-R
Register is 0. This means that when the CLEAR pulse is ap- are completely programmable, certain limitations must be
plied and the registers are initialized by loading the default set as to when and how the parts can be reprogrammed.
values the CLOCK is disabled. Before operation can begin, Care must be taken when reprogramming any End Time reg-
Bit 10 must be changed to a 1 to enable CLOCK. If the de- isters to a new value that is lower than the current value.
fault values are needed (no other programming is required) Should the reprogramming occur when the counters are at a
then Figure 6 illustrates a hardwired solution to facilitate the count after the new value but before the old value, then the
enabling of the CLOCK after power-up. Should control sig- counters will continue to count up to 4096 before rolling over.
nals be difficult to obtain, Figure 7 illustrates a possible solu- For this reason one of the following two precautions are rec-
tion to automatically enable the CLOCK upon power-up. Use ommended when reprogramming “on-the-fly”. The first rec-
of the ’ACT715-R/LM1882-R eliminates the need for most of ommendation is to reprogram horizontal values during the
this circuitry. Modifications of the Figure 7 circuit can be horizontal blank interval only and/or vertical values during
made to obtain the lone CLEAR pulse still needed upon the vertical blank interval only. Since this would require deli-
power-up. cate timing requirements the second recommendation may
Note that, although during a Vectored Restart none of the be more appropriate.
preprogrammed registers are affected, some signals are af- The second recommendation is to program a Vectored Re-
fected for the duration of one frame only. These signals are start as the final step of reprogramming. This will ensure that
the Horizontal and Vertical Drive signals. After a Vectored all registers are set to the newly programmed values and
Restart the beginning of these signals will occur at the first that all counters restart at the first CLK position. This will
CLK. The end of the signals will occur as programmed. At avoid overrunning the counter end times and will maintain
the completion of the first frame, the signals will resume to the video integrity.
their programmed start and end time.

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 Additional Applications Information (Continued)

DS100232-10

FIGURE 6. Default RS170 Hardwire Configuration

DS100232-11

Note: A 74HC221A may be substituted for the 74HC423A Pin 6 and Pin 14 must be hardwired to GND
Components
R1: 4.7k C1: 10 µF
R2:10k C2: 50 pF

FIGURE 7. Circuit for Clear and Load Pulse Generation

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13
 Physical Dimensions inches (millimeters) unless otherwise noted

20-Terminal Ceramic Leadless Chip Carrier (L)

NS Package Number E20A

20-Lead Ceramic Dual-In-Line Package (D)

NS Package Number J20A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Integrated Circuit (S)

NS Package Number M20B

20-Lead Plastic Dual-In-Line Package (P)

NS Package Number N20B

15 www.national.com
LM1882 • 54ACT715 • LM1882-R • 54ACT715-R Programmable Video Sync Generator

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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys- 2. A critical component in any component of a life support
tems which, (a) are intended for surgical implant into device or system whose failure to perform can be rea-
the body, or (b) support or sustain life, and whose fail- sonably expected to cause the failure of the life support
ure to perform when properly used in accordance device or system, or to affect its safety or effectiveness.
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.