LM1881 Video Sync Separator

February 1995

LM1881 Video Sync Separator

General Description Features
The LM1881 Video sync separator extracts timing informa- Y AC coupled composite input signal
tion including composite and vertical sync, burst/back porch Y l 10 kX input resistance
timing, and odd/even field information from standard nega- Y k 10 mA power supply drain current
tive going sync NTSC, PAL*, and SECAM video signals with Y Composite sync and vertical outputs
amplitude from 0.5V to 2V p-p. The integrated circuit is also Y Odd/even field output
capable of providing sync separation for non-standard, fast- Y Burst gate/back porch output
er horizontal rate video signals. The vertical output is pro-
duced on the rising edge of the first serration in the vertical
Y Horizontal scan rates to 150 kHz
sync period. A default vertical output is produced after a
Y Edge triggered vertical output
time delay if the rising edge mentioned above does not oc- Y Default triggered vertical output for non-standard video
cur within the externally set delay period, such as might be signal (video games-home computers)
the case for a non-standard video signal.

Connection Diagram
LM1881N

TL/H/9150 – 1
Order Number LM1881M or LM1881N
See NS Package Number M08A or N08E

*PAL in this datasheet refers to European broadcast TV standard ‘‘Phase Alternating Line’’, and not to Programmable Array Logic.

C1995 National Semiconductor Corporation TL/H/9150 RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings
If Military/Aerospace specified devices are required, Storage Temperature Range b 65§ C to a 150§ C
please contact the National Semiconductor Sales ESD Susceptibility (Note 2) 2 kV
Office/Distributors for availability and specifications.
Soldering Information
Supply Voltage 13.2V Dual-In-Line Package (10 sec.) 260§ C
Input Voltage 3 Vpp (VCC e 5V) Small Outline Package
6 Vpp (VCC t 8V) Vapor Phase (60 sec.) 215§ C
Output Sink Currents; Pins 1, 3, 5 5 mA Infrared (15 sec.) 220§ C
Output Sink Current; Pin 7 2 mA See AN-450 ‘‘Surface Mounting Methods and their Effect on
Product Reliability’’ for other methods of soldering surface
Package Dissipation (Note 1) 1100 mW
mount devices.
Operating Temperature Range 0§ C b 70§ C

Electrical Characteristics
VCC e 5V; Rset e 680 kX; TA e 25§ C; Unless otherwise specified

Tested Design Units

Parameter Conditions Typ
Limit (Note 3) Limit (Note 4) (Limits)
Supply Current Outputs at Logic 1 VCC e 5V 5.2 10 mAmax
VCC e 12V 5.5 12 mAmax
DC Input Voltage Pin 2 1.3 Vmin
1.5
1.8 Vmax
Input Threshold Voltage Note 5 55 mVmin
70
85 mVmax
Input Discharge Current Pin 2; VIN e 2V 6 mAmin
11
16 mAmax
Input Clamp Charge Current Pin 2; VIN e 1V 0.8 0.2 mAmin
RSET Pin Reference Voltage Pin 6; Note 6 1.10 Vmin
1.22
1.35 Vmax
Composite Sync. & Vertical IOUT e 40 mA; VCC e 5V 4.5 4.0 Vmin
Outputs Logic 1 VCC e 12V 11.0 Vmin
IOUT e 1.6 mA VCC e 5V 3.6 2.4 Vmin
Logic 1 VCC e 12V 10.0 Vmin
Burst Gate & Odd/Even IOUT e 40 mA; VCC e 5V 4.5 4.0 Vmin
Outputs Logic 1 VCC e 12V 11.0 Vmin
Composite Sync. Output IOUT e b1.6 mA; Logic 0; Pin 1 0.2 0.8 Vmax
Vertical Sync. Output IOUT e b1.6 mA; Logic 0; Pin 3 0.2 0.8 Vmax
Burst Gate Output IOUT e b1.6 mA; Logic 0; Pin 5 0.2 0.8 Vmax
Odd/Even Output IOUT e b1.6 mA; Logic 0; Pin 7 0.2 0.8 Vmax
Vertical Sync Width 230 190 msmin
300 msmax
Burst Gate Width 2.7 kX from Pin 5 to VCC 2.5 msmin
4
4.7 msmax
Vertical Default Time Note 7 32 msmin
65
90 msmax
Note 1: For operation in ambient temperatures above 25§ C, the device must be derated based on a 150§ C maximum junction temperature and a package thermal
resistance of 110§ C/W, junction to ambient.
Note 2: ESD susceptibility test uses the ‘‘human body model, 100 pF discharged through a 1.5 kX resistor’’.
Note 3: Typicals are at TJ e 25§ C and represent the most likely parametric norm.
Note 4: Tested Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 5: Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontal output pulse.
Note 6: Careful attention should be made to prevent parasitic capacitance coupling from any output pin (Pins 1, 3, 5, and 7) to the RSET pin (Pin 6).
Note 7: Delay time between the start of vertical sync (at input) and the vertical output pulse.

2
Typical Performance Characteristics
Rset Value Selection Vertical Default
vs Vertical Serration Sync Delay Time Burst/Black Level
Pulse Separation vs Rset Gate Time vs Rset

Vertical Pulse Vertical Pulse Supply Current vs

Width vs Rset Width vs Temperature Supply Voltage

TL/H/9150 – 2

3
Application Notes
The LM1881 is designed to strip the synchronization signals from between 40 ns to as much as 200 ns due to this filter.
from composite video sources that are in, or similar to, the This much delay will not usually be significant but it does
N.T.S.C. format. Input signals with positive polarity video (in- contribute to the sync delay produced by any additional sig-
creasing signal voltage signifies increasing scene bright- nal processing. Since the original video may also undergo
ness) from 0.5V (p-p) to 2V (p-p) can be accommodated. processing, the need for time delay correction will depend
The LM1881 operates from a single supply voltage between on the total system, not just the sync stripper.
5V DC and 12V DC. The only required external components
VERTICAL SYNC OUTPUT
beside power supply and set current decoupling are the in-
put coupling capacitor and a single resistor that sets internal A vertical sync output is derived by internally integrating the
current levels, allowing the LM1881 to be adjusted for composite sync waveform (Figure 3) . To understand the
source signals with line scan frequencies differing from generation of the vertical sync pulse, refer to the lower left
15.734 kHz. Four major sync signals are available from the hand section Figure 3 . Note that there are two comparators
I/C: composite sync including both horizontal and vertical in the section. One comparator has an internally generated
scan timing information; a vertical sync pulse; a burst gate voltage reference called V1 going to one of its inputs. The
or back porch clamp pulse; and an odd/even output. The other comparator has an internally generated voltage refer-
odd/even output level identifies which video field of an inter- ance called V2 going to one of its inputs. Both comparators
laced video source is present at the input. The outputs from have a common input at their noninverting input coming
the LM1881 can be used to gen-lock video camera/VTR from the internal integrator. The internal integrator is used
signals with graphics sources, provide identification of video for integrating the composite sync signal. This signal comes
fields for memory storage, recover suppressed or contami- from the input side of the composite sync buffer and are
nated sync signals, and provide timing references for the positive going sync pulses. The capacitor to the integrator
extraction of coded or uncoded data on specific video scan is internal to the LM1881. The capacitor charge current is
lines. set by the value of the external resistor Rset. The output of
the integrator is going to be at a low voltage during the
To better understand the LM1881 timing information and
normal horizontal lines because the integrator has a very
the type of signals that are used, refer to Figure 2(a–e)
short time to charge the capacitor, which is during the hori-
which shows a portion of the composite video signal from
zontal sync period. The equalization pulses will keep the
the end of one field through the beginning of the next field.
output voltage of the integrator at about the same level,
COMPOSITE SYNC OUTPUT below the V1. During the vertical sync period the narrow
The composite sync output, Figure 2(b) , is simply a repro- going positive pulses shown in Figure 2 is called the serra-
duction of the signal waveform below the composite video tion pulse. The wide negative portion of the vertical sync
black level, with the video completely removed. This is ob- period is called the vertical sync pulse. At the start of the
tained by clamping the video signal sync tips to 1.5V DC at vertical sync period, before the first Serration pulse occurs,
Pin 2 and using a comparator threshold set just above this the integrator now charges the capacitor to a much higher
voltage to strip the sync signal, which is then buffered out to voltage. At the first serration pulse the integrator output
Pin 1. The threshold separation from the clamped sync tip is should be between V1 and V2. This would give a high level
nominally 70 mV which means that for the minimum input at the output of the comparator with V1 as one of its inputs.
level of 0.5V (p-p), the clipping level is close to the halfway This high is clocked into the ‘‘D’’ flip-flop by the falling edge
point on the sync pulse amplitude (shown by the dashed of the serration pulse (remember the sync signal is inverted
line on Figure 2(a) ). This threshold separation is indepen- in this section of the LM1881). The ‘‘Q’’ output of the ‘‘D’’
dent of the signal amplitude, therefore, for a 2V (p-p) input flip-flop goes through the OR gate, and sets the R/S flip-
the clipping level occurs at 11% of the sync pulse ampli- flop. The output of the R/S flip-flop enables the internal
tude. The charging current for the input coupling capacitor is oscillator and also clocks the ODD/EVEN ‘‘D’’ flip-flop. The
0.8 mA, whereas the discharge current is only 11 mA, typi- ODD/EVEN field pulse operation is covered in the next sec-
cally. This allows relatively small capacitor values to be tion. The output of the oscillator goes to a divide by 8 circuit,
usedÐ0.1 mF is generally recommended. thus resetting the R/S flip-flop after 8 cycles of the oscilla-
tor. The frequency of the oscillator is established by the
Normally the signal source for the LM1881 is assumed to be
internal capacitor going to the oscillator and the external
clean and relatively noise-free, but some sources may have
Rset. The ‘‘Q’’ output of the R/S flip-flop goes to pin 3 and is
excessive video peaking, causing high frequency video and
the actual vertical sync output of the LM1881. By clocking
chroma components to extend below the black level refer-
the ‘‘D’’ flip-flop at the start of the first serration pulse
ence. Some video discs keep the chroma burst pulse pres-
means that the vertical sync output pulse starts at this point
ent throughout the vertical blanking period so that the burst
in time and lasts for eight cycles of the internal oscillator as
actually appears on the sync tips for three line periods in-
shown in Figure 2 .
stead of at black level. A clean composite sync signal can
be generated from these sources by filtering the input sig- How Rset affects the integrator and the internal oscillator is
nal. When the source impedance is low, typically 75X, a shown under the Typical Performance Characteristics. The
620X resistor in series with the source and a 510 pF capaci- first graph is ‘‘Rset Value Selection vs Vertical Serration
tor to ground will form a low pass filter with a corner fre- Pulse Separation’’. For this graph to be valid, the vertical
quency of 500 kHz. This bandwidth is more than sufficient to sync pulse should last for at least 85% of the horizontal half
pass the sync pulse portion of the waveform; however, any line (47% of a full horizontal line). A vertical sync pulse from
subcarrier content in the signal will be attenuated by almost any standard should meet this requirement; both NTSC and
18 dB, effectively taking it below the comparator threshold. PAL do meet this requirement (the serration pulse is the
Filtering will also help if the source is contaminated with remainder of the period, 10% to 15% of the horizontal
thermal noise. The output waveforms will become delayed

4
Application Notes (Continued)

TL/H/9150 – 3
FIGURE 2. (a) Composite Video; (b) Composite Sync; (c) Vertical Output Pulse;
(d) Odd/Even Field Index; (e) Burst Gate/Back Porch Clamp

*Components Optional, TL/H/9150 – 4

See Text
FIGURE 3

5
Application Notes (Continued)
half line). Remember this pulse is a positive pulse at the Sync Delay Time vs Rset’’ graph to select the necessary
integrator but negative in Figure 2 . This graph shows how Rset to give the desired delay time for the vertical sync out-
long it takes the integrator to charge its internal capacitor put signal. If a second pulse is undesirable, then check the
above V1. ‘‘Vertical Pulse Width vs Rset’’ graph to make sure the verti-
WITH Rset too large the charging current of the integrator cal output pulse will extend beyond the end of the input
will be too small to charge the capacitor above V1, thus vertical sync period. In most systems the end of the vertical
there will be no vertical synch output pulse. As mentioned sync period may be very accurate. In this case the preferred
above, Rset also sets the frequency of the internal oscillator. design may be to start the vertical sync pulse at the end of
If the oscillator runs too fast its eight cycles will be shorter the vertical sync period, similar to starting the vertical sync
than the vertical sync portion of the composite sync. Under pulse after the first serration pulse. A VGA standard is to be
this condition another vertical sync pulse can be generated used as an example to show how this is done. In this stan-
on one of the later serration pulses after the divide by 8 dard a horizontal line is 32 ms long. The vertical sync period
circuit resets the R/S flip-flop. The first graph also shows is two horizontal lines long, or 64 ms. The vertical default
the minimum Rset necessary to prevent a double vertical sync delay time must be longer than the vertical sync peri-
pulse, assuming that the serration pulses last for only three od of 64 ms. In this case Rset must be larger than 680 kX.
full horizontal line periods (six serration pulses for NTSC). Rset must still be small enough for the output of the integra-
The actual pulse width of the vertical sync pulse is shown in tor to reach V1 before the end of the vertical period of the
the ‘‘Vertical Pulse Width vs Rset’’ graph. Using NTSC as an input pulse. The first graph can be used to confirm that Rset
example, lets see how these two graphs relate to each oth- is small enough for the integrator. Instead of using the verti-
er. The Horizontal line is 64 ms long, or 32 ms for a horizon- cal serration pulse separation, use the actual pulse width of
tal half line. Now round this off to 30 ms. In the ‘‘Rset Value the vertical sync period, or 64 ms in this example. This graph
Selection vs Vertical Serration Pulse Separation’’ graph the is linear, meaning that a value as large as 2.7 MX can be
minimum resistor value for 30 ms serration pulse separation used for Rset (twice the value as the maximum at 30 ms).
is about 550 kX. Going to the ‘‘Vertical Pulse Width vs Rset’’ Due to leakage currents it is advisable to keep the value of
graph one can see that 550 kX gives a vertical pulse width Rset under 2.0 MX. In this example a value of 1.0 MX is
of about 180 ms, the total time for the vertical sync period of selected, well above the minimum of 680 kX. With this value
NTSC (3 horizontal lines). A 550 kX will set the internal for Rset the pulse width of the vertical sync output pulse of
oscillator to a frequency such that eight cycles gives a time the LM1881 is about 340 ms.
of 180 ms, just long enough to prevent a double vertical ODD/EVEN FIELD PULSE
sync pulse at the vertical sync output of the LM1881.
An unusual feature of LM1881 is an output level from Pin 7
The LM1881 also generates a default vertical sync pulse that identifies the video field present at the input to the
when the vertical sync period is unusually long and has no LM1881. This can be useful in frame memory storage appli-
serration pulses. With a very long vertical sync time the inte- cations or in extracting test signals that occur only in alter-
grator has time to charge its internal capacitor above the nate fields. For a composite video signal that is interlaced,
voltage level V2. Since there is no falling edge at the end of one of the two fields that make up each video frame or
a serration pulse to clock the ‘‘D’’ flip-flop, the only high picture must have a half horizontal scan line period at the
signal going to the OR gate is from the default comparator end of the vertical scanÐi.e., at the bottom of the picture.
when output of the integrator reaches V2. At this time the This is called the ‘‘odd field’’ or ‘‘field 1’’. The ‘‘even field’’
R/S flip-flop is toggled by the default comparator, starting or ‘‘field 2’’ has a complete horizontal scan line at the end of
the vertical sync pulse at pin 3 of the LM1881. If the default the field. An odd field starts on the leading edge of the first
vertical sync period ends before the end of the input vertical equalizing pulse, whereas the even field starts on the lead-
sync period, then the falling edge of the vertical sync (posi- ing edge of the second equalizing pulse of the vertical re-
tive pulse at the ‘‘D’’ flip-flop) will clock the high output from trace interval. Figure 2(a) shows the end of the even field
the comparator with V1 as a reference input. This will retrig- and the start of the odd field.
ger the oscillator, generating a second vertical sync output
To detect the odd/even fields the LM1881 again integrates
pulse. The ‘‘Vertical Default Sync Delay Time vs Rset’’
the composite sync waveform (Figure 3) . A capacitor is
graph shows the relationship between the Rset value and
charged during the period between sync pulses and dis-
the delay time from the start of the vertical sync period be-
charged when the sync pulse is present. The period be-
fore the default vertical sync pulse is generated. Using the
tween normal horizontal sync pulses is enough to allow the
NTSC example again the smallest resistor for Rset is 500
capacitor voltage to reach a threshold level of a comparator
kX. The vertical default time delay is about 50 ms, much
that clears a flipflop which is also being clocked by the sync
longer than the 30 ms serration pulse spacing.
waveform. When the vertical interval is reached, the shorter
A common question is how can one calculate the required integration time between equalizing pulses prevents this
Rset with a video timing standard that has no serration puls-
es during the vertical blanking. If the default vertical sync is
to be used this is a very easy task. Use the ‘‘Vertical Default

6
Application Notes (Continued)
threshold from being reached and the Q output of the flip- signal (VIRS) and line 21 is reserved for closed caption data
flop is toggled with each equalizing pulse. Since the half line for the hearing impaired. The remaining lines are used in a
period at the end of the odd field will have the same effect number of ways. Lines 17 and 18 are frequently used during
as an equalizing pulse period, the Q output will have a differ- studio processing to add and delete vertical interval test
ent polarity on successive fields. Thus by comparing the Q signals (VITS) while lines 14 through 18 and line 20 can be
polarity with the vertical output pulse, an odd/even field in- used for Videotex/Teletext data. Several institutions are
dex is generated. Pin 7 remains low during the even field proposing to transmit financial data on line 17 and cable
and high during the odd field. systems use the available lines in the vertical interval to
send decoding data for descrambler terminals.
BURST/BACKPORCH OUTPUT PULSE
Since the vertical output pulse from the LM1881 coincides
In a composite video signal, the chroma burst is located on
with the leading edge of the first vertical serration, sixteen
the backporch of the horizontal blanking period. This period,
positive or negative transitions later will be the start of line
approximately 4.8 ms long, is also the black level reference
14 in either field. At this point simple counters can be used
for the subsequent video scan line. The LM1881 generates
to select the desired line(s) for insertion or deletion of data.
a pulse at Pin 5 that can be used either to retrieve the chro-
ma burst from the composite video signal (thus providing a VIDEO LINE SELECTOR
subcarrier synchronizing signal) or as a clamp for the DC The circuit in Figure 4 puts out a single video line according
restoration of the video waveform. This output is obtained to the binary coded information applied to line select bits
simply by charging an internal capacitor starting on the trail- b0 – b7. A line is selected by adding two to the desired line
ing edge of the horizontal sync pulses. Simultaneously the number, converting to a binary equivalent and applying the
output of Pin 5 is pulled low and held until the capacitor result to the line select inputs. The falling edge of the
charge circuit times outÐ4 ms later. A shorter output burst LM1881’s vertical pulse is used to load the appropriate
gate pulse can be derived by differentiating the burst output number into the counters (MM74C193N) and to set a start
using a series C-R network. This may be necessary in appli- count latch using two NAND gates. Composite sync tran-
cations which require high horizontal scan rates in combina- sitions are counted using the borrow out of the desired num-
tion with normal (60–120 Hz) vertical scan rates. ber of counters. The final borrow out pulse is used to turn on
APPLICATIONS the analog switch (CD4066BC) during the desired line. The
falling edge of this signal also resets the start count latch,
Apart from extracting a composite sync signal free of video
thereby terminating the counting.
information, the LM1881 outputs allow a number of interest-
ing applications to be developed. As mentioned above, the The circuit, as shown, will provide a single line output for
burst gate/backporch clamp pulse allows DC restoration of each field in an interlaced video system (television) or a
the original video waveform for display or remodulation on single line output in each frame for a non-interlaced video
an R.F. carrier, and retrieval of the color burst for color syn- system (computer monitor). When a particular line in only
chronization and decoding into R.G.B. components. For one field of an interlaced video signal is desired, the odd/
frame memory storage applications, the odd/even field lev- even field index output must be used instead of the vertical
el allows identification of the appropriate field ensuring the output pulse (invert the field index output to select the odd
correct read or write sequence. The vertical pulse output is field). A single counter is needed for selecting lines 3 to 14;
particularly useful since it begins at a precise timeÐthe ris- two counters are needed for selecting lines 15 to 253; and
ing edge of the first vertical serration in the sync waveform. three counters will work for up to 2046 lines. An output buff-
This means that individual lines within the vertical blanking er is required to drive low impedance loads.
period (or anywhere in the active scan line period) can easi- MULTIPLE CONTIGUOUS VIDEO LINE
ly be extracted by counting the required number of tran- SELECTOR WITH BLACK LEVEL RESTORATION
sitions in the composite sync waveform following the start of
The circuit in Figure 5 will select a number of adjoining lines
the vertical output pulse.
starting with the line selected as in the previous example.
The vertical blanking interval is proving popular as a means Additional counters can be added as described previously
to transmit data which will not appear on a normal T.V. re- for either higher starting line numbers or an increased num-
ceiver screen. Data can be inserted beginning with line 10 ber of contiguous output lines. The back porch pulse output
(the first horizontal scan line on which the color burst ap- of the LM1881 is used to gate the video input’s black level
pears) through to line 21. Usually lines 10 through 13 are through a low pass filter (10 kX, 10 mF) providing black level
not used which leaves lines 14 through 21 for inserting sig- restoration at the video output when the output selected
nals, which may be different from field to field. In the U.S., line(s) is not being gated through.
line 19 is normally reserved for a vertical interval reference

7
Typical Applications

TL/H/9150 – 5
FIGURE 4. Video Line Selector

TL/H/9150 – 6
FIGURE 5. Multiple Contiguous Video Line Selector With Black Level Restoration

8
9
LM1881 Video Sync Separator
Physical Dimensions inches (millimeters) Lit. Ý 107636

Molded Small Outline Package (M)

Order Number LM1881M
NS Package Number M08A

Molded Dual-In-Line Package (N)

Order Number LM1881N
NS Package Number N08E
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