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AND9218/D 5 Key Steps To Designing A Compact, High Efficiency PFC Stage Using The NCP1602
AND9218/D 5 Key Steps To Designing A Compact, High Efficiency PFC Stage Using The NCP1602
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APPLICATION NOTE
Introduction
AND9218/D
Rfb2
RSENSE
DRV
4
CS/ZCD
CZ
EMI
Filter
AC Line
VIN
CIN
RZ
CP
RCS2
RCS1
RCS0
IL
GND
VCTRL
L1
FB
VCC
D1
Rfb1
CBULK
VBULK
Load
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AND9218/D
STEP 1: DEFINE THE KEY SPECIFICATIONS
LL
HL
K CSV LL
2
K CSV HL
2
138 @ 1.392
+ 135.9 V rms (eq. 1)
2
138 @ 1.801
+ 175.8 V rms (eq. 2)
2
V line,rms
boH
V line,rms
boL
K CSV boH
2
K CSV boL
2
+ 80 V
(eq. 3)
+ 72 V
(eq. 4)
Pin,avg
HL
V line,rms
2L
@ T on,max
(eq. 5)
The smaller the inductor, the higher the PFC stage power
capability. Hence, L must be low enough so that the full
power can be provided at the lowest line level:
Inductor Selection
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AND9218/D
Lv
Vline,rms
2
LL
2 @ P in,avg
@ T on,max
(eq. 6)
max
IL,pk
max
+ 2 @ 2 @
Pin,avg
max
V line,rms
(eq. 7)
LL
max
IL,pk
max
(eq. 8)
Lv
IL,pk
max
+ 2 @ 2 @
IL,rms
max
170
^ 5.3 A
90
P bridge + 2 @ V f @
(eq. 9)
5.3
^ 2.2 A
6
90 2
@ 8.5 m + 202 mH
2 @ 170
@ 8.5 m + 202 mH
f SW +
@ 390 * 2 @ 90
^ 80 kHz
4
+ @ R DS(on) @
3
1.8 @ V f
V line,rms
P out
@ h
(eq. 13)
1*
P out,max
h @ V line,rms
8 2 @ V line,rms
3p @ V out,nom
LL
LL
(eq. 14)
(eq. 10)
(eq. 11)
2 @ 90
V line,rms
2 P out
2 p @ h
(eq. 12)
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AND9218/D
nearly 0.4 A, the diode conduction losses are in the range of
0.4 W (assuming Vf = 1 V). PDIODE = 0.4 W
C bulk w
pk*pk
P out,max
C bulk @ w @ V out,nom
I c,rms
(eq. 15)
^ 42 mF
2 @ P out,max @ t HOLD*UP
2
V out,nom * V out,min
max
(eq. 18)
(eq. 19)
P
32 2
@
9p V
P
* V
in,avg max
@ V out,nom
line,rms LL
out,max
out,nom
(eq. 16)
^ 87 mF
C bulk w
399 2 * 350 2
dV out
2 @ 160 @ 10 m
32 2
170
@
90 @ 399
9p
160
399
(eq. 20)
^ 1.06 A
(eq. 17)
2It
I FB +
V REF
R fb2
2.5
R fb2
(eq. 21)
1
150 @ R fb1 R fb2 @ f line
V out,nom
V REF
*1
(eq. 22)
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AND9218/D
voltage is processed by the NCP1602 in order to get an
internal voltage representative of the line voltage value.
The NCP1602 uses this information to perform a 2-level
feed-forward function: in high-line that is detected when
Vline,rms happens to exceed (Vin,rms )HL , the PWM gain is
Loop
Gain
()
Vline,rms (V)
(Vin,rms)BOH
e.g.: 80 V
(Vin,rms)LL
e.g.: 136 V
(Vin,rms)HL
e.g.: 176 V
Figure 2. 2-Step Feed-Forward Limits the Loop Gain Variation with Respect to Line
640000 @ L @ V out,nom
(eq. 23)
V in,rms @ R load
@
1)s@
1
R load@C bulk
2
V in,rms @ R load
1920000 @ L @ V out,nom
(eq. 24)
@
1)s@
1
R load@C bulk
2
Where:
Cbulk is the bulk capacitor.
Rload is the load equivalent resistance.
L is the PFC coil inductance.
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AND9218/D
VCONTROL
VOUT
ICONTROL
R1
C2
C1
Rfb1
OTA
FB
To PWM
Comparator
Rfb2
+
VREF
R1 C1
R 0 C 1 ) C 2
1)
@
1
sR 1C 1
1 ) sR 1 @
C 1C 2
C 1)C 2
(eq. 25)
Where (R0 = Vout,nom / (Vref V GEA )), GEA being the 200-mS
error amplifier transconductance gain, Vout,nom , the bulk
nominal voltage and VREF, the OTA 2.5-V voltage reference.
C2 +
C1 +
R1 +
V line,rms
2
LL
1
^ 2.4 Hz
p @ R load,min @ C bulk
G0 +
90 2 @ 950
640000 @ 200 @ 10 *6 @ 390
@ R load,min
(eq. 26)
640000 @ L @ V out,nom
C2 +
G 0 @ tan p * f m
2
^ 154
154 @ tan p * p
2 3
(eq. 27)
2 @ p 2 @ f c @ R load,min @ C bulk @ R 0
G0
2 @ p @ fc @ R0
C1 +
* C2
* C2 ^
R load,min @ C bulk
2 @ C1
R1 +
Where:
(Vline,rms )LL is the rms voltage of the line when at its lowest
level (90 V in our case).
G0 is static gain at the lowest level of the line ((Vline,rms )LL ).
V out,nom
P out,max
950 @ 136 @ 10 *6
2 @ 2.2 @ 10 *6
154
2 @ p @ 15 @ 780 @ 10 3
399 2
^ 995
160
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AND9218/D
When the feedback network is properly designed and
correctly connected, the bulk voltage cannot exceed the
level set by the Soft OVP function (Vout,sovp = 105%
Vout,nom ). If soft OVP threshold is reached, for example
during no-load start-up, the on-time is gradually reduced
instead of disabling the drive pin (tON = 0) hence the name
soft. The FOVP threshold is set 2% higher than the soft OVP
comparator.
R CS1 ) R CS2
R CS2
V mains,rms @ 2
Vmains,rms @ 2
R CS1 ) R CS2
(eq. 32)
With:
RCS1 = 5.1 MW + 240 kW + 240 kW
RCS2 = 39 kW
We get:
For Vmains,rms = 86 V this will give PCS,STDBY = 2.6 mW
For Vmains,rms = 110 V this will give PCS,STDBY = 4.3 mW
For Vmains,rms = 230 V this will give
PCS,STDBY = 18.8 mW
For Vmains,rms = 265 V this will give
PCS,STDBY = 25.0 mW
(eq. 28)
(eq. 31)
(eq. 29)
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AND9218/D
Bench experiments have proven SMD1206 & 0805
superiority, parasitic capacitance wise, over trough hole
resistors for RCS1 , RCS2 and RCS0 resistors.
RCS0 must be placed as close as possible to CS/ZCD pin
voltage and RCS1 and RCS2 as close as possible to RCS0 .
PCB traces connecting the RCSi resistors must be kept
as short as possible, the width of the trace being as small
as possible (minimum parasitic capacitance)
It is wise to keep a safety distance of 1 cm between the
high value resistors of the CSZCD brige and DRV, Vin ,
Vdrain copper traces to avoid coupling.
Note than while decreasing the value of RCS1 and RCS2 ,
RCS0 must be increased in order to meet the 500-ns time
constant made with RCS resistor and CCS total capacitance.
V line(t)
K CS
(eq. 33)
DRAIN
RSNS
RSNS
VSNS
RCS1
RCS0
DRVBAR
CS/ZCD Pin
Re-Shaping
Filter
CSNS
CSNS
VCSint
CCS
DRV
ZCD
RF
RCS2
CF
SOURCE
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AND9218/D
how internal brown-out reference voltages translate to line
rms voltage thresholds.
V line,rms
V line,rms
BOH
BOL
K CS @ V BOH
2
K CS @ V BOL
2
143.1 @ 0.819
+ 83 V
2
(eq. 34)
143.1 @ 0.734
+ 74 V
2
(eq. 35)
V line,rms
Where:
VBOH is the 819-mV upper brown-out internal threshold.
VBOL is the 734-mV lower brown-out internal threshold.
HL
K CS @ V HL
2
143.1 @ 1.801
+ 182 V
2
(eq. 36)
V line,rms
LL
K CS @ V LL
2
143.1 @ 1.392
+ 141 V
2
(eq. 37)
X2 Capacitors Discharge:
RX1 and RX2 are designed for safety considerations. In
general, they must be selected so that the series combination
of (RX1 + RX2 = 2RX ) form with the X2 EMI capacitors a time
constant less than 3 s (?? Habituellement, la norme impose
une constant de temps de 1 s). In our case, two 1-MW
resistors (RX1 = RX2 = RX = 1 MW) are implemented so that
with the selected X2 capacitors, it leads to a 1.8-s discharge
time constant, which offers a comfortable margin.
0.5
R sense +
IL,pk
(eq. 38)
max
V line,rms
LL
4 2 @ P in,avg
K CS +
(eq. 39)
90
^ 0.094 W
4 2 @ 170
(eq. 40)
PRcs
max
4
@ R sense @
3
1*
Pin,avg
max
V line,rms
8 2 @ V line,rms
3p @ V out,nom
LL
LL
R CS2
(eq. 42)
max
R CS1 ) R CS2
V CSint(t) +
1
@ V drain(t)
K CS
(eq. 43)
V *(t) +
(eq. 41)
1
@ V in(t)
K CS
(eq. 44)
1
@ V drain(t)
V )(t) +
K CS
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AND9218/D
The ZCD digital signal resulting from the comparison
Vin (t) and Vdrain (t) is used for synchronizing the power
MOSFET turn-on. The power MOSFET turn-on event is
synchronized with the falling edge of ZCD signal.
Vdrain
5.1 MW/
500 V
RCS1a
240 kW
RCS1b
240 kW
RCS1c
ZCD
RCS0
DRV
CS/ZCD
Re-Shaping
Filter
10 kW
39 kW
CSint
Low Pass
Filter
CCS
RCS2
DRV
Vsource
80 mW
Rsense
K CS +
N prim
N aux
R CS1 ) R CS2
R CS2
(eq. 45)
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AND9218/D
Naux / Nprim = 0.1
Caux
Vdrain
Raux
Vaux
100 W
47 nF
Daux1
1N4148
300 kW
RCS1
ZCD
RCS0
DRV
CS/ZCD
Re-Shaping
Filter
27 kW
22 kW
RCS2
Line Voltage
Extraction
for ZCD
CCS
Vsource
80 mW
Rsense
Figure 6. CS/ZCD Circuitry using Auxilliary Winding Voltage with Typical Components Values
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AND9218/D
SUMMARY OF THE MAIN EQUATIONS
Table 1. DESIGN STEPS TABLE
Step
Step 1:
Key
Specifications
Components
Formula
Comments
fline : Line frequency. It is often specified in a range of 4763 Hz for 50 Hz/60 Hz applications.
(Vline,rms )LL : Lowest Level of the line voltage, e.g., 90 V.
(Vline,rms )HL : Highest Level for the line voltage (e.g., 264 V in many countries).
(Vline,rms )BOH : Brown-Output Line Upper Threshold. The circuit prevents operation until the line rms voltage exceeds
this level.
Step 2:
Power
Components
Input Diodes
Bridge Losses
P bridge + 2 @ V f @
Inductor
MOSFET
Conduction
Losses
(P on) max
Bulk Capacitor
Constraints
C bulk v
max
1*
V line,rms
P out
@ h
In our
application:
90 2
@ 12.5 m + 295 mH
Lv
2 @ 170
@ T on,max
max
Pin,avg
IL,pk
IL,pk
max
V line,rms
dV out
pk*pk
IL,rms
max
P out,max
h @ V line,rms
LL
3p @ V out,nom
LL
V out,nom * V out,min
in,avg max
P
* V
@ V out,nom
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5.3
^ 2.2 A
6
2 @ P out,max @ t HOLD*UP
max
@ w @ V out,nom
line,rms LL
170
^ 5.3 A
90
+ 2 @ 2 @
8 2 @ V line,rms
P
32 2
@
9p V
max
LL
P out,max
C bulk w
I c,rms
max
4
+ @ R DS(on) @
3
LL
+ 2 @ 2 @
IL,rms
1.8 @ V f
2 @ P in,avg
max
V line,rms
Vline,rms
Lv
IL,pk
2 P out
2 p @ h
out,max
out,nom
AND9218/D
Table 1. DESIGN STEPS TABLE (continued)
Step
Components
Step 3:
Bulk Voltage
Monitoring
and
Regulation
Loop
Resistor
Divider
Formula
R fb2 +
Compensation
G0 +
C2 +
V REF
*1
1
150 @ R fb1 R fb2 @ f line
V line,rms
2
LL
@ R load,min
640000 @ L @ V out,nom
G 0 @ tan p * f m
2
2
2 @ p 2 @ f c @ R load,min @ C bulk @ R 0
C1 +
G0
2 @ p @ fc @ R0
* C2
R load,min @ C bulk
R1 +
OVP and UV
OVP 2
2.5
I FB
V out,nom
R fb1 + R fb2 @
C fb v
Comments
2 @ C1
V out,OVP2x + K CS @ V OVP2x
Step 4:
Input Voltage
Sensing
Input Voltage
Sensing
K CS +
V line,rms
R CS1 ) R CS2
R CS2
BOH
V line,rms
BOL
V line,rms
HL
V line,rms
LL
K CS @ V BOH
2
K CS @ V BOL
2
K CS @ V HL
2
K CS @ V LL
2
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AND9218/D
Table 1. DESIGN STEPS TABLE (continued)
Step
Components
Step 5:
Current Sense
Network
Input Voltage
Sensing
Formula
R CS +
PRcs
max
V line,rms
1*
nn
Zero Current
Detection
R ZCS u
aux
p
Current
Controlled
Frequency
Fold-Back
R FF +
max
Pin,avg
V line,rms
3p @ V out,nom
LL
LL
V CL(pos)
R OCP
112 @ L @ I line
BOH
th
1
150 @ I line @ R FF
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@ V out,nom * V CL(pos)
25 2 @ V line,rms
C FF v
max
8 2 @ V line,rms
5 mA )
LL
4 2 @ P in,avg
4
@ R CS @
3
Comments
16
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Earth
C3c
C3b
C3a
S2b
86265 V rms
F1
S2a
CM1
VLINE
C5a
220 nF
400 V
C1 1 nF Type = Y
C2
1 nF
Type = Y
R1 1 MW
R2 1 MW
IN
C2
22 nF
Type = X2
U1
GBU406
220 nF Type = X2
C5b
220 nF
400 V
VIN
S1b
D4
1N4148
Socket for
External VCC
Power Source
S1a
R6
22 W
D3
1N4148
L2
200 mH
(np/ns = 10)
C7
22 mF
50 V
R5
2.2 W
D2
1N5406
R10
10 kW
DZ2
33 V
R3
80 mW
3W
Q1
IPA50R250
D1
MUR550
C6a
68 mF
450 V
Rth1
B57153S150M
C6b
68 mF
450 V
BULK
Vcc
GND
Vsource
Vbulk
DRV
Vdrain
Vaux
AND9218/D
(Detailed Schematic for our 160-W Evaluation Board, Universal Mains Application)
SCHEMATICS
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C8
1 nF
R11
27 kW
C9
2.2 mF
R12
22 kW
C10
220 nF
R27
0R
C11
NC
C13
100 nF
DRV
CS/ZCD
Top View
VCC
GND
FB
1
R27 is used
as a strap
VCTRL
R10
1800 kW
R9
1800 kW
R8
680 kW
S3
R36
NC
R31
10 kW
R32
4.7 MW
R33
1 MW
R34
NC
R42
NC
R39
NC
R30
0W
C12
NC
Q2
BSS127
R37
NC
R38
NC
R7
0W
R24
240 kW
D5
NC
R41
NC
R22
5.1 MW/
500 V
L2
200 mH
(np/ns = 10)
R40
NC
R21
39 kW
R23
240 kW
D6
NC
C30
NC
GND
DRV
Vsource
Vdrain
Vcc
Vbulk
Vaux
AND9218/D
Figure 8. Application Schematic for ZCD Sensing using Power MOSFET Drain Voltage Control Section
AND9218/D
Figure 9. NCP1602 Low Profile Evaluation Board Top View Showing Power Circuitry
Figure 10. NCP1602 Low Profile Evaluation Board Bottom View Showing the Control Circuitry
CONCLUSIONS
This paper summarizes the key steps when dimensioning
a NCP1602driven PFC stage. The proposed approach
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AND9218/D
REFERENCES
[3] Joel Turchi, Compensating a PFC stage, Tutorial
TND382/D available at:
http://www.onsemi.com/pub_link/Collateral/
TND382D.PDF.
[4] NCP1602/D Data Sheet,
http://www.onsemi.com/pub_link/Collateral/
NCP1602D.PDF.
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AND9218/D