Simstd Apr 2003 Hints

Hints, Tips and Solutions
Colin Shaw, Applications and Support Engineer
Q. How do I make my long simulation more memory to ground to these nodes to allow spice to achieve a DC
efficient ? solution .OPTIONS DEPATH =<val> .The spiceusr1.pdf in
chapter 2.12 contains options broken up into categories like
When you run a long simulation time analysis the evalu-
convergence and we welcome any customer feedback on
ated time points are normally all held in memory until
the manual information.
the end time is reached. All the data is then written out to
the output rawfile. This means a large amount of system
memory can be used up and also has to be tracked. If in Q. I kill my SmartSpice program but the license is not
the input deck the line “.OPTIONS RAWPTS=300 POST” available in Linux ?
is included then as soon as the maximum number of When you invoke SmartSpice you can run it in the Fore-
points is reached given by “RAWPTS=300” then all the ground or the background by use of the “&” character at the
vector data is saved to the raw data output file and the end of the command line. Programs run in the background
memory is free to be re-used. In this way the output raw- return the prompt straight away to the invoking window,
file is incrementally increased in size every time this limit programs run in the foreground wait for the completion
is reached. The memory required by the simulation run is of the program to return to the prompt. If the program
therefore reduced, and with less memory to manage, the is run in the foreground and then <cntrl>”C” is done the
simulation is run faster. This is particularly useful on the operating system still holds onto the process hence License
PC platform where some of the memory is required for is not available. To put a process into the background the
the operating system and RAM size is less than 1Gig. <cntrl>”Z” should be done AND then the command “bg”
to place in the background and the system will release the
Q. What is the difference between .MODIF & .ALTER process. The License is therefore available for the next ver-
for simulation run variance ? sion of SmartSpice. ( There is a License time-out feature
but this will take a while to release the License )
The .ALTER is used to globally change the circuit topol-
ogy like slotting in another sub-circuit or changing a
component. This change in the circuit is like submitting Q. I know SPICE is an Analog simulator but can I gen-
a new deck and can be incorporated in a distributed erate a digital source ?
system among a group of computers to get maximum There are 2 steps to generating a digital source, first the wave-
utilization of the resources. The .MODIF is more for form timing and second the pulse train of “0”’s and “1”.
changing parameter values associated with a model etc.
A SPICE input deck example is:
Q. My simulation fails with no convergence what extra Digital source config.

information can I obtain ?
* PWLFILEDESC.
The spice simulation of a circuit is based on a good model .param tri=150ps tfi=150ps
of the elements and sensible circuit construction. If you * PWLFILEDESC format is:
include the line “.OPTIONS EXPERT” you will get a lot * ( data_type start delay vlow vhigh fall
of reporting turned on showing model card parameter rise )
evaluation and floating nodes of the circuit. It would be * data_type= 1 - time current pairs, = 2
sensible to cut down the simulation time before turning time voltage pairs
this option on to save too much duplication of the errors *
everytime they are encountered. This reporting gives the vin inp 0 pwlfiledesc( 2 0 3ns 0v 3.3v
user more information to construct a better simulation ‘tri’ ‘tfi’ ) pwlfile test3.dat
deck. Commonly the model construction can be at fault
and this option allows the user to go back to his model pro- vcc 0 vss dc -3.3v
vider with highlighted problem areas. The other common
m1 2 inp vss vss pm w=32u l=1.6u
problem is having an isolated section of circuitry without a
m2 2 inp 0 0 nm w=10u l=1u
DC path to ground. This can happen if a section of circuitry
C1 2 0 0.01f
is connected only through a set of capacitance elements
for example. Here the user will need to add conductance
The Simulation Standard Page 10 April 2003

.MODEL NM NMOS LEVEL = 49
.MODEL PM PMOS LEVEL = 49
.tran 0.1ns 50ns 0.1ns

.print v(inp) v(2)
.temp 125
.option nomod
.END
and the referenced file (test3.dat) contains the digital
string “010110010”
What noise analysis can I do on my circuit in SmartSpice?
There are 3 ways to take account of noise in your circuit.

First there is the traditional .NOISE analysis used to
calculate the noise of each component. From there the
Figure 1. Digital source - input and circuit output.
spectral density is obtained and the integrated noise
over the specified frequency range used to calculate the
output and the input referred noise. Second there is the operating region for all device geometries. Sometimes
.TRAN NOISE which calculates the noise contributions there is too much variation in the output characteristics
of each circuit node and solves the stochicometric set of to be covered by one continuous model parameter set
equations for each time point in the transient analysis. e.g. “straight” and “dog-bone” layout designs which
And finally there is a new spice element “N” introduced contain very different electric field patterns. The total
in SmartSpice 2.3.8.C, and higher, to allow users to inject operating region is therefore broken up into sub-sections
noise at a particular circuit node. This noise is in addi- and a model produced for each of these subsets of device
tion to the element sources of noise and allows for contri- geometry. This is a binned model where each region is
butions like substrate referred noise from other parts of a different set of model card values for a smaller range
the circuit and general circuit succeptability to external of device properties like width, length and temperature.
noise sources. In this way a group of model card parameter sets can
be used to cover a wide variation in say gate width and
length variations not possible from a single scaleable
Q. My long simulation run consumes all resources and
model. In the simple case these bins are ranges of Width
then freezes ?
and Length transistor geometries that say what model
This happens when you use a PC system with less than card parameter set should be used. The only problem
1Gig of RAM or a small amount available hard disc space with this approach is a discontinuity at the boundary of
and a very long simulation time recoding all circuit node one model set to another and can be thought of as trying
activities. A new feature “.OPTIONS SAFEMODE” was to approximate a curve with a set of straight lines. Your
introduced to warn of this happening and it stops the error is because the device geometry is not covered by
simulation when either the hard disc space or the avail- any of the specified ranges in the model library. Typi-
able memory gets below 50Megs. It is then up to the user cally the binned model will have a model name of say
to close other programs and free more resources or con- nch.1, nch.2, nch.3 etc. and you device geometry is not al-
tinue at risk running out of space. The other ways are to lowed for in the say Lmin to Lmax range of any of these
limit the simulation time to something more reasonable or binned model sections.
limit the vectors that are saved rather than having every-
thing saved even circuit nodes that are not critical. To do
this instead of the “.SAVE ALL” you can use 2 pre-defined
macros to record vectors from part of the whole circuit.
Call for Questions
Xx - defines If you have hints, tips, solutions or questions to contribute,
please contact our Applications and Support Department
Phone: (408) 567-1000 Fax: (408) 496-6080
Q. My simulation fails because SmartSpice cannot e-mail: support@silvaco.com
find a binned model, what does this mean ?
Hints, Tips and Solutions Archive
Normally when a MOS model is extracted for a range of Check our our Web Page to see more details of this example
plus an archive of previous Hints, Tips, and Solutions
devices it is scaleable over the range of device geometries
i.e. it is a continuous varying function over the required
www.silvaco.com
April 2003 Page 11 The Simulation Standard

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Hints, Tips and Solutions

Colin Shaw, Applications and Support Engineer

Q. My simulation fails with no convergence what extra Digital source config.

The Simulation Standard Page 10 April 2003

.tran 0.1ns 50ns 0.1ns

What noise analysis can I do on my circuit in SmartSpice?

There are 3 ways to take account of noise in your circuit.

April 2003 Page 11 The Simulation Standard

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