Integrated Electro-Thermal Simulation in ADS

Electro-Thermal Simulation and
Thermal Floor planning in ADS
Integrated Electro-Thermal
Solution and Floor Planner
Delivers Thermally Aware
Circuit Simulation
Agenda
• Introduction
- Heating in active device
- Thermal Problems in RFIC/MMIC Design
- Solutions: Traditional Approaches
- Solutions: A New Approach
• Part I - Case Study on Electro-Thermal Simulator in ADS

- MMIC PA Design Example
- Electro-Thermal Simulation
- Thermal and Electrical Results
• Part II - Thermal Floorplanner in ADS
• Conclusion
• Appendix
Page 2
Self Heating
Thermal Material κ (W/cm•K)
Conductivity GaAs 0.46
– First level text to come here lorem(κ is a function of T!) GaN 1.3
SiC 3.5
• Second level text here lorem Si 1.5
- Third level text lorem Ge 0.6
(This equation applies for a rectangular geometry with

– First level text to come here lorem Length and Width and substrate thickness)
• Second level text here lorem 1  L(W + 2tsub ) 

Rth = ln  
2 ( L − W )  W ( L + 2tsub ) 
Tdevice = Tambient + Rth * Pdiss

Thermal Resistance, in °C/W: Converts the power dissipated through
the device into the operating temperature of the device.
Electro-Thermal
Analysis Page 3
Mutual Heating
Parallel Devices
– First level text to come here lorem
• Second level text here lorem
- Third level text lorem
TOP VIEW 1 2 3
– First level text to come here lorem
• Second level text here lorem
Active Devices Thermal R’s

add in series
SIDE VIEW
IC Substrate
~10 °C/W
Thermal Epoxy
Heat Sink ~20 °C/W

or PCB w/
Thermal VIAs Values used in this
example work
Electro-Thermal
Analysis Page 4
Time Varying Heating
Thermal Network is modeled as a RC Single Time Constant Example (Rth/Cth1 only):
Network(s) for fast pulses  = R Cth Pulsed GSM Signal at 1/8 Duty Cycle
th th
Intrinsic Device
temp tracks RF
Intrinsic Device power burst well
~ns to us Pulse=580us
Rise=28 usec
Die or Wafer
~ms
Die + Device
temp delayed in
Package responding
~s
Thermal Time Constant: Time it takes for

the heat generated to build to steady state
or to dissipate
Electro-Thermal
Analysis Page 5
Thermal Considerations In PA Design
– Long Term Failure

Self Heating – Device Performance
Mutual Heating
Time Varying Heating – Thermal Stability
– Memory Effects
Electro-Thermal
Analysis Page 6
Designing For Long Term Reliability
−
Ea • Time to failure is log-related to
Arrhenius’ Equation
MTTF = Ce kT
General Form
junction temperature
(Mean Time to Failure) - Estimate of Tj crucial for reliability
• Verification is typically done using
accelerated lifetime testing (ALT)
- Testing typically on the order of
hundreds to thousands of hours
- Involves testing at higher device
temperatures
Nitronex GaN - Can involve also increasing device
Device current density / operating voltage
• IE: MTTF α Je-n
• MTTF Requirement
- Handset ~104 hours
- Base Station ~106 hours
http://www.nitronex.com/pdfs/AN-012%20Thermal.pdf
- Instrumentation / Aerospace >>106
Electro-Thermal
Analysis Page 7
Device Electrical Considerations
– GaAs HBT
• Moderate Power and Current Density
- Handset: Size/Cost
• Vbe (↓) vs. Temperature (↑)
• Beta (↓) vs. Temperature (↑)
- Different than standard Si BJT!
– GaN
• High Power and Current Density
• Base Station: Cooling System / Heatsink
- VGSQ (↑) vs. Temp (↑)
• Or IDS (↓) vs. Temp (↑)
Electro-Thermal
Analysis Page 8
Memory Effects
• Common causes of Memory Effects in Power Amplifiers:
- Bias Network Time Constants at Modulation Frequency
- Device Level Phenomena (Dispersion and Trapping)
- Electrothermal :
Electro-Thermal
Analysis Page 9
The Problem:
Thermal Effects Impact RFIC/MMIC Design
– High Power Devices
– + High Level of Integration
– = On-Chip Temperature Rise
– IC performance depends on device temperature
– Device temperature depends on:
• Power dissipation
• Layout position
• IC / packaging material thermal properties
– This is a nonlinear problem
• Thermal conductivities vary with temperature!

????
Page 10
Traditional Approach:
Self-Heating Models
• Many transistor models now

include self-heating effects
• Requires accurate extraction of
thermal parameters
• Does not include thermal coupling
between transistors
• Does not include impact on
nearby passive components
• Does not include impact of
packaging
Page 11
Stand-alone Thermal Solvers
• Requires user to manually

transfer…
- layout and expand to 3-D
- heat sources locations IC Thermal
- power dissipation values Design Analysis
- computed device temperatures
…and perform any required iteration
Page 12
Equivalent RC Thermal Network
– Extract thermal RC network from FEM

data, add to schematic
• Must be re-extracted for any layout
change
• Requires device models to have
thermal nodes
• Large device count make cause
slow extraction of RC network
• Large thermal networks may cause
significant slowdown
• Does not account for nonlinear
thermal properties
Page 13
Thermal Non-linearities
– The thermal problem
T
c =    T + g
t
(
c = specific heat J m 3  K )
 = thermal conductivi ty (W m  K )
g = heat sources W m 3( )
– c and  are both functions of temperature and spatial location
– g is a function of temperature, time and spatial location
Page 14
A New Approach – Full Electro-Thermal Simulation
Thermal
technology
files
TDEVICES
Circuit Simulator Thermal Simulator
Read temperatures Read power dissipation
Solve electrical equations Solve thermal equation
PDISS
Write power dissipation Write temperatures
Iteration loop is
done automatically
until powers and
temperatures are
self-consistent
Page 15
Electro-Thermal Simulation Results
• More accurate circuit simulation
results, showing performance
degradation due to temperature rise
• 3D temperature maps, providing

design insight, leading to more
robust layout designs
• Device temperature data, to

uncover potential reliability issues
and failures
Page 16
Thermal Solver Technology
• Provided by Gradient Design Automation

- Focused on IC thermal simulation
• Full-chip (high capacity) 3-D FEM temperature
simulation with device- and wire-level resolution
• Linux-based
• Proven for large digital and mixed-
signal applications Mixed-Signal IC
• Used by major IC companies

- On Semi, TI, AMD, …
• Works with any IC process
- GaAs, Si, SiGe, GaN, …
45nm Digital Block with 800k Transistors

http://www.gradient-da.com/resources/technical-papers.php
Page 17
Agenda
• Introduction

• Conclusion
• Appendix
Page 18
Case Study: Two Stage LTE PA
Two-Stage LTE PA
GaAsFET; uses EEsof DemoKit
Gain >25 dB
Pout > 25 dbm with Pin >1 dbm
Page 19
Gain >25 dB; Pout > 25 dBm @ Pin >1 dBm
Page 20
Two Stage LTE PA
Stage 1 FET
4 fingers
100 um wide
PDC=900 mW
Stage 2 FET
6 fingers
200 um wide
PDC=2100 mW
Page 21
Two Stage LTE PA – Layout
Thermal analysis using Rth calculations
Simple calculation of thermal resistance
RTH for each transistor
Assume power is dissipated uniformly
throughout the transistor’s channel
FET1 channel: 100 x 46.6 um: RTH = 168 K/W

Power dissipation = 900 mW
T=RTH × PDISS=168 K/W x 0.9W = 151C T1=25+151=176C
FET2 channel: 200 x 79.9 um: RTH = 98 K/W

Power dissipation = 2100 mW
T=RTH × PDISS=98 K/W x 2.1W = 206C T2=25+206=231C
Page 22
Two Stage LTE PA – Layout
Electro-thermal simulation
Page 23
Electrothermal Simulation Setup
Step 1 – Add an Electrothermal Controller to the schematic page
Page 24
Step 2 – Open the Electrothermal Controller and specify a few
parameters as shown below
Thermal
technology
Thermal
boundary
conditions
Page 25
Step 3 – Click the “Simulate button” and electro-thermal
simulation starts
Thermal profiles,
plots and data output
Simulate results are
automatically
displayed at the end
of simulation
Page 26
Thermal Profile @ Pin=0dBm
Simulation time = 6 minutes
8 point input
power sweep:
from -10 dBm

to +4 dBm
Page 27
Thermal Profile Max @ DC
Simulation time = 56 seconds
Page 28
Thermal Profile Max @ DC
Page 29
Electro-thermal Device Temperatures
Initial hand calculation with RTH predicted TFET1=176ºC and TFET2=231ºC
Electrothermal results TFET1=135ºC and TFET2=158-181ºC
Page 30
Electro-thermal On vs Off
3 dB loss in gain
Electro-thermal OFF
Electro-thermal ON
Page 31
HB Pin/Pout
Pin Vs Pout
Electro-thermal OFF
Electro-thermal ON
Page 32
HB Power Dissipation Vs Pin
Electro-thermal OFF
Electro-thermal ON
Page 33
Harmonics
Electro-thermal ON
Electro-thermal OFF
Page 34
Modify the Layout of FET2
Spread the fingers and place ground/thermal vias
• FET2 temperatures were too high for reliability
• RF performance no longer met specs
• Modify the layout of FET2 to spread the heat out and cool the devices
Initial Design Modified Design
Tmax
TFET1 =135C TFET2 =158-181C TFET1 =135C TFET2 =107-115C
Page 35
Modified Stage 2 FET Layout
Spread out fingers and place ground/thermal vias
Page 36
Thermal Profile of Modified Layout @ Pin=0dBm
Initial Design
TFET2 = 158-181C
Modified Design
TFET2 = 107-115C
FET1 Temp now

dominates at
135C
Page 37
Thermal Profile Max @ DC of Modified Layout
Page 38
Thermal Profile of Modified Layout
Page 39
Original layout TFET1=135ºC and TFET2=158-181ºC
Modified layout TFET1=135ºC and TFET2=107-115ºC
Page 40
Modified Design - Dashed Traces
Initial Design – Electro-thermal OFF

Initial Design – Electro-thermal ON
Modified Design – Electro-thermal ON
Page 41
Modified Design - Dashed Traces

Page 42
Modified Design
HB power dissipation

Page 43
Modified Design

Page 44
Mounted on a QFN Package
Page 45
Mounting the IC onto a Package
Layer summary:
725 µm plastic package k=1.0
5 µm metal stack on chip
100 µm GaAs substrate k(25)=46
150 µm copper lead frame k=401
Page 46
Thermal Profile of Modified Design and Package
Page 47
Thermal profiles of all layers – IC and package
Page 48
Original layout TFET1=135ºC and TFET2=158-181ºC
Modified layout TFET1=135ºC and TFET2=107-115ºC
Modified, packaged TFET1=141ºC and TFET2=116-120ºC
Page 49
Simulation results – S-parameters
Page 50
Simulation results – S21
Page 51
Simulation results – Pin / Pout
Page 52
Simulation results – HB power dissipation
Page 53
Simulation results – fundamental and harmonics
Page 54
Summary: ADS Electro-thermal Solution
• Applications: high power RFIC / ADS Schematic ADS Layout
MMIC design
• Deliver ‘thermally aware’ circuit
simulation results by including effects
of on-chip temperature rise
• Include effects of package and PCB
• Easy to set up and use from within
the ADS environment
• Works with all simulation types:
DC, AC, SP, HB, Transient, Envelope
Integrated Thermal Solver
• Available in ADS 2012
Page 55
Agenda
• Introduction

• Conclusion
• Appendix
Page 56
Part II
ADS Thermal Floorplanner
• Enables initial thermal analysis
early in the design process
• Based on layout-only thermal

simulation - No schematic
design or circuit simulation
required
• User inputs device layout,

location and estimated power
dissipation
• Results provide insight into heat

coupling and dissipation of
various device layout
configurations
Page 58
Running the ADS Thermal Floorplanner
Three steps
Three steps:
1. Floorplan setup
2. Add heat sources
3. Solve for temperatures
Page 59
Step1 – Floorplan setup
Initial grid seeding (default = 5)
Controls how many coarse uniform grid

points are placed in x and y (2N points in
x and y).
It is recommended to use a value
between 4 and 8.
Grid points are then added to resolve all
geometries. Thermal simulator will do
additional iterative refinement of the grid.
Number of mesh refinements (default=4)
Controls how many times the mesh

around the heat source is refined;
Increase this value when the heat source
temperature profile picture look fuzzy
Page 60
Step2 – Add heat source
1. Select Tools > Thermal Floorplanner > Add heat source
from the Layout view OR,
2. Click Add heat source from the Thermal Floorplanner

Setup dialog box.
3. Specify the Device name. The device name is used as an

identifier for the heat source array.
4. Specify the Total power dissipated as Power in Watts (or

dBm) or as Current and voltage.
5. Select the Heat layer from where you want to draw the
array.
6. Specify the dimensions (Width, Length, Pitch, Rows, and

Column) of the heat source array. Width and length have
the same units as the PDK process. Mostly, it is in microns
(um).
7. Click Ok and instantiate it on the Layout. The heat source

array is displayed.
Page 61
Step3 – Solve for temperatures
Select Tools > Thermal Floorplanner >
Solve for temperatures
Page 62
MMIC PA Demo 1.4 mm X 1.8 mm die
FET1 FET2
Heat sources only – No Vias
Page 63
FET1 FET2
Heat sources with Vias and Metals
Page 64
FET1 FET2
Heat sources with Vias and actual FETs
Page 65
FET1
Modified FET2
Heat sources with Vias and actual FETs
Page 66
FET1
Modified FET2
Heat sources with Vias, FETs, and full layout
Page 67
Mesa Resistor heat source
Page 68
Nicr Resistor heat source
Page 69
Summary
• Enables initial thermal analysis
early in the design process
• Based on layout-only thermal

simulation - No schematic
design or circuit simulation
required
• User inputs device layout,

location and estimated power
dissipation
• Results provide insight into heat

coupling and dissipation of
various device layout
configurations
Page 70

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Electro-Thermal Simulation and

Thermal Floor planning in ADS

• Part I - Case Study on Electro-Thermal Simulator in ADS

• Part II - Thermal Floorplanner in ADS

(This equation applies for a rectangular geometry with

• Second level text here lorem 1  L(W + 2tsub ) 

Tdevice = Tambient + Rth * Pdiss

Active Devices Thermal R’s

Heat Sink ~20 °C/W

Thermal Time Constant: Time it takes for

– Long Term Failure

– + High Level of Integration

– = On-Chip Temperature Rise

– IC performance depends on device temperature

– Device temperature depends on:

– This is a nonlinear problem

• Thermal conductivities vary with temperature!

• Many transistor models now

• Requires user to manually

– Extract thermal RC network from FEM

– c and  are both functions of temperature and spatial location

– g is a function of temperature, time and spatial location

• 3D temperature maps, providing

• Device temperature data, to

• Provided by Gradient Design Automation

• Used by major IC companies

45nm Digital Block with 800k Transistors

• Part I - Case Study on Electro-Thermal Simulator in ADS

• Part II - Thermal Floorplanner in ADS

FET1 channel: 100 x 46.6 um: RTH = 168 K/W

FET2 channel: 200 x 79.9 um: RTH = 98 K/W

from -10 dBm

FET1 Temp now

Initial Design – Electro-thermal OFF

Initial Design – Electro-thermal OFF

Initial Design – Electro-thermal OFF

Initial Design – Electro-thermal OFF

• Part I - Case Study on Electro-Thermal Simulator in ADS

• Part II - Thermal Floorplanner in ADS

• Based on layout-only thermal

• User inputs device layout,

• Results provide insight into heat

2. Add heat sources

3. Solve for temperatures

Controls how many coarse uniform grid

Number of mesh refinements (default=4)

Controls how many times the mesh

2. Click Add heat source from the Thermal Floorplanner

3. Specify the Device name. The device name is used as an

4. Specify the Total power dissipated as Power in Watts (or

6. Specify the dimensions (Width, Length, Pitch, Rows, and

7. Click Ok and instantiate it on the Layout. The heat source

Heat sources only – No Vias

Heat sources with Vias and Metals

Heat sources with Vias and actual FETs

Heat sources with Vias and actual FETs

Heat sources with Vias, FETs, and full layout

Mesa Resistor heat source

Nicr Resistor heat source

• Based on layout-only thermal