MITSUBISHI SEMICONDUCTORS <HVIC>

INA RY M81700FP
ELIM
on. ange.
ificati h
l spec ct to c
PR e: T h is
Notice parame
is n o
tric
t a finaare subje
li m its

Som
HIGH VOLTAGE HALF BRIDGE DRIVER

DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
M81700FP is high voltage Power MOSFET and IGBT mod-
ule driver for half bridge applications.

FEATURES LO 1 16 NC
¡FLOATING SUPPLY VOLTAGE ................................. 600V LGND 2 15 GND
¡OUTPUT CURRENT .................................................... ±2A
¡HALF BRIDGE DRIVER VCC 3 14 LIN

¡SOP-16 NC 4 13 SD

NC 5 12 HIN
APPLICATIONS VS 6 11 VDD
PDP. HID lamp.
MOSFET and IGBT module inverter driver for refrigerator, VB 7 10 NC

air-conditioner, washing machine, servomotor and general HO 8 9 NC

purpose.

NC:NO CONNECTION

PACKAGE TYPE 16P2N

BLOCK DIAGRAM

7 VB
UV DETECT
VDD 11 HV FILTER
LEVEL
SHIFT R Q
INTER R
VDD/VCC LOCK S 8 HO
HIN 12 LEVEL RQ PULSE
SHIFT GEN
S

VDD/VCC 6 VS
SD 13 LEVEL
UV DETECT 3 VCC
SHIFT
FILTER
UV signal
S RQ
VDD/VCC
DELAY S
LIN 14 LEVEL RQ
SHIFT 1 LO

GND 15
2 LGND

Mar. 2002
 MITSUBISHI SEMICONDUCTORS <HVIC>

INA RY M81700FP
ELIM
on. ange.
ificati h
l spec ct to c
PR e: T h is
Notice parame
is n o
tric
t a finaare subje
li m its

Som
HIGH VOLTAGE HALF BRIDGE DRIVER

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Conditions Ratings Unit
VB High Side Floating Supply Absolute Voltage –0.5 ~ 624 V
VS High Side Floating Supply Offset Voltage –0.5 ~ 600 V
VBS High Side Floating Supply Voltage VBS = VB-VS –0.5 ~ 24 V
–VS Allowable Offset Supply Voltage minus serge PW < 1µs –5 V
VHO High Side Output Voltage VS–0.5 ~ VB+0.5 V
VCC Low Side Fixed Supply Voltage –0.5 ~ 24 V
VLO Low Side Output Voltage –0.5 ~ VCC+0.5 V
VDD Logic Supply Voltage –0.5 ~ 24 V
VIN Logic Input Voltage HIN, LIN –0.5 ~ VDD+0.5 V
SD Shut Down Input Voltage –0.5 ~ VDD+0.5 V
LGND Low Side Return Offset Voltage VCC-LGND < 24V –5 ~ VCC+0.5 V
dVS/dt Allowable Offset Supply Voltage Transient ±50 V/ns
Pd Package Power Dissipation Ta = 25°C, On Board 0.88 W
Kq Linear Derating Factor Ta > 25°C, On Board –8.8 mW/°C
Rth(j-c) Junction-Case Thermal Resistance 50 °C/W
Tj Junction Temperature –20 ~ 125 °C
Topr Operation Temperature –20 ~ 75 °C
Tstg Storage Temperature –40 ~ 125 °C

RECOMMENDED OPERATING CONDITIONS

Limits
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
VB High Side Floating Supply Absolute Voltage VS+10 — VS+20 V
VS High Side Floating Supply Offset Voltage 0 — 500 V
VBS High Side Floating Supply Voltage VBS = VB-VS 10 — 20 V
VCC Low Side Fixed Supply Voltage 10 — 20 V
VDD Logic Supply Voltage 5 — 20 V
VIN Logic Input Voltage HIN, LIN 0 — VDD V
SD Shut Down Input Voltage 0 — VDD V
LGND Low Side Return Offset Voltage –5 — 5 V

PERFORMANCE CURVES

Thermal Derating Factor Characteristics

2.0

1.5

1.0

0.5

0
0 25 50 75 100 125
Temperature [ ]

Mar. 2002
 MITSUBISHI SEMICONDUCTORS <HVIC>

INA RY M81700FP
ELIM
on. ange.
ificati h
l spec ct to c
PR e: T h is
Notice parame
is n o
tric
t a finaare subje
li m its

Som
HIGH VOLTAGE HALF BRIDGE DRIVER

ELECTRICAL CHARACTERISTICS (Ta=25°C, VCC=VBS (=VB–VS)=VDD=15V, LGND=0V unless otherwise specified)

Limits
Symbol Parameter Test conditions Unit
Min. Typ. Max.
IFS Floating Supply Leakage Current VB=VS=600V — — 1 µA
IBS VBS standby Current — 0.4 0.7 mA
ICC VCC standby Current — 0.75 1.5 mA
IDD VDD standby Current — — 10 µA
VOH High Level Output Voltage IO=0A, LO, HO 13.8 14.4 — V
VOL Low Level Output Voltage IO=0A, LO, HO — — 0.1 V
VIH15 High Level Input Threshold Voltage HIN, LIN — 8.4 9.5 V
VIL15 Low Level Input Threshold Voltage HIN, LIN 6.0 6.8 — V
VIH5 High Level Input Threshold Voltage HIN, LIN (VDD=5V) — 3.1 4.1 V
VIL5 Low Level Input Threshold Voltage HIN, LIN (VDD=5V) 1.4 2.4 — V
VISDH15 Shutdown High Level Input Threshold Voltage SD — 8.4 9.5 V
VISDL15 Shutdown Low Level Input Threshold Voltage SD 6.0 6.8 — V
VISDH5 Shutdown High Level Input Threshold Voltage SD (VDD=5V) — 3.1 4.1 V
VISDL5 Shutdown Low Level Input Threshold Voltage SD (VDD=5V) 1.4 2.4 — V
IIH High Level Input Bias Current VIN=15V — 75 150 µA
IIL Low Level Input Bias Current VIN=0V — — 1.0 µA
VBSuvr VBS Supply UV Reset Voltage 7.5 8.6 9.7 V
VBSuvh VBS Supply UV Hysteresis Voltage 0.1 0.4 0.7 V
tVBSuv VBS Supply UV Filter Time — 10 — µs
VCCuvr VCC Supply UV Reset Voltage 7.5 8.6 9.7 V
VCCuvh VCC Supply UV Hysteresis Voltage 0.1 0.4 0.7 V
tVCCuv VCC Supply UV Filter Time — 10 — µs
IOH Output High Level Short Circuit Pulsed Current VO=0V, VIN=15V, PW<10µs — –2.5 — A
IOL Output Low Level Short Circuit Pulsed Current VO=15V, VIN=0V, PW<10µs — 2.5 — A
ROH Output High Level On resistance IO=–200mA, ROH=(VOH-VO)/IO — 10 13 Ω
ROL Output Low Level On resistance IO=200mA, ROL=VO/IO — 2.5 3 Ω
tdLH(HO) High Side Turn-On Propagation Delay CL=1000pF between HO – VS — — 350 ns
tdHL(HO) High Side Turn-Off Propagation Delay CL=1000pF between HO – VS — — 330 ns
trH High Side Turn-On Rise Time CL=1000pF between HO – VS — — 60 ns
tfH High Side Turn-Off Fall Time CL=1000pF between HO – VS — — 30 ns
tdLH(LO) Low Side Turn-On Propagation Delay CL=1000pF between LO – GND — — 350 ns
tdHL(LO) Low Side Turn-Off Propagation Delay CL=1000pF between LO – GND — — 330 ns
trL Low Side Turn-On Rise Time CL=1000pF between LO – GND — — 60 ns
tfL Low Side Turn-Off Fall Time CL=1000pF between LO – GND — — 30 ns
∆tdLH Delay Matching, High Side and Low Side Turn-On |tdLH(HO)-tdLH(LO)| — — 30 ns
∆tdHL Delay Matching, High Side and Low Side Turn-Off |tdHL(HO)-tdHL(LO)| — — 30 ns
CL=1000pF between HO – VS
tSD Shutdown Propagation Delay — — 350 ns
CL=1000pF between LO – GND

Mar. 2002
 MITSUBISHI SEMICONDUCTORS <HVIC>

INA RY M81700FP
ELIM
on. ange.
ificati h
l spec ct to c
PR e: T h is
Notice parame
is n o
tric
t a finaare subje
li m its

Som
HIGH VOLTAGE HALF BRIDGE DRIVER

FUNCTION TABLE (X: H or L)

HIN LIN VBS UV VCC UV HO LO SD Behavioral state
L L H H L L L LO = OFF, HO = OFF
L H H H L H L LO = ON, HO = OFF
H L H H H L L LO = OFF, HO = ON
H H H H * * L
X L L H L L L LO = OFF, HO = OFF, VBS UV tripped
X H L H L H L LO = ON, HO = OFF, VBS UV tripped
L X H L L L L LO = OFF, HO = OFF, VCC UV tripped
H X H L L L L LO = OFF, HO = OFF, VCC UV tripped
X X H H L L H LO = OFF, HO = OFF, SD = ON
Note : “L” state of VBS UV and VCC UV means that UV trip voltage.
* If both input signals are “H”, refer to TIMING DIAGRAM.

TIMING DIAGRAM
1.Input/Output Timing Diagram
When input signal (HIN or LIN) is “H”, then output signal (HO or LO) is “H”.
In the case of both input signals (HIN and LIN) are “H”, first coming input signal (HIN or LIN) “H” is only accepted.
Corresponding this signal, output signal (HO or LO) becomes “H”.
Corresponding the other signal (LIN or HIN), output signal (LO or HO) keeps “L”.

HIN

LIN

HO

LO

2.Shutdown Input Timing Diagram

When shutdown input signal (SD) is “H”, then output signals (HO and LO) are “L”.
Output signals (HO and LO) keep “L” by shutdown input signal (SD) is “L” until next input signal (HIN or LIN) is “H”.

Mar. 2002
 MITSUBISHI SEMICONDUCTORS <HVIC>

INA RY M81700FP
ELIM
on. ange.
ificati h
l spec ct to c
PR e: T h is
Notice parame
is n o
tric
t a finaare subje
li m its

Som
HIGH VOLTAGE HALF BRIDGE DRIVER

3.VCC (VBS) Supply Under Voltage Lockout Timing Diagram

VCCuvh (VBSuvh)
VCC (VBS)

VCCuvt (VBSuvt) VCCuvr (VBSuvr)

tVCCuv (tVBSuv)

LO (HO)

LIN (HIN)

4.Allowable supply voltage transient

Allowable high side floating supply voltage (VBS) transient or low side fixed supply voltage (VCC) transient are
below 50V/ms. In case VBS or VCC are started more than 50V/ms, output signal (HO or LO) may be “H”.

PACKAGE OUTLINE

16 9 1.27 0.76

1.27 MIN
5.3±0.1
7.8±0.3

7.62

F
1 8
2.1 MAX
G 10.1±0.1

1.8 0.1±0.1

0.25 MAX M
1.27 +0.10
0.4 –0.05
0.6±0.2

4°±4°
0.1 MAX
1.25

+0.05
0.2 –0.02
0.605
0.755 MAX Detail G Detail F

Mar. 2002