SpyGlass

QuickStart Guide

Contents

1. Reading-in a Design .................................................................................2

2. Analyzing Clocks, Resets, and Domain Crossings..........................................6

3. Analyzing Testability ................................................................................8

4. Analyzing SDC Constraints ...................................................................... 10

5. Analyzing Voltage and Power Domains ..................................................... 12

6. Viewing Reported Issues .......................................................................... 14

7. Reducing Reported Issues ........................................................................ 16

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SpyGlass QuickStart Guide

Reading-in a Design

Getting Started
Analyze and improve your designs quickly and easily using SpyGlass Predictive Analyzer.

Pre-Requisites

• RTL or netlist design data for the chip, IP block, or any part of the chip or IP
• A simulation script if possible, to define what source files are needed, in the proper order
• Build scripts for any VHDL libraries used
• Synopsys .lib files for instantiated gates and blocks

HDL Compatibility

• Add –verilog or –VHDL for Verilog or VHDL design files, respectively

• Add –87 to command-line, if using VHDL 87

Design Input: Verilog-XL/VCS Users

Provide exactly the command-line you would give to your simulator, changing the simulator
name to spyglass –verilog.

• Example: spyglass –verilog srcs/*.v –y ../mylib +libext... +define... +incdir+

• NOTE: SpyGlass can also read –f files

HDL Library Mapping

• HDL (Verilog and VHDL) library mapping can be achieved by spyglass –lib <logicalname>
<physical_directory> <other_args>

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Design Input: MTI Users

Translate your modelsim.ini file into libmap.f file as follows:

• The library mapping is specified using the following style, under: [LIBRARY] section L1 =
./L1_path --> -lib L1 ./L1_path
Translate your modelsim script file as follows:

• vmap L2 L2_path --> Put: -lib L2 ./L2_path into libmap.f file

• vcom -work LIB1 b.vhd c.vhd d.vhd --> spyglass -mixed -work LIB1 b.vhd c.vhd d.vhd -f
libmap.f
• vlog -work LIB2 b.v c.v d.v --> spyglass -mixed -enable_precompile_vlog -work LIB2 b.v c.v
d.v –f libmap.f

Design Input: NCSim Users

Translate each of the following commands in your cds.lib/hdl.var into libmap.f file as follows:

• DEFINE foo <path> --> -lib foo <path>. Add to file libmap.f
Now, translate your NCSim script commands as follows:

• ncvhdl -WORK <lib> ..vhdl files.. --> spyglass -mixed work <lib>…vhdl files…–f libmap.f
• ncvlog -WORK <lib> ...verilog files --> spyglass -mixed -enable_precompile_vlog work <lib>
..verilog files ..-f libmap.f
• NCSim, default is VHDL87 while for SpyGlass, it is VHDL93, hence:
- ncvhdl ent87.vhd.... --> spyglass -87 ent87.vhd..., and,
- ncsim -V93 ent93.vhd.. --> spyglass ent.93.vhdl...

HDL Library Compilation

• Compile a library using SpyGlass in normal manner with –lib option to specify library:
• spyglass <args> –lib <logicalname> <libdirectory> -work <logical name>
• Add –enable_precompile_vlog while compiling Verilog libraries
• Use –dump64bit option to create libraries for 64 bit platforms
• Do not move compiled libraries

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• Libraries cannot be shared between 32-bit and 64-bit platforms

Design Inputs: DC/PT Shell Scripts

• Obtain the list of all Verilog and VHDL files, by looking at commands:
- read_verilog/read_vhdl (for TCL shell scripts)
- read –format verilog / read –format vhdl - for tool’s native shell scripts (–format could also
be written as –f)
- analyze –format vhdl “<design_files>”/analyze –format verilog “<design_files>” (DC
command to analyze VHDL and Verilog files). The equivalent SpyGlass commands for
analyzing the VHDL and Verilog design files are as follows:
%> spyglass –vhdl
%> spyglass -verilog

- the files can be specified on the command line, or, put into a file, which is then specified
as –f option to SpyGlass

Resolving Library Elements

Required for most advanced checks (Clocks, DFT, Constraints, LP)

• For instantiated cells, for each library used:

- Select Appropriate library .lib (e.g., a.lib)
- Run->Library Compiler (spyglass_lc –mixed –gateslib<a.lib>)
- Note .sglib file created (e.g., a.sglib)
- Add –sglib option to Run->Options-(spyglass <other_command-line_options> -sglib a.lib

Handling Designware™
Design Ware Components

• Set DC_PATH variable to a Design Compiler installation: setenv DC_PATH

/net/DC2003/linux
• Add –dw switch to the command-line while running SpyGlass

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Check your Setup

Select Audit/Audit-RTL and run to check the correctness of basic design setup.

Troubleshooting
Syntax, elaboration, or out-of-date errors:
Verilog: Re-check the file order. Include files may be out of order. Also, the files containing
parameters should be placed in the file list before the files that reference those parameters.
VHDL: While compiling, check file order, if not sorted, add –sort on the command-line
Sorting via GUI: Select the option in GUI – Window->Options-Verilog or VHDL->sort

• Add option -hdlin_translate_off_skip_text to command line if translate_off pragma used

Multiple top-levels in design view:

• Multiple tops are usually an indication of something wrong (For example, missing hierarchy).
Multiple tops may also indicate that testbench files have been inadvertently included in the
file list
• –top option can still be used to select only the top-level you want to run (through SpyGlass):
-top <top-design-name>
Blackboxes:

• If design is showing blackboxes (Rule: DetectBlackBoxes), check, if they are intentional, or,
something has been missed from the design description
Hang or abnormal exit:

• Re-run, adding –w switch and note where problem occurs (spyglass.log will be helpful). If in
analysis or synthesis, note module/entity name and add command line option –stop <module
name>
• If problem in a rule, add command-line option –ignorerules <rulename>
• If design contains large inferred memories, use –handlememory option

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Analyzing Clocks, Resets, and Domain

Crossings

Getting Started

• Find clocks and resets in an unfamiliar design

• Find domain crossings and check synchronization techniques used

Pre-Requisites

• Ability to read-in the design for simpler (for example, BlockDesign/Create) analysis
• Compiled gate library for instantiated library cells
• SDC file or SpyGlass constraints file describing clocks and resets

Reading Clocks from an SDC File

• Create an SGDC file containing sdcschema –file <your_sdc_file> (e.g., sdcschema top.sdc)
• Add –sdc2sgdc option to SpyGlass run
• Translation converts clocks and set_case_analysis statements and will use them for CDC
analysis
• Translated file can be viewed under spyglass_reports/sdc2sgdc

Creating an SGDC Constraints File

• Make sure no constraints files are currently included in the analysis

• Select Methodology Clocks, template Find Clocks, then run,
cat spyglass_reports/clock-reset/auto*.sgdc > constraints.sgdc

• Review file and fix clock or reset definitions if required

• Change domain labels to reflect which synchronous domain each clock is in

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• If you have mutually exclusive clocks (for example, test, system), add set_case_analysis
constraints to SGDC on controlling signal
• Add constraints.sgdc to analysis using File >Source > Constraints

Synchronization Checks
Select Sync_checks template and run. Check Clock_sync01 violations. Control analysis:

• Parameters: –synchronize_cells , synchronize_data_cells – pass information about custom

sync cells
• Use strict_sync_check=yes option to allow logic between sync flops only if the logic can be
reduced to a wire under set_case_analysis
Reports Clock-Reset-Summary/Details are useful to analyze results

Schematic Debugging
If a rule shows a gate in policy tab, it has a related schematic view. Click the Incremental
Schematic icon to bring up the incremental schematic. Cross-probe from RTL to schematic
(double-click a signal in RTL) or from schematic gate to RTL (single-click an instance in schematic).

Analysis and Troubleshooting

If expected crossings are missing:

• Check Report >Clock-Reset-Summary for flops which will not be checked – either
unconstrained or constant D-input
• Check the parameter one_cross_per_dest. By default, only one crossing per destination is
reported
If too many domain crossings are reported:

• Check Clock-Reset-Summary report for list of domain crossings by clocks

• Eliminate any which should not appear by fixing your SGDC
- Tag Clocks in the same domain with same –domain name
- Use case analysis or cdc_false_path to eliminate crossings between non-interacting clocks
(see Clock-Reset documentation)
• Use waivers to drop violations such as violations in previously validated IPs
- Add waive –ip <ip_du_name> in your SGDC file

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• Set options to filter out groups of violations globally:

- Set allow_combo_logic to yes if OK to have combination logic before the crossing
- Set sync_reset to yes if you allow synchronous reset on a synchronizer
- Set cdc_reduce_pessimism to ignore crossing on black-boxes or destinations with hanging
nets
- Set clock_reduce_pessimism to prevent clock propagation through mux select or latch
enable pins
• Remove false violations case by case using cdc_false_path constraint:
- cdc_false_path –from <R1_qpin> -through <net> -to <R2_qpin>
- cdc_false_path –from <clk> to remove all violations with source registers clocked by clk

Analyzing Testability

Getting Started
Find and fix testability problems before they become difficult to resolve at the gate level through
SpyGlass’ unique DFT capabilities.

Pre-Requisites

• Ability to analyze design for Clock-Reset

• Create models for PLL and IO cells if required
• Create test constraints for memory and other blocks

Creating Models for PLLs

• If PLL has an external bypass in testmode, no action is required

• Otherwise, replace the PLL model with a reduced model which will propagate test clock to
outputs correctly in testmode (can be a simple gated buffer model)
- Use only 4-state (01XZ) logic
• Use module_bypass SGDC constraint to define input -> output path of black box

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Creating Models for IOs

• If IO is synthesizable, no action is required

• If you are OK with analyzing from the inbound side of the IOs, no action is required
• Otherwise, replace each IO model with a reduced model which will propagate the pad
signal to inbound signals correctly in testmode
- Use only 4-state (01XZ) logic

Creating Models for Memories, Other IP

For each model:

• If IP has an external bypass in testmode, no action is required

• If IP is known to make provision for upstream and downstream scan, add scanwrap
constraint:
scanwrap –name <IPname>

• If you want to accurately test propagation of testmodes to memory, use DFT memory related
constraints (see DFT documentation)

Updating the SGDC Constraints File

• Start with the same constraints file used for Clocks analysis
• For each clock used as a testclock, add option –testclock to that constraint, e.g.,
clock –name CLK –domain domain1 –value rtz -testclock

• Add testmode constraints to reflect correct settings for testmode signals, e.g.,
testmode –name top.scanmode –value 0

Analyze for Scan Ready

Select DFT methodology, Scan Ready template and Run

• Check Info_coverage – if coverage acceptable, go to next template

• Check Clock_11 for gated clocks not bypassed in testmode – correct each case
• Check Async_07 for asynchronous resets not disabled in test mode and correct

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Schematic Debugging
If a rule shows a gate in Msg Tree tab, it has a related schematic view. Click v to bring up a
schematic. Cross-probe from RTL to schematic (double-click a signal in RTL) or from schematic
gate to RTL (right-mouse-click->Probe to RTL).
Overlay testmode or testclock info by holding down Ctrl then double-click Infotestmode/testclock
message.

Analyze for Latch Transparency

Select Latches template and Run

• Check Latch_08 messages and correct

Troubleshooting
Can’t get coverage above 0.0?

• Look at BlackBoxDetection rule – all black boxes should have a model

Forgot to supply SpyGlass constraints file?

• Check at least one testclock is defined, on correct signal

• Check testmodes are correctly defined
If testclocks/testmodes must propagate through IP or tech-specific cells, make sure you have models
for those

Analyzing SDC Constraints

Getting Started
Obtain design inputs, create constraints files and let the tool do the rest.

Pre-Requisites

• Ability to analyze design for Clock-Reset

• SDC/Tcl constraints files for design (synthesis or STA)
• Create SpyGlass constraints file for SDC analysis

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Creating a SpyGlass Constraints File

Create a SpyGlass constraints file to describe where SpyGlass should find SDC/Tcl files, also
some characteristics for those files and related blocks. For each block (and the full chip) which
has an SDC/Tcl file, the SGDC file should contain:
current_design <blockname>
block –name <blockname>
sdcschema –type <sdcfilelist> [-mode <modename>]
[-corner <best|worst>]
–min <minval> -max <maxval>
By default, all “current_design” is assumed to be a Block also, for running Block level rules.
The sdcschema constraint identifies how to find the top SDC/Tcl file associated with the current
block. There can be more than one SDC file per block, for different functional/test modes and
different corners. The –mode and –corner options (which are optional) specify these cases.
If you are running SDC checks for multiple steps in the design flow (RTL, pre-layout, postlayout),
create a separate SGDC file for each flow step, identifying associated SDC files.

Constraints File
SDC Constraints (and, most of the commonly used non-SDC but supported by the native shell of
DC, PT, Magma) should be usable as is.
If the constraints files have reference to .db files, the corresponding library’s .lib description
should be made available. Please refer to “Resolving Library Elements” section under “Reading
in a Design”.
Commands which drive the actual execution of some tools (such as those related to actually
synthesize, perform timing-analysis, or report its results) are ignored by the policy.

Run

• Provide the –chip option if this is a full-chip analysis

• Provide the –pt option if the constraints are for PT
• Provide the –tc_magma=yes on the command line, if the constraints are for Magma

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Schematic Debugging
If a violation shows a gate, it has a related schematic view. Click i to bring up an incremental
schematic. Cross-probe from RTL to schematic (double-click a signal in RTL) or from schematic
gate to RTL (right-mouse-click->Probe to RTL).

Troubleshooting

• First check for SDCPARSE errors. An error here means constraints have not been read
correctly
• Note that SpyGlass does not interpret read_verilog or read_vhdl commands. Design source
must be supplied on the command line, as for other SpyGlass analyses
• SpyGlass Constraints supports a wide range of SDC commands, however, if you see a
violation stating that one or more commands is not supported, read your constraints into the
native tool (e.g., PT), use write_sdc to elaborate the constraints and run SpyGlass on
elaborated constraints

Analyzing Voltage and Power Domains

Getting Started
Find voltage and power domain issues in a design having multiple voltage/power domains.

Pre-Requisites

• RTL, gate netlist with .lib or post layout netlist with .plib
• SpyGlass constraints file describing voltage and power domains

Creating an SGDC Constraints File

• Define voltage domains which are always-on parts of the design and are specified using the
voltagedomain constraint
• Define power domains which are parts of design that can be switched on and switched off
and are specified using the voltagedomain constraint

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• Define isolation cells which are used to isolate the outputs of power domains and are defined
using the isocell constraint
• Define level-shifters which are used at the junction of parts of design that are working at
different voltages and are specified using the levelshifter constraint
• Supply rails for a design are specified using the supply constraint.
• Define power switches which are used to control the power domain supply and are specified
to SpyGlass LP using the powerswitch constraint

Special Features
The following special features can be used while specifying values of important nametype
arguments:

• Wildcards like * and ?. This feature is especially useful in specifying gate instance names
from flattened netlists and cell names from libraries
• Vector signal names as whole name, part-selects, or bit-selects

Important Rules

• Level-shifter checking rules – LPSVM04A, LPSVM04B

• Isolation Cell checking rules – LPSVM08, LPSVM09, LPSVM22
• Power/Ground Connectivity Checks – LPPLIB04, LPPLIB06, LPPLIB09, LPPLIB12

Analysis and Troubleshooting

If no violation is being reported or expected violation is missing:

• Open the report lp_rule_req.rpt and see if any mandatory constraint is needed for the rules
run
• Set options to check on more domain crossings
- Set –lp_flag_unconnected_nets for flagging unconnected domain crossings
- Set –lp_flag_undriven_nets for flagging the undriven domain crossings
If too many domain crossings are reported:

• Eliminate any which should not appear by fixing your SGDC

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- Specify the ports and terminals of Analog Block in correct voltagedomain using portname
field
- Specify any missing Level-Shifter and Isolation cells
- Specify –enableTerm in levelshifter constraint if level-shifter is with isolation capability
- Specify supply constraint for supply rails for ignoring violations reported on them
• Use waivers to drop violations such as violations in previously validated IPs
- Add waive –ip <ip_du_name> in your SGDC file
• Set options to filter out groups of violations:
- Set –lp_skip_buf and –lp_skip_buf_isocell for ignoring the violations on
SpyGlass generated buffers
- Set –lp_skip_pwr_gnd to ignore violations on supply nets and supply rails

Viewing Reported Issues

Getting Started
There is more than one way to view analysis results in SpyGlass. The most convenient way is to
view results graphically.

Viewing Results

• The Msg Tree tab organizes the issues in different orders based on the user preference. For
example, issues are organized by policy (clock, dft, etc), then by rule if the grouping order
“Policy” is selected. You can change the grouping order according to your requirements.
• By Module/Entity: Select the Module tab and double-click required module in Design View
• By Source file: select the File tab and double-click required file in File View
All violations/messages can be cross-probed to source HDL by double-clicking the violation.

Generating Pre-Defined Reports

• The Reports menu pull-down lists a variety of pre-defined reports which can be viewed,
searched, printed, and saved
• Some of these reports are always available, for example, simple and moresimple reports
provide standard tabular report formats

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• Some reports become available after certain runs, for example, Clock-Reset-Summary report
becomes available after running the Clock policy or methodology

Getting Help on Violations

Right-click the violation and select Help. By default, a balloon will appear providing more help
on the violation. For more complete help, select Window Æ Preferences Æ Misc, then set
Extended help mode in widgets to HTML. When you next click Help, a browser will be brought
up with a more complete description of the issue. Leave the browser up after you have finished
reviewing help – this saves on browser startup time.

Schematic Viewing
If a rule message in the policy window has a small AND gate on the left, violations on that rule
have associated schematic data. You can also use schematic viewing independently of
violations.
There are two schematic views available:

• Hierarchical – view the hierarchical schematic. A message/design-unit/design source file

needs to be selected to view the relevant portion in the hierarchy
• Incremental – view only nets and instances of interest for a specific message. Dashed
bounding boxes represent hierarchy. Dashed signals represent additional fanin/fanout (not
displayed)
• For a library cell, the underlying schematic may be viewed (if available) by right-clicking the
cell
Standard viewing operations are as follows:

• Zoom in – drag from upper-left to lower-right

• Zoom out – drag from lower-left to upper-right
• Zoom fit – drag from upper-right to lower-left
• Pop-up one level (hierarchical schematics only) – drag from lower-right to upper-left
• Dive down one level of hierarchy (hierarchical schematics only) – double-click an instance in
the hierarchy (‘drag’ means hold down left mouse key, move mouse in specified direction,
then release left mouse key)
Standard cross-probing operations are as follows:
From RTL – double-click signal in RTL
From schematic

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• Click a signal – probe to corresponding signal in RTL

- clears previous probes
• Click an instance – probe to corresponding statement in RTL
- clears previous probes
• Ctrl-click – toggle probe on and off
• Double-click a signal in hierarchical schematic – same as single-click
• Double-click a signal in incremental schematic – show more components attached to net, if
any

Reducing Reported Issues

Getting Started
You just ran SpyGlass and had a huge number of issues reported and you don’t know what to
do next.

Use Methodologies and Templates

If you run SpyGlass by selecting policies, all rules in each such policy will be run, which is rarely
what you really need. Methodologies/Templates pre-select subsets of rules that are useful in
specific situations and will generally lead to far fewer reported issues.
Select a methodology from the Methodology pull-down box. Select a template within that
methodology from the Template pull-down box, and then run SpyGlass analysis. You can see
what rules were checked by looking at the Summary tab when the run has completed.

Look at Messages by File or Module or Severity

Rather than viewing messages on the Policies tab, look at message through the File, Module, or
Serious/Warning tabs. Select the file of interest from the File View or the module of interest from
the Design View.

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Suppress Messages
Use the Waive capability to suppress individual messages or groups of messages

• Waive to ‘officially’ approve a suppression – waivers will be reported under Reports Æ

waivers for design review analysis
Right mouse click and select waive over a message

• Select This Message to remove this specific message

• Select Group… to waive using wild-cards in message
• Select other options to suppress all messages in a file, module, etc.
Select Waiver button on toolbar to see and edit a spreadsheet of all selected waiver
options

• You can read, modify, and save multiple waiver files

Right mouse click and select waiver over a design unit

• You can waive given design unit or its hierarchy

Right mouse click and select waiver over RTL source file contents

• Select waive for given line or block of lines (selected by mouse drag) to suppress messages
for selected file contents

Noisy Rules
If you find a particularly noisy rule, chances are that there are parameters you can set to control
the behavior of the rule. However, you cannot control STX or WRN rules in this way.
To find which parameters might affect the rule, right-click a violation. This will often (but not
always) tell you which parameters are relevant.
A more reliable guide is the on-line documentation for the rule. Select on-line help and pick the
appropriate policy documentation.
To change a rule parameter, select a violation on the rule then right-mouse click and select
Setup… to find parameters for that rule. Clicking in the entry field for a parameter will give help
on use of parameter and allowed values.

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For More Information:

Type spydocviewer to get menu access to detailed documentation

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