13368 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO.

11, NOVEMBER 2022

A Dynamic Current Balancing Method for Paralleled

SiC MOSFETs Using Monolithic Si-RC Snubber
Based on a Dynamic Current Sharing Model
Jianwei Lv , Cai Chen , Member, IEEE, Baihan Liu, Yiyang Yan, and Yong Kang, Senior Member, IEEE

Abstract—The dynamic current imbalance between paralleled losses and junction temperature, reducing the stability and relia-
SiC MOSFETs will cause unbalanced losses and reduce current bility of the converter. The thermal resistance of the device with
capacity. The existing current balancing methods will make the higher switching losses and junction temperature will degrade
circuit more complex or hard to design and implement. Hence,
this article proposes a dynamic current balancing method by con- earlier, which will further increase the junction temperature of
necting monolithic Si-RC snubber between paralleled MOSFETs, this device [10]. Moreover, the MOSFET with higher junction
which maintains a simple circuit structure and is easy to implement. temperature will have lower threshold voltage, which will cause
Balanced dynamic currents can be achieved by adjusting the RC higher switching current on this device. This mechanism can
snubber connecting location. Meanwhile, low voltage spike and low cause thermal runaway in the paralleled power devices. The
switching oscillation can be achieved by using RC snubber. First,
an analytical current sharing model is established for paralleled higher the switching frequency, the higher the risk of thermal
SiC MOSFETs. The key parameter affecting the balance of the runaway failure [11]. So, it is necessary to investigate the mech-
drive circuit and then affecting the dynamic current sharing is anism of dynamic current sharing and the approaches to suppress
obtained for the first time. Based on the conclusions of the model, the dynamic current imbalance among paralleled SiC MOSFETs.
this article then presents the current balancing method using RC Many studies on the current sharing mechanism focused
snubber. Then, a power module with monolithic Si-RC snubber is
designed, fabricated, and tested. Experimental results verify the on the circuits without Kelvin-source connections [12]–[14].
current sharing model and the current balancing method. The In [12] and [13], it is found that unbalanced parasitic induc-
current difference of the optimized module is reduced by more tances and unbalanced device parameters can deteriorate the
than 50% under different conditions. Finally, the effectiveness of dynamic current balance. Haihong et al. [14] further revealed
this method in the module with more paralleled MOSFETs is verified.
that inconsistent gate resistances, drain parasitic inductances
Index Terms—Dynamic current balancing, dynamic current Ld , and common source inductances Ls can cause unbalanced
sharing model, multichip SiC power modules, paralleled SiC dynamic current between paralleled SiC MOSFETs with sepa-
MOSFETs, RC snubber. rated gate drivers. Besides, to take full advantage of the high
I. INTRODUCTION switching speed and low switching losses of SiC devices, the
Kelvin-source connection is wildly used. The dynamic current
OWER electronic devices are widely used in high-power
P applications such as renewable energy, hybrid/electric ve-
hicles, and railway transportation [1]–[5]. SiC MOSFET is at-
sharing mechanism in circuits with Kelvin-source connections
is widely investigated [11], [15], [16]. Li et al. [15] investigated
the function of the Kelvin-source connection in multichip power
tracting more and more attention in these applications due to module and found that Kelvin-source connection can suppress
its higher switching speed, lower loss, and excellent thermal current imbalance to some extent. In [16], the current imbal-
performance [6]–[8]. ance between paralleled power chips caused by the unbalanced
In many cases, paralleled SiC MOSFETs are used to improve layout is investigated theoretically. A coefficient representing
the power rating [9]. However, the dynamic current imbalance the symmetric degree of the parasitic impedances is established,
between the paralleled devices needs to be eliminated. The and it can be used to quantitatively evaluate the current balancing
unbalanced dynamic current can cause unbalanced switching degree of power module layouts. In [11], the influences of unbal-
anced parasitic inductances and unequal junction temperatures
Manuscript received 25 January 2022; revised 17 April 2022; accepted 30 May on dynamic current sharing are investigated analytically. It is
2022. Date of publication 3 June 2022; date of current version 26 July 2022.
This work was supported in part by the National Natural Science Foundation concluded that in circuits with Kelvin-source connections, the
of China under Grant 52077094. Recommended for publication by Associate dynamic current imbalance is mainly caused by the imbalanced
Editor K. Sheng. (Corresponding author: Cai Chen.) power source parasitic inductances. Other parasitic inductances,
The authors are with the School of Electrical and Electronic Engineering,
Huazhong University of Science and Technology, Wuhan 430074, China (e- by contrast, have little effect on the dynamic current sharing.
mail: jianweil@hust.edu.cn; caichen@hust.edu.cn; loubeckham@hust.edu.cn; This conclusion is very useful and can guide the design of
yanyiyang@hust.edu.cn; ykang@hust.edu.cn;ykang@mail.hust.edu.cn). circuit structures. However, the internal mechanism and physical
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TPEL.2022.3179829. process of the dynamic current imbalance are not clear in the
Digital Object Identifier 10.1109/TPEL.2022.3179829 research works previously. Moreover, it is mentioned in [17] that

0885-8993 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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LV et al.: DYNAMIC CURRENT BALANCING METHOD FOR PARALLELED SIC MOSFETs 13369

the differential currents between the drive source and gate of the method by connecting dc-link RC snubber between the source
paralleled dies indicate the disturbance from the main power of paralleled MOSFETs. By adjusting the snubber connecting
loop to the drive loop, and represent the imbalance degree of location, balanced dynamic currents can be achieved. Compared
the dynamic current. However, the key factor and the internal to the existing first and second approaches, this method does not
mechanism are not analyzed. need to add any other components. The circuit maintains a simple
Apart from the abovementioned research works on the current structure and can achieve the advantages of the RC snubber.
sharing mechanism, other studies worked on the current bal- Compared to the existing third approach, this method does not
ancing approaches. Three approaches can be concluded from change the circuit layout and does not require complex structural
these works. The first approach is to suppress it actively. In design or complex calculation. The optimal connecting location
[18]–[21], current sensors are used to measure the current of of the RC snubber is determined by theoretical calculation.
each device. According to the measured currents, the driving After that, the power module with monolithic Si-RC snubber
signals are adjusted by gate delay circuits to achieve a uniform is designed, fabricated, and tested to demonstrate the current
dynamic current. In [22], a master-slave gate driver is used to balancing method. Integrating monolithic Si-RC snubber chips
achieve dynamic current balancing. The gate voltage of the in power modules is a good solution with a more compact struc-
master MOSFET is detected, and the gate voltages of the slave ture, lower loop parasitic inductance, higher thermal conduction
MOSFETS follow the master voltage by close-loop circuits. These of the snubber, and higher reliability [32], [33]. Compared
methods can achieve good results. But additional sensors and to integrated decoupling capacitor, integrated RC snubber can
circuits are needed for each MOSFET, which will increase the achieve lower oscillation. Especially, there is no low frequency
circuit complexity. oscillation, which is induced by using decoupling capacitor. Fi-
The second approach is to add additional passive components nally, to further verify the effectiveness of the current balancing
into the circuit. In [23], drive-source resistors are used in each method when more MOSFETs are paralleled, a multichip power
drive-source branch to reduce the currents on the Kelvin bonding module with a general layout is also presented and optimized.
wires. The MOSFET currents are not considered. In [24] and The rest of this article is organized as follows. Section II
[25], drive-source resistors and coupled power-source inductors establishes the analytical current sharing model. By theoreti-
are used in each drive-source branch and each power-source cal analysis, the internal dynamic current sharing mechanism
branch to achieve a balanced current. This method does not is concluded. The key parameter that influences the balance
need additional current sensors or gate regulation circuits, but of the drive circuit is obtained. Based on the conclusions of
additional resistors and inductors have to be used. the model, in Section III, the current sharing method using
The third approach is to optimize the circuit layout. In [26] dc-link RC snubber is proposed and theoretically analyzed. The
and [27], the direct bonded copper (DBC) layouts are optimized approach to obtain the optimal location of the RC snubber is
to balance the dynamic current. In [28], symmetric dc terminals presented. Then, the SiC power module with monolithic Si-RC
are used. These two methods can achieve a balanced dynamic snubber is designed and optimized to demonstrate the current
current, but they need to change the circuit layout, which limits sharing method in detail. In Sections IV and V, simulations and
their application. In [17] and [29], the bonding wires on par- experiments are performed to verify the conclusions from the
alleled SiC chips are adjusted to achieve a balanced dynamic established analytical model and to verify the current sharing
current. The lengths and connection points of bonding wires method. In Section VI, the multichip power module is optimized
have to be calculated and controlled accurately. to verify the effectiveness of the method when more MOSFETs
To further investigate the internal current sharing mechanism, are paralleled. Finally, Section VII concludes this article.
which is not clear in the former research works, an analytical
model is established first in this article. The internal dynamic cur- II. DYNAMIC CURRENT SHARING MODEL
rent sharing mechanism under unbalanced power source induc-
In order to present the dynamic current balancing method in
tances is more deeply analyzed in Kelvin-connected paralleled
this article, it is necessary to analyze the current sharing mech-
SiC MOSFETs. The relationship between the different variables
anism first. It is found in [11] that dynamic current imbalance is
is explained clearly by this model. Then, the key parameter that
mainly caused by the imbalanced power-source parasitic induc-
influences the balance of the drive circuit and then influences
tances in the circuit with Kelvin-source connections. And other
dynamic current sharing is obtained for the first time, which
parasitic inductances have little effect on the dynamic current
is directly used to present and analyze the current balancing
sharing. So, an analytical model is established in this chapter
method in this paper. Moreover, the physical explanations of
to investigate the internal dynamic current sharing mechanism
the current sharing mechanism are also concluded based on this
under unbalanced power source inductances. The parasitic cir-
model.
cuit model of a double pulse test circuit with two paralleled SiC
Recently, dc-link RC snubber has been widely researched
MOSFETs is shown in Fig. 1. The meanings of each component
[30]–[34]. Using a dc-link RC snubber can reduce or even
are summarized in Table I.
mostly eliminate switching oscillation, reducing switching EMI,
and turn-OFF overvoltage. Then, the switching speed can be
improved, and the switching losses can be reduced significantly. A. Simplified Circuit Model and Circuit Equations
Based on the conclusions of the established dynamic current The dynamic current imbalance occurs during the current
sharing model, this article presents a dynamic current balancing commutation period. So, the analytical model is based on the

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 13370 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 11, NOVEMBER 2022

Fig. 3. Simplified dynamic parasitic circuit model.

According to the circuit model in Fig. 3, the circuit equations

are derived as shown in Appendix. Equations (A6)–(A12) form
Fig. 1. Parasitic circuit model with two paralleled SiC MOSFETs. The two the mathematical model of the circuit. In [17], it is mentioned
power-source parasitic inductors are shown in red. that a smaller ik in Fig. 3 can cause a more balanced dynamic
current. However, it can be concluded from (A6) and (A7) that
TABLE I the key factor influencing the balance of the drive circuit is sIk
MEANINGS OF EACH COMPONENT (i.e., dik /dt), which is also the key parameter to analyze the
current sharing mechanism. The power circuit influences the
driving circuit through sIk , while vgs1 and vgs2 in turn determine
the MOSFET currents i1 , i2 . sIk can be obtained by solving (A6)–
(A12). Then, ig1 , ig2 , and vgs1 , vgs2 can be analyzed through sIk ,
so as to analyze i1 , i2 .

B. Solution of the Circuit Equations- the Dynamic Current

Sharing Model
By solving (A6)–(A12) with (A13)–(A15), sIk can be derived
as
ΔLs (ds + e)
sIk = (1)
as2 + bs + c
where a, b, c, d, e, and ΔLs are given by
⎧
⎪ ΔLs =Ls1 −Ls2
⎪
⎪ 
⎪
⎪ a = Ciss (2Lk +Ls1 +Ls2 ) Lg +(2Lk +Ls1 +Ls2 ) Lk −2L2k
⎪
⎨
b = gm Lk (Ls1 + Ls2 ) + Ciss (2Lk +Ls1 +Ls2 )Rg
⎪
⎪ c = 2Lk +Ls1 +Ls2
⎪
⎪
⎪
⎪ d = gm Ig0 (Lg + Lk )
⎩
e = gm (Vg − Vth ) − I0 .
(2)
As shown in (2), ΔLs is the difference of the two power source
inductances. a, b, c, d, and e are related to the circuit and MOSFET
parameters.
By solving (A6) and (A7) with (A13)–(A15), it can be derived
that

ΔIg =Ig1 −Ig2 = − 2Lk Z1 sIk
ΔI (3)
ΔVgs =Vgs1 −Vgs2 = sCissg .
Fig. 2. Equivalent dynamic parasitic circuit model.
In addition, by (A1), the unbalanced drain current can be
derived as
current commutation period. During this period, the assumptions Δi = i1 −i2 = gm Δvgs . (4)
in Appendix can be made. Based on the assumptions, the circuit
in Fig. 1 can be equivalent to the circuit in Fig. 2 during the Equations (1), (3), and (4) form the final dynamic current sharing
current commutation period. The two drain-source voltages on model. Based on (3) and (4), the current sharing equivalent cir-
the MOSFETs are not concerned. Then, all the parts in series cuit model is shown in Fig. 4(a) with the same circuit elements as
with the equivalent current sources can be neglected. Then, the the drive circuit. The block diagram describing the relationship
simplified circuit is obtained and shown in Fig. 3. between the variables is shown in Fig. 4(b). The initial conditions

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LV et al.: DYNAMIC CURRENT BALANCING METHOD FOR PARALLELED SIC MOSFETs 13371

TABLE II
POSSIBLE PARAMETER VALUES IN ACTUAL CIRCUITS WITH
CMP2-1200-0025B

Fig. 4. Current sharing equivalent circuit. (a) Circuit diagram. (b) Block
diagram describing the relationship between the variables.
b) When the MOSFETs are turned OFF, dik /dt < 0, Δig > 0,
Δvgs > 0, Δi > 0, and i1 > i2 .
The conclusions are consistent with [11] that the MOSFET with
of the inductor and capacitor in the circuit are equal to 0. It can
higher power source inductance will bear lower turn-ON dynamic
be concluded that dik /dt is the key parameter that influences the
currents and higher turn-OFF dynamic currents. It can be seen
balance of the driving circuit (Δig and Δvgs ) and influences the
from (3) and Fig. 4 that dik /dt can induce unbalanced gate current
dynamic current sharing (Δi). In the same current commutating
Δig and unbalanced gate-source voltage Δvgs . Supposing Ls1
time and under the same Lk , higher |dik /dt| can cause higher
< Ls2 , the physical explanations of the dynamic current sharing
|Δig |, higher |Δvgs |, and higher |Δi|. On the contrary, lower
mechanism can be concluded as follows.
|dik /dt| can cause lower |Δi|. This conclusion is directly used to
As shown in Fig. 3, when the MOSFETs are turned on, dis1 /dt
present and analyze the current balancing method in this article.
> 0, dis2 /dt > 0. The voltage vLs1 (= Ls1 ·dis1 /dt) ON Ls1 will
be lower than vLs2 (= Ls2 dis2 /dt) on Ls2 . The voltage potential
C. Analyses and Discussions of Dynamic Current Sharing at s1 will be lower than at s2. Then, dik /dt will be less than 0.
Mechanism The dik /dt will induce voltages ON Lk1 (= Lk1 ·dik /dt) and Lk2
(= Lk2 ·dik /dt), where Lk1 dik /dt < 0 and Lk2 ·dik /dt < 0. The
The initial conditions of the inductor and capacitor in Fig. 4 voltage ON Lk1 (= Lk1 dik /dt) has the same effect as the driving
are equal to 0. Then, it can be concluded that the sign of dik /dt voltage Vgon causing a higher ig1 , while the voltage on Lk2 (=
determines the sign of Δi. when dik /dt > 0, Δig will be negative, Lk2 ·dik /dt) has the opposite effect as the driving voltage Vgon
making Δvgs < 0 and Δi < 0. When dik /dt < 0, Δig will causing a smaller ig2 . Then, vgs1 will be higher than vgs2 , and i1
be positive, making Δvgs > 0 and Δi > 0. By solving the will be higher than i2 .
time-domain solution of sIk using (1) and combining it with the When the MOSFETs are turned OFF, dis1 /dt < 0, dis2 /dt < 0.
conclusion abovementioned, the internal process of the dynamic The voltage vLs1 (= Ls1 ·dis1 /dt) ON Ls1 will be higher than vLs2
current distribution can be obtained as follows. (= Ls2 · dis2 /dt) on Ls2 . The voltage potential at s1 will be higher
1) When Ls1 = Ls2 , ΔLs = 0. The parameters between two than at s2. Then, dik /dt will be higher than 0. The dik /dt will
MOSFETs are balanced. Then, it can be derived from (1)
induce voltages on Lk1 (= Lk1 dik /dt) and Lk2 (= Lk2 ·dik /dt)
that dik /dt = 0. Then, it can be concluded that Δig = 0, where Lk1 ·dik /dt > 0 and Lk2 ·dik /dt > 0. The voltage on Lk1
Δvgs = 0, and Δi = 0, which means that i1 = i2 . (= Lk1 dik /dt) has the same effect as the driving voltage Vgoff
2) When Ls1 < Ls2 , ΔLs < 0. Six sets of parameter values causing a lower ig1 (higher |ig1 |), while the voltage on Lk2 (=
shown in Table II are taken as examples, where CREE Lk2 ·dik /dt) has the opposite effect as the driving voltage Vgoff
CMP2-1200-0025B is used as the SiC MOSFET. causing a higher ig2 (lower |ig2 |). Then, vgs1 will be lower than
a) During the turn-ON current commutation period, it can vgs2 , and i1 will be lower than i2 .
be calculated from (1) that dik /dt < 0. Then, it can be
concluded that Δig > 0, Δvgs > 0, and Δi > 0, which
means that i1 > i2 . III. DYNAMIC CURRENT BALANCING METHOD USING
b) During the turn-OFF current commutation period, dik /dt > DC-LINK RC SNUBBER
0, Δig < 0, Δvgs < 0, Δi < 0, and i1 < i2 . Based on the conclusions of the dynamic current sharing
3) When Ls1 > Ls2 , ΔLs > 0. The conclusion is just opposite model, the dynamic current balancing method is presented. The
to that when ΔLs < 0. circuit with the method is shown in Fig. 5, where a dc-link RC
a) When the MOSFETs are turned ON, dik /dt > 0, Δig < 0, snubber is connected between the source of paralleled MOSFETs.
Δvgs < 0, Δi < 0, and i1 < i2 . The MOSFET with higher power-source parasitic inductance is

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 13372 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 11, NOVEMBER 2022

Fig. 5. Circuit with the dynamic current balancing method.

Fig. 7. Waveforms of vs1s2 , ik , i1 , and i2 during turn-ON period under different

snubber connecting locations.

A. Simplified Circuit Model and Circuit Equations

Neglecting the components in series with the equivalent cur-
Fig. 6. Equivalent dynamic circuit with the dynamic current balancing method. rent sources and the load current source (i.e., Ld1 , Ld2 , Ld , Lc ,
and La ), the equivalent circuit can be simplified into the circuit
shown in Fig. 8(a). For the dc signals, Lbus3 can be considered
marked as Q2. Then, Ls1 < Ls2 . One terminal of the RC snub- a short circuit. For the ac signals, Iload can be considered as
ber is connected to the cathode of D1. The other terminal is an open circuit. So, Lbus3 can be moved from points 1 and 2
connected to a point on the power-source parasitic inductor of to points 2 and 3, as shown in Fig. 8(b). Eventually, the circuit
Q2. Then, Ls2 is divided into two parts, namely L1 and L2 , as in Fig. 8(b) can be equivalent to the circuit shown in Fig. 8(c),
written in (5). Based on the assumptions in Appendix, the circuit where
in Fig. 5 can be equivalent to the circuit shown in Fig. 6.
Lbus = Lbus1 + Lbus2 + Lbus3 . (6)
Ls2 = L1 + L2 . (5)
Compared to the circuit in Fig. 3, the circuit in Fig. 8(c) has
the same driving circuit but a different power circuit. Taking the
It can be seen from the red dash lines in Fig. 6 that the RC
initial current commutation time as the initial time (t = 0), the
snubber can provide a dynamic current path for the MOSFETs.
driving circuit equations can be expressed as (A3) and (A4). The
During the current commutation period, some parts of the current
power circuit equations can be expressed as
can flow into the RC snubber through Ls1 , L1 , and L2 . Then, the
voltage vs1s2 between s1 and s2 will be changed. Then, dik /dt ⎧
⎪ is1 =i1 − ik
will also be changed. Fig. 7 shows waveforms under different ⎪
⎪
⎪
⎪ i s2 =i2 + ik
snubber connecting locations. As shown in Fig. 7, different snub- ⎪
⎪
⎪ (Lk1 + Lk2 ) di
dig1 dig2
⎪ dt + Lk1 dt − Lk2 dt
k
ber locations correspond to different current flowing conditions. ⎪
⎪
⎪
⎪
Then, different vs1s2 and dik /dt can be obtained. By adjusting ⎪
⎪ = Ls1 didts1 − (Ls2 − L1 ) didts2 + L1 didts3
the connecting location, a small |dik /dt| can be achieved, so as to ⎪
⎨
realize a balanced dynamic current, such as location 3 in Fig. 7. Lbus didtbus + L1 didts3 + VDD (7)
⎪
⎪ t
In this section, the approach to solve the optimized connecting ⎪
⎪ = Rsn isn + C1sn 0 isn dt + VDD
⎪
⎪
location of the RC snubber is presented by theoretical analysis. ⎪
⎪
⎪
⎪ i1 + i2 = − (ibus + isn )
Moreover, the SiC power module with monolithic Si-RC snubber ⎪
⎪
⎪
⎪ i + ibus = is3
is presented and optimized to demonstrate the current balancing ⎪
⎪ s1
⎩
method. is2 + is3 = −isn .

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LV et al.: DYNAMIC CURRENT BALANCING METHOD FOR PARALLELED SIC MOSFETs 13373

Fig. 8. Simplified dynamic circuits with the dynamic current balancing

method.

The initial conditions of the circuit can be expressed as (A14)

and (8)
⎧ Fig. 9. Solving program of the optimized snubber connecting location.
⎨ is1 (0) = is2 (0) = −is3 (0) = I0
ibus (0) = −2I0 (8)
⎩
isn (0) = 0.
ik(off) and ik(on) are the time-domain solutions of ik during the
B. Solving Program of the Optimized RC Snubber Connecting
turn-OFF and turn-ON periods. Finally, the value of L1 that makes
Location |dik /dt| smallest is chosen as the optimized solution.
The solving program of the optimized snubber connecting The values of the circuit parameters and the initial conditions
location is shown in Fig. 9. First, the values of the circuit are obtained as follows.
parameters are given, and a set of L1 values is given through the 1) Circuit Parameters: The circuit parameters include the
array L1 [n]. Then, the values of the initial conditions in (A14) MOSFET parameters, the parasitic parameters and the compo-
and (8) are calculated. Using the values of the circuit parameters nent parameters. The values of the MOSFET parameters can be
and the initial conditions, the circuit (A1), (A3), (A4), and (7) obtained by datasheet or testing. The values of the parasitic pa-
can be solved numerically. Waveforms of ik under different L1 rameters can be extracted from the detailed circuit structure. The
are obtained by solving the circuit equations. The waveforms are value of L1 corresponding to the snubber connection location is
solved during the turn-OFF and the turn-ON periods, respectively. changed as the given value.

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 13374 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 11, NOVEMBER 2022

Fig. 11. Leakage currents of the Si-RC snubber under different operating
voltages.

Fig. 10. Structure of the SiC power module using the current sharing method.
(a) Module with housing. (b) Internal module layout.

2) Initial Conditions: The values of the initial conditions

are determined by the values of I0 and Ig0 . The value of I0 is
determined by the load current Iload . When the MOSFETs are
turned ON, I0 = 0. When the MOSFETs are turned OFF, I0 =
Iload /2.
The value of Ig0 can be obtained by solving the drive circuit.
When the MOSFETs are turned OFF, Ig0 can be expressed as
Fig. 12. Parasitic circuit model of the double pulse teste circuit and the power
Vgoff − (I0/gm + Vth ) module using the dynamic current balancing method.
Ig0 = . (9)
Rg
TABLE III
When the MOSFETs are turned ON, taking the initial driving PARAMETER VALUES OF THE POWER MODULE
time as the initial time, it can be derived that
(Vgon − Vgoff )Ciss
Ig = (10)
s2 (Lg + Lk )Ciss + sRg Ciss + 1
Vgon − Vgoff Vgoff
Vgs = + . (11)
s [s2 (Lg + Lk )Ciss + sRg Ciss + 1] s
Solving (10) and (11), when vgs is equal to Vth , ig is equal to
the initial gate current Ig0 of the current commutation period.

C. SiC Power Module Using the Presented Current Balancing

Method different operating voltages. The rated voltage is 900 V, which
The SiC power module using this method is designed, as is compatible with the operating voltage of SiC devices with
shown in Fig. 10. A SiC Schottky diode (S6305) is used as maximum drain-source voltage up to 1.2 kV. The landing point
the high-side free-wheeling diode D1, and two SiC MOSFETs of the snubber bonding wires locates between the sources of the
(CPM2-1200-0025B) are paralleled as the low-side switch. To two MOSFETs achieving the current balancing structure.
facilitate measurement of the currents, the height of the power The parasitic circuit model of the power module is depicted
bonding wires is adjusted to 3 mm, and the height of the as the black part in Fig. 12. Mutual inductors are not considered.
drive bonding wires is adjusted to 2 mm. To realize a balanced By finite element analysis (FEM) simulation, the values of the
dynamic current, a 4.4 nF, 3.5 Ω monolithic Si-RC snubber chip parasitic inductances are extracted. The parameter values are
from Fraunhofer IISB is used as the RC branch [36], soldered listed in Table III. L1 is a function of x, where x(mm) is the
on the dc+ copper and connected to the dc- copper by bonding distance between the landing point of the Q2 bonding wires and
wires. Fig. 11 shows the leakage currents of the RC chip under the landing point of the RC snubber bonding wires, as depicted

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LV et al.: DYNAMIC CURRENT BALANCING METHOD FOR PARALLELED SIC MOSFETs 13375

Fig. 13. Waveforms of ik under different values of x. (a) Waveforms of ik

during the turn-ON period. (b) Waveforms of ik during the turn-OFF period.

in Fig. 10(b). Ls2 _b is one part of Ls2 contributed by the bonding Fig. 14. Capacitor board and drive board for double pulse test. (a) Capacitor
wires, and Ls2 _c is the other part of Ls2 contributed by the copper board. (b) Drive board.
layer, where
Ls2 = Ls2_b + L2_c = L1 + L2 . (12)
The double pulse test circuit for the power module is depicted
as the blue part in Fig. 12. Vg is determined by the recommended
driving voltage of the MOSFETs, where Vgon = 20 V, and Vgoff
= −5 V. Dividing Lg _t , Ls _t , Lg _ext , Ls _ext , and Rg _ext into
the two drive loops, the parasitic circuit model can be equivalent
to the circuit in Fig. 5, where
⎧
⎪
⎪ Lbus2 =Lbus2_ext + Lbus2_in
⎪
⎪
⎪
⎪ L bus3 =Lbus3_ext + Lbus3_in
⎪
⎪
⎨ Lload =Lload_ext + Lload_in
Lg1 = 2Lg_ext + 2Ls_ext + 2Lg_t + 2Ls_t + Lg1_1 (13)
⎪
⎪
⎪
⎪ L g2 = 2L g_ext + 2L s_ext + 2L g_t + 2L s_t + L g2_1
⎪
⎪
⎪
⎪ Rg1 =Rg1_in + 2Rg_ext
⎩
Rg2 =Rg2_in + 2Rg_ext .
The program shown in Fig. 9 is realized by MATLAB. When
Iload = 75 A, Lbus = 30.58 nH, Rg _ext(on) = 2.2 Ω, Rg _ext(off)
= 4.7 Ω, and Lg1 = Lg2 = 67.63 nH, the waveforms of ik under
different values of x are shown in Fig. 13.
When x is large, such as 9.56 mm or 14.7 mm, L1 is small,
and L2 is large. The snubber branch is close to Q1. The sign of
Fig. 15. Simulation waveforms of the circuit without the RC branch.
dik /dt is the same as the circuit without RC snubber. During the (a) Waveforms during the turn-ON period. (b) Waveforms during the turn-OFF
turn-ON period, dik /dt < 0. During the turn-OFF period, dik /dt > period.
0. It can be analyzed from the current sharing model that i1 will
be larger than i2 during the turn-ON period and will be smaller
than i2 during the turn-OFF period. is established and simulated in LTspice. The parameter values
When x is small, such as 0 mm, L1 is large, and L2 is small. The shown in Table III are used in the simulation. The double pulse
snubber branch is close to Q2 changing the sign of dik /dt. During test capacitor board and drive board are designed, as shown
the turn-ON period, dik /dt > 0 at the beginning. During the turn- in Fig. 14. The parasitic parameters of the test boards are ex-
OFF period, dik /dt < 0 at the beginning. It can be analyzed from tracted by FEM simulation. It is obtained that Lbus1 + Lbus2˙ext +
the current sharing model that i1 will be lower than i2 at the Lbus3 _ext = 18.6 nH and Lg _ext + Ls _ext = 16.08 nH, which
beginning of the turn-ON period and will be larger than i2 at the are used in the simulation. The dc bus voltage in the simulation
beginning of the turn-OFF period. is 300 V to be consistent with the experiments unless otherwise
The connecting location where x = 3.68 mm can be chosen specified.
as the optimized solution. At this location, L1 = 1.92 nH and L2
= 2.27 nH. A. Verification of the Dynamic Current Sharing Model
Excluding the RC branch, the simulation circuit can be con-
IV. SIMULATION VERIFICATIONS
verted into the circuit without the snubber. When Iload = 70 A
To verify the conclusions of the dynamic current sharing and Rg _ext(on) = Rg _ext(off) = 5.6 Ω, the simulation waveforms
model and the current balancing method, the circuit in Fig. 12 are shown in Fig. 15. Because Ls1 < Ls2 , during the turn-ON

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 13376 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 11, NOVEMBER 2022

Fig. 16. Simulation waveforms of the circuit under 300 V bus voltage and
Fig. 17. Simulation waveforms of the circuit under 600 V bus voltage and
under different snubber connecting locations. (a) Waveforms during the turn-ON
under different snubber connecting locations. (a) Waveforms during the turn-ON
period. (b) Waveforms during the turn-OFF period.
period. (b) Waveforms during the turn-OFF period.

period, dik /dt < 0, Δig > 0, Δvgs > 0, Δi > 0, and i1 > i2 .
During the turn-OFF period, dik /dt > 0, Δig < 0, Δvgs < 0, Δi
< 0, and i1 < i2 . The results are consistent with the conclusions
drawn by the current sharing model.

B. Verification of the Dynamic Current Balancing Method

The terminal connecting location where L1 = 0 nH is used
to compare with the optimized connecting location. When
Rg _ext(on) = 2.2 Ω, Rg _ext(off) = 4.7 Ω, and Iload = 75 A,
the simulation waveforms under the terminal and optimized
connecting locations are shown in Fig. 16. Under the terminal
connecting location, dik /dt < 0 during turn-ON period making Fig. 18. Fabricated baseline modules. (a) Outside view of the power modules
i1 > i2 and dik /dt > 0 during turn-OFF period making i1 < i2 . with case. (b) Module 0 without RC snubber. (c) Module 1 with RC snubber
connected on the optimized location. (d) Module 1 with RC snubber connected
According to the calculation in Chapter III, the chosen optimized on the terminal location.
connecting location is x = 3.68 mm, where L1 = 1.92 nH. It
can be concluded that |dik /dt| is smaller during the turn-ON and
turn-OFF periods under the optimized connecting location. Then,
|Δig |, |Δvgs |, and |Δi| are smaller. The current balancing method V. EXPERIMENTAL VERIFICATIONS
and the approach to solve the optimized connecting location of In this chapter, experimental verifications are conducted. Two
the RC snubber are verified. Moreover, the relationship between baseline modules are fabricated and tested, as shown in Fig. 18.
dik /dt, Δig , Δvgs , and Δi is consistent with the conclusions of RC snubber is removed in module 0 to verify the conclusions
the current sharing model. If dik /dt > 0, Δig will be reduced. of the current sharing model. To avoid the influence of device
If dik /dt < 0, Δig will be increased. If Δig > 0, Δvgs will be parameter differences between different modules, the bonding
increased. If Δig < 0, Δvgs will be reduced. wires of the RC chip in module 1 are broken and reconnected, to
To further demonstrate the method, the simulation waveforms realize two different snubber connecting locations with a single
under 600 V bus voltage are shown in Fig. 17. It is shown that module, as shown in Fig. 18(c) and (d).
the current sharing method can still achieve good effectiveness The double pulse test boards in Fig. 14 are fabricated. The
under higher bus voltage. experimental test rig is shown in Fig. 19. i1 and i2 are measured

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LV et al.: DYNAMIC CURRENT BALANCING METHOD FOR PARALLELED SIC MOSFETs 13377

Fig. 19. Experimental test rig.

on the power-source bonding wires by two 120 A/30 MHz Ro-

gowski coils. ig1 and ig2 are measured on the gate bonding wires.
ik is measured by simultaneously placing the Rogowski coil on Fig. 20. Experimental waveforms of module 0 when Iload = 70 A. (a)
the gate and drive-source wires. vds is measured on the DBC Waveforms during the turn-ON period. (b) Waveforms during the turn-OFF period.
copper traces by a passive 500 MHz/1000 V voltage probe from
Tektronix. vgs is measured on the gate and drive-source wires as
close to the MOSFET as possible by a passive 500 MHz/400 V
voltage probe from LeCroy. As the ig and vgs measurements
are too easy to damage the bonding wires, ig and vgs are only
measured in the experiments that verify the current sharing
model. Cause the modules are not encapsulated, the dc bus
voltage is 300 V to prevent creepage discharge. Though the bus
voltage is relatively low for 1200 V MOSFETs, the experiments
can still achieve our verification purposes.

A. Verification of the Dynamic Current Sharing Model

The experimental switching waveforms of module 0 without
RC snubber are shown in Fig. 20 when Iload = 70 A and
Rg _ext(on) = Rg _ext(off) = 5.6 Ω. The mechanism of the Fig. 21. Experimental waveforms of module 0 when Iload = 52.5 A. (a)
waveforms is consistent with the theoretical analyses and the Waveforms during the turn-ON period. (b) Waveforms during the turn-OFF period.
simulation results. Because Ls1 < Ls2 , during the turn-ON period,
dik /dt < 0, Δig > 0, Δvgs > 0, Δi > 0, and i1 > i2 . During the
turn-OFF period, dik /dt > 0, Δig < 0, Δvgs < 0, Δi < 0, and i1
< i2 .
When Iload = 52.5 A and Iload = 35 A, the waveforms of
ik , i1 and i2 are shown in Figs. 21 and 22, respectively. The
relationship between ik and Δi is consistent with the conclusions
drawn by the current sharing model. During the turn-ON period,
dik /dt < 0, making i1 > i2 . During the turn-OFF period, dik /dt
> 0, making i1 < i2 . Moreover, Δi and the variation of ik are
smaller under the lower load current.

B. Verification of the Dynamic Current Balancing Method

The module with terminal connecting location (the TL mod-
Fig. 22. Experimental waveforms of module 0 when Iload = 35 A. (a)
ule) and the module with optimized connecting location (the OL Waveforms during the turn-ON period. (b) Waveforms during the turn-OFF period.
module) are tested and compared. Simulation and experiment

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 13378 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 11, NOVEMBER 2022

Fig. 23. Experimental and simulation waveforms of the TL module and OL

module when Iload = 75 A, Rg _ext(on) = 2.2 Ω, and Rg _ext(off) = 4.7 Ω.
(a) Waveforms during the turn-ON period. (b) Waveforms during the turn-OFF
period. Fig. 24. Experimental turn-ON current waveforms of the two modules under
different Rg _ext(on) and Iload . (a) Rg _ext(on) = 2.2 Ω and Iload = 75 A. (b)
Rg _ext(on) =2.2 Ω and Iload = 50 A. (c) Rg _ext(on) = 4.7 Ω and Iload = 75 A.
(d) Rg _ext(on) = 4.7 Ω and Iload = 50 A.
waveforms are depicted in the same plots in Fig. 23, when
Rg _ext(on) = 2.2 Ω, Rg _ext(off) = 4.7 Ω and Iload = 75 A.
Compared to the TL module, the OL module performs lower
|dik /dt| and lower |Δi| during current commutating periods. The
dynamic current of the OL module is balanced well. The current
balancing method and the approach to solve the optimized
connecting location of the RC snubber can be well verified. There
are deviations between simulation and experiment results. One
reason for the deviations is that there are errors and relatively
large interferences during the measurements of the small cur-
rents. And the other reason is that the SiC device parameters
in the simulation model are not consistent well with the actual
device parameters. Though there are derivations, the verification
purpose is achieved, which also proves the robustness of this
method.
The turn-ON current waveforms under different Rg _ext(on)
and different Iload are shown in Fig. 24. It can be concluded
that the turn-ON dynamic current of the OL module is more
balanced under different switching conditions. It can also be seen
by comparing (a) with (c) in Fig. 24 that for the OL module, i2
tends to be closer to i1 and even larger than i1 when the turn-ON
speed is faster. It means i2 tends to change faster than i1 under Fig. 25. Experimental turn-OFF current waveforms of the two modules under
different Rg _ext(off) and Iload . (a) Rg _ext(off) = 2.2 Ω and Iload = 75 A. (b)
a faster switching speed. Rg _ext(off) =2.2 Ω and Iload = 50 A. (c) Rg _ext(off) = 4.7 Ω and Iload =
The turn-OFF current waveforms under different Rg _ext(off) 75 A. (d) Rg _ext(off) = 4.7 Ω and Iload = 50 A.
and different Iload are shown in Fig. 25. It can be concluded
that the turn-OFF dynamic current of the OL module is more
balanced under different switching conditions. It can also be points where Rg _ext(on) = 2.2 Ω and Rg _ext(off) = 4.7 Ω, |Δi|
seen by comparing (a) with (c) or (b) with (d) in Fig. 25 that for performs the lowest under different load currents.
the OL module, i2 tends to be lower than i1 when the turn-OFF As shown from the dotted lines in Fig. 26, as for the OL
speed is faster. It also means i2 tends to change faster than i1 module, Δi will be smaller and even become negative under a
under a faster switching speed. faster switching speed during the turn-ON period. And it will be
To further demonstrate the advantages of the current balancing larger and even become positive under a faster switching speed
method. The values of Δi when i1 +i2 = Ilaod /2 under different during the turn-OFF period. This is because the impedance of the
Rg _ext and Iload are depicted in Fig. 26. Under different condi- RC branch is smaller under a faster switching speed, and there
tions, the current difference |Δi| of the OL module is reduced will be more transient current flows into the RC branch. Then,
by more than 50% compared to the TL module. On the design vs1s2 and dik /dt will be changed. Through the effect of dik /dt, i2

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LV et al.: DYNAMIC CURRENT BALANCING METHOD FOR PARALLELED SIC MOSFETs 13379

Fig. 27. Turn-ON and turn-OFF switching loss differences of the two modules
under different Rg _ext and Iload . (a) Turn-ON loss differences. (b) Turn-OFF
loss differences.
Fig. 26. Δi values of the two modules under different Rg _ext and Iload . (a)
Δi values during the turn-ON period. (b) Δi values during the turn-OFF period.

for the OL module, when the switching speed is faster, Δ Eon

will tend to be closer to i1 . If the switching speed is fast enough, is lower, and Δ Eoff is larger. As for the TL module, when the
i2 will be larger than i1 during the turn-ON period and lower than switching speed is faster, |Δ Eon | and |Δ Eoff | are lower.
i1 during the turn-OFF period. Moreover, to further verify the current balancing method, the
As shown from the solid lines in Fig. 26, for the TL module, difference of the total switching loss between Q1 and Q2 has to
Δi will also be smaller under a faster switching speed during the be compared. The total switching loss is the sum of turn-ON loss
turn-ON period. And it will also be larger under a faster switching and turn-OFF loss. The total switching loss of Q1 and the total
speed during the turn-OFF period. The faster the switching speed, switching loss of Q2 can be expressed as
the lower the |Δi| is. However, the sign of Δi will not change.

To investigate the influence of the current balancing method E1 = E1on + E1off

(15)
on the switching loss difference, the turn-ON and turn-OFF E2 = E2on + E2off
switching loss differences between Q1 and Q2 under different
conditions are depicted in Fig. 27. The turn-ON and turn-OFF loss where E1 is the switching loss of Q1, and E2 is the switching
differences can be expressed as loss of Q2. Then, according to (14) and (15), the difference of
the total switching loss between Q1 and Q2 can be expressed as

ΔEon = E1on − E2on

(14) ΔE = E1 − E2 = (E1on + E1off ) − (E2on + E2off )
ΔEoff = E1off − E2off
= (E1on − E2on ) + (E1off − E2off )
where E1on is the turn-ON loss of Q1, E2on is the turn-ON loss of
Q2, E1off is the turn-OFF loss of Q1, and E2off is the turn-OFF = ΔEon + ΔEoff . (16)
loss of Q2. It is shown in Fig. 27 that under different conditions,
the turn-ON and turn-OFF losses of the OL module are more It can be seen from (16) that ΔE is the sum of the turn-ON
balanced than that of the TL module. The |Δ Eon | and |Δ Eoff | loss difference Δ Eon and the turn-OFF loss difference Δ Eoff . A
of the OL module are also reduced by more than 50% compared smaller |ΔE| indicates that the total switching loss of Q1 is closer
to the TL module. Moreover, the changing tendencies of Δ Eon to that of Q2. Fig. 28 shows the |ΔE| under different Rg _ext and
and Δ Eoff with Rg _ext and Iload are almost the same as Δi. As Iload , where ΔE(TL) is the ΔE in the TL module, and ΔE(OL)

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 13380 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 11, NOVEMBER 2022

Fig. 29. Structure of the power module with more paralleled devices. (a)
Three-dimensional structure of the module. (b) Equivalent circuit (parasitic
components and drive loops are not depicted).

balancing method is verified. In some cases, the difference

between |ΔE(OL) | and |ΔE(TL) | is small. This is because ΔE(TL)
is the sum of ΔEon(TL) and ΔEoff(TL) , as shown in (17). And
the signs of ΔEon(TL) and ΔEoff(TL) are opposite, as shown
in Fig. 27. In these cases, though the values of |ΔEon(TL) |
and |ΔEoff(TL) | are relatively large, the difference between
|ΔEon(TL) | and |ΔEoff(TL) | is small, making |ΔE(TL) | small.

VI. APPLICATION IN CIRCUIT WITH MORE

A. Paralleled Devices
To further verify the effectiveness of the method when more
MOSFETs are paralleled, a multichip power module with a general
layout is optimized in this chapter. The three-dimensional (3-D)
structure of this module is shown in Fig. 29(a). Six SiC MOSFETs
(S4102) are paralleled as the low-side switch, and six SiC diodes
(S6305) are used as the high-side free-wheeling diode to form
a 1200 V/300 A chopper module. To simplify the structure and
design process, the MOSFETs are divided into three groups: 1)
switch 1 (Q1 and Q2), 2) switch 2 (Q3 and Q4), and 3) switch
3 (Q4 and Q5). Two groups of integrated snubbers (snubber 1
Fig. 28. Comparison of |ΔE| between the two modules under different con- and snubber 2) are connected between the source of the three
ditions. (a) Iload = 75 A. (b) Iload = 64 A. (c) Iload = 50 A. (d) Iload =
25 A. switches to perform the current balancing method. Each group
of snubber contains two 4.4 nF, 3.5 Ω monolithic Si-RC chips to
ensure the current capacity. Then, the circuit can be considered as
is the ΔE in the OL module, as shown in containing three paralleled switches and two snubber branches.

The equivalent circuit of the module is shown in Fig. 29(b),
ΔE(TL) = ΔEon(TL) + ΔEoff(TL) where parasitic components and the drive loops are not depicted.
(17)
ΔE(OL) = ΔEon(OL) + ΔEoff(OL) . By adjusting the connecting locations of snubber 1 and snub-
ber 2 between the source of the three switches, the dynamic
In most cases, |ΔE(OL) | is much lower than |ΔE(TL) |, which current can be balanced. The following simple optimization
means that the switching loss between Q1 and Q2 is more method based on simulation is adopted to optimize the con-
balanced in the OL module. The effectiveness of the current necting locations.

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LV et al.: DYNAMIC CURRENT BALANCING METHOD FOR PARALLELED SIC MOSFETs 13381

differences during turn-ON and turn-OFF periods are reduced by

77% and 71.1%, respectively. Moreover, it can be concluded
from Fig. 30(c) that the current difference can be further re-
duced by optimizing the connecting locations. Compared to the
module without internal snubbers, the current differences during
turn-ON and turn-OFF periods are reduced by 84.4% and 81.3%,
respectively. The effectiveness of the current balancing method
when more MOSFETs are paralleled is verified.

VII. CONCLUSION
A. Conclusions of the Current Sharing Model
To present the current balancing method in this article, the
dynamic current sharing mechanism is deeply analyzed first
by an analytical model. This model obtains the key parameter
that influences the dynamic current sharing and the influence
relationship between different parameters. The physical expla-
nations are also concluded.
dik /dt is the key parameter that influences the balance of
the drive circuit and the dynamic current. The sign of dik /dt
Fig. 30. Turn-ON and turn-OFF waveforms under different snubber connecting
locations when Iload = 300 A. (a) Module with no internal snubber. (b) Module
determines the sign of Δi. If dik /dt > 0, Δig < 0, Δvgs < 0,
with snubbers connected to the middle point of the source copper traces between Δi < 0, and i1 < i2 . If dik /dt < 0, Δig > 0, Δvgs > 0, Δi >
the switches. (c) Module with snubbers connected to the optimized location. 0, and i1 > i2 . If Ls1 < Ls2 , during the turn-ON period, dik /dt
< 0 making i1 > i2 . During the turn-OFF period, dik /dt > 0,
making i1 < i2 . If Ls1 > Ls2 , during the turn-ON period, dik /dt >
The parasitic parameter matrix of the module is extracted 0 making i1 < i2 . During the turn-OFF period, dik /dt < 0, making
from the 3-D model using Q3D. Then, the double pules test i1 > i2 . Moreover, in the same current commutating time, higher
is conducted in LTspice with the extracted matrix and device |dik /dt| can cause higher |Δig |. Then, |Δvgs | is higher making |Δi|
models. Then, the switching waveforms under different snubber higher.
connecting locations can be obtained by changing the 3-D model The conclusions of the model are verified by simulations
and performing simulations. and experiments. The conclusions can be used to guide the
1) The connecting location of snubber 2 is first adjusted to current balancing design of power electronic circuits or power
make the dynamic current of switch 3 close to 1/3 of the modules and can be extended to the case when more chips are
total current. paralleled.
2) Then, the connecting location of snubber 1 is adjusted to
make the dynamic current of switch 1 close to 1/3 of the
total current. B. Conclusions of the Current Balancing Method
3) Then, a balanced dynamic current can be achieved. Based on the conclusions of the dynamic current sharing
The more convenient theoretical model to calculate the opti- model, this article presents a dynamic current balancing method
mized locations in the circuit with 3 or more paralleled switches by connecting the dc-link RC snubber between paralleled MOS-
will be presented in future work. FETs, which maintains a simple circuit structure and is easy to
The turn-ON and turn-OFF waveforms under different snubber implement. A balanced dynamic current can be achieved by
connecting locations are shown in Fig. 30 when Iload = 300 A. adjusting the RC snubber connecting location. And this method
The drain currents of Q1–Q6 are depicted as i1 –i6 , respectively. is demonstrated by the SiC power module with the monolithic
The waveforms of the module with no internal snubber are Si-RC snubber. The optimized location of the RC snubber is
shown in Fig. 30(a). To decouple the link inductance and damp determined by theoretical calculation. By simulations and exper-
the oscillation, an outside RC snubber is added near the module iments, the current balancing method and the method to solve the
terminal. The dynamic current difference is large. The current RC snubber’s optimized connecting location are well verified.
difference is 80 A (26.7% of Iload ) during the turn-ON period The OL module performs more than 50% lower dynamic current
when the MOSFETs’ current reaches Iload . During the turn-OFF differences and more than 50% lower switching loss differences
period, the current difference is 23.5 A (7.8% of Iload ) when the under different conditions.
MOSFETs’ current reaches Iload /5. Moreover, to demonstrate the effectiveness of the method
The waveforms of the module with integrated snubbers are when more MOSFETs are paralleled, a multichip power module
shown in Fig. 30(b) and (c). From Fig. 30(b), the dynamic current is optimized by simulation. The optimized module performs a
can be well balanced when the snubbers are simply connected balanced dynamic current.
to the middle point of the copper traces between the switches. This method can also be used in circuits with paralleled
Compared to the module without internal snubbers, the current discrete SiC MOSFETs.

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 13382 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 11, NOVEMBER 2022

APPENDIX Solve the Laplace transform of (A3) and (A4). Then, the
equations of ig1 , ig2 , vgs1 , and vgs2 can be derived as
A. Assumptions During the Current Commutation Period 
During the current commutation period, the following as- Ig1 = V1 −sLZ1
k1 Ik

(A6)
sumptions can be made. Ig2 = V2 +sLZ2
k2 Ik

1) The influence of power source parasitic inductances is

 vgs1 (0)
studied. The characteristic parameters of the two paral- Vgs1 = V1sC
−sLk1 Ik
iss Z1
+ s
leled MOSFETs are considered the same. vgs2 (0)
(A7)
2) The MOSFETs work in the saturation region. They can be Vgs2 = V2sC
+sLk2 Ik
iss Z2
+ s
equivalent to current sources, with current values varying where V1 , V2 are determined by the values of the initial condi-
between 0 and Iload /2. The equivalent current sources tions in the circuit and given by
are controlled by the gate-source voltages, which can be 
V −v (0)
expressed as V1 = g sgs1 + (Lg1 + Lk1 )ig1 (0) + Lk1 ik (0)
V −v (0) (A8)

V2 = g sgs2 + (Lg2 + Lk2 )ig2 (0) − Lk2 ik (0)
i1 = gm (vgs1 −Vth )
(A1) and Z1 , Z2 are the impedances of the two driving loops, respec-
i2 = gm (vgs2 −Vth )
tively, and given by
where gm is the transconductance of the MOSFETs and Vth is the

Z1 =Rg1 + sLg1 + sC1iss + sLk1

threshold voltage of the MOSFETs. (A9)
Z2 =Rg2 + sLg2 + sC1iss + sLk2 .
3) The drain-source parasitic capacitance (Cds ) of the MOS-
FETs is neglected [16]. The gate-source voltage of each MOSFET is Performing Laplace transform, (A1) can be written as
determined by the gate current flowing into the input capacitance

I1 =gm (Vgs1 −Vth /s)

[35]. The input capacitance can be written as (A10)
I2 =gm (Vgs2 −Vth /s).
Ciss = Cdg + Cgs (A2) Solve (A5) and perform Laplace transform. Then, the equa-
tion of the power circuit can be expressed as
where Cdg is the drain-gate parasitic capacitance, and Cgs is the
s(Lk1 + Lk2 + Ls1 + Ls2 )Ik
gate-source parasitic capacitance. (A11)
=sLs1 I1 −sLs2 I2 −sLk1 Ig1 +sLk2 Ig2 +V3
4) Due to the high value of the dc-link bulk capacitance Clink
and the dc-link decoupling capacitance Cdec , the voltage on where V3 is also determined by the values of the initial conditions
the dc-link capacitors is considered constant. So, the dc-link and given by
capacitors can be equivalent to a constant voltage source.
V3 = (Lk1 + Lk2 )ik (0) + Lk1 ig1 (0) − Lk2 ig2 (0)
5) The load inductance Lload is large enough to be equivalent
to a constant current source Iload . − Ls1 is1 (0) + Ls2 is2 (0). (A12)
6) During the current commutation period, the diode D1 is
Analyzing the influence of unbalanced power source induc-
conducted and is considered short circuit.
tances on the dynamic current sharing, it can be supposed that
⎧
⎨ Lg1 =Lg2 =Lg
B. Circuit Equations of the Simplified Circuit in Fig. 3
Lk1 =Lk2 =Lk (A13)
⎩
According to the circuit model in Fig. 3, taking the initial Rg1 =Rg2 =Rg .
current commutation time as the initial time (t = 0), the equations
The initial conditions of the circuit can be expressed as
of the drive circuit can be expressed as ⎧
 ⎪
⎪ is1 (0) = is2 (0) = I0
dig1 dig1 ⎨
Vg =ig1 Rg1 + Lg1 dt + vgs1 + ( dt + dt )Lk1
dik
ig1 (0) = ig2 (0) = Ig0
(A3) (A14)
dig2 dig2 ⎪
⎪ vgs1 (0) =vgs2 (0) =I0 /gm + Vth
Vg =ig2 Rg2 + Lg2 dt + vgs2 + ( dt − dt )Lk2
dik
⎩
ik (0) = 0.
where Then, according to (A13) and (A14), V1 , V2 , V3 , Z1 , and Z2
 t can be written as
vgs1 = C1iss 0 ig1 dt + vgs1 (0) ⎧ V −I /g −V
t (A4) ⎨ V1 =V2 = g 0 s m th + (Lg + Lk )Ig0
vgs2 = C1iss 0 ig2 dt + vgs2 (0). V = − (Ls1 −Ls2 )I0 (A15)
⎩ 3
Z1 =Z2 =Z=Rg + sLg + sC1iss + sLk .
The equations of the power circuit can be expressed as
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 13384 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 11, NOVEMBER 2022

Cai Chen (Member, IEEE) received the B.S. and Yiyang Yan received the B.S. degree in functional
Ph.D. degrees in electrical and electronic engineering material and the M.S. degree in electrical and elec-
from Huazhong University of Science and Technol- tronic engineering from Huazhong University of Sci-
ogy, Wuhan, China, in 2008 and 2014, respectively. ence and Technology, Wuhan, China, in 2018 and
He is an Associate Research Fellow with Huazhong 2021, respectively, where he is currently working
University of Science and Technology. From Mar. toward the Ph.D. degree with the School of Electrical
2013 to Dec. 2013, he was an Intern with GE Global and Electronic Engineering.
Research Center, Shanghai, China. From 2014 to His current research interests include wide-
2016, he was with the Advanced Semiconductor, bandgap devices double-sided cooling package, high
Packaging and Integration Lab, Huazhong University power density inverters, and package thermal model-
of Science and Technology, Wuhan, Hubei, China as a ing.
Postdoctoral Researcher. From 2016 to Oct. 2017, he was a visiting scholar with
the Center for High Performance Power Electronics, The Ohio State University,
Columbus, OH, USA. From 2017 to Oct. 2018, he was a visiting scholar with
the College of Engineering, University of Arkansas, Fayetteville, AR, USA. In
2019, he was with the Huazhong University of Science and Technology, Wuhan,
China, as an Associate Research Fellow. His research interests include WBG
devices packaging, integration, packaging EMI issues, packaging reliability, and
high-density applications.
Yong Kang (Senior Member, IEEE) was born in
Hubei Province, China, in Oct. 16, 1965. He received
the B.E. M.E, and Ph.D. degrees from Huazhong
Baihan Liu received the B.S. degree in electrical and
University of Science and Technology, Wuhan China,
electronic engineering in 2021 from Huazhong Uni-
in 1988, 1991, and 1994, respectively.
versity of Science and Technology, Wuhan, China,
In 1994, he was with Huazhong University of Sci-
where he is currently working toward the Ph.D. degree
ence and Technology as a Lecturer and was promoted
with the School of Electrical and Electronic Engineer-
ing. to Associate professor in 1996 and to Full Professor
in 1998. He has authored more than 60 technical pa-
His current research interests include wide bandgap
pers. His research interests include power electronic
devices packaging, integration, and high-temperature
converter, ac drivers, electromagnetic compatibility,
applications.
their digital control techniques, WBG device packaging, and applications.

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