Computer Fundamentals 2
Computer Fundamentals 2
Answer
C. LCDs essentially act as a capacitor and consume almost no power
127. A computer language that enables Programmable Array Logic (PAL) users to
generate a file that can be used to blow a PAL.
A. JEDEC
B. PALASM
C. TURBO C++
D. Visual C
Answer
B. PALASM
A. Data bus
B. Address
C. Control bus
D. Calling bus
Answer
A. Data bus
129. A table used by PLD language, such as PALASM, to calculate the expected
outputs for a set of inputs.
A. Excitation table
B. State table
C. Stimulation table
D. Truth table
Answer
C. Simulation table
130. A programmable block of logic within a gate array, that contains a flip-flop for
storage and also allows the user to specify logic functions on its inputs.
A. Programmable block
B. PLD
C. Configurable logic block
D. Block diagram
Answer
C. Configurable logic block
131. This type of bus carries the memory address from the computer to the memory.
A. Data bus
B. Address bus
C. Control bus
D. Parallel bus
Answer
B. Address bus
132. This bus carries lines that control the operation of the memory from the
microprocessor to the memory.
A. Data bus
B. Address bus
C. Control bus
D. Bus lines
Answer
C. Control bus
133. A register which holds the address of the word currently being accessed.
A. Hold register
B. Memory address register
C. Memory data register
D. Access register
Answer
B. Memory address register
134. A register which holds the data being written into or read out of the addressed
memory location.
A. Hold register
B. Memory address register
C. Memory data register
D. Glitch register
Answer
B. Memory data register
135. A preproduction register model of a system built for testing and debugging.
A. Wire list
B. Maybe (colloquial)
C. Prototype
D. Sample
Answer
C. Prototype
A. Buzz-out
B. Debugging
C. Trap
D. Fault corrector
Answer
B. Debugging
A. 2
B. 3
C. 4
D. 5
Answer
B. 3
138. A sequential logic circuit where the storage elements commonly used is time-
delay devices (usually gates).
A. Synchronous SLC
B. Asynchronous SLC
C. Counter
D. Register
Answer
B. Asynchronous SLC
139. A block added to the combinational logic circuit to form a sequential logic circuit
is the
A. ROM
B. counter
C. clock
D. memory
Answer
D. memory
140. The state of the flip-flop before the occurrence of a clock pulse is called as its
A. present state
B. next state
C. current input
D. present output
Answer
A. present state
141. The state of the flip-flop after the occurrence of a clock pulse is called as its
A. current state
B. present state
C. next state
D. current input
Answer
C. next state
142. It is said to be a universal gate because any digital system can be implemented
with it.
A. NAND
B. AND
C. OR
D. Exclusive OR
Answer
A. NAND
A. T
B. D
C. JK
D. RS
Answer
B. D
144. An n-bit binary parallel adder requires ___________ in its least design.
A. n half adders
B. n half subtractor
C. n full adders
D. n half subtractor and n full adder
Answer
C. n full adders
A. number of inputs
B. number of comparator bits
C. number of out puts
D. number of inputs and outputs
Answer
B. number of comparator bits
A. setting
B. cascading inputs
C. input terminals
D. address
Answer
B. cascading inputs
A. 2
B. 4
C. 16
D. 32
Answer
B. 4
148. If F = xy + x’y’ Boolean expression is to be implemented using decoders and OR
gates, the connection involves
Answer
C. 2 to 4 line decoder with 1 OR gate
Solution
F= xy + x’y’
11 00
Truth Table:
INPUTS OUTPUTS
X Y F
0 0 1 n = 2(x,y)
0 1 0
1 0 0
1 1 1
NC = not connected
Therefore 2 x 4 decoder with one OR gate
149. How many AND gates and 4-bit binary adders are needed to implement a 2-bit to
3-bit binary multiplier?
Answer
B. 2 AND gates and one 4-bit binary adder
Solution:
B2B1B0 let:
x A1A0 A 0 . B0 = d 0 A1 . B0 = e0
d2d1d0 A 0 . B1 = d 1 A1 . B1 = e1
+e2e1e0 A 0 . B2 = d 2 A2 . B2 = e2
Circuit diagram:
150. From a 3-bit binary counter design using T flip-flops, determine the number of T
flip-flops needed in its circuit implementation.
A. 1
B. 2
C. 3
D. 4
Answer
C. 3
151. A system coordinating I/O between the transmitting and receiving devices.
A. Charging
B. Handshaking
C. Interfacing
D. Polling
Answer
B. Handshaking
152. An area of memory that holds the ASCII characters that are being displayed on a
monitor.
A. Space
B. Start bit
C. Terminal
D. Screen image
Answer
D. Screen image
153. An IC that transform parallel data to serial in the asynchronous format and vice
versa.
A. UART
B. USART
C. MODEM
D. RS232C
Answer
A. UART
154. An instruction that alters the normal course of a program by causing it to jump to
another instruction.
A. Rotate instruction
B. Skip instruction
C. Jump
D. ACC
Answer
C. JUMP
155. An instruction that causes data to be brought from memory into an accumulator
register.
A. LOAD
B. LOOP
C. FETCH
D. JUMP
Answer
A. LOAD
156. The portion of an instruction cycle where the instruction is sent from memory to
the instruction register.
A. LOAD
B. ACCUMULATE
C. FETCH
D. EXECUTE
Answer
C. FETCH
157. An instruction that causes data in the accumulator to be moved to the memory or
a peripheral register.
A. FETCH
B. STORE
C. LOOP
D. LOAD
Answer
B. STORE
158. This occurs when the result of an arithmetic operation is a more negative number
than the output register can accommodate.
A. Error
B. Overflow
C. Underflow
D. Don’t care
Answer
C. Underflow
159. This occurs when of an arithmetic operation is a larger number than the output
register can accommodate.
A. Overflow
B. Inflow
C. Underflow
D. Lock-ahead carry
Answer
A. Overflow
A. 2’s complement
B. Inversion
C. Signed numbers
D. Indeterminate
Answer
A. 2’s complement
161. Which of the following is the language used in making an internet web page?
Answer
B. Hypertext mark-up language
162. A program which can be executed on several different computers to compare their
speed and performance.
A. Compiler
B. Assembler
C. Diagnostic program
D. Benchmark
Answer
D. Benchmark
163. A single word memory location used to temporarily hold data during program
execution.
A. Accumulator
B. Register
C. Buffer
D. Stack
Answer
B. Register
164. Refer to the debugging method in which the program is executed one instruction
at a time and the register contents can be examined after each step?
A. Text editing
B. Syntax analyzing
C. Trace
D. Semantic tracing
Answer
C. Trace
165. In a computer system, it is a unit of hardware where the control keys are located.
A. CPU
B. Keyboard
C. I/O section
D. Console
Answer
D. Console
166. If a certain circuit acts an AND gate when used with positive logic (H = 1, L = 0),
what function will it perform when used with negative logic (H = 0, L = 1)?
A. OR
B. AND
C. NAND
D. NOR
Answer
A. OR
167. TTL, DTL, and ECL, which are frequently used to refer to certain “families” of
digital integrated circuits, are actually names of
Answer
D. general varieties of electronic circuits used as logic gates from which, in
essence, the building blocks in each series are constructed
168. In the data sheet of a digital building block, operating speed is typically expressed
in terms of
A. capacitance C
B. transition frequency
C. propagation delay times for both possible output transitions
D. miles per hour or centimeters per second
Answer
C. propagation delay times for both possible output transitions
169. The fan out capability of a digital building block depends on the current capability
of its output and the current requirement of each input driven by that output, and
maybe defined as the
Answer
A. number of inputs that one output can transmit to
170. Noise margin, which is one indication of how likely it is that information
communicated between digital building blocks will be incorrect due to noise,
depends on
A. output current capabilities and input current requirements
B. output power and required input power for the two logic states
C. the “safety margin” between the output voltage produced by the transmitting
block and input voltage required by the receiving block for each two logic
state
D. the “safety margin” between the noise level and the noise figure
Answer
C. the “safety margin” between the output voltage produced by the
transmitting block and input voltage required by the receiving block for each
of the two logic state.
171. Typical propagation delay range for modern digital integrated circuits is
A. 1 to 100 milliseconds
B. 1 to 100 microseconds
C. 1 to 100 nanoseconds
D. 1 to 100 picoseconds
Answer
C. 1 to 100 nanoseconds
172. The most commonly used IC package for the digital integrated circuit is the
A. CMOS pack
B. DIP ceramic
C. DIP plastic
D. Flat pack
Answer
C. DIP plastic
A. ribbon
B. bus
C. wire wrap
D. multiplexed line
Answer
B. bus
174. Which of the following is a form of Morgan’s theorem?
A. A + B = ( AB )
B. AB = ( A + B )
C. ( A + B )’ = A’ . B’
D. A.B = A’ . B’
Answer
C. ( A + B )’ = A’ . B’
Answer
C. both outputs are the same
A. sequential
B. synchronous
C. synchronous
D. pulsed
Answer
B. synchronous
A. frequency divider
B. ripple shift counter
C. BCD counter
D. Binary counter
Answer
C. BCD counter
178. Which of the items below can perform parallel-to-serial data conversion?
A. Shift register
B. Binary counter
C. Multiplexer
D. Decoder
Answer
A. Shift register
A. Counter
B. Resistor network
C. Current switches
D. Reference
Answer
A. Counter
A. 0 and 1
B. High and low
C. True and false
D. All of the choices
Answer
A. 0 and 1
A. 8
B. 4
C. 2
D. 16
Answer
A. 8
A. 1010
B. 0111
C. 1111
D. 1000
Answer
C. 1111
A. A
B. C
C. D
D. E
Answer
D. E
A. 0111110
B. 0111111
C. 0111000
D. 0100011
Answer
B. 0111111
185. In the 7400 Family of TTL Devices, Quad 2-input NAND gates has a device
number equivalent to
A. 7400
B. 7402
C. 7432
D. 7486
Answer
A. 7400
186. Quad 2-input XOR gates in the 7400 Family of TTL devices has a device number
equivalent to
A. 7402
B. 7486
C. 7408
D. 7404
Answer
B. 7486
A. J = 0, K = 0
B. J = 1, K = 0
C. J = 1, K = 1
D. J = 0, K = 1
Answer
C. J = 1, K = 1
188. A digital circuit test equipment which is a troubleshooting tool that generates a
short-duration pulse when activated manually, usually by pressing a button is the
______________.
A. logic probe
B. VOM
C. logic clip
D. logic pulser
Answer
D. Logic pulser
A. R = 0, S = 0
B. R = 1, S = 0
C. R = 0, S = 1
D. R = 1, S = 1
Answer
A. R = 0, S = 0
Answer
A. connecting the two inputs of the JK flip-flop together
191. The number of digits used by a number system.
A. Base
B. Radix
C. 2^n
D. n
Answer
B. Radix
A. Reset
B. Set
C. Undetermined
D. Preset
Answer
A. Reset
Answer
A. Less than 12 gates
Answer
B. Between 12 to 99 gates
Answer
D. 10,000 or more
196. Which of the items below is not a type of the hardware organization in a
computer?
A. Architecture
B. Implementation
C. Hardware realization
D. Assembler
Answer
D. Assembler
197. It consists of instructions and that the computer hardware manipulates to perform
useful work.
A. Software
B. Program
C. File
D. Data
Answer
A. Software
A. data base
B. file
C. input
D. all of the choices
Answer
D. all of the choices
199. The most primitive instructions that can be given to a computer are interpreted
directly by the hardware _____________ form.
A. assembly language
B. machine language
C. high-level language
D. simulator
Answer
B. machines language
200. It represents machine instruction mnemonic names and allows no addresses and
other constants represented be symbols rather bit strings.
A. Assembler
B. Machine language
C. Assembly language
D. Interpreter
Answer
C. Assembly language
A. Assembler
B. Interpreter
C. Compiler
D. Debugger
Answer
C. Compiler
202. Text editors and formatters belong to the area of computing known as
_____________.
A. software
B. word processing
C. compilers
D. assemblers
Answer
B. word processing
Answer
A. the heart of the computer
204. Processors with more than two registers for arithmetic and logical operations are
classified as
Answer
B. general register processors
A. ROM
B. RAM
C. PLA
D. PLD
Answer
A. ROM
206. With a ____________ a processor can store data at any address and read back the
stored information at any time
A. RWM
B. ROM
C. PLA
D. PROM
Answer
A. RWM
207. The system program use to translate directly an assembly language to machine
language is called
A. assembler
B. compiler
C. text editor
D. debugger
Answer
A. assembler
A. SOC
B. EOC
C. PAC
D. EAR
Answer
A. SOC
209. Speeds of modems are generally classified by the number of ____________ they
can transmit.
Answer
B. bits per second
Answer
C. between 2400 and 9600 bps
A. phase-shift modulation
B. dibit modulation
C. frequency shift keying
D. amplitude modulation
Answer
C. frequency shift keying
212. Low speed modems generally handle data rates between
Answer
B. 300 and 2400 bps
213. The most important memory element which is made of an assembly of logic gates
is called
A. latch
B. bistable multivibrator
C. flip-flop
D. all of the choices
Answer
C. Flip-flop
214. What is the normal resting state of the SET and CLEAR inputs in a flip-flop?
A. Low, high
B. High, low
C. High, high
D. Low, low
Answer
A. Low, high
215. What will be the states of Q and Q’ after a flip-flop has been cleared?
A. Q = 1, Q’ = 0
B. Q = 0, Q’ = 1
C. Q = 0, Q’ = 0
D. Q = 1, Q’ = 1
Answer
B. Q = 0, Q’ = 1
216. When power is first applied to any flip-flop circuit, it is impossible to predict the
initial state of Q and Q’. What could be done to ensure that NAND latch always
started off in the Q = 1 state?
A. Apply a momentary HIGH to PRESET input
B. Apply a momentary LOW to SET input
C. Apply a momentary LOW to CLEAR input
D. Apply a momentary HIGH to CLEAR input
Answer
B. Apply a momentary LOW to SET input
217. When a flip-flop is set, what are the states of Q and Q’?
A. Q = 1, Q’ = 0
B. Q = 0, Q’ = 1
C. Q = 0, Q’ = 0
D. Q = 1, Q’ = 1
Answer
A. Q = 1, Q’ = 0
Answer
A. Synchronous control inputs and clock input
219. The flip-flop can change only when the appropriate clock transition occurs. IT is a
condition called
A. edge triggered
B. latching
C. clocking
D. pulsing
Answer
A. edge triggered
220. It is required interval immediately following the active edge of the clock signal
during which the control input must be held stable.
A. Hold time
B. Pulsing time
C. Set-up time
D. All the time
Answer
C. Set-up time
221. It is required interval immediately following the active edge held of clocks during
which the control input must be held.
A. Set-up time
B. Hold time
C. Pulsing time
D. Propagation time
Answer
B. Hold time
222. What JK input condition will always set Q upon the occurrence of the active clock
transition?
A. J = 0, K = 0
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 1, K = 1
Answer
B. J = 1, K = 0
223. How does the operation of an asynchronous input differ from that a synchronous
input?
Answer
A. It works independently of the clock input
224. The triangle inside the rectangle which is part of the IEEE/ANSI symbol at clock
input
A. indicates the function of those inputs that are common to more than one
circuit on the chip
B. indicates triggering on a NGT
C. indicates edge-triggered operation
D. all of the choices
Answer
B. indicates edge-triggered operation
225. Which type of flip-flop is best suited for synchronous transfer because it requires
the fewest interconnections from one flip-flop to the other?
A. JK
B. T
C. RS
D. D
Answer
D. D
226. The fastest method for transferring data from one register to another is the
A. serial transfer
B. parallel transfer
C. hybrid transfer
D. FIFO
Answer
B. parallel transfer
227. What is the major advantage of serial transfer over parallel transfer?
Answer
C. Fewer interconnections between registers
228. A 20kHz clock signal is applied to a JK flip-flop when J = , K = 1. What is the
frequency of the flip-flop output waveform?
A. 20 kHz
B. 10 kHz
C. 40 kHz
D. 5 kHz
Answer
B. 10 kHz
229. How many flip-flops are required for a counter that will count 0 to 255?
A. 2
B. 4
C. 16
D. 8
Answer
D. 8
Solution:
Proof:
A. Converter
B. Inverter
C. Transducer
D. Compiler
Answer
C. Transducer
231. What does a computer do with the data it receives from an ADC?
Answer
D. All of the choices
Answer
B. control a physical variable according to an electrical input signal
233. The maximum deviation of DAC output from its ideal value, expressed as
percentage of full scale
Answer
A. Full scale error
234. The time it takes for the DAC output to settle to within ½ step size of its full scale
value when the digital input changes from zero to full scale.
A. Setting time
B. Set-up time
C. Hold time
D. Full scale time
Answer
A. Setting time
235. Why are voltage DAC’s generally slower than current DAC’s?
Answer
A. Because of the response time of the op-amp current-to-voltage converter
236. What is the function of the comparator in the ADC?
A. Tells control logic when the DAC output exceeds the analog input
B. Compares two parameters only
C. Addition and multiplication
D. Arithmetic operation
Answer
A. Tells control logic when the DAC output exceeds the analog input
A. It is a code placed in the last one or two ROM locations that represents the
sum of the expected ROM data from all other locations
B. Used as a mean to test for leakage in one or more ROM locations
C. Prevents decoding glitches
D. Regulates ROM
Answer
A. It is a code place in the last one or two ROM locations that represents the
sum of the expected ROM data from all other locations.
Answer
B. Synchronization of digital information transmission between the computer
and external I/O devices
239. Which of the items below is not one of the three major sections of an MPU?
A. The binary code that represent the operation to be performed by the CPU
B. The address of the data to be operated as the CPU executes the instruction
called by the opcode.
C. A short abbreviation for the operation
D. All of the choices
Answer
B. The address of the data to be operated as the CPU executes the instruction
called by the opcode.
241. What device puts data on the data bus during a write operation?
A. ALU
B. CPU
C. Keyboard
D. Accumulator
Answer
B. CPU
Answer
A. a short abbreviation for the operation
243. Arrival of a clock signal at the data inputs of different flip-flops at delay times as
a result for propagation delays.
A. Clock transition
B. Buffer address
C. Clock skew
D. None of the choices
Answer
C. clock skew
244. A circuit made up of combination logic gates, with no feedback from output to
input.
Answer
A. Combinational logic circuit
245. A logic circuit that depending on the status of its select inputs will channel its data
input to one of several data outputs
A. MUX
B. DMUX
C. RAM
D. ROM
Answer
B. DMUX
Answer
D. (75.4)8
Solution:
247. An analog memory circuit used to eliminate apenure error is called a
A. MUX
B. DMUX
C. Track/store amplifier
D. Flip-flop
Answer
C. Track/store amplifier
A. Logic probe
B. Oscilloscope
C. Logic analyzer
D. Logic monitor
Answer
D. Logic monitor
A. a source program
B. an object program
C. machine program
D. users program
Answer
B. an object program
A. 1001.01
B. 1.11
C. 10.11
D. 1.00
Answer
B. 1.11
Solution: