SN54/74LS173A 4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS

The SN54 / 74LS173A is a high-speed 4-Bit Register featuring 3-state outputs for use in bus-organized systems. The clock is fully edge-triggered allowing either a load from the D inputs or a hold (retain register contents) depending on the state of the Input Enable Lines (IE1, IE2). A HIGH on either Output Enable line (OE1, OE2) brings the output to a high impedance state without affecting the actual register contents. A HIGH on the Master Reset (MR) input resets the Register regardless of the state of the Clock (CP), the Output Enable (OE1, OE2) or the Input Enable (IE1, IE2) lines. Fully Edge-Triggered 3-State Outputs Gated Input and Output Enables Input Clamp Diodes Limit High-Speed Termination Effects
16 1

4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS

LOW POWER SCHOTTKY

J SUFFIX CERAMIC CASE 620-09

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC 16 MR 15 D0 14 D1 13 D2 12 D3 11 IE2 10 IE1 9
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1

N SUFFIX PLASTIC CASE 648-08

16

1 OE1

2 OE2

3 Q0

4 Q1

5 Q2

6 Q3

7 CP

8 GND

D SUFFIX SOIC CASE 751B-03

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

PIN NAMES

LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 (7.5) U.L.

D0 D3 IE1 IE2 OE1 OE2 CP MR Q0 Q3

Data Inputs Input Enable (Active LOW) Output Enable (Active LOW) Inputs Clock Pulse (Active HIGH Going Edge) Input Master Reset Input (Active HIGH) Outputs (Note b)

0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 (25) U.L.

LOGIC SYMBOL
9 10 1 2 IE CP 1 2 OE MR D0 D1 D2 D3 14 13 12 11

NOTES: a. 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges.

7 1 2

Q0 Q1 Q2 Q3

15

3 4 5 6

VCC = PIN 16 GND = PIN 8

FAST AND LS TTL DATA 5-316

SN54/74LS173A
LOGIC DIAGRAM
D0
14

D1
13

D2
12

D3
11

IE1 IE2

10

CP
7

CP D Q Q

MR

15

OE1 OE2

Q0

Q1

Q2

Q3

VCC = PIN 16 GND = PIN 8 = PIN NUMBERS

TRUTH TABLE
MR H L L L L L CP x L IE1 x x H x L L IE2 x x x H L L Dn x x x x L H Qn L Qn Qn Qn L H

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

When either OE1, or OE2 are HIGH, the output is in the off state (High Impedance); however this does not affect the contents or sequential operation of the register.

GUARANTEED OPERATING RANGES

Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Parameter 54 74 54 74 54 74 54 74 Min 4.5 4.75 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 1.0 2.6 12 24 Unit V C mA mA

FAST AND LS TTL DATA 5-317

SN54/74LS173A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current 30 0.4 130 30 0.35 0.5 20 20 20 V A A A mA mA mA mA 2.4 3.1 0.25 0.4 V V 2.4 0.65 3.4 0.8 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VO = 2.7 V VCC = MAX, VO = 0.4 V VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C)

Limits Symbol fMAX tPLH tPHL tPHL tPZH tPZL tPLZ tPHZ Parameter Maximum Input Clock Frequency Propagation Delay, Clock to Output Propagation Delay, MR to Output Output Enable Time Output Disable Time Min 30 Typ 50 17 22 26 15 18 11 11 25 30 35 23 27 17 17 Max Unit MHz ns ns ns ns CL = 5.0 pF, RL = 667 VCC = 5.0 V CL = 45 pF, RL = 667 Test Conditions

AC SETUP REQUIREMENTS (TA = 25C)

Limits Symbol tW ts ts th trec Parameter Clock or MR Pulse Width Data Enable Setup Time Data Setup Time Hold Time, Any Input Recovery Time Min 20 35 17 0 10 Typ Max Unit ns ns ns ns ns VCC = 5.0 V Test Conditions

FAST AND LS TTL DATA 5-318

SN54/74LS173A

AC WAVEFORMS

1 / fmax CP 1.3 V tW 1.3 V ts(L) MR tW th(L) 1.3 V Q 1.3 V Q tPLH 1.3 V tPHL 1.3 V trec 1.3 V CP tPHL

ts(H)

th(H) 1.3 V

D or E

Figure 1

Figure 2

VE

1.3 V

1.3 V

VE

1.3 V tPHZ

1.3 V

tPLZ VOUT

tPZL 1.3 V VOL VOUT

tPZH 1.3 V

VOH 1.3 V
0.5 V

0.5 V

Figure 3

Figure 4

AC LOAD CIRCUIT
VCC

RL

SWITCH POSITIONS
SYMBOL SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed

SW1

tPZH tPZL

TO OUTPUT UNDER TEST

tPLZ tPHZ
5 k

CL*

SW2

* Includes Jig and Probe Capacitance.

Figure 5

FAST AND LS TTL DATA 5-319

-A-

Case 751B-03 D Suffix 16-Pin Plastic SO-16

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. 751B 01 IS OBSOLETE, NEW STANDARD 751B 03.

16

-B1 8

P
8 PL

0.25 (0.010)

R X 45 G -TD 16 PL
0.25 (0.010)
M

C
SEATING PLANE

K
T B
S

DIM A B C D F G J K M P R

MILLIMETERS MIN MAX

9.80 3.80 1.35 0.35 0.40 10.00 4.00 1.75 0.49 1.25

INCHES MIN MAX

0.386 0.150 0.054 0.014 0.016 0.393 0.157 0.068 0.019 0.049

1.27 BSC 0.19 0.10 0 0.25 0.25 7

0.050 BSC 0.008 0.004 0 0.009 0.009 7

5.80 0.25

6.20 0.50

0.229 0.010

0.244 0.019

Case 648-08 N Suffix 16-Pin Plastic -A16 9

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: INCH. DIMENSION L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B" DOES NOT INCLUDE MOLD FLASH. 5. 6. ROUNDED CORNERS OPTIONAL. 648 01 THRU 07 OBSOLETE, NEW STANDARD 648 08.

B
1 8

F S

C -TK
SEATING PLANE

H G D 16 PL
0.25 (0.010)
M

DIM A B C D F G H J K L M S

MILLIMETERS MIN MAX

18.80 6.35 3.69 0.39 1.02 19.55 6.85 4.44 0.53 1.77

INCHES MIN MAX

0.740 0.250 0.145 0.015 0.040 0.770 0.270 0.175 0.021 0.070

2.54 BSC 1.27 BSC 0.21 2.80 7.50 0 0.38 3.30 7.74 10

0.100 BSC 0.050 BSC 0.008 0.110 0.295 0 0.015 0.130 0.305 10

0.51

1.01

0.020

0.040

-A16 9

Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH.

-B1 8

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.

5. 620 01 THRU 08 OBSOLETE, NEW STANDARD 620 09.

-TSEATING PLANE

K E F D 16 PL
0.25 (0.010)
M

N G
T A
S

M J 16 PL
0.25 (0.010)
M

DIM A B C D E F G J K L M N

MILLIMETERS MIN MAX

19.05 6.10 19.55 7.36 4.19 0.39 0.53

INCHES MIN MAX

0.750 0.240 0.770 0.290 0.165 0.015 0.021

1.27 BSC 1.40 1.77

0.050 BSC 0.055 0.070

2.54 BSC 0.23 0.27 5.08 7.62 BSC 0

0.100 BSC 0.009 0.011 0.200 0.300 BSC 0

15

15

0.39

0.88

0.015

0.035

FAST AND LS TTL DATA 5-320

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FAST AND LS TTL DATA 5-321

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