LB 820-2054

8
1
CK
APPD
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
REV
SCHEM,MLB
ZONE
ECN
ENG
APPD
DESCRIPTION OF CHANGE
463525
PRODUCTION RELEASE
DATE
DATE
9/19/2006
9/19/2006
D
Date
Page
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
Contents
Sync
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
(.csa)
Page
TABLE_TABLEOFCONTENTS_HEAD
N/A
Table of Contents
N/A
System Block Diagram
N/A
N/A
N/A
N/A
N/A
Power Block Diagram
N/A
BOM Configuration
N/A
Functional / ICT Test
N/A
Signal Aliases/Misc Comps
N/A
6
7
CPU 1 OF 2-FSB
(MASTER)
CPU 2 OF 2-PWR/GND
(MASTER)
8
9
CPU Decoupling & VID
N/A
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
10
CPU MISC1-TEMP SENSOR
(MASTER)
11
CPU ITP700FLEX DEBUG
(MASTER)
12
NB CPU Interface
(MASTER)
13
NB PEG / Video Interfaces
(MASTER)
14
NB Misc Interfaces
(MASTER)
NB DDR2 Interfaces
(MASTER)
15
16
NB Power 1
(MASTER)
(MASTER)
(MASTER)
17
NB Power 2
(MASTER)
18
NB Grounds
(MASTER)
07/25/2006
(MASTER)
(MASTER)
(MASTER)
07/25/2006
(MASTER)
19
NB (GM) Decoupling
M59_MG
20
NB Config Straps
(MASTER)
21
SB: 1 OF 4
(MASTER)
22
SB: 2 of 4
(MASTER)
SB: 3 OF 4
M59_MG
23
24
SB: 4 OF 4
(MASTER)
(MASTER)
(MASTER)
(MASTER)
25
SB Decoupling
(MASTER)
SB Misc
(MASTER)
26
27
M1 SMBus Connections
(MASTER)
(MASTER)
(MASTER)
(MASTER)
28
DDR2 SO-DIMM Connector A
(MASTER)
DDR2 SO-DIMM Connector B
(MASTER)
29
30
Memory Active Termination
(MASTER)
(MASTER)
(MASTER)
(MASTER)
05/07/2006
(MASTER)
(MASTER)
(MASTER)
(MASTER)
(MASTER)
31
Memory Vtt Supply
(MASTER)
DDR2 VRef
(MASTER)
32
33
CLOCKS
(MASTER)
34
Clock Termination
M59_MG
37
Mobile Clocking
(MASTER)
PATA Connector
(MASTER)
38
39
FireWire Link (TSB83AA22)
(MASTER)
FireWire PHY (TSB83AA22)
(MASTER)
40
41
ETHERNET CONTROLLER
(MASTER)
(MASTER)
(MASTER)
(MASTER)
42
Ethernet Connector
(MASTER)
Yukon Power Control
(MASTER)
43
Date
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Contents
Sync
44
(MASTER)
FW PHY Power Supply
(MASTER)
FireWire Port Power
(MASTER)
45
Schematic / PCB #s
(MASTER)
46
PART NUMBER
DESCRIPTION
REFERENCE DES
051-7150
QTY
1
SCHEM,MLB,M59
SCH
CRITICAL
CRITICAL
820-2054
PCBF,MLB,M59
PCB
CRITICAL
BOM OPTION
(MASTER)
FireWire Ports
(MASTER)
Camera Connector
(MASTER)
External USB Connector
(MASTER)
Left I/O Board Connector
(MASTER)
49
(MASTER)
52
(MASTER)
55
(MASTER)
57
(MASTER)
PCI-E Connections
(MASTER)
SMC
(MASTER)
SMC Support
(MASTER)
LPC+ Debug Connector
(MASTER)
Thermal Sensors
(MASTER)
Current & Voltage Sensing
(MASTER)
SPI BOOTROM
(MASTER)
ALS Support
(MASTER)
Fan Connectors
(MASTER)
Sudden Motion Sensor (SMS)
(MASTER)
TPM
(MASTER)
IMVP6 CPU VCore Regulator
(MASTER)
5V / 1.5V Power Supply
(MASTER)
2.5V & 1.2V Regulators
M59_MG
1.8V Supply
M59_MG
58
www.laptop-schematics.com
(.csa)
(MASTER)
59
(MASTER)
60
(MASTER)
61
(MASTER)
62
(MASTER)
63
(MASTER)
64
(MASTER)
65
(MASTER)
66
(MASTER)
67
(MASTER)
75
(MASTER)
76
(MASTER)
77
09/19/2006
05/07/2006
78
05/07/2006
79
05/07/2006
3.3V / 1.05V Power Supplies
M59_MG
3.3V G3Hot Supply & Power Control
M59_MG
Power Aliases
M59_MG
80
08/01/2006
81
05/07/2006
82
(MASTER)
PBus-In,Batt. & 3G Pwr Connectors
(MASTER)
ATI M56 PCI-E
(MASTER)
GPU (M56) Core Supplies
(MASTER)
84
(MASTER)
85
(MASTER)
86
(MASTER)
ATI M56 Core Power
(MASTER)
ATI M56 Frame Buffer I/F
(MASTER)
GPU Straps
M59_MG
87
(MASTER)
88
07/25/2006
89
(MASTER)
GDDR3 Frame Buffer A
(MASTER)
GDDR3 Frame Buffer B
(MASTER)
ATI M56 GPIO/DVO/Misc
(MASTER)
ATI M56 Video Interfaces
(MASTER)
90
(MASTER)
91
(MASTER)
93
(MASTER)
94
07/25/2006
Internal Display Connectors
M59_MG
External Display Connector
M59_MG
97
07/25/2006
98
(MASTER)
M59 Specific Connectors
(MASTER)
LVDS Interface Pull-downs
M59_MG
Revision History
N/A
99
08/01/2006
100
N/A
101
(MASTER)
Napa Platform Constraints
(MASTER)
More System Constraints
(MASTER)
M59 Spacing & Physical Constraints
(MASTER)
M59 Net Properties
(MASTER)
102
(MASTER)
103
(MASTER)
104
(MASTER)
DIMENSIONS ARE IN MILLIMETERS
Apple Computer Inc.
METRIC
XX
X.XX
DRAFTER
NOTICE OF PROPRIETARY PROPERTY
DESIGN CK
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
X.XXX
ENG APPD
MFG APPD
QA APPD
DESIGNER
RELEASE
SCALE
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
ANGLES
TITLE
DO NOT SCALE DRAWING
SCHEM,MLB
NONE
DRAWING
SIZE
TITLE=M59_MLB
ABBREV=DRAWING
THIRD ANGLE PROJECTION
LAST_MODIFIED=Mon Sep 25 10:45:58 2006
MATERIAL/FINISH
NOTED AS
APPLICABLE
DRAWING NUMBER
REV.
A.0.0
051-7150
SHT
OF
84
GDDR3
Core Duo
(Merom)
CPU
Frame Buffer
THERMAL
128MB/256MB
SENSOR
ITP700FLEX
CPU Debug
Connector
479 BGA
Inverter
Connector
P.76
P.72-73
P.10
P.11
PWM
P.7-9
D
J2800
ATI M56P
LCD Panel
FSB
Dual-Channel LVDS
DDR2 SO-DIMM A
"Expansion Slot" Connector
(Lower/Outer)
GPU
P.76,79
PCIe x16
S-Video/Composite
CH.A
P.28
DVI-I/DL Connector
945GM
NB
P.67-71,74-75
P.77
LVDS Graphics
MUX
P.99
J2900
DDR2 SO-DIMM B
CH.B
DDR2 VTT
"Factory Slot" Connector

(Upper/Inner)
1466UFCBGA
& REGULATOR
P.29
RJ45 (Ethernet)
Yukon Gig-E
ENET
Yukon Power
Controller
Connector
P.39
BUFFER
P.39
P.40
P.32
DMI x4
1394a/b (FireWire)
TSB83AA22 FireWire
FW
Controller
Connectors
P.30-31
DDR2 VREF
P.12-20
Dual-Channel TMDS
w/TV-Out Support
P.44
P.37-38
Port Power
PCI
P.43
ICH7-M
PHY Power
P.43
USB x2
Right USB 2.0
PCIe x1
PCIe x1
Connector
PCIe x1
P.46
Left I/O &
SB
SATA
HDD/IR/SIL
Connector
USB
USB
Audio Board
USB
Connector
P.78
Azalia (HD-Audio)
P.47
609 BGA
USB
Camera
Connector
P.21-26
P.45
USB x2
Geyser KB/TP/BT
SMBus
Connector
P.78
PATA
ODD
Connector
66MHZ
16BITS
LPC 33MHZ
P.36
BootROM
P.54
CK410 Clock
TPM
SB SMBus
Controller
H8S/2116
P.27
P.33-34
Supplies
LPC
Debug
P.57-64,69
Connector
P.58
P.51
ALS
Temperature
SMC SMBus
Sensors
Power
SPI
SMC
SMBus x5
SYNC_MASTER=N/A
SYNC_DATE=N/A
P.27
P.52
System Block Diagram
P.55,78
SMS

P.57
Battery SMBus
Fan
Connector
Connectors
PWM/Tach
P.49-50
Analog
P.56
P.66
Sensors
SIZE
P.53
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
84
U8000
ENABLE
J5500
Q7610
3.425
LIO Flex
PPDCIN_G3H
PP5V_S3
PP3V42_G3H
G3Hot
Connector
18.5V - 9V
5.0V
3.425V
(LT3470)
SMC_PM_G2_ENABLE
PM_SLP_S3_L
1.5V
5V
PM_SLP_S4_LS5V
Q7615
U7600
Q3820
ENABLES
J8200
5V/1.5V
LIO Power
PPBUS_G3H
Connector
12.6V - 9V
PP5V_S5
PP5V_S0
PP5V_S0_IDE_ODD
5.0V
5.0V
5V
S5/S0
PP1V5_S0
1.5V
PM_SLP_S3_LS5V
(LTC3728)
ODD_PWR_EN_L (SB GPIO14)
PGOOD
Q7945
NC
SMC_PM_G2_ENABLE
U7900
IMVP_VR_ON
Q4300
PP3V3_S3
PP3V3_S3AC
3.3V
3.3V
ENABLE
IMVP_PWRGD_IN
3.3V
U7530
PM_SLP_S4_LS5V
PP3V3_S5
ENABLES
Q7720
PM_SLP_S3BATT
S5
3.3V
CPU VCore
S0
(ISL9504)
PP2V5_S0
PM_SLP_S3BATT
U7700
(ISL6269B)
PPVCORE_S0_CPU
2.5V
ENABLE
PGOOD
1.25V - 0.8V
RSMRST_PWRGD
"IMVP6"
2.5V
PM_SLP_S3_LS5V_L
PP2V5_S3
PM_SLP_S3_L
PGOOD
S3
(TPS62510)
U7950
VR_PWRGOOD_DELAY
Q7721
2.5V
PP2V5_D3C
ENABLE
J5500
PGOOD
2.5V
1.05V
Inverter
NC
PM_SLP_S3BATT
U7750
PP1V05_S0
S0
Connector
1.05V
(ISL6269B)
PM_SLP_S4_L
1.2V
ENABLE
IMVP_PWRGD_IN/ALL_SYS_PWRGD
U8500
1.8V
PP1V2_D3C
1.2V
1.2V
(LTC3412)
PP1V8_S3
S3
PP1V2_S3
S3
=GPUVCORE_EN_L
1.8V
PGOOD
ENABLE
(TPS51117)
Q7770
PGOOD
U7800
P1V2R2V5D3C_EN_LS5V
ENABLE
P1V2R2V5D3C_EN_LS5V
NC
GPU VCore
PGOOD
PPVCORE_D3C_GPU
Q7947
D3C
NC
Q7948
1.1V - 0.95V
(ISL6269B)
PP3V3_S0
PP3V3_D3C
3.3V
3.3V
PGOOD
PM_SLP_S3_L
NC
U3100
PM_SLP_S3_LS5V
ENABLE
P3V3D3C_EN_L
Power Block Diagram

SYNC_MASTER=N/A
Q7845
Q4500
SYNC_DATE=N/A
Q4501
0.9V (Vtt)
PP0V9_S0
PP1V8_D3C
PPBUS_S5_FWPORT
0.9V
1.8V
12.6V - 9V

S0
(TPS51100)

SIZE
APPLE COMPUTER INC.
P1V8D3C_EN
FW_PWRCTRL_GATE1
SHT
NONE
REV.
051-7150
SCALE
FW_PWRCTRL_GATE2_1/2
DRAWING NUMBER
A.0.0
OF
84
2.16Ghz BOMs
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
630-7849
PCBA,2.16GHZ,128VRAM,M59,MBP15
EEE_WTE,M59_COMMON,CPU_2_16GHZ,VRAM_SAM128
BOM NUMBER
BOM NAME
BOM OPTIONS
630-7851
PCBA,2.33GHZ,256VRAM,M59,MBP15
EEE_WTG,M59_COMMON,CPU_2_33GHZ,VRAM_SAM256
TABLE_BOMGROUP_ITEM
2.33Ghz BOMs
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
BOMOPTION Groups
Bar Code Label / EEE #s

PART NUMBER
QTY
TABLE_BOMGROUP_HEAD
DESCRIPTION
REFERENCE DES
CRITICAL
BOM GROUP
BOM OPTIONS
M59_COMMON
ALTERNATE,COMMON,M59_COMMON1,M59_COMMON2,M59_COMMON3
M59_COMMON1
BOOTROM_FINAL,ENET_LOWPWR_EN,ENETPWR_S3AC,GPU_BB_CTL,D3CPGOOD_3V3
M59_COMMON2
ITP,KBDLED_HAS,LPCPLUS,LVDS_PD,MEMVREF_S3
M59_COMMON3
MEMVTT_EN_PU,RTUSB_ESD,SMC_PRGRM,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU
VRAM_INF128
GPU_MEM_NOT_SAM,VRAM_128_INFINEON
VRAM_SAM128
VRAM_128_SAMSUNG
VRAM_INF256
GPU_MEM_256M,GPU_MEM_NOT_SAM,VRAM_256_INFINEON
VRAM_SAM256
GPU_MEM_256M,VRAM_256_SAMSUNG
M59_TPM
TPM
BOM OPTION
826-4393
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:WTE]
CRITICAL
EEE_WTE
826-4393
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:WTG]
CRITICAL
EEE_WTG
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
extra TPM options:

SMC_TPM_GPIO2
SMC_TPM_GPIO1
SMC_TPM_PP
Module Parts
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
333S0354
IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA
U8900,U8950,U9000,U9050
CRITICAL
VRAM_128_SAMSUNG
333S0350
U8900,U8950,U9000,U9050
CRITICAL
VRAM_256_SAMSUNG
333S0358
U8900,U8950,U9000,U9050
CRITICAL
VRAM_128_HYNIX
333S0351
U8900,U8950,U9000,U9050
CRITICAL
VRAM_256_HYNIX
333S0376
U8900,U8950,U9000,U9050
CRITICAL
VRAM_128_INFINEON
333S0377
U8900,U8950,U9000,U9050
CRITICAL
VRAM_256_INFINEON
337S3391
IC,MDC,B2,PRQ,2.16G,34W,667M,4M,479BGA
U0700
CRITICAL
CPU_2_16GHZ
337S3393
IC,MDC,B2,PRQ,2.33G,34W,667M,4M,479BGA
U0700
CRITICAL
CPU_2_33GHZ
341S1922
IC,EFI,BOOTROM DEVELOPMENT (UNLOCKED),M59
U6301
CRITICAL
BOOTROM_DEVEL
341S1923
IC,EFI,BOOTROM FINAL (LOCKED),M59
U6301
CRITICAL
BOOTROM_FINAL
338S0274
IC,SMC,HS8/2116
U5800
CRITICAL
SMC_BLANK
341S1929
IC,PRGRM,SMC (NEW),M59
U5800
CRITICAL
SMC_PRGRM
338S0269
IC,945GM,NORTHBRIDGE
U1200
CRITICAL
338S0270
IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO
U4101
CRITICAL
338S0368
IC,ATI,M56L-LLP,GRPHXCRTL,LF 880BGA
U8400
CRITICAL
341S1789
IC, TPM, 28-PIN TSSOP
U6700
CRITICAL
341S1797
IC,EEPROM,SERIAL IIC,8KBIT,SO8
U4102
CRITICAL
343S0385
IC,ICH7M,BGA
U2100
CRITICAL
353S1461
IC,ISL9504,SYNC REG CTRL,QFN48
U7530
CRITICAL
359S0109
LOW POWER CLOCK SYNTHESIZER, 68PIN
U3301
CRITICAL
TPM
Alternate Parts
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
128S0094
BOM OPTION
REF DES
COMMENTS:
128S0060
ALL
330uF,2V,9MOHM,D2
128S0095
128S0060
ALL
330uF,2V,6MOHM,D2
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
128S0081
128S0061
ALL
150uF,6.3V,25MOHM,C2
376S0448
376S0445
ALL
Si7806ADN for FDM6296
353S1465
353S1461
ALL
Screened ISL6262 for ISL9504
152S0287
152S0435
ALL
Alternates for Coilcraft MSS5131
128S0093
128S0092
ALL
33uF,16V,D2
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
BOM Configuration
TABLE_ALT_ITEM
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
84
Functional Test Points
IMVP6_RBIAS
IMVP6_COMP
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
P5VS5_RUNSS
P1V5S0_RUNSS
P1V2S3_RT
P1V2S3_RUNSS
P3V3S5_COMP
P3V3S5_FSET
P1V05S0_COMP
P1V05S0_FSET
TRUE
P3V42G3H_FB
TRUE
TRUE
GPUVCORE_COMP
GPUVCORE_FSET
59C7
59B7
60C5 64A6
5B7 60C4 64C6
61B6
41C4 61B7
5B7 63C6
5B7 63D6
5C7 63A7
5B7 63B7
64C3
68C7
68C7
GPUBBP_ADJ
GPUBBN_FB
GPUVCORE_FB
68C7
GPUVCORE_FB_RC
68C3
TRUE
GPUVCORE_ISEN
GPUVCORE_UG
TRUE
TRUE
7C8 7D8 12C4 84C6

7D6 12C4 84D6
7B3 7B4 7C3 7C4 12B6 12C6 12D6 84D6

7D6 12B4 84D6
IMVP6_COMP_RC
59B8
IMVP6_DFB
59B6
TRUE
IMVP6_FB
59B7
TRUE
IMVP6_OCSET
59C6
TRUE
IMVP6_VDIFF
59C7
TRUE
IMVP6_VDIFF_RC
59B8
TRUE
P1V05S0_BOOT
63B5
TRUE
P1V05S0_BOOT_R
63B5
TRUE
P1V05S0_COMP
5D7 63A7
TRUE
P1V05S0_COMP_R
63A7
TRUE
P1V05S0_FB
=PP5V_S0_FAN_LT
TRUE
TRUE
FAN_LT_PWM
FAN_LT_TACH
TRUE
TRUE
FAN_RT_PWM
FAN_RT_TACH
56B6
56B6
7B3 7B4 7C3 7C4 12B4 84D6
FUNC_TEST
7D6 12B4 84D6
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
TRUE
TRUE
7D6 12B4 84D6

7D6 12B4 84D6
7D8 12A4 12B4 84D6
LPC_AD<0>
LPC_AD<1>
LPC_FRAME_L
PM_CLKRUN_L
BOOT_LPC_SPI_L
SMC_TMS
DEBUG_RST_L
SMC_TRST_L
SMC_TDO
SMC_MD1
SMC_TX_L
FWH_INIT_L
PCI_CLK_PORT80_LPC
LPC_AD<2>
LPC_AD<3>
INT_SERIRQ
PM_SUS_STAT_L
SMC_TDI
SMC_TCK
SMC_RST_L
SMC_NMI
SMC_RX_L
SV_SET_UP
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
P1V05S0_LG
63A5
TRUE
P1V05S0_PHASE
63B5
TRUE
P1V05S0_UG
63B5
TRUE
P1V5S0_RUNSS
5D7 60C4 64C6
TRUE
P3V3S5_BOOT
63D4
TRUE
P3V3S5_BOOT_R
63D4
TRUE
P3V3S5_COMP
5D7 63C6
TRUE
P3V3S5_COMP_R
63C6
TRUE
P3V3S5_FB
63C6
TRUE
P3V3S5_FB_RC
63C2
TRUE
P3V3S5_FSET
5D7 63D6
TRUE
P3V3S5_ISEN
63C4
TRUE
P3V3S5_LG
63C4
TRUE
P3V3S5_UG
63D4
TRUE
CK410_XTAL_IN
33C6
=PP3V3_S3_LTALS
ALS_GAIN
LTALS_OUT
GND
TRUE
TRUE
TRUE
TRUE
5D7 63B7
63A5
66B5
FUNC_TEST
7B3 7B4 7C3 7C4 12B4 84D6
63A3
P1V05S0_ISEN
27C1 66B5
Left I/O Data Connector
7D6 12B4 84D6
51C4 65D3
51C4 65A1
21D4 49D7 51C4 58C6

21D4 49D7 51C4 58C6
21C5 49C7 51C4 58C6
22B3 49C7 51B4

49B5 50B2 51B4
26B1 51B4
49C1 51B4
49B5 50B2 51B4
49C1 51B4
46B5 49C7 50B2 50B3
51B4
21C4 50D3 51C5
34D6 51C5
21D4 49C7 51C5 58C6
21D4 49C7 51C5 58C6
23C8 49C7 51C5 58C6
23C5 49C5 50A2 51B5
58C6
49B5 50B2 51B5
49C5 50B2 51B5
49C3 50D6 51B5
49C1 51B5
46B5 49C7 50B2 50B3
51B5
23B6 23C3 51B5
65C3 78C5
6D5 49B5 78C6
55C7 78C6
Thermal Diode Connectors

FUNC_TEST
HSTHMSNS_DX_P
HSTHMSNS_DX_N
RSFSTHMSNS_D_P
RSFSTHMSNS_D_N
TRUE
TRUE
TRUE
TRUE
52C5
52C5
52D5
52C5
Other Func Test Points

FUNC_TEST
TRUE
=PP1V05_S0_REG
TRUE
TRUE
PM_SYSRST_L
SMC_ONOFF_L
53A4 63A2 65D8
23C5 26C5 49B7
2 TPs per
TRUE
TRUE
TRUE
TRUE
=PP1V8_S3_REG
=PP1V5_S0_REG
PPVCORE_S0_GPU
PPVCORE_S0_CPU
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
ACZ_SDATAIN<0>
ACZ_SDATAOUT
ACZ_BITCLK
ACZ_RST_L
EXCARD_OC_L
LTUSB_OC_L
LIO_BATT_ISENSE
SMC_SYS_ISET
SMC_BATT_ISET
SMC_BATT_CHG_EN
SMC_BC_ACOK
SMC_ADAPTER_EN
LIO_P3V3S0_EN_L
LIO_DCIN_ISENSE
LIO_P3V3S3_EN
SMC_BATT_TRICKLE_EN_L
SYS_ONEWIRE
MINI_CLKREQ_L
SMC_EXCARD_CP
EXCARD_CLKREQ_L
SMC_EXCARD_PWR_EN
LIO_PLT_RESET_L
ACZ_SYNC
=USB2_LT_N
=USB2_LT_P
=USB2_EXCARD_N
=USB2_EXCARD_P
=PCIE_EXCARD_R2D_N
=PCIE_EXCARD_R2D_P
=PCIE_EXCARD_D2R_N
=PCIE_EXCARD_D2R_P
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
=PCIE_MINI_R2D_N
=PCIE_MINI_R2D_P
=PCIE_MINI_D2R_N
=PCIE_MINI_D2R_P
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
=SMBUS_LIO_SMC_SCL
=SMBUS_LIO_SMC_SDA
=SMBUS_LIO_SB_SCL
=SMBUS_LIO_SB_SDA
PCIE_WAKE_L
47D6 65C6
47C6 65A8
47C6 65B1
47D6 65D3
47D4
47C4
47A4
47A4
21C7 47B6 84B4

21C7 47B6 84B4
21C7 47B6 84B4
21C7 47B3 84B4
6C3 47C6 50B3
6D3 47C6
47C6 53C3
47C6 49B5
47B6 49B5
47C6 49D7 50A2
47B6 49C5 50A2
43B7 47C6 49D5
50A2
47B6 64C6
47B6 53C5
47B6 64A6
47B6 49D7 50A2
47C6 49B7 50B2
34A3 47C6
47B6 49B7 50A2
34A3 47C6
47B6 49B7
26C1 47C6
21C7 47B6 84B4
6D3 47C3
6D3 47C3
6C3 47C3
6C3 47C3
47B3 48C6
47B3 48C6
47B3 48B6
47B3 48C6
34C3 47B3
34B3 47B3
47B3 48C6
47B3 48C6
47C3 48C6
47C3 48C6
34D4 47C3
34D4 47C3
27D1 47C3
27D1 47C3
27B6 47C3
27B6 47C3
23C8 39C6 47C3
Left I/O Power Connector

FUNC_TEST
FUNC_TEST
ISENSE_CAL_EN
=PP5V_S0_ISENSECAL
=PP1V5_S0_LIO
=PPDCIN_G3H_LIO
=PP5V_S5_LIO
=PP3V42_G3H_LIO
PP5V_S0_AUDIO_PWR
PP5V_S0_AUDIO
GND_AUDIO_PWR
GND_AUDIO
49C5 50B2 50C6 78C2
Current Sense Calibration

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
23C8 49C5 51C4 58C6
Left ALS Connector
TRUE
27C1 66B5
56B3
63A7
P1V05S0_FSET
49C5 50B2 66B5
56B3
FUNC_TEST
P1V05S0_FB_RC
SMC_BS_ALRT_L
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
GND_BATT
TRUE
TRUE
TRUE
TRUE
56C7 65A1
7B3 7B4 7C3 7C4 12B4 84D6
68D5
TRUE
FUNC_TEST
TRUE
7D6 12C4 84D6
68C5
TRUE
TRUE
TRUE
7D6 12C4 84D6
68C5
GPUVCORE_PHASE
TRUE
TRUE
Battery Digital Connector
FUNC_TEST
7C8 7D8 12C4 12D4 84D6
68C5
GPUVCORE_LG
TRUE
Fan Connectors
FSB_A_L<31..3>
FSB_ADS_L
FSB_ADSTB_L<1..0>
FSB_BNR_L
FSB_BREQ0_L
FSB_D_L<63..0>
FSB_DBSY_L
FSB_DINV_L<3..0>
FSB_DRDY_L
FSB_DSTBN_L<3..0>
FSB_DSTBP_L<3..0>
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_REQ_L<4..0>
68A3
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
EXPOSED_VIA
68B7
TRUE
TRUE
NO_TEST
TRUE
TRUE
TRUE
TRUE
CPU FSB NO_TESTs
EXPOSED_VIA
53A8 65A1
62C1 65B8
60C1 65C8
=PPBUS_G3H_LIO_CONN
GND
TRUE
TRUE
49B7 53A8
65C3 66C4
Power Supply NO_TESTs

NO_TEST
Request for at least 10 GND test points

NOTE: 10 additional GND test points are
called out separately in these notes.
65D1
GND
TRUE
8 TPs, 2 with each of above TP pairs
Camera Connector
EXPOSED_VIA property indicates that the net
should have a via with 10-mil soldermask
TRUE
opening for use as engineering probe point.
Misc EXPOSED_VIA Nets
Functional / ICT Test
FUNC_TEST
=PP5V_S3_CAMERA
=USB2_CAMERA_N
=USB2_CAMERA_P
45C3 65B1
6C3 45C3
SYNC_MASTER=N/A
PPVBATT_G3C_RTC
GND
TRUE
TRUE
26D6
SYNC_DATE=N/A

6D3 45B3
Inverter Connector
FUNC_TEST
EXPOSED_VIA
TRUE
TRUE
TRUE
TRUE
RTC Battery Connector
FUNC_TEST
DMI_N2S_P<1..0>
DMI_N2S_N<1..0>
SB_CLK100M_SATA_P
SB_CLK100M_SATA_N
TRUE
TRUE
TRUE
TRUE
TRUE
14B4 22D2
14B4 22D2
21B6 34C3
21B6 34C3
GND_CHASSIS_INVERTER
PPBUS_S0_INVERTER
GND_INVERTER
INVERTER_PWM
PP5V_INVERTER_SW
6A8
76B5
SIZE
76A5
76A5
APPLE COMPUTER INC.
76B5
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
84
USB Port "A" (Debug Port) = Right USB 2.0 Port

46B5
=USB2_RT_P
46B5
=USB2_RT_N
USB2_RT_P
USB_A_P
22C2
USB_A_N
22C2
USB_A_OC_L
22C4 22D8
MAKE_BASE=TRUE
USB2_RT_N
MAKE_BASE=TRUE
TP_CPU_A32_L
7C8
NC_MEM_A_A<15..14>
TP_CPU_A33_L
7B8
NC_MEM_B_A<15..14>
TP_CPU_A34_L
7B8
MAKE_BASE=TRUE
NO_TEST=TRUE
28C3
MEM_B_A<15..14>
29C3
NB_CFG<4..3>
14C6
TP_SMC_RSTGATE_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_A33_L
MAKE_BASE=TRUE
NO_TEST=TRUE
SMC_RSTGATE_L
6B7 49D7
=RTALS_GAIN
55C4
46C5
TP_NB_CFG<4..3>
USB Port "B" = Trackpad (Geyser)
MAKE_BASE=TRUE
78C3
=USB_TRACKPAD_P
78C3
=USB_TRACKPAD_N
TP_CPU_A35_L
7B8
TP_NB_CFG<6>
NB_CFG<6>
TP_CPU_A36_L
7B8
TP_CPU_A37_L
7B8
TP_CPU_A38_L
7B8
NB_CFG<8>
NC_ENET_CTRL12
14C6
MAKE_BASE=TRUE
NB_CFG<11..10>
NC_ENET_CTRL25
14C6
MAKE_BASE=TRUE
ENET_CTRL25
47C3 5B1
=USB2_LT_P
47C3 5B1
=USB2_LT_N
7B8
NB_CFG<15..14>
14C6
47C6 5C1
TP_NB_CFG<17>
TP_CPU_APM0_L
7B8
TP_CPU_APM1_L
7B8
NB_CFG<17>
USB2_LT_P
USB2_LT_N
LTUSB_OC_L
Ethernet Power Management Support
14C6
TP_CPU_EXTBREF
7B6
TP_CPU_HFPLL
7B8
TP_NB_CFG<13..12>
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_SB_SUS_CLK
SUS_CLK_SB
SB_GPIO30
TP_CPU_SPARE0
7B6
NC_SB_XOR_T5
NC_CPU_SPARE2
7B6
NC_SB_XOR_U5
21C6
TP_SB_XOR_U5
21C6
TP_SB_XOR_V3
21C6
TP_CPU_SPARE2
7B6
TP_CPU_SPARE4
7B6
NC_SB_XOR_V3
22C2
USB_C_OC_L
22C4 22D8
NC_SB_XOR_V4
USB_D_P
22C2
USB_D_N
22C2
USB_D_OC_L
22C4 22D8
USB_E_P
22C2
USB_E_N
22C2
USB_E_OC_L
22C4 22D8
MAKE_BASE=TRUE
USB Port "E" = ExpressCard

47C3 5B1
=USB2_EXCARD_P
47C3 5B1
=USB2_EXCARD_N
USB2_EXCARD_P
MAKE_BASE=TRUE
NOTE: BOM options "USB_G_OC_PU" and

"ENET_LOWPWR_EN" are mutually-exclusive.
USB2_EXCARD_N
MAKE_BASE=TRUE
50B3 47C6 5C1
EXCARD_OC_L
MAKE_BASE=TRUE
USB Port "F" = IR Receiver

78B4
=USB_IR_P
78B4
=USB_IR_N
USB_IR_P
USB_F_P
22C2
USB_F_N
22C2
USB_G_P
22C2
USB_G_N
22C2
MAKE_BASE=TRUE
TP_SB_XOR_V4
21C6
Inverter PWM Reset Alias
MAKE_BASE=TRUE
NO_TEST=TRUE
USB2_CAMERA_N
MAKE_BASE=TRUE
OUT
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
USB2_CAMERA_P
UNUSED_USB_D_OC_L
2 39B8 ENET_LOWPWR_EN
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_SPARE4
TP_SB_XOR_T5
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_CPU_SPARE1
MAKE_BASE=TRUE
NO_TEST=TRUE
=USB2_CAMERA_N
5%
1/16W
MF-LF
402
23C3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
=USB2_CAMERA_P
45C3 5A4
R0600
IN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_SPARE1
22C2
USB_C_N
MAKE_BASE=TRUE
14C6
22D8 22C4
MAKE_BASE=TRUE
NO_TEST=TRUE
45B3 5A4
ENET_LOWPWR_EN
NB_CFG<13..12>
MAKE_BASE=TRUE
NC_CPU_SPARE0
USB_C_P
USB Port "D" = Camera
NOTE: NB_CFG<13..12> require test access
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_HFPLL
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_CPU_EXTBREF
22C4 22D8
MAKE_BASE=TRUE
TP_CPU_A39_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_APM1_L
22C2
USB_B_OC_L
MAKE_BASE=TRUE
39C8
MAKE_BASE=TRUE
NC_CPU_APM0_L
22C2
USB_B_N
USB Port "C" = Left USB 2.0 Port
39C8
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_NB_CFG<15..14>
MAKE_BASE=TRUE
NO_TEST=TRUE
ENET_CTRL12
MAKE_BASE=TRUE
NO_TEST=TRUE
TP_NB_CFG<11..10>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_A39_L
USB_B_P
MAKE_BASE=TRUE
TP_NB_CFG<8>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_A38_L
USB_TRACKPAD_N
UNUSED_USB_B_OC_L
14C6
MAKE_BASE=TRUE
NC_CPU_A37_L
USB_TRACKPAD_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_A36_L
RTUSB_OC_L
MAKE_BASE=TRUE
ALS_GAIN
MAKE_BASE=TRUE
NC_CPU_A35_L
=RTUSB_OC_L
MAKE_BASE=TRUE
78C6 49B5 5B2
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_A34_L
MAKE_BASE=TRUE
NO_TEST=TRUE
MEM_A_A<15..14>
NC_CPU_A32_L
USB_IR_N
MAKE_BASE=TRUE
TP_SB_XOR_W3
NC_SB_XOR_W3
21C6
USB Port "G" = Bluetooth (M13L)
MAKE_BASE=TRUE
NO_TEST=TRUE
26C1
M59_INVERTER_PLT_RST_L
=INVERTER_PWM_PLT_RST_L
76A8
78C2
=USB_BT_P
78C2
=USB_BT_N
USB_BT_P
MAKE_BASE=TRUE
USB_BT_N
MAKE_BASE=TRUE
USB Port "H" = Reserved
FireWire Aliases
42C4
=PP3V3_FWPHY_REG
PP3V3_FWPHY
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE
42C1
=PP1V95_FWPHY_CORE_LDO
49D7 6D4
=PP3V3_FWPHY
=PP3V3_FWPHY_CORE
=PP3V3_FWLATEVG
=PP3V3_FWLATEVG_ACTIVE
TP_USB_H_P
6C2 22C2
TP_USB_H_N
6C2 22C2
MAKE_BASE=TRUE
TP_USB_H_N
22C2 6C1
42C4
MAKE_BASE=TRUE
44A8
43A7
PP1V95_FWPHY
=PP1V95_FWPHY
38D5
VOLTAGE=1.95V
MAKE_BASE=TRUE
=PP1V8_FWPHY_OSC
38B2
=SMC_FWRSTGATE_L
37A8
=FW_PCI_IDSEL
37B7
=FW_PCI_GNT_L
37D3
=FW_PCI_REQ_L
37D3
SMC_RSTGATE_L
TP_USB_H_P
22C2 6C1
38D7 44B8
MAKE_BASE=TRUE
37C6 22A7
PCI_AD<19>
MAKE_BASE=TRUE
PCI_GNT3_L
22B6
Thermal Module Holes
MAKE_BASE=TRUE
PCI_REQ3_L
26D2 22B6
LVDS pulldown aliases
Add 2 blind vias per hole per side to GND
MAKE_BASE=TRUE
Top CPU TM Hole
79B8
=LVDS_PD_U_CLK_N
79B8
=LVDS_PD_U_CLK_P
Chassis GNDs
76B2 76D7 79C1
LVDS_U_CLK_CONN_P
76B2 76D7 79C1
MAKE_BASE=TRUE
79C8
=LVDS_PD_U_DATA_P<0>
79C8
=LVDS_PD_U_DATA_N<0>
LVDS_U_DATA_CONN_P<0>
76C2 76D7 79D1
MAKE_BASE=TRUE
GND_CHASSIS_RTUSB
VOLTAGE=0V
MAKE_BASE=TRUE
LVDS_U_CLK_CONN_N
MAKE_BASE=TRUE
Top GPU Right TM Hole
=GND_CHASSIS_RTUSB
=GND_CHASSIS_FW_PORT2L
=GND_CHASSIS_FW_EMI_R
LVDS_U_DATA_CONN_N<0>
76C2 76D7 79D1
MAKE_BASE=TRUE
46B2
44A1
79B8
79B8
79B8
79B8
79C8
=LVDS_PD_L_CLK_N
76C2 76D7 79C1
MAKE_BASE=TRUE
44A3
Left CPU TM Hole
Right CPU TM Hole
Bottom Left GPU TM Hole
76C2 76D7 79C1
MAKE_BASE=TRUE
76B2 76D7 79C1
MAKE_BASE=TRUE
GND_CHASSIS_DVI_TOP
VOLTAGE=0V
MAKE_BASE=TRUE
0.01UF
C0600
=GND_CHASSIS_DVI2
=GND_CHASSIS_DVI4
GND_CHASSIS_DVI_BOT
R0601
0
77B5
ZT0614
ZT0613
44C1
44A1
RAM door (Torx) holes

ZT0630
VOLTAGE=0V
GND_CHASSIS_LVDS
VOLTAGE=0V
MAKE_BASE=TRUE
10%
50V
X7R 2
402
=GND_CHASSIS_LCD1
=GND_CHASSIS_LCD2
=GND_CHASSIS_LCD3
=GND_CHASSIS_LCD4
OG-503040
5A4
76D3
SHLD-SM-LF
79C8
=LVDS_PD_L_DATA_N<1>
76C2 76D7 79C1
LVDS_L_DATA_CONN_N<1>
79C8
=LVDS_PD_L_DATA_P<2>
76C2 76D7 79C1
79C8
LVDS_L_DATA_CONN_P<2>
76C2 76D7 79C1
MAKE_BASE=TRUE
76C2 76D7 79C1
MAKE_BASE=TRUE
VOLTAGE=0V
ZT0611
HOLE-VIA-P5RP25
VOLTAGE=0V
1GND_CHASSIS_LNDACARD_HOLE
C0631
10%
2 50V
X7R
402
45B5 45C5
10%
2 50V
X7R
402
C0611
10%
50V
2 X7R
402
0.01UF
ZT0610
HOLE-VIA-P5RP25
VOLTAGE=0V
1
SYNC_MASTER=N/A
C0615
SYNC_DATE=N/A

C0614
0.01UF
10%
50V
2 X7R
402
10%
50V
2 X7R
402

C0610
0.01UF
C0613
SIZE
0.01UF
10%
50V
2 X7R
402
10%
50V
2 X7R
402
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7150
SCALE
0.01UF
C0612
0.01UF
1GND_CHASSIS_BATTCONN_HOLE
ZT0631
76A6
1
1
HOLE-VIA-P5RP25
76B2
Signal Aliases/Misc Comps
VOLTAGE=0V
0.01UF
0.01UF
=GND_CHASSIS_INVERTER
=GND_CHASSIS_CAMERA
76C2 76D7 79C1
MAKE_BASE=TRUE
VOLTAGE=0V
76C3
GND_CHASSIS_INVERTER
VOLTAGE=0V
MAKE_BASE=TRUE
MAKE_BASE=TRUE
VOLTAGE=0V
C0630
10%
50V
2 X7R
402
76D2
VOLTAGE=0V
79D8
1GND_CHASSIS_LIOFLEX_HOLE
1
GND_CHASSIS_RAMDOOR_HOLE_1
SH0600
76C2 76D7 79C1
HOLE-VIA-P5RP25
1
GND_CHASSIS_RAMDOOR_HOLE_0
HOLE-VIA-P5RP25
0.01UF
1 GND_CHASSIS_DIMM_NOTCH
ZT0612
HOLE-VIA-P5RP25
ZT0602
C0602
76C2 76D7 79C1
HOLE-VIA-P5RP25
40B2
Chassis connection to be made at the mounting hole east of the LVDS connector
1 GND_CHASSIS_RIGHT_FAN_NOTCH
=GND_CHASSIS_ENET
=GND_CHASSIS_FW_PORT1
=GND_CHASSIS_FW_PORT2U
76C2 76D7 79C1
LVDS_L_CLK_CONN_P
MAKE_BASE=TRUE
HOLE-VIA-P5RP25
GND_CHASSIS_ENET
79D8
79D8
1 GND_CHASSIS_RIGHT_FAN_HOLE
77A2
=LVDS_PD_L_CLK_P
MAKE_BASE=TRUE
HOLE-VIA-P5RP25
77A2
79C8
MAKE_BASE=TRUE
ZT0615
5%
1/16W
MF-LF
2 402
VOLTAGE=0V
MAKE_BASE=TRUE
LVDS_L_CLK_CONN_N
MAKE_BASE=TRUE
77A3
Frame holes
=GND_CHASSIS_DVI1
=GND_CHASSIS_DVI3
=GND_CHASSIS_DVI5
76C2 76D7 79D1
MAKE_BASE=TRUE
77A5
10%
50V 2
X7R
402
VOLTAGE=0V
MAKE_BASE=TRUE
A.0.0
OF
84
OMIT
U0700
IO
84D6 12D4 5D5
IO
84D6 12D4 5D5
IO
84D6 12D4 5D5
IO
84D6 12D4 5D5
IO
84D6 12C4 5D5
IO
84C6 12C4 5D5
IO
84D6 12B4 5D5

84D6 12B4 5D5
84D6 12A4 5D5
IO
84D6 12A4 5D5
IO
84D6 12C4 5D5
IO
84D6 12C4 5D5
IO
84D6 12C4 5D5
IO
84D6 12C4 5D5
IO
84D6 12C4 5D5
IO
84D6 12C4 5D5

84D6 12C4 5D5
84D6 12C4 5D5
84D6 12C4 5D5
84D6 12C4 5D5
84D6 12C4 5D5
84D6 12C4 5D5
84D6 12C4 5D5
84D6 12C4 5D5
IO
IO
84D6 12C4 5D5

84C6 12C4 5D5
84C6 21C4
21C2
84C6 21C4
84C6 21C4
84C6 21C4
84C6 21C4
84C6 21C4
P1 A15*
R1 A16*
L2 ADSTB0*
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
IO
84D6 12A4 5D5
P2 A12*
L1 A13*
P4 A14*
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
IN
IN
IN
IN
W6 A20*
U4 A21*
Y5 A22*
U2 A23*
R4 A24*
T5 A25*
T3 A26*
W3 A27*
W5 A28*
Y4 A29*
W2 A30*
Y1 A31*
V4 ADSTB1*
84D6 12B4
F1
84D6 12C4 5D5
84D6 12B4
FSB_DEFER_L
5D5 FSB_DRDY_L
5D5 FSB_DBSY_L
FSB_BREQ0_L
D5 STPCLK*
C6 LINT0
B4 LINT1
A3 SMI*
TP_CPU_A32_L
6D7 TP_CPU_A33_L
6D7 TP_CPU_A34_L
6D7 TP_CPU_A35_L
6D7 TP_CPU_A36_L
6D7 TP_CPU_A37_L
6D7 TP_CPU_A38_L
6D7 TP_CPU_A39_L
6D7 TP_CPU_APM0_L
6C7 TP_CPU_APM1_L
AA1 RSVD1
AA4 RSVD2
AB2 RSVD3
AA3 RSVD4
M4 RSVD5
N5 RSVD6
T2 RSVD7
V3 RSVD8
B2 RSVD9
C3 RSVD10
TP_CPU_HFPLL
B25 RSVD11
54.9
1%
1/16W
MF-LF
2 402
IO
IO
IO
IO
FSB_IERR_L
21C4 CPU_INIT_L
IN
FSB_LOCK_L
IO
INIT*
D20
B3
LOCK*
H4
84D6 12B4 5D5
RESET*
RS0*
B1
84D6 12C4 11B5
IN
F3
F4
84D6 12A4
IN
84D6 12A4
IN
G3
84D6
IN
TRDY*
G2
84D6
HIT*
G6
E4
IERR*
R0702
IO
PLACE TESTPOINT ON
FSB_IERR_L WITH A GND
0.1" AWAY
84C6
84C6
FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
12A4 FSB_RS_L<2>
12A4 FSB_TRDY_L
FSB_HIT_L
5D5 FSB_HITM_L
=PP1V05_S0_CPU
IN
84D6 12B4 5D5
IO
84D6 12B4
IO
7B5 7B6 7D5 8C7 9B7 11B3 11C5 65D6
A6 A20M*
A5 FERR*
C4 IGNNE*
6D7
6C7
E1
BR0*
HITM*
Y2 A17*
U5 A18*
R3 A19*
CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L
IN
DBSY*
F21
84D6
R0703
L5 REQ4*
CPU_A20M_L
CPU_FERR_L
CPU_IGNNE_L
IN
84D6 12B4
RS1*
RS2*
K3 REQ0*
H2 REQ1*
K2 REQ2*
J3 REQ3*
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_ADSTB_L<1>
IO
H5
BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*
TCK
TDI
TDO
TMS
TRST*
DBR*
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
THERMDA
D21
A24
THERMDC
A25
PROCHOT*
THERMTRIP*
BCLK0
BCLK1
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
C7
XDP_BPM_L<0>
84C6 11B3 XDP_BPM_L<1>
11B3 7A8 XDP_TCK
11B3 7B8 XDP_TDI
11B5 XDP_TDO
11B3 7B8 XDP_TMS
11B3 XDP_TRST_L
26C6 11B4 XDP_DBRESET_L
84C6 11B3
CPU_PROCHOT_L
10B6 CPU_THERMD_P
10B6 CPU_THERMD_N
IO
IO
IO
54.9
OMIT
1%
1/16W
MF-LF
2 402
U0700
IO
IO
IO
IN
IN
OUT
IN
IN
R0704
PM_THRMTRIP_L
FSB_CLK_CPU_P
34D3 FSB_CLK_CPU_N
A22
34D3
A21
TP_CPU_EXTBREF
T22
TP_CPU_SPARE0
TP_CPU_SPARE1
TP_CPU_SPARE2
TP_CPU_SPARE3
TP_CPU_SPARE4
TP_CPU_SPARE5
TP_CPU_SPARE6
TP_CPU_SPARE7
D2
F6
D3
C1
AF1
D22
C23
C24
84D6 12D6 5D5
IO
84D6 12D6 5D5
IO
84D6 12D6 5D5
IO
84D6 12D6 5D5
IO
84D6 12D6 5D5
68
5%
1/16W
MF-LF
2 402
OUT
50D3 50C1
50C1 21C2 14B6
OUT
OUT
CPU_PROCHOT_L TO SMC
AND CPU VR TO INFORM
CPU IS HOT
OUT
PM_THRMTRIP#
SHOULD CONNECT TO
ICH7-M AND GMCH
WITHOUT T-ING (NO
STUB)
IN
IN
IO
84D6 12D6 5D5
IO
84D6 12D6 5D5
IO
84D6 12D6 5D5
IO
84D6 12D6 5D5
IO
84D6 12D6 5D5
IO
IO
84D6 12C6 5D5
IO
84D6 12C6 5D5
IO
84D6 12C6 5D5
IO
84D6 12B4 5D5
IO
84D6 12B4 5D5
IO
84D6 12B4 5D5
IO
84D6 12C6 5D5
IO
84D6 12C6 5D5
IO
84D6 12C6 5D5
IO
84D6 12C6 5D5
IO
6C7
84D6 12C6 5D5
IO
6C7
84D6 12C6 5D5
IO
84D6 12C6 5D5
IO
SPARE[7-0],HFPLL:
ROUTE TO TP VIA AND
PLACE GND VIA W/IN 1000 MILS
6C7
=PP1V05_S0_CPU
84D6 12C6 5D5
IO
84D6 12C6 5D5
IO
84D6 12C6 5D5
IO
84D6 12C6 5D5
IO
84D6 12C6 5D5
IO
84D6 12C6 5D5
R0705
1K
1%
1/16W
MF-LF
2 402
7B5 7D5 8C7 9B7 11B3 11C5 65D6
84C6
R0720
11B3 7C6
XDP_TMS
54.9 2
2.0K
XDP_TDI
1%
1/16W
MF-LF
2 402
34C6
R0721
OUT
34B6
OUT
34B6
54.9 2
OUT
84D6 12C6 5D5
IO
IO
IO
84D6 12B4 5D5
IO
84D6 12B4 5D5
IO
84D6 12B4 5D5
IO
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTBN_L<0>
FSB_DSTBP_L<0>
FSB_DINV_L<0>
E22 D0*
F24 D1*
E26 D2*
E25 D6*
E23 D7*
K24 D8*
G24 D9*
J24 D10*
J23 D11*
H26 D12*
F26 D13*
K22 D14*
H25 D15*
H23 DSTBN0*
(2 OF 4)
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2*
DSTBP2*
DINV2*
N22 D16*
K25 D17*
P26 D18*
R23 D19*
L25 D20*
L22 D21*
L23 D22*
M23 D23*
P25 D24*
P22 D25*
P23 D26*
T24 D27*
R24 D28*
D48*
D49*
D50*
D51*
D52*
D53*
L26 D29*
T25 D30*
N24 D31*
M24 DSTBN1*
N25 DSTBP1*
C26 TEST1
CPU_TEST2
D25 TEST2
CPU_BSEL<0>
CPU_BSEL<1>
CPU_BSEL<2>
B22 BSEL0
B23 BSEL1
C21 BSEL2
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3*
DSTBP3*
DINV3*
M26 DINV1*
CPU_TEST1
1%
402
D32*
D33*
BGA
G22 DSTBP0*
J26 DINV0*
AD26 GTLREF
A2 NC
LAYOUT NOTE: 0.5" MAX LENGTH
YONAH
CPU
H22 D3*
F23 D4*
G25 D5*
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTBN_L<1>
FSB_DSTBP_L<1>
FSB_DINV_L<1>
CPU_GTLREF
R0706
1%
402
11B3 7C6
IO
84D6 12C6 5D5
84D6 12C6 5D5
=PP1V05_S0_CPU
IO
84D6 12D6 5D5
6C7
65D6 11C5 11B3 9B7 8C7 7D5 7B6
IO
84D6 12D6 5D5
84D6 12D6 5D5
OUT
6C7
MISC
R0722
XDP_TCK
54.9 2
402
1
R0712
1%
402
51
5%
1/16W
MF-LF
2 402
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
SLP*
PSI*
IO
84D6
12C6
84D6
12C6
84D6
12C6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B4
V23
84D6
12B4
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20
U26
U1
PWRGOOD
IO
84D6
12C6 5D5
84D6
12C6 5D5
84D6
12B4
COMP1
DPSLP*
DPWR*
84D6
12C6 5D5
84D6
12C6 5D5
Y25
R26
DPRSTP*
NOSTUFF
AA23
COMP0
COMP2
COMP3
R0730
11B3 7C6
84D6 12D4 5D5
J1 A9*
N3 A10*
P5 A11*
DEFER*
DRDY*
7B5 7B6 7D5 8C7 9B7 11B3 11C5 65D6
DATA GRP2
IO
IO
DATA GRP3
IO
84D6 12D4 5D5
IO
84D6 12C4 5D5
DATA GRP0
IO
84D6 12D4 5D5
=PP1V05_S0_CPU
84D6 12C4 5D5
E2
G5
BPRI*
BGA
FSB_ADS_L
FSB_BNR_L
12C4 FSB_BPRI_L
H1
ADS*
BNR*
DATA GRP1
84D6 12D4 5D5
(1 OF 4)
CONTROL
IO
K5 A6*
M1 A7*
N2 A8*
XDP/ITP SIGNALS
IO
THERM
IO
84D6 12D4 5D5
YONAH
CPU
HCLK
84D6 12D4 5D5
84D6 12D4 5D5
J4 A3*
L4 A4*
M3 A5*
ADDR GROUP0
IO
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_ADSTB_L<0>
ADDR GROUP1
IO
84D6 12D4 5D5
RESERVED
84D6 12D4 5D5
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
5D5 FSB_D_L<36>
5D5 FSB_D_L<37>
5D5 FSB_D_L<38>
5D5 FSB_D_L<39>
5D5 FSB_D_L<40>
5D5 FSB_D_L<41>
5D5 FSB_D_L<42>
5D5 FSB_D_L<43>
5D5 FSB_D_L<44>
5D5 FSB_D_L<45>
5D5 FSB_D_L<46>
5D5 FSB_D_L<47>
5D5 FSB_DSTBN_L<2>
5D5 FSB_DSTBP_L<2>
5D5 FSB_DINV_L<2>
84D6
12B6 5D5
84D6
12B6 5D5
84D6
12B6 5D5
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B6
84D6
12B4
84D6
12B4
84D6
12B4
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
5D5 FSB_D_L<51>
5D5 FSB_D_L<52>
5D5 FSB_D_L<53>
5D5 FSB_D_L<54>
5D5 FSB_D_L<55>
5D5 FSB_D_L<56>
5D5 FSB_D_L<57>
5D5 FSB_D_L<58>
5D5 FSB_D_L<59>
5D5 FSB_D_L<60>
5D5 FSB_D_L<61>
5D5 FSB_D_L<62>
5D5 FSB_D_L<63>
5D5 FSB_DSTBN_L<3>
5D5 FSB_DSTBP_L<3>
5D5 FSB_DINV_L<3>
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
LAYOUT NOTE:
COMP0,2 CONNECT WITH
TRACE LENGTH SHORTER
COMP1,3 CONNECT WITH
TRACE LENGTH SHORTER
IO
IO
IO
IO
IO
R0716
IO
IO
IO
27.4 2
402
R0717
IO
IO
54.9 2
1%
IO
402
R0718
IO
CPU_COMP<0>
84C6 CPU_COMP<1>
84C6 CPU_COMP<2>
84C6 CPU_COMP<3>
CPU_DPRSTP_L
21C4 CPU_DPSLP_L
12B4 FSB_DPWR_L
21C4 CPU_PWRGD
12A4 FSB_SLPCPU_L
59C7 CPU_PSI_L
ZO=27.4OHM, MAKE
THAN 0.5".
ZO=55OHM, MAKE
THAN 0.5".
IO
84C6
V1
27.4 2
R0719
1
E5
B5
59C7 21C4
IN
84C6
IN
D24
84D6
D6
D7
84C6
AE6
IO
54.9 2
1%
402
IN
IN
IN
IN
NOSTUFF
1
R0707
1K
5%
1/16W
MF-LF
2 402
CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9
CPU 1 OF 2-FSB
WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50
SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM
TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
84
OMIT
=PPVCORE_S0_CPU
OMIT
A7 VCC_1
A9 VCC_2
A10 VCC_3
A12 VCC_4
A13 VCC_5
A15 VCC_6
BGA
(3 OF 4)
VCC_71 AC9
VCC_72 AC12
VCC_73 AC13
VCC_74 AC15
VCC_75 AC17
VCC_76 AC18
B7 VCC_10
B9 VCC_11
B10 VCC_12
VCC_77 AD7
VCC_78 AD9
VCC_79 AD10
B12 VCC_13
B14 VCC_14
B15 VCC_15
VCC_80 AD12
VCC_81 AD14
C9 VCC_19
C10 VCC_20
C12 VCC_21
C13 VCC_22
C15 VCC_23
C17 VCC_24
C18 VCC_25
D9 VCC_26
D10 VCC_27
D12 VCC_28
D14 VCC_29
VCC_82 AD15
VCC_83 AD17
VCC_84 AD18
VCC_85 AE9
VCC_86 AE10
VCC_87 AE12
VCC_88 AE13
VCC_89 AE15
VCC_90 AE17
VCC_91 AE18
VCC_92 AE20
VCC_93 AF9
VCC_94 AF10
VCC_95 AF12
VCC_96 AF14
VCC_97 AF15
VCC_98 AF17
D15 VCC_30
D17 VCC_31
D18 VCC_32
E7 VCC_33
VCC_99 AF18
VCC_100 AF20
E9 VCC_34
E10 VCC_35
E12 VCC_36
VCCP_1 V6
VCCP_2 G21
E13 VCC_37
E15 VCC_38
E17 VCC_39
VCCP_3 J6
VCCP_4 K6
VCCP_5 M6
E18 VCC_40
E20 VCC_41
F7 VCC_42
VCCP_6 J21
VCCP_7 K21
VCCP_8 M21
F9 VCC_43
F10 VCC_44
F12 VCC_45
VCCP_9 N21
VCCP_10 N6
VCCP_11 R21
F14 VCC_46
F15 VCC_47
F17 VCC_48
VCCP_12 R6
VCCP_13 T21
F18 VCC_49
F20 VCC_50
AA7 VCC_51
AA9 VCC_52
AA10 VCC_53
AA12 VCC_54
AA13 VCC_55
YONAH
CPU
VCC_68 AB20
VCC_69 AB7
VCC_70 AC7
A17 VCC_7
A18 VCC_8
A20 VCC_9
B17 VCC_16
B18 VCC_17
B20 VCC_18
U0700
AA15 VCC_56
AA17 VCC_57
AA18 VCC_58
AA20 VCC_59
AB9 VCC_60
AC10 VCC_61
A14 VSS_4
A16 VSS_5
A19 VSS_6
A23 VSS_7
A26 VSS_8
8B5 9D7 53A6 53D7 65D1
(CPU CORE POWER)
=PP1V05_S0_CPU
7B5 7B6 7D5 9B7 11B3 11C5 65D6
(CPU IO POWER 1.05V)
VCCP_14 T6
VCCP_15 V21
VCCP_16 W21
VCCA=1.5 ONLY
VCCA B26
=PP1V5_S0_CPU
9B7 65C6
(CPU INTERNAL PLL POWER 1.5V)

VID0 AD6
VID1 AF5
VID2 AE5
VID3 AF4
VID4 AE3
VID5 AF2
VID6 AE2
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
OUT
9C2 84B6
OUT
9C2 84B6
OUT
9C2 84B6
OUT
9C2 84B6
OUT
9C2 84B6
OUT
9C2 84B6
OUT
9C2 84B6
VID FOR CPU POWER SUPPLY

IF NO USE, NEED PULL-UP OR
PULL-DOWN
8D7 9D7 53A6 53D7 65D1
R0802
100
1%
1/16W
MF-LF
AB10 VCC_62
AB12 VCC_63
AB14 VCC_64
AB15 VCC_65
AB17 VCC_66
AB18 VCC_67
=PPVCORE_S0_CPU
2 402
VCCSENSE AF7
CPU_VCCSENSE_P
OUT
59B1 84B6
VSSSENSE AE7
CPU_VCCSENSE_N
OUT
59A1 84B6
R0803
LAYOUT NOTE: CONNECT R0803

TO TP_VSSSENSE WITH NO
STUB.
100
1%
1/16W
MF-LF
2 402
LAYOUT NOTE:
CPU_VCCSENSE_P/CPU_VCCSENSE_N USE
ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.
LAYOUT NOTE:
PROVIDE A TEST POINT (WITH NO STUB)
TO CONNECT A DIFFERENCTIAL PROBE
BETWEEN VCCSENSE AND VSSSENSE AT THE
LOCATION WHERE THE TWO 54.9 OHM
RESISTORS TERMINATE THE 55 OHM
TRANSMISSION LINE
LAYOUT NOTE:
VCCSENSE AND VSSSENSE LINES
SHOULD BE OF EQUAL LENGTH
U0700 VSS_82
VSS_83
YONAH
CPU
BGA
(4 OF 4)
P6
P21
VSS_84 P24
VSS_85 R2
VSS_86 R5
VSS_87 R22
VSS_88 R25
VSS_89 T1
B6 VSS_9
B8 VSS_10
B11 VSS_11
B13 VSS_12
B16 VSS_13
B19 VSS_14
VSS_90 T4
VSS_91 T23
VSS_92 T26
B21 VSS_15
B24 VSS_16
C5 VSS_17
C8 VSS_18
C11 VSS_19
VSS_96 U24
VSS_97 V2
VSS_98 V5
VSS_99 V22
VSS_100 V25
C14 VSS_20
C16 VSS_21
C19 VSS_22
VSS_101 W1
VSS_102 W4
VSS_103 W23
C2 VSS_23
C22 VSS_24
C25 VSS_25
D1 VSS_26
D4 VSS_27
VSS_104 W26
VSS_105 Y3
VSS_106 Y6
D8 VSS_28
D11 VSS_29
D13 VSS_30
VSS_109 AA2
VSS_110 AA5
VSS_111 AA8
D16 VSS_31
D19 VSS_32
D23 VSS_33
VSS_112 AA11
VSS_113 AA14
VSS_114 AA16
D26 VSS_34
E3 VSS_35
E6 VSS_36
VSS_115 AA19
VSS_116 AA22
VSS_117 AA25
E8 VSS_37
E11 VSS_38
E14 VSS_39
E16 VSS_40
E19 VSS_41
VSS_118 AB1
VSS_119 AB4
E21 VSS_42
E24 VSS_43
F5 VSS_44
VSS_123 AB16
VSS_124 AB19
VSS_125 AB23
F8 VSS_45
F11 VSS_46
F13 VSS_47
F16 VSS_48
F19 VSS_49
VSS_126 AB26
VSS_127 AC3
VSS_128 AC6
F2 VSS_50
F22 VSS_51
F25 VSS_52
VSS_131 AC14
VSS_132 AC16
VSS_133 AC19
G4 VSS_53
G1 VSS_54
G23 VSS_55
VSS_134 AC21
VSS_135 AC24
VSS_136 AD2
G26 VSS_56
H3 VSS_57
H6 VSS_58
VSS_137 AD5
VSS_138 AD8
VSS_139 AD11
H21 VSS_59
H24 VSS_60
J2 VSS_61
J5 VSS_62
J22 VSS_63
VSS_140 AD13
VSS_141 AD16
J25 VSS_64
K1 VSS_65
K4 VSS_66
VSS_145 AE1
VSS_146 AE4
VSS_147 AE8
K23 VSS_67
K26 VSS_68
L3 VSS_69
VSS_148 AE11
VSS_149 AE14
VSS_150 AE16
L6 VSS_70
L21 VSS_71
L24 VSS_72
M2 VSS_73
M5 VSS_74
VSS_151 AE19
VSS_152 AE23
M22 VSS_75
M25 VSS_76
N1 VSS_77
VSS_156 AF8
VSS_157 AF11
VSS_158 AF13
N4 VSS_78
N23 VSS_79
N26 VSS_80
P3 VSS_81
VSS_159 AF16
VSS_160 AF19
VSS_161 AF21
VSS_93 U3
VSS_94 U6
VSS_95 U21
A4 VSS_1
A8 VSS_2
A11 VSS_3
VSS_107 Y21
VSS_108 Y24
VSS_120 AB8
VSS_121 AB11
VSS_122 AB13
VSS_129 AC8
VSS_130 AC11
VSS_142 AD19
VSS_143 AD22
VSS_144 AD25
VSS_153 AE26
VSS_154 AF3
VSS_155 AF6
VSS_162 AF24
CPU 2 OF 2-PWR/GND
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
84
D
CPU VCORE HF AND BULK DECOUPLING
=PPVCORE_S0_CPU
4x 330uF. 20x 22uF 0805

1
C0900
C0901
C0902
C0903
C0904
C0905
C0906
C0907
C0908
22UF
22UF
22UF
22UF
22UF
22UF
22UF
22UF
22UF
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
CPU VCORE VID Connections
C0909
22UF
Resistors to allow for override of CPU VID

Will probably be removed before production
65D1 53D7 53A6 8D7 8B5
RP0990
0
5%
1
C0919
84B6 8B7
22UF
22UF
22UF
22UF
22UF
22UF
22UF
22UF
22UF
22UF
84B6 8B7
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
20%
6.3V
CERM
805
C0910
C0911
C0912
C0913
C0914
C0915
C0916
C0917
C0918
84B6 8B7
84B6 8B7
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
IMVP6_VID<0>
IMVP6_VID<1>
IMVP6_VID<2>
IMVP6_VID<3>
59C7
59C7
59C7
59C7
1/16W
SM-LF
CRITICAL
1
CRITICAL
1
C0950
330UF
330UF
20%
2 2.5V
RP0991
0
20%
3 2 2.5V
POLY
D2T
C0954
330UF
20%
3 2 2.5V
POLY
D2T
CRITICAL
1
C0953
330UF
20%
CRITICAL
1
C0952
POLY
D2T
2 2.5V
5%
POLY
D2T
84B6 8B7
84B6 8B7
84B6 8B7
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
NC
IMVP6_VID<4>
IMVP6_VID<5>
IMVP6_VID<6>
59C7
59C7
59C7
NC
1/16W
SM-LF
VCCA (CPU AVdd) Decoupling

65C6 8B7
=PP1V5_S0_CPU
1x 10uF, 1x 0.01uF
C0980
10uF
C0981
0.01UF
20%
6.3V
X5R
603
20%
16V
CERM
402
VCCP (CPU I/O) Decoupling

65D6 11C5 11B3 8C7 7D5 7B6 7B5
=PP1V05_S0_CPU
1x 470uF, 6x 0.1uF 0402

C0935
470uF
20%
2.5V
TANT
D2T
C0936
C0937
C0938
C0939
C0940
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
C0941
0.1UF
20%
10V
CERM
402
CRITICAL
NOTE: This cap is shared

between CPU and NB
CPU Decoupling & VID
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
84
CPU ZONE THERMAL SENSOR

65B3 =PP3V3_S0_THRM_SNR
C1002
LAYOUT NOTE:
LAYOUT NOTE:
ADD GND GUARD TRACE
ROUTE CPU_THERMD_P AND
FOR CPU_THERMD_P AND
CPU_THERMD_N ON SAME
CPU_THERMD_N
LAYER.
0.1UF
10%
16V
X5R
402
R10061
10K
5%
1/16W
MF-LF
402 2
10 MIL TRACE
10 MIL SPACING
R1005
10K
5%
1/16W
MF-LF
2 402
VDD
R1001
OUT
7C6
CPU_THERMD_P
499
1%
1/16W
MF-LF
402
(TO CPU INTERNAL THERMAL DIODE)
(TC0D)
THRM_CPU_DX_P
THRM_CPU_DX_N
C1001
2 D+
3 D-
ALERT*/ 6
THRM_ALERT_L
THM2*
THM* 4 THRM_ALERT
U1001
TMP401
MSOP
CRITICAL
SCLK 8
SDATA 7
27D1
SMB_THRM_CLK
IO
27D1
SMB_THRM_DATA
IO
0.001UF
R1002
IN
7C6
CPU_THERMD_N
499
10%
50V
CERM
402
GND
5
1%
1/16W
MF-LF
402
PLACE U1001 NEAR THE U1200
CPU MISC1-TEMP SENSOR
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
10
84
CPU ITP700FLEX DEBUG SUPPORT

C
Note: This connection to 1V5_S0 is to steal this mounting pad to add to the 1.5V S0 shape
and to provide better feeding of the 1.5V NB rail through its current sense resistor
65C6
=PP1V5_S0_ITPMOUNT
ITPCONN
65D6 11B3 9B7 8C7 7D5 7B6 7B5
CRITICAL
=PP1V05_S0_CPU
J1101
ITP
52435-2872
R1101 1R1103
54.9
1%
1/16W
MF-LF
2 402
F-RT-SM
29
54.9
1%
1/16W
MF-LF
2 402
7C6 7B8
7C6 7B8
7C6
OUT
OUT
R1102
7C6
IN
1%
1/16W
MF-LF
402
ITP
OUT
XDP_TCK
IN
FSB_CPURST_L
84C6 34D3
(FROM CK410M HOST 133/167MHZ)

84C6 34D3
IN
IN
4
5
6
ITP_TDO
CPU_XDP_CLK_N
CPU_XDP_CLK_P
8
9
10
11B3 7C6 7A8
22.6 2
OUT
(FBO)
XDP_TCK
11
ITPRESET_L
12
IO
XDP_BPM_L<5>
13
84C6 7C6
IO
XDP_BPM_L<4>
84C6 7C6
IO
XDP_BPM_L<3>
84C6 7C6
IO
XDP_BPM_L<2>
84C6 7C6
IO
XDP_BPM_L<1>
IO
XDP_BPM_L<0>
84C6
1%
1/16W
MF-LF
402
65D3 26C5 23D1
NC
(TCK)
NC
R1100
84D6 12C4 7D6
XDP_TRST_L
22.6 2
1
XDP_TDO
OUT
ITP
11B3 7C6 7A8
XDP_TDI
XDP_TMS
84C6 7C6
14
15
16
=PP3V3_S5_SB_PM
17
18
R1104
240
19
20
5%
1/16W
MF-LF
2 402
21
22
84C6 7C6
23
NC
(AND WITH RESET BUTTON)
OUT
26C6 7C6
XDP_DBRESET_L
24
25
65D6 11C5 9B7 8C7 7D5 7B6 7B5
=PP1V05_S0_CPU
26
(DBA#) INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.
(DEBUG PORT ACTIVE)
(DBR#) TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC
(DEBUG PORT RESET)
27
C1100
28
0.1UF
10%
2 16V
X5R
402
30
518S0320
1
R1106
ITP TCK SIGNAL LAYOUT NOTE:

ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTORS TCK PIN TO CPUS
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX
CONNECTORS FBO PIN.
680
5%
1/16W
MF-LF
2 402
CPU ITP700FLEX DEBUG
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
11
84
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7C4 5D5
IO
84D6 7B4 5D5
IO
84D6 7B4 5D5
IO
IO
84D6 7B4 5D5
IO
84D6 7B4 5D5
IO
84D6 7B4 5D5
IO
84D6 7B4 5D5
IO
84D6 7B4 5D5
IO
IO
84D6 7B4 5D5
IO
84D6 7B4 5D5
IO
84D6 7C3 5D5
IO
84D6 7C3 5D5
IO
84D6 7C3 5D5
IO
84D6 7C3 5D5
IO
84D6 7C3 5D5
IO
84D6 7C3 5D5
IO
IO
84D6 7C3 5D5
IO
IO
84D6 7C3 5D5
IO
84D6 7C3 5D5
IO
84D6 7C3 5D5
1%
1/16W
MF-LF
402
R1221
24.9
1%
1/16W
MF-LF
402
IO
IO
IO
84D6 7B3 5D5
IO
84D6 7B3 5D5
IO
R1225
84D6 7B3 5D5
IO
221
84D6 7B3 5D5
IO
84D6 7B3 5D5
IO
84D6 7B3 5D5
IO
1%
1/16W
MF-LF
402
R1226
100
IO
84D6 7C3 5D5
84D6 7B3 5D5
IO
84D6 7C3 5D5
84D6 7C3 5D5
54.9
IO
84D6 7C3 5D5
84D6 7C3 5D5
IO
84D6 7C3 5D5
84D6 7C3 5D5
R1220 1
IO
84D6 7B4 5D5
84D6 7C3 5D5
65D6 34C8 34C6 34B8 19D7 12C2 12A7
IO
84D6 7B4 5D5
84D6 7B4 5D5
=PP1V05_S0_FSB_NB
IO
84D6 7B4 5D5
84D6 7B4 5D5
IO
84D6 7C4 5D5
1%
1/16W
MF-LF
402
IO
84D6 7B3 5D5
IO
84D6 7B3 5D5
IO
84D6 7B3 5D5
IO
84D6 7B3 5D5
IO
C1226
84D6 7B3 5D5
IO
0.1uF
84D6 7B3 5D5
IO
10%
16V
X5R
402
84D6 7B3 5D5
IO
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8
NB_FSB_XRCOMP
NB_FSB_XSCOMP
NB_FSB_XSWING
65D6 34C8 34C6 34B8 19D7 12C2 12B7
E1
E2
E4
NB_FSB_YRCOMP
NB_FSB_YSCOMP
NB_FSB_YSWING
=PP1V05_S0_FSB_NB
R1230
54.9
1%
1/16W
MF-LF
402
R1235
221
34D3
IN
34D3
IN
Y1
U1
W1
FSB_CLK_NB_P
FSB_CLK_NB_N
AG2
AG1
HD0*
HD1*
HD2*
HD3*
HD4*
HD5*
HD6*
HD7*
HD8*
HD9*
HD10*
HD11*
HD12*
HD13*
HD14*
HD15*
HD16*
HD17*
HD18*
HD19*
HD20*
HD21*
HD22*
HD23*
HD24*
HD25*
HD26*
HD27*
HD28*
HD29*
HD30*
HD31*
HD32*
HD33*
HD34*
HD35*
HD36*
HD37*
HD38*
HD39*
HD40*
HD41*
HD42*
HD43*
HD44*
HD45*
HD46*
HD47*
HD48*
HD49*
HD50*
HD51*
HD52*
HD53*
HD54*
HD55*
HD56*
HD57*
HD58*
HD59*
HD60*
HD61*
HD62*
HD63*
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
HCLKIN
HCLKIN*
OMIT
U1200
945GM
NB
BGA
(1 OF 10)
HA3*
HA4*
HA5*
HA6*
HA7*
HA8*
HA9*
HA10*
HA11*
HA12*
HA13*
HA14*
HA15*
HA16*
HA17*
HA18*
HA19*
HA20*
HA21*
HA22*
HA23*
HA24*
HA25*
HA26*
HA27*
HA28*
HA29*
HA30*
HA31*
84D6 7D8
5D5
84D6 7D8
5D5
H9
C9
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
7D8
5D5 FSB_A_L<8>
7D8
5D5 FSB_A_L<9>
7D8
5D5 FSB_A_L<10>
7D8
5D5 FSB_A_L<11>
7D8
5D5 FSB_A_L<12>
7D8
5D5 FSB_A_L<13>
7D8
5D5 FSB_A_L<14>
7D8
5D5 FSB_A_L<15>
7D8
5D5 FSB_A_L<16>
7C8
5D5 FSB_A_L<17>
7C8
5D5 FSB_A_L<18>
7C8
5D5 FSB_A_L<19>
7C8
5D5 FSB_A_L<20>
7C8
5D5 FSB_A_L<21>
7C8
5D5 FSB_A_L<22>
7C8
5D5 FSB_A_L<23>
7C8
5D5 FSB_A_L<24>
7C8
5D5 FSB_A_L<25>
7C8
5D5 FSB_A_L<26>
7C8
5D5 FSB_A_L<27>
7C8
5D5 FSB_A_L<28>
7C8
5D5 FSB_A_L<29>
7C8
5D5 FSB_A_L<30>
7C8
5D5 FSB_A_L<31>
84D6 7D8
5D5
84D6 7D8
5D5
84D6 7D8
5D5
E11
G11
F11
84D6
G12
84D6
F9
84D6
H11
84D6
J12
84D6
G14
84D6
D9
84D6
J14
84D6
H13
84D6
J15
84D6
F14
84D6
D12
84D6
A11
84D6
C11
84D6
A12
84D6
A13
84D6
E13
84D6
G13
84D6
F12
84D6
B12
84D6
B14
84D6
C12
84D6
A14
84D6
C14
84D6
D14
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
=PP1V05_S0_FSB_NB
IO
HADS*
HADSTB0*
HADSTB1*
HAVREF
HBNR*
HBPRI*
HBREQ0*
HCPURST*
HDBSY*
HDEFER*
HDPWR*
HDRDY*
HDVREF
HDINV0*
HDINV1*
HDINV2*
HDINV3*
E8
84C6 7D8
5D5
84C6 7C8
5D5
B9
C13
J13
C6
F6
C7
B7
A7
C3
84D6
J9 7B3
H8
FSB_ADS_L
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
NB_FSB_VREF
FSB_BNR_L
FSB_BPRI_L
FSB_BREQ0_L
FSB_CPURST_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DPWR_L
FSB_DRDY_L
12A7 12B7 19D7 34B8 34C6 34C8 65D6
IO
1
84D6 7D6
5D5
HOST
R1210
100
IO
IO
2
1%
1/16W
MF-LF
402
IO
IO
1
OUT
IO
OUT
IO
C1211
10%
16V
X5R
402
R1211
200
0.1uF
2
2
1%
1/16W
MF-LF
402
OUT
IO
IO
K13
J7
W8
U3
84D6 7C4
5D5
84D6
AB10
HDSTBN0*
HDSTBN1*
HDSTBN2*
HDSTBN3*
K4
HDSTBP0*
HDSTBP1*
HDSTBP2*
HDTSBP3*
K3
HHIT*
HHITM*
HLOCK*
D3
HREQ0*
HREQ1*
HREQ2*
HREQ3*
HREQ4*
D8
HRS0*
HRS1*
HRS2*
B4
HSLPCPU*
HTRDY*
E3
T7
Y5
84D6 7C4
5D5
84D6 7B4
5D5
84D6 7C3
5D5
84D6
AC4
T6
AA5
84D6
B3
G8
FSB_DSTBP_L<0>
FSB_DSTBP_L<1>
FSB_DSTBP_L<2>
7B3
5D5 FSB_DSTBP_L<3>
84D6 7D6
5D5
84D6 7D6
5D5
84D6 7D6
5D5
84D6
84D6
F8
84D6
FSB_REQ_L<0>
FSB_REQ_L<1>
7D8
5D5 FSB_REQ_L<2>
7D8
5D5 FSB_REQ_L<3>
7D8
5D5 FSB_REQ_L<4>
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
E6
D6
E7
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
84D6 7D8
5D5
84D6 7D8
5D5
B8
A8
FSB_DSTBN_L<0>
FSB_DSTBN_L<1>
FSB_DSTBN_L<2>
7B3
5D5 FSB_DSTBN_L<3>
84D6 7C4
5D5
84D6 7B4
5D5
84D6 7C3
5D5
AC5
D4
FSB_DINV_L<0>
FSB_DINV_L<1>
FSB_DINV_L<2>
7B3
5D5 FSB_DINV_L<3>
84D6 7B4
5D5
84D6 7C3
5D5
7A3
FSB_SLPCPU_L
FSB_TRDY_L
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
1%
1/16W
MF-LF
402
NB CPU Interface
R1231
24.9
1%
1/16W
MF-LF
402
R1236
100
1%
1/16W
MF-LF
402
SYNC_DATE=(MASTER)
C1236

0.1uF
2
10%
16V
X5R
402

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
12
84
=PP1V5_S0_NB_PCIE
1
U1200
19D3
OUT
OUT
79A7
IO
79A7
IO
19D3
79A4
IO
OUT
19D3
IN
19D3
IN
79D3
79D3
79C3
79C3
79D3
79D3
OUT
OUT
OUT
OUT
OUT
OUT
79D3
OUT
79D3
OUT
79D3
OUT
79D3
OUT
79D3
OUT
79C3
79D3
79D3
OUT
79C3
79C3
OUT
OUT
OUT
OUT
OUT
TV-Out Signal Usage:

19D5
Composite: DACA only

S-Video:
DACB & DACC only
Component: DACA, DACB & DACC
19D5
19D5
19D5
Unused DAC outputs must remain powered, but can omit

filtering components. Unused DAC outputs should
connect to GND through 75-ohm resistors.
19D5
19C5
19C5
OUT
OUT
OUT
OUT
OUT
OUT
OUT
LVDS_BKLTCTL
LVDS_BKLTEN
LVDS_CLKCTLA
LVDS_CLKCTLB
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_IBG
TP_LVDS_VBG
LVDS_VDDEN
LVDS_VREFH
LVDS_VREFL
LVDS_A_CLK_N
LVDS_A_CLK_P
LVDS_B_CLK_N
LVDS_B_CLK_P
EXP_A_COMPI
D40
BGA
EXP_A_COMPO
D38
EXP_A_RXN0
EXP_A_RXN1
F34
L_CLKCTLB
L_DDC_CLK
L_DDC_DATA
EXP_A_RXN2
H34
EXP_A_RXN3
EXP_A_RXN4
J38
EXP_A_RXN5
EXP_A_RXN6
M38
EXP_A_RXN7
P38
EXP_A_RXN8
EXP_A_RXN9
R34
L_BKLTCTL
J30
H30
L_BKLTEN
L_CLKCTLA
H29
G26
EXP_A_RXP0
D34
67D1
EXP_A_RXP1
EXP_A_RXP2
F38
EXP_A_RXP3
H38
EXP_A_RXP4
EXP_A_RXP5
J34
EXP_A_RXP6
M34
EXP_A_RXP7
EXP_A_RXP8
N38
EXP_A_RXP9
EXP_A_RXP10
R38
EXP_A_RXP11
V38
EXP_A_RXP12
EXP_A_RXP13
W34
EXP_A_RXP14
AA34
EXP_A_RXP15
AB38
PEG_D2R_P<0>
67D1 PEG_D2R_P<1>
67D1 PEG_D2R_P<2>
67D1 PEG_D2R_P<3>
67D1 PEG_D2R_P<4>
67C1 PEG_D2R_P<5>
67C1 PEG_D2R_P<6>
67C1 PEG_D2R_P<7>
67C1 PEG_D2R_P<8>
67C1 PEG_D2R_P<9>
67C1 PEG_D2R_P<10>
67B1 PEG_D2R_P<11>
67B1 PEG_D2R_P<12>
67B1 PEG_D2R_P<13>
67B1 PEG_D2R_P<14>
67B1 PEG_D2R_P<15>
EXP_A_TXN0
EXP_A_TXN1
F36
67D5
EXP_A_TXN2
H36
EXP_A_TXN3
EXP_A_TXN4
J40
EXP_A_TXN5
EXP_A_TXN6
M40
EXP_A_TXN7
P40
EXP_A_TXN8
EXP_A_TXN9
R36
EXP_A_TXN10
V36
EXP_A_TXN11
EXP_A_TXN12
W40
C25
CRT_DDC_CLK
CRT_DDC_DATA
G23
HSYNC
EXP_A_TXN13
AA40
J22
CRT_IREF
CRT_VSYNC
EXP_A_TXN14
EXP_A_TXN15
AB36
B38
C35
F32
C33
C32
L_IBG
L_VBG
L_VDDEN
L_VREFH
L_VREFL
A32
LA_CLK
EXP_A_RXN10
V34
E27
LB_CLK*
LB_CLK
EXP_A_RXN11
EXP_A_RXN12
W38
EXP_A_RXN13
AA38
EXP_A_RXN14
EXP_A_RXN15
AB34
E26
B35
A37
LA_DATA1*
LA_DATA2*
LVDS_A_DATA_P<0>
LVDS_A_DATA_P<1>
LVDS_A_DATA_P<2>
B37
LA_DATA0
B34
LA_DATA1
A36
LA_DATA2
LVDS_B_DATA_N<0>
LVDS_B_DATA_N<1>
LVDS_B_DATA_N<2>
G30
D30
LB_DATA0*
LB_DATA1*
F29
LB_DATA2*
F30
D29
F28
LB_DATA0
LB_DATA1
LB_DATA2
C18
TV_DACA_OUT
TV_DACB_OUT
A19
TV_DACC_OUT
A16
J20
TV_IREF
B16
B18
TV_IRTNA
TV_IRTNB
B19
TV_IRTNC
19D5
19D5
19D5
19D5
CRT Disable
19D5
Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie

HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core
rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.
OUT
OUT
OUT
OUT
OUT
OUT
19D5
IO
19D5
IO
19D5
OUT
19D5
19D5
OUT
OUT
CRT_BLUE
CRT_BLUE_L
CRT_GREEN
CRT_GREEN_L
CRT_RED
CRT_RED_L
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC_R
CRT_IREF
CRT_VSYNC_R
E23
CRT_BLUE
D23
CRT_BLUE*
C22
CRT_GREEN
CRT_GREEN*
B22
A21
B21
C26
H23
CRT_RED
CRT_RED*
VGA
19D5
N34
LA_CLK*
TV-Out Disable
Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.
Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and
VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.
L34
A33
LA_DATA0*
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
G38
T38
Y34
G34
L38
P34
T34
Y38
67D1
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
EXP_A_TXP0
D36
EXP_A_TXP1
EXP_A_TXP2
F40
EXP_A_TXP3
H40
EXP_A_TXP4
EXP_A_TXP5
J36
EXP_A_TXP6
M36
EXP_A_TXP7
EXP_A_TXP8
N40
EXP_A_TXP9
EXP_A_TXP10
R40
T36
EXP_A_TXP11
V40
EXP_A_TXP12
EXP_A_TXP13
W36
EXP_A_TXP14
AA36
EXP_A_TXP15
AB40
T40
Y36
G36
L40
P36
Y40
IN
67D5
N36
SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL
IN
AC40
L36
SDVO_TVCLKIN#
SDVO_INT#
SDVO_FLDSTALL#
IN
PEG_R2D_C_N<0>
67D5 PEG_R2D_C_N<1>
67D5 PEG_R2D_C_N<2>
67D5 PEG_R2D_C_N<3>
67C5 PEG_R2D_C_N<4>
67C5 PEG_R2D_C_N<5>
67C5 PEG_R2D_C_N<6>
67C5 PEG_R2D_C_N<7>
67C5 PEG_R2D_C_N<8>
67C5 PEG_R2D_C_N<9>
67B5 PEG_R2D_C_N<10>
G40
1%
1/16W
MF-LF
402
SDVO Alternate Function
AC38
G25
C37
TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT
(3 OF 10)
R1310
PEG_COMP
PEG_D2R_N<0>
67D1 PEG_D2R_N<1>
67D1 PEG_D2R_N<2>
67D1 PEG_D2R_N<3>
67C1 PEG_D2R_N<4>
67C1 PEG_D2R_N<5>
67C1 PEG_D2R_N<6>
67C1 PEG_D2R_N<7>
67C1 PEG_D2R_N<8>
67C1 PEG_D2R_N<9>
67B1 PEG_D2R_N<10>
67B1 PEG_D2R_N<11>
67B1 PEG_D2R_N<12>
67B1 PEG_D2R_N<13>
67B1 PEG_D2R_N<14>
67B1 PEG_D2R_N<15>
LVDS_A_DATA_N<0>
LVDS_A_DATA_N<1>
LVDS_A_DATA_N<2>
LVDS_B_DATA_P<0>
LVDS_B_DATA_P<1>
LVDS_B_DATA_P<2>
945GM
NB
D32
PCI-EXPRESS GRAPHICS
19D3
OUT
LVDS
79A4
TV
79A4
Can leave all signals NC if LVDS is not implemented

Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used
VCCD_LVDS must remain powered with proper decoupling.
Otherwise, tie VCCD_LVDS to GND also.
19D7 65C6
24.9
OMIT
LVDS Disable
PEG_R2D_C_P<0>
67D5 PEG_R2D_C_P<1>
67D5 PEG_R2D_C_P<2>
67D5 PEG_R2D_C_P<3>
67D5 PEG_R2D_C_P<4>
67C5 PEG_R2D_C_P<5>
67C5 PEG_R2D_C_P<6>
67C5 PEG_R2D_C_P<7>
67C5 PEG_R2D_C_P<8>
67C5 PEG_R2D_C_P<9>
67B5 PEG_R2D_C_P<10>
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SDVOB_RED#
SDVOB_GREEN#
SDVOB_BLUE#
SDVOB_CLKN
SDVOC_RED#
SDVOC_GREEN#
SDVOC_BLUE#
SDVOC_CLKN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SDVOB_RED
SDVOB_GREEN
SDVOB_BLUE
SDVOB_CLKP
SDVOC_RED
SDVOC_GREEN
SDVOC_BLUE
SDVOC_CLKP
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NB PEG / Video Interfaces
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
13
84
R1440 1
10K
OMIT
5%
1/16W
MF-LF
402
19D3
19D3
34C7
IN
34B7
IN
34B7
IN
6D6
IN
6D6
IN
20C7
IN
6D6
IN
20C7
IN
6D6
IN
20B7
IN
6D6
IN
6D6
IN
6C6 IN
=PP3V3_S0_NB
R1420 1
10K
5%
1/16W
MF-LF
402 2
50D5 49B7
IN
84C6 59C8 23C3
IN
6C6
IN
6D6
IN
6D6
IN
20C5
IN
6D6
IN
20B5
IN
20B5
IN
20A5
IN
23C5
OUT
50C1 21C2 7C6
26C1
IN
NB_RST_IN_L
100
59C7 26B5
OUT
IN
5%
1/16W
MF-LF
402
19D3
19D3
IO
IO
22A6
OUT
33B4
OUT
AY35
R32
RSVD2
RSVD3
BGA
SM_CK1
SM_CK2
AR1
(2 OF 10)
SM_CK3
AW40
MEM_CLK_P<0>
28A3 MEM_CLK_P<1>
29A3 MEM_CLK_P<2>
29D3 MEM_CLK_P<3>
SM_CK0*
SM_CK1*
AW35
28D3
SM_CK2*
AY7
SM_CK3*
AY40
AG11
RSVD4
RSVD5
AF11
RSVD6
H7
RSVD7
RSVD8
K30
RSVD9
A41
RSVD10
RSVD11
TP_NB_XOR_LVDS_A35
TP_NB_XOR_LVDS_A34
TP_NB_XOR_LVDS_D28
TP_NB_XOR_LVDS_D27
A35
RSVD12
A34
RSVD13
RSVD14
D27
RSVD15
NB_BSEL<0>
NB_BSEL<1>
NB_BSEL<2>
NB_CFG<3>
NB_CFG<4>
NB_CFG<5>
NB_CFG<6>
NB_CFG<7>
NB_CFG<8>
NB_CFG<9>
NB_CFG<10>
NB_CFG<11>
NB_CFG<12>
NB_CFG<13>
NB_CFG<14>
NB_CFG<15>
NB_CFG<16>
NB_CFG<17>
NB_CFG<18>
NB_CFG<19>
NB_CFG<20>
K16
K18
CFG0
CFG1
J18
CFG2
F18
CFG3
CFG4
PM_BMBUSY_L
J29
D28
E15
F15
CFG5
E18
D19
CFG6
CFG7
D16
CFG8
G16
CFG9
CFG10
E16
PM_THRMTRIP_L
VR_PWRGOOD_DELAY
NB_RST_IN_L_R
G15
K15
CFG13
C15
H16
CFG14
CFG15
G18
CFG16
H15
J25
CFG17
CFG18
K27
CFG19
J26
CFG20
G28
PM_BM_BUSY*
F25
PM_EXTTS0*
H26
PM_EXTTS1*
PW_THRMTRIP*
G6
SDVO_CTRLCLK
SDVO_CTRLDATA
NB_SB_SYNC_L
CLK_NB_OE_L
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPD
CFG11
CFG12
D15
28D3
AW7
MEM_CLK_N<0>
28A3 MEM_CLK_N<1>
29A3 MEM_CLK_N<2>
29D3 MEM_CLK_N<3>
AT1
SM_CKE0
SM_CKE1
AU20
SM_CKE2
BA29
SM_CKE3
AY29
30D6
28C6
30D6
28C3
MEM_CKE<0>
MEM_CKE<1>
30D6
29C6 MEM_CKE<2>
30D6
29C3 MEM_CKE<3>
AT20
SM_CS0*
SM_CS1*
AW13
SM_CS2*
SM_CS3*
AY21
SMOCDCOMP0
AL20
SMOCDCOMP1
AF10
30D6
28B3
30D6
28B6
MEM_CS_L<0>
MEM_CS_L<1>
30D6
29B3 MEM_CS_L<2>
30D6
29B6 MEM_CS_L<3>
AW12
AW21
SM_ODT0
BA13
SM_ODT1
SM_ODT2
BA12
SM_ODT3
AU21
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NC
NC
=PP1V8_S3_MEM_NB
30C6
28B3
30C6
28B6
30C6
29B3
MEM_ODT<0>
MEM_ODT<1>
MEM_ODT<2>
30C6
29B6 MEM_ODT<3>
AY20
1
OUT
R1410
OUT
80.6
OUT
OUT
AK1
32B3
SMVREF1
AK41
32B3
G_CLKIN*
AF33
AT9
D41
NB_CLK100M_GCLKIN_N
34C4 NB_CLK100M_GCLKIN_P
34B4
34B2 NB_CLK_DREFCLKIN_N
34B4
34B2 NB_CLK_DREFCLKIN_P
34B4 NB_CLK_DREFSSCLKIN_N
34B4 NB_CLK_DREFSSCLKIN_P
DMI_RXN0
AE35
22D2
DMI_RXN1
DMI_RXN2
AF39
DMI_RXN3
AH39
DMI_S2N_N<0>
22D2 DMI_S2N_N<1>
22D2 DMI_S2N_N<2>
22D2 DMI_S2N_N<3>
34C4
AG33
A27
D_REFCLKIN
A26
D_REFSSCLKIN*
D_REFSSCLKIN
C40
AG35
DMI_S2N_P<0>
DMI_S2N_P<1>
22D2 DMI_S2N_P<2>
22D2 DMI_S2N_P<3>
IN
C1415
IN
0.1uF
IN
IN
AE39
IN
DMI_RXP3
AG39
H32
CLK_REQ*
D1
NC0
DMI_TXN1
DMI_TXN2
AF41
DMI_TXN3
AH41
AG37
C41
NC1
C1
DMI_TXP0
DMI_TXP1
AC37
BA41
NC2
NC3
BA40
NC4
DMI_TXP2
AF37
BA39
DMI_TXP3
BA3
NC5
NC6
AG41
BA2
NC7
BA1
NC8
NC9
B41
AY41
NC10
NC11
AY1
NC12
AW41
AW1
NC13
NC14
A40
NC15
A4
A39
NC16
NC17
A3
NC18
B2
DMI_N2S_P<0>
DMI_N2S_P<1>
22D2 DMI_N2S_P<2>
22D2 DMI_N2S_P<3>
AE41
20%
10V
CERM
402
80.6
1%
1/16W
MF-LF
2 402
IN
DMI_RXP1
DMI_RXP2
AE37
0.1uF
IN
R1411
IN
RSTIN*
DMI_TXN0
IN
AH34
ICH_SYNC*
C1416
IN
22D2
K28
IN
IN
22D2
DMI_N2S_N<0>
DMI_N2S_N<1>
22D2 DMI_N2S_N<2>
22D2 DMI_N2S_N<3>
MEM_VREF_NB_0
MEM_VREF_NB_1
IN
AC35
AF35
20%
10V
CERM
402
IN
DMI_RXP0
H27
MEM_RCOMP_L
MEM_RCOMP
SMVREF0
G_CLKIN
D_REFCLKIN*
16B6 19D7 65B6
1%
1/16W
MF-LF
402
AV9
PWROK
SDVO_CTRLCLK
SDVO_CTRLDATA
SMRCOMP*
SMRCOMP
AH33
H28
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SM_CK0
J19
PM_EXTTS_L
PM_DPRSLPVR
R1430
945GM
NB
F7
NC
19D3
RSVD1
F3
TP_NB_XOR_FSB2_H7
TP_NB_TESTIN_L
NB_TV_DCONSEL0
NB_TV_DCONSEL1
19D3
T32
NC
NC
NC
NC
NC
NC
(D_PLLMON1#)
(D_PLLMON1)
(H_EDRDY#)
(H_PCREQ#)
(H_PLLMON1#)
(H_PLLMON1)
(H_PROCHOT#)
(TESTIN#)
(TV_DCONSEL0)
(TV_DCONSEL1)
(VSS_MCHDETECT)
(LA_DATAN3)
(LA_DATAP3)
(LB_DATAN3)
(LB_DATAP3)
U1200
RSVD
DDR MUXING
CFG
R1441
CLK
5%
1/16W
MF-LF
402
PM
10K
65B3 20B4 20A4 19C7 14D6
=PP3V3_S0_NB
MISC
DMI
65B3 20B4 20A4 19C7 14C7
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NC
NB Misc Interfaces
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
14
84
OMIT
IO
28D3
IO
28D3
IO
28D6
IO
28D6
IO
28D6
28D6
28D3
28D3
28D6
28D6
IO
IO
IO
IO
IO
28D6
IO
28D6
IO
28D3
IO
28C3
28C6
28C6
28C6
28C3
28C3
28C3
28C3
IO
IO
IO
IO
IO
IO
IO
IO
IO
28C6
IO
28C3
IO
28C6
IO
28C6
28C3
28C6
IO
IO
IO
28C3
IO
28B3
IO
28B6
IO
28B3
IO
28B6
28B3
28B6
28B3
28B6
IO
IO
IO
IO
IO
28A3
IO
28A6
IO
28A3
28A6
IO
28D3
28C6
IO
IO
IO
28A3
IO
28A6
IO
28A6
IO
28A3
IO
28A6
IO
28A3
IO
28A6
IO
28A6
IO
28A3
IO
28A6
IO
28A3
IO
28A3
IO
28A3
IO
28B3
IO
28A6
IO
28B6
IO
28B6
IO
28A6
IO
28A3
28B3
IO
IO
AJ35
SA_DQ0
AJ34
SA_DQ1
SA_DQ2
AM31
AJ36
SA_DQ3
SA_DQ4
AK35
SA_DQ5
AM33
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AY13
30B6
28B6
SA_BS1
SA_BS2
AV14
SA_CAS*
SA_DM2
AL26
AN22
SA_DQ8
SA_DM3
SA_DM4
AM14
SA_DM5
AL9
AR3
SA_DQ11
SA_DM6
SA_DM7
SA_DQ12
SA_DQ13
AH4
SA_DQS0
AK33
SA_DQ14
SA_DQ15
SA_DQS1
AT33
AN28
SA_DQ16
SA_DQS2
SA_DQS3
SA_DQS4
AN12
SA_DQS5
SA_DQS6
AN8
SA_DQS7
AG5
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
AN20
SA_DQ27
AP24
SA_DQ28
SA_DQ29
AP20
SA_DQ30
SA_DQS0*
SA_DQS1*
SA_DQS2*
SA_DQS3*
AK32
AU33
AN27
AM21
SA_DQS4*
AM12
SA_DQS5*
SA_DQS6*
AL8
SA_DQS7*
AH5
AN3
SA_MA0
AY16
SA_MA1
AU14
SA_MA2
SA_MA3
AW16
SA_MA4
SA_MA5
BA17
SA_DQ36
SA_DQ37
SA_MA6
AV17
AU17
SA_DQ38
SA_MA7
SA_MA8
SA_MA9
AT16
AK9
SA_DQ39
SA_DQ40
SA_DQ41
SA_MA10
SA_MA11
AU13
AN7
SA_MA12
AV20
SA_MA13
AV12
AT21
AR12
SA_DQ31
SA_DQ32
AR14
SA_DQ33
AP13
SA_DQ34
SA_DQ35
AP12
AT13
AT12
AL14
AL12
AK8
AK7
SA_DQ42
SA_DQ43
AP9
SA_DQ44
AN9
SA_DQ45
SA_DQ46
AT5
SA_RAS*
SA_RCVENIN*
AW17
AT17
30B6
28B3
AW14
AK23
29D6
IO
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MEM_A_A<0>
30C6
28B6 MEM_A_A<1>
30C6
28B3 MEM_A_A<2>
30C6
28B6 MEM_A_A<3>
30C6
28B3 MEM_A_A<4>
30C6
28B6 MEM_A_A<5>
30C6
28C3 MEM_A_A<6>
30C6
28C3 MEM_A_A<7>
30C6
28C6 MEM_A_A<8>
30C6
28C6 MEM_A_A<9>
30C6
28B6 MEM_A_A<10>
30C6
28C3 MEM_A_A<11>
30C6
28C6 MEM_A_A<12>
30C6
28B3 MEM_A_A<13>
AU16
OUT
OUT
30C6
28B3
BA16
IO
OUT
MEM_A_DQS_P<0>
28D6 MEM_A_DQS_P<1>
28C6 MEM_A_DQS_P<2>
28C3 MEM_A_DQS_P<3>
28B6 MEM_A_DQS_P<4>
28A6 MEM_A_DQS_P<5>
28A3 MEM_A_DQS_P<6>
28A3 MEM_A_DQS_P<7>
28D6 MEM_A_DQS_N<0>
28D6 MEM_A_DQS_N<1>
28C6 MEM_A_DQS_N<2>
28C3 MEM_A_DQS_N<3>
28B6 MEM_A_DQS_N<4>
28A6 MEM_A_DQS_N<5>
28A3 MEM_A_DQS_N<6>
28B3 MEM_A_DQS_N<7>
AP3
29D3
OUT
28D6
AM22
OUT
OUT
MEM_A_CAS_L
28D3 MEM_A_DM<0>
28D3 MEM_A_DM<1>
28C3 MEM_A_DM<2>
28C6 MEM_A_DM<3>
28B3 MEM_A_DM<4>
28A3 MEM_A_DM<5>
28A6 MEM_A_DM<6>
28A6 MEM_A_DM<7>
AM35
SA_DQ9
SA_DQ10
SA_DQ19
MEM_A_BS<0>
MEM_A_BS<1>
MEM_A_BS<2>
(4 OF 10)
SA_DQ6
SA_DQ7
AP21
AL23
BA20
AU12
AJ33
SA_DQ25
SA_DQ26
AL22
BGA
30B6
28B6
30B6
28B3
30B6
28C6
SA_BS0
SA_DM0
SA_DM1
SA_DQ17
SA_DQ18
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
MEM_A_RAS_L
OUT
NC
NC
29D6
IO
29D3
IO
29D6
IO
29D3
IO
29D3
29D6
29D3
29D3
29D6
29D3
IO
IO
IO
IO
IO
IO
29D3
IO
29D6
IO
29D6
IO
29D6
IO
29C3
29C3
29C3
29C6
29C6
29C6
29C3
29C6
29C6
IO
IO
IO
IO
IO
IO
IO
IO
IO
29C6
IO
29C3
IO
29C6
IO
29C3
IO
29C6
IO
29C3
IO
29C3
IO
29B3
IO
29B6
IO
29B6
IO
29B6
29B6
29B3
29B3
29B3
IO
IO
IO
IO
IO
29B6
IO
29B6
IO
29A6
29A6
IO
IO
29B3
IO
29B3
IO
29A3
IO
29A3
IO
29A3
IO
29A6
IO
AY2
SA_DQ47
SA_DQ48
AW2
SA_DQ49
AP1
29A3
IO
AN2
SA_DQ50
SA_DQ51
29A6
IO
AV2
SA_DQ52
29A6
IO
AT3
29A3
IO
AN1
SA_DQ53
SA_DQ54
29A6
IO
AL2
SA_DQ55
29A3
IO
AG7
SA_DQ56
SA_DQ57
29A3
IO
29A3
IO
SA_DQ58
SA_DQ59
29A3
IO
AF6
29A6
IO
AG9
SA_DQ60
29A6
IO
AH6
SA_DQ61
SA_DQ62
29A6
IO
AF4
AF8
SA_DQ63
29A3
AL5
AF9
AG4
U1200
945GM
NB
SA_RCVENOUT*
AK24
SA_WE*
AY14
30B6
28B6
MEM_A_WE_L
OUT
29A6
IO
IO
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
AY28
30A6
29B6
30A6
29B3
30A6
29C6
SB_CAS*
AR24
30A6
29B6
SB_DM0
SB_DM1
AK36
SB_DQ6
SB_DQ7
SB_DM2
AT36
BA31
SB_DQ8
SB_DM3
SB_DM4
SB_DQ9
SB_DQ10
SB_DM5
AH8
BA5
SB_DQ11
SB_DM6
SB_DM7
AK39
SB_DQ0
AJ37
SB_DQ1
SB_DQ2
AP39
AJ38
SB_DQ3
SB_DQ4
AK38
SB_DQ5
AR41
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
945GM
NB
BGA
SB_BS0
AT24
SB_BS1
SB_BS2
AV23
MEM_B_BS<0>
MEM_B_BS<1>
MEM_B_BS<2>
OUT
OUT
OUT
(5 OF 10)
AN4
MEM_B_CAS_L
29D3 MEM_B_DM<0>
29D3 MEM_B_DM<1>
29C3 MEM_B_DM<2>
29C6 MEM_B_DM<3>
29B3 MEM_B_DM<4>
29A6 MEM_B_DM<5>
29A6 MEM_B_DM<6>
29A3 MEM_B_DM<7>
SB_DQS0
AM39
29D6
SB_DQ14
SB_DQ15
SB_DQS1
AT39
AU35
SB_DQ16
SB_DQS2
SB_DQS3
SB_DQS4
AR16
SB_DQS5
SB_DQS6
AR10
SB_DQS7
AN5
SB_DQ12
SB_DQ13
AR38
AL17
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SB_DQS0*
SB_DQS1*
AM40
SB_DQS2*
SB_DQS3*
AT35
SB_DQS4*
AP16
SB_DQS5*
SB_DQS6*
AT10
SB_DQS7*
AP5
MEM_B_DQS_P<0>
29D6 MEM_B_DQS_P<1>
29C6 MEM_B_DQS_P<2>
29C3 MEM_B_DQS_P<3>
29B6 MEM_B_DQS_P<4>
29A3 MEM_B_DQS_P<5>
29A3 MEM_B_DQS_P<6>
29A6 MEM_B_DQS_P<7>
29D6 MEM_B_DQS_N<0>
29D6 MEM_B_DQS_N<1>
29C6 MEM_B_DQS_N<2>
29C3 MEM_B_DQS_N<3>
29B6 MEM_B_DQS_N<4>
29B3 MEM_B_DQS_N<5>
29A3 MEM_B_DQS_N<6>
29A6 MEM_B_DQS_N<7>
SB_MA0
AY23
30B6
29B3
SB_MA1
AW24
SB_MA2
SB_MA3
AY24
SB_MA4
SB_MA5
AT27
SB_DQ36
SB_DQ37
SB_MA6
AU27
AV28
SB_DQ38
SB_MA7
SB_MA8
SB_MA9
AW27
AJ11
SB_DQ39
SB_DQ40
SB_DQ41
SB_MA10
SB_MA11
AV24
AH10
SB_MA12
AY27
SB_MA13
AR23
MEM_B_A<0>
30B6
29B6 MEM_B_A<1>
30B6
29B3 MEM_B_A<2>
30B6
29B6 MEM_B_A<3>
30B6
29B3 MEM_B_A<4>
30B6
29B6 MEM_B_A<5>
30B6
29C3 MEM_B_A<6>
30B6
29C3 MEM_B_A<7>
30B6
29C6 MEM_B_A<8>
30B6
29C6 MEM_B_A<9>
30B6
29B6 MEM_B_A<10>
30B6
29C3 MEM_B_A<11>
30B6
29C6 MEM_B_A<12>
30B6
29B3 MEM_B_A<13>
SB_RAS*
SB_RCVENIN*
AU23
30A6
29B3
MEM_B_RAS_L
OUT
SB_RCVENOUT*
AK18
SB_WE*
AR27
30A6
29B6
MEM_B_WE_L
OUT
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
AT31
SB_DQ25
SB_DQ26
AU29
SB_DQ27
BA33
AW31
SB_DQ28
SB_DQ29
AV29
SB_DQ30
AU31
AW29
AM19
SB_DQ31
SB_DQ32
AL19
SB_DQ33
AP14
SB_DQ34
SB_DQ35
AN14
AN17
AM16
AP15
AL15
AJ9
AN10
SB_DQ42
SB_DQ43
AK13
SB_DQ44
AH11
SB_DQ45
SB_DQ46
AK10
BA10
SB_DQ47
SB_DQ48
AW10
SB_DQ49
BA4
AW4
SB_DQ50
SB_DQ51
AY10
SB_DQ52
AY9
AW5
SB_DQ53
SB_DQ54
AY5
SB_DQ55
AV4
SB_DQ56
SB_DQ57
AJ8
AR5
AK3
SB_DQ58
SB_DQ59
AT4
SB_DQ60
AK5
AJ5
SB_DQ61
SB_DQ62
AJ3
SB_DQ63
AK4
DDR SYSTEM MEMORY B
28D3
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
DDR SYSTEM MEMORY A
IO
OMIT
U1200
28D3
AR29
AR7
AU39
AP29
AT7
AR28
AT28
AV27
BA27
AK16
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NC
NC
NB DDR2 Interfaces
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
15
84
NCTF balls are Not Critical To Function
AD27
AC27
AB27
AA27
VCC_NCTF4
W27
V27
VCC_NCTF5
VCC_NCTF6
U27
VCC_NCTF7
T27
VCC_NCTF8
VCC_NCTF9
AD26
VCC_NCTF10
AC26
VCC_NCTF11
VCC_NCTF12
AB26
AA26
C1613
0.47UF
0.47UF
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
L16
N16
M17
M16
VCC_109
VCC_110
VCC_108
P17
L18
N17
VCC_106
VCC_107
VCC_105
N18
L19
M18
VCC_103
VCC_104
VCC_102
N19
Y19
M19
VCC_100
VCC_101
AA19
AB19
VCC_SM105
VCC_SM106
VCC_SM107
AJ6
AV1
AJ1
VCC_SM103
VCC_SM104
AL6
AK6
VCC_SM102
AN6
VCC_SM87
VCC_SM88
AK11
AP6
VCC_SM86
AG12
VCC_SM100
VCC_SM101
VCC_SM84
VCC_SM85
AJ12
AR6
VCC_SM83
AK12
VCC_SM98
VCC_SM99
VCC_SM81
VCC_SM82
AJ13
AT6
VCC_SM80
AJ14
AV6
VCC_SM78
VCC_SM79
AR15
VCC_SM97
VCC_SM76
VCC_SM77
AU15
AW6
VCC_SM75
AV15
VCC_SM95
VCC_SM96
VCC_SM73
VCC_SM74
AY15
AY6
VCC_SM72
BA15
VCC_SM94
VCC_SM70
VCC_SM71
AJ16
BA6
VCC_SM69
AH17
AP8
VCC_SM67
VCC_SM68
AJ18
AR8
VCC_SM65
VCC_SM66
AK19
VCC_SM92
VCC_SM93
VCC_SM64
AP19
VCC_SM91
VCC_SM62
VCC_SM63
AT19
AT8
VCC_SM61
AU19
AV8
VCC_SM59
VCC_SM60
AW19
AW8
VCC_SM58
AY19
VCC_SM89
VCC_SM90
VCC_SM56
VCC_SM57
AK20
AY8
VCC_SM54
VCC_SM55
AJ22
BA8
VCC_SM53
AK22
=PP1V8_S3_MEM_NB
10%
6.3V
CERM-X5R
402
VCC_98
VCC_99
VCC_97
M20
N20
L20
VCC_95
VCC_96
VCC_94
W20
Y20
P20
VCC_92
VCC_93
VCC_91
AB20
AC20
L21
M21
N21
VCC_SM51
VCC_SM52
AR22
AH12
VCC_SM50
AT22
AH13
VCC_SM48
VCC_SM49
AV22
AJ15
VCC_SM47
AW22
AT15
VCC_SM45
VCC_SM46
BA22
AW15
VCC_SM43
VCC_SM44
BA23
AH16
VCC_SM42
AH24
AJ17
VCC_SM40
VCC_SM41
AH25
AJ19
VCC_SM39
AJ25
AR19
VCC_SM37
VCC_SM38
AJ26
AV19
VCC_SM36
AR26
BA19
VCC_SM34
VCC_SM35
AU26
AK21
VCC_SM32
VCC_SM33
AW26
AP22
VCC_SM31
AY26
AU22
VCC_SM29
VCC_SM30
AH27
AY22
VCC_SM28
AJ27
AJ23
VCC_SM26
VCC_SM27
AJ28
AJ24
VCC_SM25
AH29
AH26
VCC_SM23
VCC_SM24
AK29
AT26
VCC_SM21
VCC_SM22
AM29
AV26
VCC_SM20
AM30
BA26
VCC_SM18
VCC_SM19
AP30
AH28
VCC_SM17
AR30
AJ29
VCC_SM15
VCC_SM16
AU30
AL29
VCC_SM14
AV30
AN30
VCC_SM12
VCC_SM13
AY30
AT30
VCC_SM10
VCC_SM11
AR34
AW30
VCC_SM9
AT34
BA30
VCC_SM7
VCC_SM8
AV34
AU34
VCC_SM6
AW34
AY34
VCC_SM4
VCC_SM5
65B6 19D7 14C2
NB_VCCSM_LF2
NB_VCCSM_LF1
0.47UF
2
C1614
C1615
VCC_89
VCC_90
VCC_87
VCC_88
VCC_86
AA21
AC21
W21
VCC_84
VCC_85
VCC_83
M22
N22
L22
VCC_81
VCC_82
VCC_80
W22
P22
VCC_78
VCC_79
AB22
AC22
L23
M23
N23
Y22
VCC_76
VCC_77
VCC_75
VCC_73
VCC_74
VCC_72
Y23
AA23
P23
VCC_70
VCC_71
VCC_69
M24
AB23
VCC_67
VCC_68
P24
L25
M25
N25
L26
N26
P26
L27
N24
VCC_65
VCC_66
VCC_64
VCC_62
VCC_63
VCC_61
VCC_59
VCC_60
VCC_58
N27
M27
VCC_56
VCC_57
L28
M28
P27
VCC_54
VCC_55
VCC_53
P28
R28
T28
U28
V28
N28
VCC_51
VCC_52
VCC_50
VCC_48
VCC_49
VCC_47
AA28
Y28
VCC_45
VCC_46
L29
M29
AB28
VCC_43
VCC_44
VCC_42
R29
U29
V29
W29
Y29
AA29
L30
P29
VCC_40
VCC_41
VCC_39
VCC_37
VCC_38
VCC_36
VCC_34
VCC_35
N30
P30
M30
VCC_32
VCC_33
VCC_31
T30
U30
R30
VCC_29
VCC_30
VCC_28
W30
Y30
AA30
M31
V30
VCC_26
VCC_27
VCC_25
VCC_23
VCC_24
P31
R31
N31
VCC_21
VCC_22
VCC_20
T31
V31
W31
J32
L32
AA31
VCC_15
VCC_16
VCC_14
M32
P32
V32
N32
VCC_12
VCC_13
VCC_11
VCC_10
Y32
W32
VCC_8
VCC_9
J33
L33
AA32
VCC_6
VCC_7
VCC_5
(6 OF 10)
P33
N33
VCC_3
VCC_4
W33
VCC_SM3
AM41
BA34
BGA
VCC_2
VCC_0
VCC_1
AU40
Layout Note:
Place near pin BA23
10uF
20%
6.3V
X5R
603
C1621
C1610
C1612
10uF
0.47UF
0.47UF
0.47UF
20%
6.3V
X5R
603
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
Layout Note:
Place in cavity
VSS_NCTF7
AE20
VSS_NCTF8
VSS_NCTF9
AE19
VSS_NCTF10
AC17
VSS_NCTF11
VSS_NCTF12
Y17
AE18
U17
AG27
VCC_NCTF18
R26
VCCAUX_NCTF1
VCCAUX_NCTF2
AF27
T26
VCCAUX_NCTF3
AF26
AD25
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
AB25
VCCAUX_NCTF4
VCCAUX_NCTF5
AG25
AC25
VCC_NCTF22
VCC_NCTF23
VCCAUX_NCTF6
VCCAUX_NCTF7
AG24
VCCAUX_NCTF8
AG23
W25
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
U25
VCCAUX_NCTF9
VCCAUX_NCTF10
AF23
V25
VCCAUX_NCTF11
AF22
T25
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
AD24
VCCAUX_NCTF12
VCCAUX_NCTF13
AG21
R25
VCCAUX_NCTF14
AG20
AC24
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
AA24
VCCAUX_NCTF15
VCCAUX_NCTF16
AF20
AB24
VCC_NCTF33
VCC_NCTF34
VCCAUX_NCTF17
VCCAUX_NCTF18
AF19
VCCAUX_NCTF19
AG18
V24
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
T24
VCCAUX_NCTF20
VCCAUX_NCTF21
AF18
U24
VCCAUX_NCTF22
AG17
R24
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
V23
VCCAUX_NCTF23
VCCAUX_NCTF24
AF17
AD23
VCCAUX_NCTF25
AD17
U23
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
R23
VCCAUX_NCTF26
VCCAUX_NCTF27
AB17
T23
VCC_NCTF44
VCC_NCTF45
VCCAUX_NCTF28
VCCAUX_NCTF29
W17
VCC_NCTF46
VCC_NCTF47
VCCAUX_NCTF30
T17
R17
T22
VCC_NCTF48
R22
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
AF16
AD21
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
U21
VCCAUX_NCTF34
VCCAUX_NCTF35
AE16
V21
VCCAUX_NCTF36
AC16
T21
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
AD20
VCCAUX_NCTF37
VCCAUX_NCTF38
AB16
R21
VCC_NCTF55
VCC_NCTF56
VCCAUX_NCTF39
VCCAUX_NCTF40
Y16
VCC_NCTF57
VCC_NCTF58
VCCAUX_NCTF41
V16
U16
R20
VCC_NCTF59
AD19
VCCAUX_NCTF42
VCCAUX_NCTF43
VCC_NCTF60
VCC_NCTF61
VCCAUX_NCTF44
R16
U19
VCC_NCTF62
T19
VCCAUX_NCTF45
VCCAUX_NCTF46
AG15
VCCAUX_NCTF47
AE15
AD18
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
AB18
VCCAUX_NCTF48
VCCAUX_NCTF49
AD15
AC18
VCC_NCTF66
VCC_NCTF67
VCCAUX_NCTF50
VCCAUX_NCTF51
AB15
VCC_NCTF68
VCC_NCTF69
VCCAUX_NCTF52
Y15
W15
V18
VCC_NCTF70
U18
VCCAUX_NCTF53
VCCAUX_NCTF54
VCC_NCTF71
VCC_NCTF72
VCCAUX_NCTF55
U15
VCCAUX_NCTF56
VCCAUX_NCTF57
T15
U20
T20
V19
AA18
Y18
W18
T18
AE21
VCCAUX_NCTF0
V20
AE22
AE24
VCC_NCTF16
VCC_NCTF17
V22
Layout Note:
Place near pin BA15
AE23
VSS_NCTF5
VSS_NCTF6
VCC_NCTF15
AD22
C1611
VSS_NCTF4
U26
U22
C1620
AE25
AE26
V26
W24
VCC_SM1
VCC_SM2
NB_VCCSM_LF4
NB_VCCSM_LF5
(7 OF 10)
AE27
VSS_NCTF2
VSS_NCTF3
W26
Y24
VCC_SM0
OMIT
AT41
945GM
NB
Speed
400MTs
533MTs
667MTs
AU41
U1200
BGA
VSS_NCTF0
VSS_NCTF1
Y26
Y25
1.8V Max Current

1 Channel
2 Channel
1300mA
2400mA
1500mA
2800mA
1700mA
3200mA
945GM
NB
VCC_NCTF13
VCC_NCTF14
AA25
VCC
AA33
1.05V or 1.5V
VCC_18
VCC_19
16D3 19C8 19D2 19D7
VCC_17
=PPVCORE_S0_NB
U1200
VCC_NCTF2
VCC_NCTF3
Y27
R27
1.05V, Internal Graphics: 3500mA Max

1.05V, External Graphics: 1500mA Max
65D6
1.5V, Internal Graphics: 5500mA Max
VCC_NCTF0
VCC_NCTF1
=PP1V5_S0_NB_VCCAUX
17B6 19C4
19D7 65B6
AG26
=PPVCORE_S0_NB
NCTF
65D6 19D7 19D2 19C8 16C8
These connections can break without

impacting part performance.
OMIT
AF25
AF24
AG22
AF21
AG19
R19
R18
AE17
AA17
V17
AG16
AD16
AA16
W16
T16
AF15
AC15
AA15
V15
R15
NB Power 1
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
16
84
6
70mA Max VCCA_CRTDAC/VCCSYNC
19D7 19D1
65A6 19D7 19A6
OMIT
=PP2V5_S0_NB_VCCSYNC
H22
VCCSYNC
=PP2V5_S0_NB_VCC_TXLVDS
C30
VCC_TXLVDS0
VCC_TXLVDS1
B30
60mA Max
A30
VTT0
AC14
945GM
NB
VTT1
VTT2
AB14
BGA
VTT3
VTT4
V14
VCC_TXLVDS2
1500mA Max VCC3G/3GPLL
VTT5
R14
VCC3G1
VCC3G2
VTT6
VTT7
P14
V41
VCC3G3
VTT8
M14
R41
VCC3G4
VCC3G5
VTT9
VTT10
L14
VTT11
AC13
VTT12
VTT13
AB13
VTT14
VTT15
Y13
N41
L41
19A3
PP1V5_S0_NB_VCCA_3GPLL
=PP2V5_S0_NB_VCCA_3GBG
GND_NB_VSSA_3GBG
19D1
PP2V5_S0_NB_VCCA_CRTDAC
19B3
65A6 19D7 19C5
AC33
G41
VCCA_3GPLL
VCCA_3GBG 2mA Max
AD13
AA13
VSSA_3GBG
F21
VCCA_CRTDAC0
See VCCSYNC
VCCA_CRTDAC1
VTT16
V13
U13
W13
GND_NB_VSSA_CRTDAC
G21
VSSA_CRTDAC
VTT17
VTT18
PP1V5_S0_NB_VCCA_DPLLA
PP1V5_S0_NB_VCCA_DPLLB
PP1V5_S0_NB_VCCA_HPLL
B26
VCCA_DPLLA 50mA Max
VTT19
R13
C39
VCCA_DPLLB 50mA Max

VCCA_HPLL 45mA Max
VTT20
VTT21
N13
VCCA_LVDS 10mA Max
VTT22
L13
A38
B39
VSSA_LVDS
VTT23
VTT24
AB12
19A3
=PP2V5_S0_NB_VCCA_LVDS
GND_NB_VSSA_LVDS
19B6
PP1V5_S0_NB_VCCA_MPLL
AF2
VCCA_MPLL 45mA Max
Y12
PP3V3_S0_NB_VCCA_TVBG
GND_NB_VSSA_TVBG
H20
VTT25
VTT26
VCCA_TVBG
VSSA_TVBG
VTT27
V12
VCCA_TVDACC0
VTT28
VTT29
U12
PP3V3_S0_NB_VCCA_TVDACC
E20
F20
VCCA_TVDACC1
VTT30
R12
C20
VCCA_TVDACB0
VCCA_TVDACB1
VTT31
VTT32
P12
19D1
34B2 19A6
19A6
19B6
65A6 19A4
19C1
19C1
19C1
19D1
AF1
G20
PP3V3_S0_NB_VCCA_TVDACB
D20
19D1
65B6 19D7
65B6 19A5
PP3V3_S0_NB_VCCA_TVDACA
=PP1V5_S0_NB_VCCD_HMPLL
=PP1V5_S0_NB_VCCD_LVDS
20mA Max
65B3 19C7 19C6
=PP3V3_S0_NB_VCC_HV
40mA Max
19D1
65B6 19D7 19C4 16D1
PP1V5_S0_NB_VCCD_QTVDAC
=PP1V5_S0_NB_VCCAUX
1900mA Max
W12
T12
N12
VTT33
M12
VCCA_TVDACA1
L12
AH1
VCCD_HMPLL0
VTT34
VTT35
VTT36
VTT37
P11
150mA Max
VCCD_HMPLL1
A28
VCCD_LVDS0
VTT38
M11
B28
VCCD_LVDS1
VCCD_LVDS2
VTT39
VTT40
R10
VTT41
N10
VTT42
VTT43
M10
VTT44
N9
VTT45
VTT46
M9
P8
VCCD_TVDAC
A23
VCC_HV0
B23
VCC_HV1
B25
VCC_HV2
H19
VCCD_QTVDAC
24mA Max
R11
AH2
N11
P10
P9
R8
AK31
VCCAUX0
VTT47
VTT48
AF31
VCCAUX1
VTT49
M8
AE31
VCCAUX2
VCCAUX3
VTT50
VTT51
P7
AC31
AL30
VCCAUX4
VTT52
M7
AK30
VTT53
VTT54
R6
AJ30
VCCAUX5
VCCAUX6
AH30
VCCAUX7
VTT55
M6
AG30
VCCAUX8
VCCAUX9
VTT56
VTT57
A6
VCCAUX10
VCCAUX11
VTT58
VTT59
P5
C1713
N5
0.47UF
AC30
VCCAUX12
VTT60
M5
AG29
VTT61
VTT62
P4
AF29
VCCAUX13
VCCAUX14
10%
6.3V
CERM-X5R
402
AE29
VCCAUX15
VTT63
M4
AD29
VTT64
VTT65
R3
AC29
VCCAUX16
VCCAUX17
AG28
VCCAUX18
VTT66
N3
AF28
VCCAUX19
VCCAUX20
VTT67
VTT68
M3
VCCAUX21
VCCAUX22
VTT69
VTT70
P2
AJ21
AH21
VCCAUX23
VTT71
D2
AJ20
VCCAUX24
VCCAUX25
VTT72
VTT73
AB1
AH20
AH19
VCCAUX26
VTT74
P1
C1711
P19
VCCAUX27
VCCAUX28
VTT75
VTT76
N1
0.47UF
P16
M1
AH15
VCCAUX29
10%
6.3V
CERM-X5R
402
P15
VCCAUX30
VCCAUX31
AE30
AD30
AE28
AH22
AH14
AG14
AA12
VCCA_TVDACA0
AF30
M13
F19
D21
PP1V5_S0_NB_VCCD_TVDAC
T13
E19
C28
19D1
120mA Max
AF14
VCCAUX32
VCCAUX33
AE14
VCCAUX34
Y14
AF13
VCCAUX35
VCCAUX36
AE13
VCCAUX37
AF12
AE12
VCCAUX38
VCCAUX39
AD12
VCCAUX40
19C8 19D7 65D6
800mA Max
N14
H41
E21
VCC3G6
T14
VCC3G0
AB41
Y41
W14
AJ41
POWER
PP1V5_S0_NB_VCC3G
=PP1V05_S0_NB_VTT
U1200
(8 OF 10)
19B3
N8
N7
P6
NB_VTTLF_CAP3
R5
1
N4
P3
R2
M2
NB_VTTLF_CAP2
NB_VTTLF_CAP1
R1
1
C1712
0.22uF
20%
6.3V
X5R
402
NB Power 2
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
17
84
OMIT
AC41
AA41
W41
AK34
VSS_98
VSS_99
AG34
AC34
VSS_103
VSS_104
AW33
F41
VSS_6
VSS_7
AV40
VSS_8
VSS_105
AR33
VSS_106
VSS_107
AE33
AN40
VSS_9
VSS_10
AK40
VSS_11
VSS_108
Y33
VSS_109
VSS_110
V33
AH40
VSS_12
VSS_13
AG40
VSS_14
VSS_111
R33
AF40
VSS_15
VSS_16
VSS_112
VSS_113
M33
VSS_17
VSS_18
VSS_114
VSS_115
G33
VSS_19
VSS_116
D33
VSS_117
VSS_118
B33
AR39
VSS_20
VSS_21
AN39
VSS_22
VSS_119
AG32
VSS_120
VSS_121
AF32
AC39
VSS_23
VSS_24
AB39
VSS_25
VSS_122
AC32
VSS_26
VSS_27
VSS_123
VSS_124
AB32
VSS_28
VSS_29
VSS_125
VSS_126
B32
VSS_30
VSS_127
AV31
VSS_31
VSS_32
VSS_128
VSS_129
AN31
VSS_33
VSS_130
AG31
VSS_131
VSS_132
AB31
L39
VSS_34
VSS_35
J39
VSS_36
VSS_133
AB30
VSS_37
VSS_38
VSS_134
VSS_135
E30
VSS_136
VSS_137
AN29
D39
VSS_39
VSS_40
AT38
VSS_41
VSS_138
T29
VSS_42
VSS_43
VSS_139
VSS_140
N29
VSS_44
VSS_141
G29
VSS_142
VSS_143
E29
AE38
VSS_45
VSS_46
C38
VSS_47
VSS_144
B29
VSS_48
VSS_49
VSS_145
VSS_146
A29
VSS_50
VSS_51
VSS_147
VSS_148
AW28
VSS_4
VSS_5
AE40
B40
AY39
AW39
AV39
AJ39
AA39
Y39
W39
V39
T39
R39
P39
N39
M39
H39
G39
F39
AM38
AH38
AG38
AF38
AK37
AH37
AB37
AA37
NB
BGA
(9 OF 10)
VSS
VSS_163
B27
VSS_164
VSS_165
AN26
VSS_69
VSS_166
K26
VSS_70
VSS_71
VSS_167
VSS_168
F26
VSS_72
VSS_73
VSS_169
VSS_170
AK25
AN21
VSS_200
VSS_293
A9
AL21
VSS_201
VSS_202
VSS_294
VSS_295
AG8
AB21
Y21
VSS_203
VSS_296
AA8
P21
VSS_204
VSS_205
VSS_297
VSS_298
U8
VSS_299
VSS_300
C8
H21
VSS_206
VSS_207
C21
VSS_208
VSS_301
AV7
AW20
VSS_209
VSS_210
VSS_302
VSS_303
AP7
AR20
AM20
VSS_211
VSS_304
AJ7
AA20
VSS_212
VSS_213
VSS_305
VSS_306
AH7
K20
B20
VSS_214
VSS_307
AC7
A20
VSS_215
VSS_216
VSS_308
VSS_309
R7
VSS_217
VSS_218
VSS_310
VSS_311
D7
VSS_172
VSS_173
H25
VSS_77
VSS_174
D25
AR35
VSS_78
VSS_79
VSS_175
VSS_176
A25
VSS_80
VSS_177
AU24
VSS_81
VSS_82
VSS_178
VSS_179
AL24
BA7
AL7
AF7
AG6
VSS_222
VSS_315
U6
P18
VSS_223
VSS_224
VSS_316
VSS_317
N6
H18
D18
VSS_225
VSS_318
H6
A18
VSS_226
VSS_227
VSS_319
VSS_320
B6
VSS_321
VSS_322
AF5
AP17
VSS_228
VSS_229
AM17
VSS_230
VSS_323
AY4
AK17
VSS_324
VSS_325
AR4
AV16
VSS_231
VSS_232
AN16
VSS_233
VSS_326
AL4
AL16
VSS_234
VSS_235
VSS_327
VSS_328
AJ4
J16
F16
VSS_236
VSS_329
U4
C16
VSS_237
VSS_238
VSS_330
VSS_331
R4
VSS_332
VSS_333
F4
AK15
VSS_239
VSS_240
N15
VSS_241
VSS_334
AY3
M15
VSS_335
VSS_336
AW3
L15
VSS_242
VSS_243
B15
VSS_244
VSS_337
AL3
Y6
K6
AV5
AD5
AP4
Y4
J4
C4
BA14
VSS_245
VSS_246
VSS_338
VSS_339
AT14
VSS_247
VSS_340
AF3
AK14
VSS_248
VSS_249
VSS_341
VSS_342
AD3
VSS_343
VSS_344
AA3
U14
VSS_250
VSS_251
K14
VSS_252
VSS_345
AT2
H14
VSS_346
VSS_347
AR2
E14
VSS_253
VSS_254
AV13
VSS_255
VSS_348
AK2
AR13
VSS_349
VSS_350
AJ2
AN13
VSS_256
VSS_257
AM13
VSS_258
VSS_351
AB2
AL13
VSS_259
VSS_260
VSS_352
VSS_353
Y2
VSS_261
VSS_262
VSS_354
VSS_355
T2
F13
D13
VSS_263
VSS_356
J2
B13
VSS_357
VSS_358
H2
AY12
VSS_264
VSS_265
AC12
VSS_266
VSS_359
C2
K12
VSS_360
AL1
H12
VSS_267
VSS_268
E12
VSS_269
AA11
VSS_270
VSS_271
Y11
VSS_272
AV3
AH3
AD11
G7
AH18
P13
VSS_92
VSS_93
K8
AB6
AW23
VSS_91
AD8
VSS_313
VSS_314
AG13
VSS_89
VSS_90
E9
VSS_312
BA24
VSS_88
Y9
VSS_220
VSS_221
E25
AV35
AH9
VSS_219
P25
BA9
C19
AA14
VSS_75
VSS_76
AC10
G19
D26
B36
VSS
AL10
AD6
AD14
K25
(10 OF 10)
K19
M26
VSS_171
AN34
G9
A15
VSS_74
D35
VSS_291
VSS_292
C27
C36
F35
VSS_198
VSS_199
J27
VSS_67
VSS_68
G35
R9
AR21
AM15
VSS_66
H35
VSS_290
AM27
AW36
J35
VSS_197
AV21
AN15
AY36
L35
BA21
J28
F27
M35
VSS_288
VSS_289
AD28
VSS_161
VSS_162
N35
VSS_195
VSS_196
AB9
A22
AU28
VSS_64
VSS_65
P35
AR9
BA28
F37
VSS_86
VSS_87
VSS_286
VSS_287
AR17
G27
R35
VSS_193
VSS_194
AY17
VSS_160
VSS_85
F22
C29
VSS_63
T35
AW9
K29
G37
V35
VSS_285
AB29
AK27
VSS_83
VSS_84
VSS_192
W19
VSS_158
VSS_159
W35
G22
AT29
VSS_61
VSS_62
Y35
VSS_283
VSS_284
AC19
AP27
AA35
VSS_190
VSS_191
U10
K22
AN19
VSS_156
VSS_157
AB35
W10
AA22
Y31
VSS_59
VSS_60
AH35
VSS_282
AJ31
E28
BA35
VSS_189
AY31
VSS_155
AC36
C23
G32
VSS_58
AE36
VSS_280
VSS_281
J21
W28
AF36
VSS_187
VSS_188
AG10
F23
K21
VSS_153
VSS_154
AG36
AJ10
J23
AE32
VSS_56
VSS_57
AH36
VSS_279
AH32
AC28
AN36
VSS_186
F33
VSS_152
D37
K23
H33
VSS_55
H37
AP10
AV10
VSS_184
VSS_185
D22
AM28
J37
VSS_277
VSS_278
BGA
W23
E22
VSS_150
VSS_151
L37
B11
T33
VSS_53
VSS_54
M37
D11
VSS_275
VSS_276
AB33
W37
N37
945GM
NB
VSS_274
VSS_182
VSS_183
AV33
AP28
P37
J11
VSS_181
AM23
C34
VSS_149
R37
VSS_273
AN23
U1200
AC23
VSS_52
T37
VSS_180
AH23
Y37
V37
AT23
AF34
VSS_101
VSS_102
P41
AJ40
945GM
OMIT
VSS_97
AE34
AP40
U1200
VSS_100
VSS_3
J41
VSS_1
VSS_2
T41
M41
VSS_0
AG3
AC3
G3
AP2
AD2
U2
N2
F2
NB Grounds
SYNC_DATE=(MASTER)

VSS_94
VSS_95

VSS_96
SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
18
84
7
65D6 19D7
=PP1V05_S0_NB_CRT
Power Interface
These are the power signals that leave the NB "block"
Rail Totals:
=PPVCORE_S0_NB
=PP1V05_S0_FSB_NB
=PP1V05_S0_NB_VTT
=PP1V05_S0_NB_CRT
IN
2310mA Max?
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
3200mA Max
IN
IN
IN
LVDS_CLKCTLA
TP_LVDS_CLKCTLB
13B5
NC_NB_XOR_LVDS_A34
MAKE_BASE=TRUE
13B5
MAKE_BASE=TRUE
13B5
MAKE_BASE=TRUE
MAKE_BASE=TRUE
13B5
13B5
?mA
100mA
24mA
150mA
1900mA
19D2 19D6
65B6
17C6 65B6
16D1 17B6
19C4 65B6
3200mA Max
17D6 19D1
70mA Max
60mA Max
2mA Max
17D6 19A6
65A6
17D6 19C5
65A6
TP_CRT_DDC_CLK
14C6
(MCH H/V SYNC 2.5V PWR)
TP_NB_XOR_LVDS_D27
14C6
TP_NB_XOR_LVDS_D28
14C6
SDVO_CTRLCLK
14B6
SDVO_CTRLDATA
14B6
PP1V5_S0_NB_VCCD_TVDAC
LVDS_IBG
13D5
(MCH TVDAC DIGITAL QUIET 1.5V PWR)
65B6 19D7 19D6
TP_CRT_DDC_DATA
(MCH TVDAC DEDICATED PWR 1.5V)
=PP1V5_S0_NB_TVDAC
17C6
13B5
CRT_DDC_DATA
13B5
MAKE_BASE=TRUE
PP1V5_S0_NB_VCCD_QTVDAC
R1990
65B6 19D7 19D2
17D6 19D7
MAKE_BASE=TRUE
CRT_DDC_CLK
MAKE_BASE=TRUE
1.5K
=PP1V5_S0_NB_TVDAC
TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
?mA Max
40mA Max
14C7 14D6
20A4 20B4 65B3
17C6 19C6
65B3
TP_NB_XOR_LVDS_A35
MAKE_BASE=TRUE
Max
Max
Max
Max
Max
14C2 16B6
65B6
14C6
NO_TEST=TRUE
TP_SDVO_CTRLCLK
TP_SDVO_CTRLDATA
13D2 65C6
17D6
13D5
NO_TEST=TRUE
NC_NB_XOR_LVDS_D28
CRT_HSYNC_R
CRT_VSYNC_R
17D6
GND_NB_VSSA_CRTDAC
LVDS_CLKCTLB
TP_NB_XOR_LVDS_A34
NO_TEST=TRUE
NC_NB_XOR_LVDS_D27
13B5
PP2V5_S0_NB_VCCA_CRTDAC
NO_TEST=TRUE
NC_NB_XOR_LVDS_A35
13B5
1
(MCH CRTDAC ANALOG 2.5V PWR)
=PPVCORE_S0_NB
MAKE_BASE=TRUE
13B5
1500mA Max
19B8 65B6
65D6 19D7 19C8 16D3 16C8
MAKE_BASE=TRUE
13B5
19B5 65C6
=PP3V3_S0_NB
=PP3V3_S0_NB_VCC_HV
IN
40mA Max?
19B5 65C6
IN
Max
Max?
Max
Max
?mA Max
60A7 65C6
65C8
=PP1V8_S3_MEM_NB
IN
132mA Max
19D6 65D6
=PP1V5_S0_NB
=PP1V5_S0_NB_3G
=PP1V5_S0_NB_3GPLL
=PP1V5_S0_NB_PCIE
=PP1V5_S0_NB_PLL
=PP1V5_S0_NB_TVDAC
=PP1V5_S0_NB_VCCAUX
IN
3674mA Max
1500mA
10mA
800mA
?mA
16D3
19D2 65D6
12B7
34B8 34C6 34C8 65D6
19C8
16C8
19C8
12A7
12C2
17D3
65D6
TP_LVDS_CLKCTLA
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_RED_L
CRT_GREEN_L
CRT_BLUE_L
CRT_IREF
13C5
13C5
PP3V3_S0_NB_VCCA_TVDACA
LVDS_VREFH
13C5
13C5
17B6
(MCH TV OUT CHANNEL A 3.3V PWR)
1%
1/16W
MF-LF
2 402
13D5
LVDS_VREFL
17C6
(MCH TV OUT CHANNEL B 3.3V PWR)
13D5
PP3V3_S0_NB_VCCA_TVDACB
13C5
17C6
13C5
(MCH TV OUT CHANNEL C 3.3V PWR)
13C5
PP3V3_S0_NB_VCCA_TVDACC
17C6
(MCH TV DAC BAND GAP 3.3V PWR)
65D6
16D3 16C8
19D7 19D2
=PPVCORE_S0_NB
PP3V3_S0_NB_VCCA_TVBG
17C6
GND_NB_VSSA_TVBG
17C6
GMCH CORE PWR 1.05V BYPASS
1500mA Max
CRITICAL
1
C1900
470uF
65D6 19D7 17D3
20%
2 2.5V
TANT
D2T
C1902
C1903
C1904
C1905
C1906
10uF
1uF
0.22uF
0.22uF
20%
6.3V
X5R
603
20%
6.3V
X5R
603
10%
6.3V
CERM
402
20%
6.3V
X5R
402
20%
6.3V
X5R
402
C1907
0.22uF
20%
6.3V
X5R
402
MCH VCC_HV BYPASS

(MCH HV BUFFER 3.3V PWR)
MCH VTT BYPASS

(MCH FSB 1.05V PWR)
=PP1V05_S0_NB_VTT
10uF
65B3 19C7 17C6
800mA Max
(SHARE C0940 470UF)
MCH VCCA_3GBG BYPASS

(MCH PCIE/DMI BAND GAP 2.5V PWR)
=PP3V3_S0_NB_VCC_HV
40mA Max
65A6 19D7 17D6
GMCH VCCAUX FILTER

(MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V)
65B6 19D7 17B6 16D1
=PP1V5_S0_NB_VCCAUX
2mA Max
1
C1965
C1967
C1914
4.7uF
C1966
2.2uF
0.22uF
10uF
20%
6.3V
CERM
603
20%
6.3V
CERM1
603
20%
6.3V
X5R
402
Layout Note:
Place in cavity
20%
6.3V
X5R
603
1900mA Max
C1915
C1916
0.1uF
2
0.1uF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
65C6 19D7
GMCH VCC3G FILTER

(PCI-E/DMI ANALOG 1.5V PWR)
91nH
=PP1V5_S0_NB_3G
1
L1934
100mA Max
0603
45mA Max
C1934
22UF
20%
6.3V
CERM
805
1 IN
3 EN
C1950
GND
1
1uF
10%
6.3V
CERM
402
OUT
NR/FB
VOLTAGE=1.5V
GMCH VCCA_DPLLA FILTER

(CRT/TVOUT PLL 1.5V PWR)
17C6
VOLTAGE=1.5V
0.01uF
10%
16V
CERM
402
C1952
10uF
C1972
Layout Note:
10uF caps should
be close to MCH
on opposite side.
10uF
2
20%
6.3V
X5R
603
B
1500mA Max
R1975
20%
6.3V
X5R
603
VOLTAGE=1.5V
5%
1/16W
MF-LF NO STUFF
402
C1953
0.1uF
20%
10V
CERM
402
17C6 65A6 19D7 17D6
20%
10V
CERM
402
MCH VCCD_LVDS BYPASS

(MCH LVDS DIGITAL 1.5V PWR)
65B6 17C6
60MA MAX
C1975
10uF
20%
6.3V
X5R
603
C1976
0.1uF
20%
10V
CERM
402
GND_NB_VSSA_3GBG
17D6
Layout Note: Route to caps, then GND
C1991
0.1uF
20%
10V
CERM
402
NB (GM) Decoupling
MCH VCCA_LVDS BYPASS

(MCH LVDS ANALOG 2.5V PWR)
65A6 17C6
20MA MAX
20%
6.3V
CERM
603
0.1uF
2
50MA MAX
MCH VCC_TXLVDS BYPASS

(MCH LVDS TRANSMITTER 2.5V PWR)
4.7UF
C1954
17D6
VOLTAGE=1.5V
2
1%
1/16W
MF-LF
402
34B2
C1990
1
PP1V5_S0_NB_VCCA_3GPLL
0.51
PP1V5_S0_NB_3GPLL_F
VOLTAGE=1.5V
50MA MAX
GMCH VCCA_DPLLB FILTER

(LVDS PLL 1.5V PWR)
PP1V5_S0_NB_VCCA_DPLLB
R1954
PP1V5_S0_NB_DPLL
TPS73115_NR
C1951
Layout Note:
3GPLL 10uF cap should
be placed in cavity
5%
1/16W
MF-LF
402
5
4
20%
10V
CERM
402
SOT23-5
=PP1V5_S0_NB_3GPLL
0.1uF
CRITICAL
TPS73115
65C6 19D7
17C6
C1937
NO STUFF
=PP2V5_S0_NB_DPLL
GMCH VCCA_3GPLL FILTER

(3GIO PLL 1.5V PWR)
0805
R1953
65A6
20%
6.3V
X5R
603
L1975
45mA Max
1
22UF
10uF
20%
2.5V
POLY
CASE-B2
1.0UH-220MA-0.12-OHM
VOLTAGE=1.5V
0603
20%
6.3V
CERM
805
C1971
220UF
20%
10V
CERM
402
GMCH VCCA_MPLL FILTER

(MCH MEMORY PLL 1.5V PWR)
PP1V5_S0_NB_VCCA_MPLL
C1936
17D6
0.1uF
FERR-120-OHM-0.2A
1
C1970
1500mA Max
C1935
L1936
U1900
Layout Note:
Place L and C
close to MCH
17C6
VOLTAGE=1.5V
PP1V5_S0_NB_VCC3G
VOLTAGE=1.5V
2
1210
GMCH VCCA_HPLL FILTER

(HOST PLL 1.5V PWR)
PP1V5_S0_NB_VCCA_HPLL
FERR-120-OHM-0.2A
=PP1V5_S0_NB_PLL
Layout Note:
Place on the edge
L1970
65B6 19D7
C1918
0.1uF
SYNC_MASTER=M59_MG
SYNC_DATE=07/25/2006
10MA MAX
C1992
10uF
20%
6.3V
X5R
603
C1993
C1994
0.1uF
0.01UF
20%
10V
CERM
402
20%
16V
CERM
402

C1995
0.1uF
20%
10V
CERM
402

GND_NB_VSSA_LVDS
SIZE
17C6
Layout Note: Route to caps, then GND
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
19
84
Internal pull-ups
NB_CFG<3>
RESERVED
NB_CFG<4>
RESERVED
=
=
=
=
Partial Clock Gating Disable

XOR Mode Enabled
All-Z Mode Enabled
Normal Operation
NB_CFG<14>
RESERVED
NB_CFG<15>
RESERVED
00
01
10
11
NB_CFG<13:12>
NB_CFG<5>
14C6
Internal pull-up
NBCFG_DMI_X2
1
NB_CFG<5>
High = DMIx4
DMI x2 Select
Low
R2075
2.2K
= DMIx2
2
5%
1/16W
MF-LF
402
PROBABLY NOT NEEDED

NB_CFG<16>
14C6
Internal pull-up
NB_CFG<6>
RESERVED
FSB Dynamic
ODT
NBCFG_DYN_ODT_DISABLE
1
NB_CFG<16>
R2085
High = Enabled
2.2K
Low
5%
1/16W
MF-LF
402
= Disabled
2
NB_CFG<7>
14C6
Internal pull-up
NO STUFF
1
NB_CFG<7>
High = Mobile CPU
CPU Strap
Low
R2077
2.2K
= RESERVED
2
5%
1/16W
MF-LF
402
NB_CFG<17>
RESERVED
=PP3V3_S0_NB
14C7 14D6 19C7 20A4 20B4 65B3
NBCFG_VCC_1V5
1
NB_CFG<18>
NB_CFG<8>
RESERVED
VCC Select
Low
= 1.05V
2
5%
1/16W
MF-LF
402
NB_CFG<18>
14C6
R2058
2.2K
High = 1.5V
Internal pull-down
=PP3V3_S0_NB
NB_CFG<9>
14C6
Internal pull-up
NBCFG_PEG_REVERSE
1
NB_CFG<9>
High = Normal
2.2K
NB_CFG<19>
High = Reversed
PCIE Graphics
Lane Reversal
Low
5%
1/16W
MF-LF
402
DMI Lane
Reversal
Low
= Reversed
2
14C7 14D6 19C7 20A4 20B4 65B3
NBCFG_DMI_REVERSE
1
R2079
R2059
2.2K
= Normal
2
5%
1/16W
MF-LF
402
NB_CFG<19>
14C6
Internal pull-down
=PP3V3_S0_NB
945 External Design Spec says reserved
NB_CFG<10>
RESERVED
NB_CFG<20>
High = Both active
PCIe Backward
Interop. Mode
Low
14B6
= Only SDVO
or PCIe x1
14C7 14D6 19C7 20B4 65B3
NBCFG_SDVO_AND_PCIE
1
R2060
2.2K
5%
1/16W
MF-LF
402
NB_CFG<20>
Internal pull-down
PROBABLY NOT NEEDED

NB Config Straps
NB_CFG<11>
RESERVED
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
20
84
PP3V3_S5_SB_RTC
=PP3V3_S0_SB_GPIO
R2105
402 MF-LF
1/16W 1%
R2194
10K
U2100
26D4 IN
SB_RTC_RST_L
AA3
SB_SM_INTRUDER_L
26D4 IN
NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L
6C6
RTCRST*
Y5
INTRUDER*
SB_INTVRMEN W4 INTVRMEN
ICH7-M
SB
LAD0
LAD1
LAD2
LAD3
BGA
(1 OF 6)
LPC
OUT
AB1
RTCX1
AB2
RTCX2
RTC
26C8
SB_RTC_X1
SB_RTC_X2
LDRQ0*
LDRQ1*/GPIO23
W1
EE_CS
Y1
EE_SHCLK
Y2
EE_DOUT
W3 (INT PU)
EE_DIN
TP_SB_XOR_W1
TP_SB_XOR_Y1
TP_SB_XOR_Y2
TP_SB_XOR_W3
LFRAME*
A20GATE
A20M*
AA6
AB5
AC4
Y6 51C5
58C6
51C4
49D7 5D2
58C6
49C7
AC3
AA5
79A4
AB3
58C6
51C4
49C7 5C2
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
5C2 LPC_AD<3>
TP_SB_DRQ0_L
TP_SB_GPIO23
LPC_FRAME_L
IO
IO
NOTE: LAD<0-3> HAVE INTERNAL 20K PU
IO
IO
NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU

IO
NOSTUFF
OUT
AE22
AH28
84C6 7C8
LAN_CLK
(WEAK INT PD)
6C6
6C6
84B4 47B6 5C1
OUT
84B4 47B6 5C1
OUT
84B4 47B3 5C1
OUT
84B4 47B6 5C1
IN
ACZ_BITCLK
ACZ_SYNC
ACZ_RST_L
ACZ_SDATAIN<0>
R2195
R2198
1
1
R2197
5%
1/16W
MF-LF
402
U3
TP_SB_XOR_U5
TP_SB_XOR_V4
TP_SB_XOR_T5
U5
LAN_RXD0
V4
LAN_RXD1 (WEAK
T5
LAN_RXD2
LAN_RSTSYNC
3984B4 SB_ACZ_BITCLK
3984B4 SB_ACZ_SYNC
U1
ACZ_BIT_CLK
R6
ACZ_SYNC
3984B4 SB_ACZ_RST_L
R5
ACZ_RST*
T2
ACZ_SDIN0
T3 20K PD
ACZ_SDIN1
T1 20K PD
ACZ_SDIN2
TP_SB_ACZ_SDIN1
TP_SB_ACZ_SDIN2
FERR*
INT PU)
GPIO49/CPUPWRGD
U7
LAN_TXD0
V6
LAN_TXD1
V7
LAN_TXD2
TP_SB_XOR_U7
TP_SB_XOR_V6
TP_SB_XOR_V7
TP1/DPRSTP*
TP2/DPSLP*
CPU
6C6
TP_SB_XOR_U3
IGNNE*
INIT3_3V*
INIT*
INTR
RCIN*
AC-97/
AZALIA
NOTE:
POR IS SMC WILL PUT LAN INTF
INTO RESET STATE TO SAVE PWR.
INTEL CONFIRMS OK TO LEAVE PINS AS NC
CPUSPL*
LAN
V3
TP_SB_XOR_V3
AG27
TP_CPU_CPUSLP_L
NMI
SMI*
STPCLK*
20K PD
84B4 47B6 5C1
OUT
ACZ_SDATAOUT
R2196
3984B4 SB_ACZ_SDATAOUT
T4
THRMTRIP*
ACZ_SDOUT
SB_A20GATE
NOTE: PULLED UP PER INTEL
CPU_A20M_L OUT
OUT
36A5
OUT
78B7
IN
78B7
IN
78B2
34C3 5A7
IN
34C3 5A7
IN
OUT
SATA_C_D2R_N
SATA_C_D2R_P
SATA_C_R2D_C_N
SATA_C_R2D_C_P
AF7
SATA_2RXN
AE7
SATA_2RXP
AG6
SATA_2TXN
AH6
SATA_2TXP
SB_CLK100M_SATA_N
SB_CLK100M_SATA_P
AF1
SATA_CLKN
AE1
SATA_CLKP
SATA_RBIAS_N
SATA_RBIAS_P
AH10
SATARBIASN
AG10
SATARBIASP
IDE_PDIOR_L
IDE_PDIOW_L
IDE_PDDACK_L
IDE_IRQ14
IDE_PDIORDY
IDE_PDDREQ
AF15
AH15
AF16
AH16
AG16
AE15
36A5
IN
36A5
IN
36C5
OUT
36C5
OUT
36C5
NOTE: DDREQ HAS INTERNAL 11.5K PD
OUT
AF3
SATA_0RXN
AE3
SATA_0RXP
AG2
SATA_0TXN
AH2
SATA_0TXP
OUT
36C4
IN
36C4
IN
36C4
IN
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
IDE
36A5
78B2
IN
SATA_A_D2R_N
SATA_A_D2R_P
SATA_A_R2D_C_N
SATA_A_R2D_C_P
SATA
36A5
IN
59C7 7B3
CPU_DPRSTP_L
CPU_DPSLP_L
84C6 7B3
=PP1V05_S0_SB_CPU_IO
21D3 23B3 23D5 65B3
5%
1/16W
MF-LF
402
OUT
R2199
R2110
10K
54.9
5%
1/16W
MF-LF
2 402
MF-LF 402
1/16W 1%
7C8
AG22
AG21
AF22
AF25
84C6 7B3
CPU_IGNNE_L
FWH_INIT_L
84C6 7D6 CPU_INIT_L
84C6 7C8 CPU_INTR
84C6 7C8
51C5 50D3 5C2
AG23
CPU_NMI
CPU_SMI_L
84C6 7C8
84C6 7C8
84C6 7C8
CPU_STPCLK_L
CPU_FERR_L
IN
OUT
OUT
OUT
R2100
OUT
NOTE: KEYBOARD CONTROLLER RESET CPU
OUT
NOSTUFF
OUT
CPU_RCIN_L
AH24
AF23
AH22
CPU_PWRGD
NOTE: R2110=56 IN CV.

CHANGED TO 54.9 FOR
BOM CONSOLIDATION
OUT
AG26
AG24
21C1 24C3 25C4 65D6
2.2K 2
1
NOTE: RISING-EDGE TRIGGERED AT CPU
MF-LF 402
1/16W 5%
49C7
SMC_RCIN_L
IN
NOTE: R2108=56 IN CV.

CHANGED TO 54.9 FOR
2
BOM CONSOLIDATION
R2108
54.9
OUT
R2107
OUT
AF26
CPU_THERMTRIP_R
24.9 2
MF-LF 402
1/16W 1%
50C1
14B6 7C6
21C1 24C3 25C4 65D6
LAYOUT NOTE: R2108 TO BE

< 2 IN OF R2107 W/O STUB
PM_THRMTRIP_L
IN
MF-LF 402
1/16W 1%
TP_SB_SATALED_L AF18 SATALED*

36A5
AF24
AH25
=PP3V3_S0_SB_GPIO
R2101
(INT PU)
6C6
LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE
5%
1/16W
MF-LF
2 402
OMIT
IN
21C3 23B3 23D5 65B3
NOTE: ENABLE INTERNAL 1.05V SUSPEND REG
332K
26C8
26D3 25A4 24B3
DIOR* (HSTROBE)
DIOW* (STOP)
DDACK*
IDEIRQ
IORDY (DSTROBE)
DA0
DA1
DA2
DCS1*
DCS3*
DDREQ
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
AH17
AE17
AF17
AE16
AD16
IDE_PDD<0>
IDE_PDD<1>
IDE_PDD<2>
36C5 IDE_PDD<3>
36C5 IDE_PDD<4>
36C5 IDE_PDD<5>
36C5 IDE_PDD<6>
36C5 IDE_PDD<7>
36D4 IDE_PDD<8>
36C4 IDE_PDD<9>
36C4 IDE_PDD<10>
36C4 IDE_PDD<11>
36C4 IDE_PDD<12>
36C4 IDE_PDD<13>
36C4 IDE_PDD<14>
36C4 IDE_PDD<15>
36C5
IO
36C5
IO
36C5
IO
IDE_PDA<0>
36C5 IDE_PDA<1>
36C5 IDE_PDA<2>
36C4
36C5
36C4
IDE_PDCS1_L
IDE_PDCS3_L
LAYOUT NOTE: R2107 TO BE

< 2 IN OF SB
IO
IO
IO
IO
IO
NOTE: DD<7> HAS INTERNAL 11.5K PD
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES RS
AC 07
ACZ_BIT_CLK
SB: 1 OF 4
INTEL HIGH DEFINITION AUDIO

INTERNAL 20K PD ENABLED WHEN
ACZ_RST#
SYNC_DATE=(MASTER)
INTERNAL 20K PD ONLY ENABLED IN S3COLD
- LSO BIT IN AC97 GLOBAL CONTROL REG = 1; OR

NONE
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
ACZ_SDIN[0-2]
INTERNAL 20K PD
INTERNAL 20K PD
ACZ_SDOUT
INTERNAL 20K PD ENABLED DURING RESET AND WHEN
INTERNAL 20K PD ENABLED WHEN

SIZE
ACZ_SYNC
INTERNAL 20K PD
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
21
84
R2200
R2250
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
R2255
10K
5%
1/16W
MF-LF
2 402
OMIT
USB_G_OC_PU
USB_E_OC_PU
R2223 1R2222 1R2226
R2251
10K
5%
1/16W
MF-LF
2 402
10K
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
U2100
39D5
IN
39D5
IN
39C5
OUT
39C5
22C4 6D1
22C4 6D1
22C4 6C1
22C4 6C1
22C4
22C4 6C5
22C4
USB_A_OC_L
USB_B_OC_L
USB_C_OC_L
USB_D_OC_L
USB_E_OC_L
OUT
48C3
IN
48C3
IN
48C3
OUT
48C3
SB_GPIO29
SB_GPIO30
SB_GPIO31
OUT
48B3
IN
48C3
IN
48C3
OUT
48C3
OUT
48B3 IN
48B3
48B3
OUT
48B3
65D3
=PP3V3_S5_SB_IO
OUT
48B3
IN
48B3
IN
48B3
54C7 49D5
IO
54C7 49B5
IO
49D5
IO
54C1 49D5
IO
54C1 49D5
IO
48B3
R2206
10K
MF-LF
1/16W
402 5%
R2207
10K
MF-LF
1/16W
402 5%
OUT
NOSTUFF
R2205
OUT
48A3
10K
MF-LF
1/16W
402 5%
48B3
48B3
IN
IN
IN
OUT
48B3
OUT
ICH7-M
SB
PCIE_A_D2R_N
PCIE_A_D2R_P
PCIE_A_R2D_C_N
PCIE_A_R2D_C_P
F26
PERN1
F25
PERP1
E28
PETN1
E27
PETP1
PCIE_B_D2R_N
PCIE_B_D2R_P
PCIE_B_R2D_C_N
PCIE_B_R2D_C_P
H26
PERN2
H25
PERP2
G28
PETN2
G27
PETP2
Y26
DMI1RXN
Y25
DMI1RXP
W28
DMI1TXN
W27
DMI1TXP
PCIE_C_D2R_N
PCIE_C_D2R_P
PCIE_C_R2D_C_N
PCIE_C_R2D_C_P
K26
PERN3
K25
PERP3
J28
PETN3
J27
PETP3
AB26
DMI2RXN
AB25
DMI2RXP
AA28
DMI2TXN
AA27
DMI2TXP
PCIE_D_D2R_N
PCIE_D_D2R_P
PCIE_D_R2D_C_N
PCIE_D_R2D_C_P
M26
PERN4
M25
PERP4
L28
PETN4
L27
PETP4
PCIE_E_D2R_N
PCIE_E_D2R_P
PCIE_E_R2D_C_N
PCIE_E_R2D_C_P
P26
PERN5
P25
PERP5
N28
PETN5
N27
PETP5
PCIE_F_D2R_N
PCIE_F_D2R_P
PCIE_F_R2D_C_N
PCIE_F_R2D_C_P
T25
PERN6
T24
PERP6
R28
PETN6
R27
PETP6
BGA
(3 OF 6)
P5
SPI_MOSI
P2
SPI_MISO
D3
C4
D5
D4
E5
C3
A2
B3
22D8
22D8
22D8
22D8
14B4
DMI_N2S_N<1>
DMI_N2S_P<1>
14B4 DMI_S2N_N<1>
14B4 DMI_S2N_P<1>
14B4 5A7
14B4 5A7
DMI_N2S_N<2>
DMI_N2S_P<2>
DMI_S2N_N<2>
14B4 DMI_S2N_P<2>
14B4
AD25
DMI3RXN
AD24
DMI3RXP
AC28
DMI3TXN
AC27
DMI3TXP
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
14B4
IN
14B4
OUT
DMI_N2S_N<3>
DMI_N2S_P<3>
14B4 DMI_S2N_N<3>
14B4 DMI_S2N_P<3>
14B4
14B4
34C3
34C3
OUT
IN
IN
OUT
OUT
SB_CLK100M_DMI_N
SB_CLK100M_DMI_P
IN
PP1V5_S0_SB_VCC1_5_B
R2203
1
DMI_IRCOMP_R
PD)
PD)
OC0*
OC1*
OC2*
OC3*
OC4*
OC5*/GPIO29
OC6*/GPIO30
OC7*/GPIO31
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
D2
USBRBIAS*
D1
USBRBIAS
USB_A_N
USB_A_P
USB_B_N
6D1 USB_B_P
6D1 USB_C_N
6D1 USB_C_P
6C1 USB_D_N
6D1 USB_D_P
6C1 USB_E_N
6C1 USB_E_P
6C1 USB_F_N
6C1 USB_F_P
6C1 USB_G_N
6C1 USB_G_P
6C2
6C1 TP_USB_H_N
6C2
6C1 TP_USB_H_P
6D1
IO
6D1
IO
6D1
IO
EXTERNAL 0
TRACKPAD (GEYSER)
IO
IO
EXTERNAL 1
IO
IO
NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD
CAMERA
IO
IO
EXTERNAL 2
IO
IO
IR
IO
IO
BLUETOOTH
IO
IO
IO
R2204
USB_RBIAS_PN
22.6 2
E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6
37C6
IO
37C6
IO
PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>
IO
PCI_FRAME_L F16 FRAME*
37D6
IO
IO
37D6
IO
37D6
IO
37D6
IO
37D6
IO
37D6
IO
37D6
IO
37C6
IO
37C6
IO
37C6
IO
37C6
IO
37C6
IO
37C6
IO
37C6
IO
37C6
IO
37C6
IO
37C6
IO
37C6
IO
37C6 6B7
IO
37C6
IO
37C6
IO
37C6
IO
37C6
IO
37C6
IO
37C6
IO
37C6
IO
37C6
IO
37C6
IO
37C6
IO
37D3 26D2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
25D8 65B3
U2100
ICH7-M
SB
BGA
(2 OF 6)
REQ0*
GNT0*
REQ1*
GNT1*
REQ2*
GNT2*
REQ3*
GNT3*
REQ4*/GPIO22
GNT4*/GPIO48
GPIO1/REQ5*
GPIO17/GNT5*
D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8
1
26D2 PCI_REQ0_L
TP_PCI_GNT0_L
26D2 PCI_REQ1_L
TP_PCI_GNT1_L
26D2 PCI_REQ2_L
TP_PCI_GNT2_L
PCI_REQ3_L
6B7 PCI_GNT3_L
TP_PCI_GNT4_L
IN
OUT
IN
R2298
R2299
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
OUT
IN
OUT
IN
OUT
SB_CRT_TVOUT_MUX
IO
PCI_PME_FW_L
IN
NOTE: FWH_WP_L NOT USED
OUT
37D3
51B4 49C7 5C2
BOM NOTE FOR PD ON PCI_GNT3_L:
PCI
37C6
C/BE0*
37B6
C/BE1*
37B6
C/BE2*
37B6
C/BE3*
IRDY*
PAR
PCICLK
DEVSEL*
PERR*
PLOCK*
SERR*
STOP*
TRDY*
PLTRST*
PCIRST*
(INT 20K PU) PME*
B15
C12
D12
C15
PCI_C_BE_L<0>
PCI_C_BE_L<1>
PCI_C_BE_L<2>
PCI_C_BE_L<3>
A7 37D3 26D2 PCI_IRDY_L

E10
37B6 PCI_PAR
A9 34D6 PCI_CLK_SB
37D3
A12 26D2
PCI_DEVSEL_L
C9 37D3 26D2 PCI_PERR_L
E11
26D2 PCI_LOCK_L
37C3
B10
26D2 PCI_SERR_L
37C3
F15
26D2 PCI_STOP_L
37C3
F14
26D2 PCI_TRDY_L
C26
B18
B19
PLT_RST_L
PCI_RST_L
TP_PCI_PME_L
79A4 26C3
37C2
IO
IO
IO
IO
BOOT_LPC_SPI_L
OUT
R2211
1K
NO STUFF - DEFAULT
STUFF - A16 SWAP OVERRIDE
5%
1/16W
MF-LF
2 402
(STRAPPED TO TOP-BLOCK SWAP MODE

IE SB INVERTS A16 FOR ALL CYCLES
TARGETING FWH BIOS SPACE)
IO
IO
IN
SB BOOT BIOS SELECT
IO
IO
IO
STRAP
GNT5#
R2211
GNT4#
R2210
IO
LPC (DEFAULT)
11
UNSTUFF
IO
PCI
10
UNSTUFF
STUFF
OUT
SPI
01
STUFF
UNSTUFF
IO
UNSTUFF
OUT
NOTE: GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)
SB: 2 OF 4
NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L
26D2
IO
26D2
IO
26D2
IO
37D3 26D2
IO
INT_PIRQA_L
INT_PIRQB_L
INT_PIRQC_L
INT_PIRQD_L
TP_SB_XOR_AE5
TP_SB_XOR_AD5
TP_SB_XOR_AG4
TP_SB_XOR_AH4
TP_SB_XOR_AD9
A3
PIRQA*
B4
PIRQB*
C5
PIRQC*
B5
PIRQD*
AE5
AD5
AG4
AH4
AD9
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
VOLTAGE=0V
LAYOUT NOTE:
PLACE R2204 < 1/2 IN FROM SB
NOTE:
GNT[0-3]# HAVE INT 20K PU
ENABLED ONLY WHEN PCIRST#=0
AND PWROK=H
OMIT
37D6
LAYOUT NOTE:
PLACE R2203 < 1/2 IN FROM SB
24.9 2
1%
1/16W
MF-LF
402
=PP3V3_S0_SB
INT I/F GPIO2/PIRQE*

GPIO3/PIRQF*
GPIO4/PIRQG*
GPIO5/PIRQH*
MISC
RSVD5
RSVD6
NOTE: CHANGE SYMBOL
RSVD7
TO RSVD[1-9]
RSVD8
MCH_SYNC*
G8
F7
F8
G7
SB_GPIO2 IO
26C2 SB_GPIO3
IO
77A1 SB_GPIO4
IO
36C7 ODD_PWR_EN_L
IO

AE9 TP_SB_XOR_AE9
AG8 TP_SB_XOR_AG8
AH8 TP_SB_XOR_AH8
F21
TP_SB_RSVD9 (AKA TP3, INTERNAL 20K PU)
AH20 14B6 NB_SB_SYNC_L
IN

SIZE
DRAWING NUMBER
SHT
NONE
REV.
051-7150
SCALE
26D2
APPLE COMPUTER INC.
24D5 25B6
IN
1/16W MF-LF 1% 402
SPI_SI
SPI_SO
USB_A_OC_L
6D1 USB_B_OC_L
6D1 USB_C_OC_L
6C1 USB_D_OC_L
6C1 USB_E_OC_L
22D8 SB_GPIO29
22D8 6C5 SB_GPIO30
22D8 SB_GPIO31
14B4 5A7
C25
DMI_ZCOMP
D25
DMI_IRCOMP
R2
SPI_CLK (INT
P6
SPI_CS*
P1
SPI_ARB (INT
IN
DMI_N2S_N<0>
DMI_N2S_P<0>
DMI_S2N_N<0>
14B4 DMI_S2N_P<0>
14B4 5A7
AE28
DMI_CLKN
AE27
DMI_CLKP
SPI_SCLK
SPI_CE_L
SPI_ARB
22D8 6D1
V26
DMI0RXN
V25
DMI0RXP
U28
DMI0TXN
U27
DMI0TXP
5%
1/16W
MF-LF
2 402
USB_D_OC_PU
1
DMI
10K
USB
R2225
PCI-EXP
USB_C_OC_PU
1
22C4 6D1
=PP3V3_S5_SB_USB
SPI
65C3
A.0.0
OF
22
84
NOTE FOR R2323 (DEF=NOSTUFF)

STRAPPING @ PWROK RISING:
SB WILL DISABLE TCO TIMER
SYSTEM REBOOT FEATURE
21C3 21D3 23B3 65B3
=PP3V3_S5_SB
8
1
D
65D3 25C8 23D4 23B7 23A7
=PP3V3_S5_SB
7 6
1 NOSTUFF 1 NOSTUFF 1 NO_REBOOT_MODE
R2318
R2395
R2396
R2397
R2327
R2326
R2323
10K
8.2K
10K
8.2K
10K
10K
1K
1/16W
2 402
MF-LF
5%
1/16W
2 402
MF-LF
5%
1/16W
2 402
MF-LF
5%
1/16W
2 402
MF-LF
5%
1/16W
402
2 MF-LF
5%
1/16W
2 MF-LF
402
5%
23A7 23B7 23D8 25C8 65D3
RP2300
=PP3V3_S5_SB_PM
5%
1/16W
SM-LF
1/16W
2 402
MF-LF
5%
2 3
U2100
ICH7-M
SB
R2398
R2320
R2317
R2316
1K
10K
10K
10K
1/16W
2 402
MF-LF
5%
1/16W
402
2 MF-LF
5%
1/16W
402
2 MF-LF
5%
1/16W
402
2 MF-LF
5%
27D8
IO
27D8
IO
C22
B22
SMB_LINK_ALERT_L A26
B25
SMLINK<0>
A25
SMLINK<1>
SMB_CLK
SMB_DATA
NOT USED
PM_RI_L
SB_SPKR
49B7 26C5 5B2
IN
PM_SUS_STAT_L
PM_SYSRST_L
14B6
IN
PM_BMBUSY_L
58C6 51B5 50A2 49C5 5C2
OUT
SMB_ALERT_L
A28
AB18
B23
NOTE: RESERVED FOR FUTURE

33C4
OUT
33C4
OUT
A21
23A6
23A6
IO
26A4
47C3 39C6 5B1
IN
IO
49B7 IN
IN
PCIE_WAKE_L
INT_SERIRQ
PM_THRM_L
IN
SMC_RUNTIME_SCI_L
SMC_EXTSMI_L
SUSCLK
PWROK
GPIO16/DPRSLPVR
TP0/BATLOW*
(INT 20K PU) PWRBTN*
LAN_RST*
GPIO32/CLKRUN*
RSMRST*
TP_GPU_D3COLD_RST_L AC19 GPIO33/AZ_DOCK_EN*

U2
TP_AZ_DOCK_RST_L
GPIO34/AZ_DOCK_RST*
IN
VR_PWRGD_CK410
IO
49B7
GPIO26
AC1
CLK14
B2
CLK48
TP_SB_GPIO6
AD22
DEF=GPI
VRMPWRGD
OD
GPIO
AA4
AC22
C21
C23
C19
34A6
34C7
6C6
100 1
100 1
2
2
R2302
R2303
100 1
R2305
36B5
SB_CLK14P3M_TIMER
SB_CLK48M_USBCTLR
SUS_CLK_SB
64C8 49C5
43B7 42A8
SATA_C_DET_L
5%
2 1/16W
MF-LF
402
IN
IN
IN
OUT
50A2 49C5
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
26A6
PM_SB_PWROK
IN
84C6
59C8 14B7
PM_DPRSLPVR
OUT
64B8
49C5 41B6
1/16W
2 402
MF-LF
5%
OUT
OUT
OUT
NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN
PM_PWRBTN_L
IN
PM_LAN_ENABLE
IN
49D7
49D7
Y4
49B7
PM_BATLOW_L
IN
49D7
PM_RSMRST_L
IN
NOTE:
SMC WILL DRIVE 0-1-0 TO KEEP LAN INTF
IN RESET STATE TO SAVE PWR
R2399
DEF=GPI
AC21
GPIO6
AC18
GPIO7
E21
GPIO8
C20
B24
SLP_S3*
D23
SLP_S4*
F22
SLP_S5*
F20
WAKE*
AH21
SERIRQ
AF20
THRM*
26B8
49B7
GPIO11/SMBALERT*
B21
GPIO27
E23
GPIO28
AG18
PM_CLKRUN_L
C
58C6 51C5 49C7 5C2
BIOS_REC
FWH_MFG_MODE
AF19 SB_GPIO21
GPIO21/SATA0GP
AH18 SB_GPIO19
GPIO19/SATA1GP
AH19
GPIO36/SATA2GP
AE19 SB_GPIO37
GPIO37/SATA3GP
GPIO0/BM_BUSY*
AC20
GPIO18/STPPCI*
AF21
GPIO20/STPCPU*
PM_STPPCI_L
PM_STPCPU_L
SB_GPIO26
58C6 51C4 49C5 5C2
RI*
A19
SPKR (INT WEAK PD)
A27
SUS_STAT*
A22
SYS_RST*
8.2K
10K
SATA GPIO
(4 OF 6)
SMBCLK
SMBDATA
LINKALERT*
SMLINK0
SMLINK1
CLKS
SMB
SYS GPIO
PWR MNGT
R2319 R2343
BGA
1
11B5 26C5 65D3
OMIT
10K
DEF=GPI
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35
64B7
GPIO38
GPIO39
E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20
=PP3V3_S0_SB_GPIO
SMS_INT_L
SMC_SB_NMI
40A3 LAN_ENERGY_DET
50B2 49B5
49D7
1
IN
100K
5% 1/16W
402 MF-LF
IN
IN
49D5
SMC_WAKE_SCI_L
IN
IDE_RESET_L OUT
SV_SET_UP 5C2 23B6 51B5
CRB_SV_DET 23B6
TP_SB_GPIO25_DO_NOT_USE
33B4 SB_CLK100M_SATA_OE_L
OUT
TP_SB_GPIO38 IO
23A3 SATA_C_PWR_EN_L
OUT
36D5
NOTE FOR GPIO25:

- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS
- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)
65D3 25C8 23D8 23D4 23A7
=PP3V3_S5_SB
B
1 NOSTUFF
R2306 R2308
10K
10K
1/16W
2 402
MF-LF
5%
1/16W
2 402
MF-LF
5%
NOTE:
SV_SET_UP IS LINDACARD DETECT
HI = PRESENT
LO = NOT PRESENT
SV_SET_UP
CRB_SV_DET
=PP3V3_S0_SB_GPIO
5C2 23C3 51B5
21C3 21D3 23D5 65B3
23C3
R2388
10K
LAYOUT NOTE:
5%
1/16W
MF-LF
2 402
1 NOSTUFF
R2307 R2309
PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE
65D3 25C8 23D8 23D4 23B7
10K
1/16W
2 402
MF-LF
5%
0
1/16W
402
2 MF-LF
5%
23B3
SATA_C_PWR_EN_L
=PP3V3_S5_SB
1
SB: 3 OF 4
R2313
R2310
10K
10K
1/16W
402
2 MF-LF
5%
1/16W
402
2 MF-LF
5%
1 NOSTUFF
1 NOSTUFF
SYNC_MASTER=M59_MG

FWH_MFG_MODE 23C5
BIOS_REC 23C5
R2314
0
1/16W
2 402
MF-LF
5%

R2311
10K
SIZE
1/16W
402
2 MF-LF
5%
APPLE COMPUTER INC.
DRAWING NUMBER
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
23
84
OMIT
OMIT
A4
A23
N24
P24
R18
U14
V27
AA24
AB27
AD11
B1
D10
F4
G18
J1
L24
M17
N14
N17
N18
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P27
P28
R1
R11
R12
R13
R14
R15
R16
R17
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB28
AC2
AC5
AC9
AC11
AD1
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
5
25D7
AD3
AD4
AD7
AD8
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N15
N16
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27
U2100
ICH7-M
SB
BGA
(6 OF 6)
VSS
25C7
25B6 22C1
PP5V_S5_SB_V5REF_SUS
65B3 25C6 25B8 24B5
=PP3V3_S0_SB_VCC3_3
G10
AD17
F6
AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23
B27
PP1V5_S0_SB_VCCDMIPLL
AG28
=PP1V5_S0_SB_VCC1_5_A_ARX
AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5
25A5
65C6 25D6
PP5V_S0_SB_V5REF
65C6 25D6
65B3 25C6 25B8 24B5
65C6 25C6
=PP1V5_S0_SB_VCCSATAPLL
=PP3V3_S0_SB_VCC3_3
=PP1V5_S0_SB_VCC1_5_A_ATX
AD2
AH11
AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9
V5REF
V5REF_SUS
U2100
ICH7-M
SB
BGA
(5 OF 6)
CORE
VCC1_05
VCC PAUX
VCCLAN_3_3
VCCA3GP
VCC3_3/VCCHDA
VCCSUS3_3/VCCSUSHDA
VCC1_5_B
V_CPU_IO
IDE
VCC3_3
PCI
VCC3_3
VCCRTC
=PPVCORE_S0_SB
25D3 65D6
NOTE FOR VCCLAN_3_3:

S3 IF INTERNAL LAN IS USED
S0 OR S3 IF NOT
=PP3V3_S0_SB_VCCLAN3_3 25D3
65B3
U6
R7
=PP3V3_S0_SB_3V3_1V5_VCCHDA
=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA
AE23
AE26
AH26
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
=PP3V3_S0_SB_VCC3_3_IDE
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
W5
25C4 65B3
65D3
NOTE:
VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V
DEPENDING ON VIO OF AZALIA INTERFACE
CODEC ICS CONSIDERED SO FAR ARE 3.3V
21C1 25C4 65D6
25B4 65B3
=PP3V3_S0_SB_VCC3_3_PCI
PP3V3_S5_SB_RTC
25A4 65B3
21D6 25A4 26D3
=PP3V3_S5_SB_VCCSUS3_3 24A5
25B6 25D2 65C3
A24
C24
D19
VCCSUS3_3
D22
G19
VCC3_3
VCCDMIPLL
ARX
VCC1_5_A
USB
VCCSUS3_3
VCCSATAPLL
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
=PP3V3_S5_SB_VCCSUS3_3_USB
25D2 65C3
VCC3_3
AB17
VCC1_5_A AC17
VCC1_5_A
ATX
VCC1_5_A
T7
F17
G17
=PP1V5_S0_SB_VCC1_5_A
25C2 65C6
AB8
VCC1_5_A AC8
K7
65C3 25D2 25B6 24B3
E3 VCCSUS3_3
65C6 25B6
=PP1V5_S0_SB_VCCUSBPLL
C1
VCCSAUS1_5
CHANGE SYMBOL TO 1.05
AA2
Y7
V5
V1
W2
W7
P7
=PP3V3_S5_SB_VCCSUS3_3
VOLTAGE GENERATED INTERNALLY

SO NO CONNECT HERE
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
C28
G20
VOLTAGE GENERATED INTERNALLY

SO NO CONNECT HERE
VCCUSBPLL
VCCLAN1_5
CHANGE SYMBOL TO 1.05
USB CORE
VCC1_5_A
A1
H6
H7
J6
J7
SB: 4 OF 4
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
25B2 65C6
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.

0
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
24
84
65A1
=PP3V3_S0_SB
65C6
=PP5V_S0_SB
2
ICH VCC1_5_A/ARX BYPASS

(ICH LOGIC&IO[ARX] 1.5V PWR)
24B5 =PP1V5_S0_SB_VCC1_5_A_ARX
1
R2502
100
1/16W
MF-LF
402
5%
10%
2 16V
X5R
402
BAT54DW
SOT-363
ICH V5REF BYPASS

(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)
PP5V_S0_SB_V5REF 24D5
D
1
C2511
0.1UF
D2502
C2503
65C6 24B5
PLACEMENT NOTE:
PLACE C2503 < 2.54MM OF PIN AD17 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
10%
16V
2 X5R
402
C2502
C2517
0.1UF
D2502
3
65B3 25B8
ICH V5REF_SUS BYPASS

(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)
PP5V_S5_SB_V5REF_SUS 24D5
C2504
C2513
0.1UF
ICH VCC_PAUX/VCCLAN3_3 BYPASS

(ICH LAN I/F BUFFER 3.3V PWR)
=PP3V3_S0_SB_VCCLAN3_3
24D3 65B3
1
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PIN AH11
0
PLACEMENT NOTE:
PLACE C2504 < 2.54MM OF PIN F6 OF SB
0
65C6 24A5
C2514
1UF
65C3 24B3
10%
2 16V
X5R
402
65B3
0.1UF
220UF
10%
2 16V
X5R
402
20%
2 2.5V
POLY
CASE-B2
0.1UF
10%
2 16V
X5R
402
0.1UF
C2521
0.1UF
C
ICH VCC1_5A BYPASS
(ICH LOGIC&IO 1.5V PWR)
65C6 24A3
ICH V_CPU_IO BYPASS

(ICH CPU I/O 1.05V PWR)
24C3 21C1 =PP1V05_S0_SB_CPU_IO
1
65C3 25D2 24B3 24A5
10%
2 16V
X5R
402
C2520
0.1UF
10%
2 16V
X5R
402
PLACEMENT NOTE:
PLACE C2520 NEAR PIN E3 OF SB
C2522
0.1UF
C2524
4.7UF
10%
2 16V
X5R
402
20%
2 6.3V
CERM
603
ICH USB CORE/VCC1_5_A BYPASS

(ICH USB CORE 1.5V PWR)
0
65C6 24A3
ICH VCCUSBPLL BYPASS

(ICH USB PLL 1.5V PWR)
ICH VCC3_3 BYPASS
(ICH IO BUFFER 3.3V PWR)
=PP3V3_S0_SB_VCC3_3
65C6 24A5
1
C2515
10%
16V
2 X5R
402
PLACEMENT NOTE:
PLACE C2509 NEAR PIN B27 OF SB
ICH IDE/VCC3_3 BYPASS

(ICH IDE I/O 3.3V PWR)
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PINS AA7 ... AG19
0.1UF
10%
2 16V
X5R
402
0.1UF
10%
16V
2 X5R
402
0.1UF
C2523
0.1UF
65B3 24C3
C2509
C2510
PLACEMENT NOTE:
PLACE CAPS NEAR PINS
AB8 AND AC8 OF SB
PLACEMENT NOTE:
PLACE C2500 & C2505-07 < 2.54MM OF SB
NEAR PINS D28, T28, AD28
ICH VCCSUS3_3 BYPASS

(ICH SUSPEND 3.3V PWR)
10%
16V
2 X5R
402
10%
16V
2 X5R
402
22C1 24D5
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
C2500 1 C2505 1 C2506 1 C2507
C2532
0.1UF
10%
16V
2 X5R
402
10%
16V
2 X5R
402
PLACEMENT NOTE:
PLACE NEAR PINS AE23, AE26 & AH26 OF SB
0.1UF
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN AG9
ICH VCCA3GP(VCC1_5_B BYPASS

(ICH IO,LOGIC 1.5V PWR)
C2533
PLACEMENT NOTE:
K3 ... N7 OF SB
SM-3
65B3 25C6 24B5
0.1UF
ICH VCC3_3/VCCHDA BYPASS

(ICH INTEL HDA CORE 3.3V PWR)
24C3 =PP3V3_S0_SB_3V3_1V5_VCCHDA
65D6
=PP1V5_S0_SB
0.1UF
10%
2 16V
X5R
402
C2519
ICH VCC1_5_A/ATX BYPASS

(ICH LOGIC&IO[ATX] 1.5V PWR)
10%
6.3V
2 CERM
402
L2500
C2534
0.1UF
ICH USB/VCCSUS3_3 BYPASS

(ICH SUSPEND USB 3.3V PWR)
10%
16V
2 X5R
402
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN U6
100-OHM-EMI
C2531
10%
16V
2 X5R
402
VOLTAGE=5V
0.1UF
PLACEMENT NOTE:
A24 ... G19 AND P7 OF SB
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN AD2
ICH VCC3_3 BYPASS

(ICH IO BUFFER 3.3V PWR)
24B5 =PP3V3_S0_SB_VCC3_3
SOT-363
10%
16V
2 X5R
402
PLACEHOLDER
FOR 270UF
20%
2 2.5V
POLY
CASE-C2
PLACEMENT NOTE:
PLACE CAP UNDER SB NEAR PINS V1,
V5, W2, OR W7
BAT54DW
NC
1/16W
MF-LF
402
5%
C2516
330UF
10%
6.3V
2 CERM
402
24D3 65D6
=PP3V3_S5_SB
R2501
1UF
ICH VCCSATAPLL BYPASS

(ICH SATA PLL 1.5V PWR)
10%
2 16V
X5R
402
10
25A8
65C6
65C3 25B6 24B3 24A5
=PP5V_S5_SB
2
65B1
C2518
0.1UF
0
65D3 23D8 23D4 23B7 23A7
ICH VCCSUS3_3 BYPASS

(ICH SUSPEND 3.3V PWR)
ICH CORE/VCC1_05 BYPASS

(ICH CORE 1.05V PWR)
=PPVCORE_S0_SB
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN AG5
VOLTAGE=5V
0.1UF
10%
16V
2 X5R
402
PLACEMENT NOTE:
PLACE CAPS AT EDGE OF SB
5
NC
65B3 22B5
PLACEMENT NOTE:
PLACE C2520 NEAR PIN C1 OF SB
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PINS A1 ... J7
C2512
0.1UF
10%
16V
2 X5R
402
C2525
0.1UF
10%
16V
2 X5R
402
ICH PCI/VCC3_3 BYPASS

(ICH PCI I/O 3.3V PWR)
65B3 24B3
PLACEMENT NOTE:
DISTRIBUTE IN PCI SECTION OF SB
NEAR PINS A5 ... G16
C2526
0.1UF
10%
16V
2 X5R
402
C2527
0.1UF
C2528
0.1UF
10%
16V
2 X5R
402
10%
16V
2 X5R
402
65C6 25C8
SB: 4 OF 4
=PP1V5_S0_SB
L2507
R2500
1
1/10W 5%
MF-LF 603
ICH VCCDMIPLL BYPASS

(ICH DMI PLL 1.5V PWR)
PP1V5_S0_SB_VCCDMIPLL
0.28-OHM
PP1V5_S0_SB_VCCDMIPLL_F
VOLTAGE=1.5V
24B5
VOLTAGE=1.5V
1206
1
C2501
0.01UF
ICH VCCRTC BYPASS

(ICH RTC 3.3V PWR)
PP3V3_S5_SB_RTC
20%
2 6.3V
X5R
603
PLACEMENT NOTE:
PLACE CAPS NEAR PIN W5 OF SB
C2530
0.1UF
10%
16V
2 X5R
402
C2529
0.1UF
10%
16V
2 X5R
402

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7150
SCALE

C2508
10UF
10%
2 16V
CERM
402
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON
SECONDARY SIDE OR 3.56MM ON PRIMARY
26D3 24B3 21D6
A.0.0
OF
25
84
RTC Battery Connector
65B3
PP3V3_G3C_SB_RTC_D
D2600
CRITICAL
J2600
1
6
NC
R2607
1
2
5A2
37D3 22A7
IO
37D3 22A6
IO
SOT-363
=PP3V42_G3H_SB_RTC
65D3
PPVBATT_G3C_RTC
1K
VOLTAGE=3.3V
PPVBATT_G3C_RTC_R
C2610
37C3 22A6
IO
1UF
37C3 22A6
IO
37C3 22A6
IO
10%
6.3V
CERM
402
37D3 22A6
IO
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
NC
NC 2
NC
NC
20K
518S0452
21D6
5%
1/16W
MF-LF
402
NOTE: R2607 and D2600 form the doublefault protection for RTC battery.
37D3 22A6
IO
22A6
IO
22B6
IN
22B6
IN
22B6
IN
R2600
NC
OUT
C2605
1UF
R2606
1M
SB_RTC_RST_L
5%
1/16W
MF-LF
402
21D6
10%
6.3V
CERM
402
22B6 6B7
SB_SM_INTRUDER_L
=PP3V3_S0_SB_PCI
21D6 24B3 25A4
BAT54DW
BM02B-ACHKS-A-GAN-TF-LF
M-RT-SM
3
PP3V3_S5_SB_RTC
MAKE_BASE=TRUE
VOLTAGE=3.3V
OUT
IN
22A7
IO
22A7
IO
22A7
IO
37D3 22A7
IO
22A6
IO
22A6
IO
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
PCI_SERR_L
PCI_DEVSEL_L
PCI_PERR_L
PCI_LOCK_L
R2623
R2624
R2625
R2626
R2627
R2628
R2630
R2629
PCI_REQ0_L
PCI_REQ1_L
PCI_REQ2_L
PCI_REQ3_L
R2632
R2631
R2633
R2634
INT_PIRQA_L
INT_PIRQB_L
INT_PIRQC_L
INT_PIRQD_L
SB_GPIO2
SB_GPIO3
R2637
R2636
R2638
R2639
R2640
R2642
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
Pullup on SB_GPIO4 removed as it now defaults low

for use as DVI_HPD in muxed graphics solution.
Platform Reset Connections

SB RTC Crystal Circuit
C
1
10M
21D6
5%
1/16W
MF-LF
402
ITP
SM-2
5%
50V
CERM
402
3
2
Y2600
32.768K
NC
NC
5%
1/16W
MF-LF
402
CRITICAL
IN
PM_SYSRST_L
MAKE_BASE=TRUE
5%
50V
CERM
402
PLT_RST_L
LIO_PLT_RESET_L
MAKE_BASE=TRUE
LIO represents X loads (2?)
5%
1/16W
MF-LF
402
OUT
NB_RST_IN_L
OMIT
100K
5%
1/16W
MF-LF
402 2
PLTRST_D3COLD_IN_L
Silk: "SYS RST"
Hook to inverter PWM AND gate (except M59)

This RST is used to mask a glitch output from
the NB PWM output during reset.
R2681
MC74VHC1G08
SC70
U2680
37A7
PLT_RST_BUF_L
2
1
3
1
R2680
C2680
100K
0.1UF
5%
1/16W
MF-LF
402
20%
10V
CERM
402
DEBUG_RST_L
R2683
1
TPM_LRESET_L
58B7
ENET_RST_L
39C6
=PP3V3_S0_SB_PM
65A3 26B4
C2607
2
20%
10V
CERM
402
MC74VHC1G00
1.8K
2
R2686 1
5%
1/16W
MF-LF
402
MC74VHC1G08
5
1
SC70
59C7
VR_PWRGD_CK410_L
MAKE_BASE=TRUE
IN
OUT
23C3
PM_SB_PWROK
VR_PWRGOOD_DELAY
IN
ALL_SYS_PWRGD
IN
23C5
TP_GPU_D3COLD_RST_L
GPU_D3COLD_RESET_L
26C1
SC70
CK410_PD_VTT_PWRGD_L
PLTRST_D3COLD_IN_L
PLTRST_D3COLD_L
1
3
1
5%
1/16W
MF-LF
402
PEG_RESET_L
67A5
C2685
20%
10V
CERM
402
=GPU_DDC_ENABLE
79A7
R2688
=GPU_HPD_ENABLE
77B2
GPU_SIGNAL_ENABLE
5%
1/16W
MF-LF
402
100K
0.1UF
2
1K
1
MAKE_BASE=TRUE
R2622
10K
R2689
MC74VHC1G08
U2685
1
MAKE_BASE=TRUE
10K
5%
1/16W
MF-LF
402
64B1
49D7
R2687
1
5%
1/16W
MF-LF
402
U2601
2
R2612 1
59C7
14B6
D3Cold Reset for GPU
10K
5%
1/16W
MF-LF
402
U2603
Initial resistor values are based on CRB,

but may change after characterization.
R2611
SC70-5
=PP3V3_S0_RSTBUF
0.1UF
OUT 23C5 VR_PWRGD_CK410
49C7
5%
1/16W
MF-LF
402
0.1UF
20%
10V
CERM
402
SMC_LRESET_L
R2682
=PP3V3_S0_SB_PM
C2611
33A4
OUT
100
5%
1/16W
MF-LF
402
R2684
1
5C2 51B4
Linda Card represents 3 loads
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
65B3 26B8
26A4
INVERTER_PLT_RST_L
=PP3V3_S0_RSTBUF
65A3 26B4
65B3 26B6
14B7
100-ohm on NB page
Buffered
5C1 47C6
MAKE_BASE=TRUE
R2698 1
This part is never stuffed,

it provides a set of pads
on the board to short or
to solder a reset button.
IN
2
5%
1/16W
MF-LF
402
12pF
79A4 22A6
1K
XDP_DBRESET_L
C2609
1
SB_RTC_X2
M59_INVERTER_PLT_RST_L 6C5
On M59 this RST is used for layout reasons
R2685
10K
R2696
5%
1/16W
MF-LF
402
R2609 1
SB_RTC_X1_R
Unbuffered
R2697 1
12pF
SB_RTC_X1
=PP3V3_S5_SB_PM
C2608
R2610
21D6
65D3 23D1 11B5
5%
1/16W
MF-LF
402
C2689
0.001UF
1G00 used as small & cheap inverter
10%
50V
CERM
402
SB Misc
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7164
A.0.0
OF
26
84
ICH7-M SMBus Connections

65B3
23D5
SMB_CLK
23D5
SMB_DATA
65B3
R2700 1
U2100
(MASTER)
SMC "0" SMBus Connections
=PP3V3_S0_SMBUS_SB
ICH7-M
R2701
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SMBUS_SB_SCL
SMC
SLGLP436: U3301
(Write: 0xD2 Read: 0xD3)
U5800
(MASTER)
SMB_CK410_CLK
33B6
49C7
SMB_0_S0_CLK
SMB_CK410_DATA
33B6
49C5
SMB_0_S0_DATA
SMC "B" SMBus Connections
=PP3V3_S0_SMBUS_SMC_0_S0
65B3
R2750 1
Clock Chip
R2751
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
GPU Temp
SMC
TMP401: U6150
(Write: 0x98 Read: 0x99)
U5800
(MASTER)
=SMBUS_GPU_TDIODE_SCL
52B3
49B5
SMB_B_S0_CLK
=SMBUS_GPU_TDIODE_SDA
52B3
49B5
SMB_B_S0_DATA
=PP3V3_S0_SMBUS_SMC_B_S0
R2760 1
R2761
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
CPU Temp
TMP401: U1001
SMB_THRM_CLK
10B3
SMB_THRM_DATA
10B3
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
4.7K
SMBUS_SMC_B_S0_SCL
MAKE_BASE=TRUE
SMBUS_SB_SDA
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SO-DIMM "A"
Remote Temps
J2800
(Write: 0xA0 Read: 0xA1)
MAX6695: U6100
Left I/O Board
Left I/O SMBus Connections:
J5400
(See Table)
LIO - TMP106
28A6
=SMBUS_REMTHMSNS_SCL
52C2
M35B - TMP106
=I2C_SODIMMA_SDA
28A6
=SMBUS_REMTHMSNS_SDA
52C2
SO-DIMM "B"
SMC "A" SMBus Connections
J2900
(Write: 0xA4 Read: 0xA5)
=I2C_SODIMMB_SCL
29A6
=I2C_SODIMMB_SDA
29A6
=PP3V3_S3_SMBUS_SMC_A_S3
65D3
R2770 1
SMC
Trackpad
Trackpad I2C Connections:
J4900
(See Table)
U1 - Trackpad Controller
49B5
SMB_A_S3_CLK
49B5
SMB_A_S3_DATA
5%
1/16W
MF-LF
402 2
R2771
5%
1/16W
MF-LF
2 402
78C2
=I2C_TRACKPAD_SDA
78C2
SMBUS_SMC_A_S3_SCL
49B5
Left I/O Board

J5500
(See Table)
ExpressCard Slot
(Address determined by ARP)
SMB_BSA_CLK
5B1 47C3
=SMBUS_LIO_SB_SDA
5B1 47C3
R2781
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
Battery
J8250
SMBUS_SMC_BSA_SCL
49B5
SMB_BSA_DATA
SMBUS_SMC_BSA_SDA
=SMBUS_BATT_SCL
5D1 66B5
=SMBUS_BATT_SDA
5D1 66B5
MAKE_BASE=TRUE
Top-Case
J4900
(See Table)
Palm Rest Temp - TMP275
SMC "Battery B" SMBus Connections

=SMBUS_TOPCASE_SCL
78C2
=SMBUS_TOPCASE_SDA
78C2
65B3
=SMBUS_LIO_SB_SCL
4.7K
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
Top-Case SMBus Connections:

Left I/O SMBus Connections:
R2780 1
U5800
(MASTER)
MAKE_BASE=TRUE
=I2C_TRACKPAD_SCL
5B1
47C3
=PP3V42_G3H_SMBUS_SMC_BSA
SMC
4.7K
MAKE_BASE=TRUE
U2 - Keyboard Controller
4.7K
U5800
(MASTER)
5B1
47C3
=SMBUS_LIO_SMC_SDA
SMC "Battery A" SMBus Connections
NOTE: SMC RMT bus remains powered and may be active in S3 state
65C3
=SMBUS_LIO_SMC_SCL
=PP3V3_S0_SMBUS_SMC_BSB
R2790
SMC
49C5
SMB_BSB_CLK
49C7
SMB_BSB_DATA
100K
U5800
(MASTER)
R2791
100K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
SMBUS_SMC_BSB_SCL
MAKE_BASE=TRUE
SMBUS_SMC_BSB_SDA
MAKE_BASE=TRUE
=I2C_SODIMMA_SCL
M1 SMBus Connections
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
27
84
Page Notes
32B3 29D6
C2801
C2800
2.2uF
20%
6.3V
CERM1
603
Signal aliases required by this page:

- =I2C_SODIMMA_SCL
- =I2C_SODIMMA_SDA
0.1uF
2
5A
MEM_A_DQ<14>
15C7 MEM_A_DQ<13>
15C7
20%
10V
CERM
402
7A
9A
15C5
15C5
11A
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
13A
15A
BOM options provided by this page:

(NONE)
15C7
15C7
17A
MEM_A_DQ<10>
MEM_A_DQ<11>
19A
21A
NOTE: This page does not supply VREF.

The reference voltage must be provided
by another page.
23A
MEM_A_DQ<5>
15D7 MEM_A_DQ<4>
15D7
25A
27A
29A
MEM_A_DQS_N<0>
15C5 MEM_A_DQS_P<0>
15C5
31A
33A
35A
MEM_A_DQ<6>
15D7 MEM_A_DQ<7>
15D7
37A
39A
41A
43A
MEM_A_DQ<19>
15C7 MEM_A_DQ<18>
15C7
45A
47A
49A
MEM_A_DQS_N<2>
15C5 MEM_A_DQS_P<2>
15C5
51A
53A
15C7
15C7
55A
MEM_A_DQ<20>
MEM_A_DQ<16>
57A
59A
61A
MEM_A_DQ<28>
15C7 MEM_A_DQ<25>
15C7
63A
65A
67A
15C5 MEM_A_DM<3>
NC
69A
71A
15C7
"Expansion" (surface-mount) slot
15C7
73A
MEM_A_DQ<27>
MEM_A_DQ<30>
75A
77A
30D6 14C4
79A
MEM_CKE<0>
81A
NC
30B6 15D5
83A
85A
MEM_A_BS<2>
87A
89A
MEM_A_A<12>
15B5 MEM_A_A<9>
15B5 MEM_A_A<8>
30C6 15B5
30C6
30C6
91A
93A
95A
97A
MEM_A_A<5>
MEM_A_A<3>
15C5 MEM_A_A<1>
30C6 15B5
99A
30C6 15B5
30C6
101A
103A
105A
MEM_A_A<10>
15D5 MEM_A_BS<0>
15B5 MEM_A_WE_L
30C6 15B5
30B6
30B6
107A
109A
111A
113A
MEM_A_CAS_L
14C4 MEM_CS_L<1>
30B6 15D5
30D6
115A
117A
30C6 14C4
119A
MEM_ODT<1>
121A
15B7
15B7
123A
MEM_A_DQ<35>
MEM_A_DQ<39>
125A
127A
MEM_A_DQS_N<4>
15C5 MEM_A_DQS_P<4>
129A
MEM_A_DQ<37>
15C7 MEM_A_DQ<33>
135A
15C5
131A
133A
15B7
137A
139A
141A
MEM_A_DQ<60>
15B7 MEM_A_DQ<59>
15A7
143A
145A
15C5
147A
MEM_A_DM<7>
149A
15B7
15A7
151A
MEM_A_DQ<58>
MEM_A_DQ<61>
153A
155A
15B7
15B7
157A
MEM_A_DQ<43>
MEM_A_DQ<45>
159A
161A
NC
163A
165A
167A
MEM_A_DQS_N<5>
15C5 MEM_A_DQS_P<5>
15C5
169A
171A
173A
15B7 MEM_A_DQ<41>
15B7 MEM_A_DQ<46>
175A
177A
179A
MEM_A_DQ<51>
15B7 MEM_A_DQ<50>
15B7
181A
183A
15C5
185A
MEM_A_DM<6>
187A
189A
MEM_A_DQ<53>
15B7 MEM_A_DQ<48>
29A3 =PPSPD_S0_MEM
27D6 =I2C_SODIMMA_SDA
27D6 =I2C_SODIMMA_SCL
15B7
65A3 29A6
191A
193A
195A
197A
199A
VREF
VSS1
CRITICAL
DQ1
VSS4
VSS0
DQ4
J2800
DQ0
DQ5
F-RT-SM-M9
DQS0*
DQS0
VSS6
DQ2
DQ3
VSS8
=PP1V8_S3_MEM
NC
201
1A
MEM_VREF
3A
Power aliases required by this page:

- =PP1V8_S3_MEM
- =PPSPD_S0_MEM (2.5V - 3.3V)
203
=PP1V8_S3_MEM
VSS2
DM0
VSS5
DQ6
DQ7
VSS7
DQ12
DQ13
DQ8
DQ9
VSS9
DM1
VSS10
VSS11
DQS1*
DQS1
CK0
CK0*
VSS12
VSS13
DQ10
DQ11
DQ14
DQ15
VSS14
VSS15
KEY
VSS16
DQ16
VSS17
DQ20
DQ17
DQ21
VSS18
DQS2*
VSS19
NC0
DQS2
DM2
VSS21
DQ18
VSS22
DQ22
DQ19
VSS23
DQ23
VSS24
DQ24
DQ28
DQ25
VSS25
DQ29
VSS26
DM3
DQS3*
NC1
VSS27
DQS3
VSS28
DQ26
DQ30
DQ31
VSS30
DQ27
VSS29
CKE0
VDD0
NC/CKE1
VDD1
NC2
NC/A15
BA2
VDD2
NC/A14
VDD3
A12
A11
A9
A8
A7
A6
VDD4
VDD5
A5
A3
A4
A2
A1
VDD6
A0
VDD7
A10/AP
BA1
BA0
WE*
RAS*
S0*
VDD8
VDD9
CAS*
NC/S1*
ODT0
NC/A13
VDD10
VDD11
NC/ODT1
VSS31
NC3
VSS32
DQ32
DQ33
DQ36
DQ37
VSS33
VSS34
DQS4*
DQS4
DM4
VSS35
VSS36
DQ38
DQ34
DQ35
DQ39
VSS37
VSS38
DQ44
DQ40
DQ41
DQ45
VSS39
VSS40
DM5
DQS5*
DQS5
VSS41
VSS42
DQ42
DQ43
DQ46
DQ47
VSS43
VSS44
DQ48
DQ49
DQ52
DQ53
VSS45
VSS46
NC_TEST
VSS47
CK1
CK1*
DQS6*
DQS6
VSS48
DM6
VSS49
VSS50
DQ50
DQ51
DQ54
DQ55
VSS51
VSS52
DQ56
DQ57
DQ60
DQ61
VSS53
VSS54
DM7
VSS55
DQS7*
DQS7
DQ58
DQ59
VSS56
DQ62
VSS57
DQ63
SDA
SCL
VSS58
SA0
VDDSPD
SA1
65B6 29D6 29D3 29B2 28D3 28B2
2A
4A
MEM_A_DQ<8>
MEM_A_DQ<12>
6A
15C7
15C7
8A
10A
MEM_A_DM<1>
15D5
12A
14A
MEM_A_DQ<15>
MEM_A_DQ<9>
16A
15C7
15C7
18A
20A
MEM_A_DQ<2>
MEM_A_DQ<3>
22A
15D7
15D7
24A
26A
MEM_A_DM<0>
15D5
28A
30A
MEM_CLK_P<0>
MEM_CLK_N<0>
32A
14D4
14D4
34A
36A
MEM_A_DQ<1>
MEM_A_DQ<0>
38A
15D7
15D7
40A
42A
44A
MEM_A_DQ<23>
MEM_A_DQ<22>
46A
15C7
15C7
48A
50A
DIMM_OVERTEMP_L
MEM_A_DM<2>
52A
29C3 50D3
15D5
54A
56A
MEM_A_DQ<21>
MEM_A_DQ<17>
58A
15C7
15C7
60A
62A
MEM_A_DQ<29>
MEM_A_DQ<24>
64A
15C7
15C7
66A
68A
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
70A
15C5
15C5
72A
74A
76A
MEM_A_DQ<26>
MEM_A_DQ<31>
15C7
MEM_CKE<1>
14C4 30D6
15C7
78A
80A
82A
84A
MEM_A_A<15>
MEM_A_A<14>
86A
6D6
6D6
88A
90A
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<6>
92A
94A
DDR2 Bypass Caps
15B5 30C6
15B5 30C6
(For return current)
15B5 30C6
96A
65B6 29D6 29D3 29B2 28D6 28D3
98A
MEM_A_A<4>
MEM_A_A<2>
MEM_A_A<0>
100A
102A
=PP1V8_S3_MEM
15B5 30C6
15C5 30C6
15C5 30C6
204
C2808
C2809
104A
10UF
106A
20%
6.3V
X5R
603
20%
6.3V
X5R
603
C2810
C2811
MEM_A_BS<1>
MEM_A_RAS_L
MEM_CS_L<0>
108A
110A
15D5 30B6
15B5 30B6
10UF
14C4 30D6
112A
114A
MEM_ODT<0>
MEM_A_A<13>
116A
14C4 30C6
15B5 30C6
1UF
1UF
1UF
120A
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C2814
C2815
NC
122A
124A
MEM_A_DQ<38>
MEM_A_DQ<34>
126A
C2812
118A
C2813
1UF
10%
6.3V
CERM
402
C2817
15B7
15B7
128A
130A
MEM_A_DM<4>
15C5
134A
MEM_A_DQ<32>
MEM_A_DQ<36>
136A
C2816
1UF
1UF
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C2818
C2819
C2821
132A
15C7
15B7
138A
140A
MEM_A_DQ<57>
MEM_A_DQ<63>
142A
15B7
15A7
144A
146A
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
148A
15C5
15C5
C2820
1UF
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
1UF
2
10%
6.3V
CERM
402
150A
152A
MEM_A_DQ<56>
MEM_A_DQ<62>
154A
15B7
15A7
156A
158A
MEM_A_DQ<40>
MEM_A_DQ<42>
160A
15B7
15B7
162A
164A
MEM_CLK_P<1>
MEM_CLK_N<1>
166A
14D4
14D4
168A
170A
MEM_A_DM<5>
15C5
172A
174A
MEM_A_DQ<47>
MEM_A_DQ<44>
176A
DDR2 SO-DIMM Connector A
15B7
15B7
178A
180A
MEM_A_DQ<54>
MEM_A_DQ<55>
182A
15B7
15B7
184A
186A
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
188A
SYNC_DATE=(MASTER)

15C5
15C5
190A
192A
MEM_A_DQ<52>
MEM_A_DQ<49>
194A
15B7
15B7
SIZE
196A
198A
200A
APPLE COMPUTER INC.
ADDR=0xA0(WR)/0xA1(RD)
DRAWING NUMBER
NC
SHT
NONE
REV.
051-7150
SCALE
202
516S0471
28B2 28D6 29B2 29D3 29D6 65B6
DDR2-SODIMM-DUAL
A.0.0
OF
28
84
Page Notes
32B3 28D6
201
MEM_VREF
1B
3B

- =PP1V8_S3_MEM
- =PPSPD_S0_MEM (2.5V - 3.3V)
C2901
C2900
2.2uF
20%
6.3V
CERM1
603

- =I2C_SODIMMB_SCL
- =I2C_SODIMMB_SDA
MEM_B_DQ<15>
15C4 MEM_B_DQ<14>
0.1uF
2
5B
15C4
20%
10V
CERM
402
7B
9B
15C2
15C2
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
11B
13B
15B

(NONE)
=PP1V8_S3_MEM
15C4
15C4
MEM_B_DQ<10>
MEM_B_DQ<13>
17B
19B
21B
NOTE: This page does not supply VREF.

The reference voltage must be provided
by another page.
MEM_B_DQ<7>
15D4 MEM_B_DQ<2>
23B
15D4
25B
27B
MEM_B_DQS_N<0>
15C2 MEM_B_DQS_P<0>
29B
15C2
31B
33B
15D4
15D4
MEM_B_DQ<1>
MEM_B_DQ<4>
35B
37B
39B
41B
MEM_B_DQ<21>
15C4 MEM_B_DQ<19>
43B
15C4
45B
47B
49B
MEM_B_DQS_N<2>
15C2 MEM_B_DQS_P<2>
15C2
51B
53B
55B
MEM_B_DQ<20>
15C4 MEM_B_DQ<23>
15C4
57B
59B
61B
MEM_B_DQ<29>
15C4 MEM_B_DQ<24>
15C4
63B
65B
15C2 MEM_B_DM<3>
67B
NC
69B
71B
15C4
"Factory" (thru-hole) slot
15C4
MEM_B_DQ<27>
MEM_B_DQ<25>
73B
75B
77B
30D6 14C4
MEM_CKE<2>
79B
81B
NC
30A6 15D2
MEM_B_BS<2>
83B
85B
87B
MEM_B_A<12>
15B2 MEM_B_A<9>
15B2 MEM_B_A<8>
89B
30B6 15B2
30B6
30B6
91B
93B
95B
MEM_B_A<5>
MEM_B_A<3>
15C2 MEM_B_A<1>
97B
30B6 15B2
99B
30B6 15B2
30B6
101B
103B
105B
MEM_B_A<10>
15D2 MEM_B_BS<0>
15B2 MEM_B_WE_L
30B6 15B2
30A6
30A6
107B
109B
111B
MEM_B_CAS_L
14C4 MEM_CS_L<3>
113B
30A6 15D2
30D6
115B
117B
30C6 14C4
MEM_ODT<3>
119B
121B
15B4 MEM_B_DQ<36>
15C4 MEM_B_DQ<33>
123B
125B
127B
MEM_B_DQS_N<4>
15C2 MEM_B_DQS_P<4>
129B
15C2
131B
133B
MEM_B_DQ<34>
15B4 MEM_B_DQ<35>
135B
15B4
137B
139B
MEM_B_DQ<40>
15B4 MEM_B_DQ<41>
141B
15B4
143B
145B
15C2
MEM_B_DM<5>
147B
149B
15B4
15B4
MEM_B_DQ<42>
MEM_B_DQ<43>
151B
153B
155B
15A4
15B4
MEM_B_DQ<62>
MEM_B_DQ<59>
157B
159B
161B
NC
163B
165B
MEM_B_DQS_N<7>
15C2 MEM_B_DQS_P<7>
167B
15C2
169B
171B
MEM_B_DQ<60>
15A4 MEM_B_DQ<61>
173B
15A4
175B
177B
MEM_B_DQ<54>
15B4 MEM_B_DQ<51>
179B
15B4
181B
183B
15C2
MEM_B_DM<6>
185B
187B
MEM_B_DQ<52>
15B4 MEM_B_DQ<49>
28A6 =PPSPD_S0_MEM
27C6 =I2C_SODIMMB_SDA
27C6 =I2C_SODIMMB_SCL
189B
15B4
65A3 29A3
191B
193B
195B
197B
199B
VREF
VSS1
DQ0
CRITICAL
J2900
DQ1
VSS4
DQS0*
DQS0
VSS6
DQ2
DQ3
VSS8
F-RT-TH1
DQ5
VSS2
DM0
DQ6
DQ7
VSS7
DQ12
DQ13
VSS9
DM1
VSS10
VSS11
DQS1*
DQS1
CK0
CK0*
VSS12
VSS13
DQ10
DQ11
DQ14
DQ15
VSS14
VSS15
KEY
VSS16
DQ16
VSS17
DQ20
DQ17
DQ21
VSS18
DQS2*
VSS19
NC0
DQS2
DM2
VSS21
DQ18
VSS22
DQ22
DQ19
VSS23
DQ23
VSS24
DQ24
DQ28
DQ25
VSS25
DQ29
VSS26
DM3
DQS3*
NC1
VSS27
DQS3
VSS28
DQ26
DQ30
DQ27
VSS29
CKE0
VDD0
DQ31
VSS30
NC/CKE1
VDD1
NC2
NC/A15
BA2
VDD2
NC/A14
VDD3
A12
A11
A9
A8
A7
A6
VDD4
VDD5
A5
A3
A4
A2
A1
VDD6
A0
VDD7
A10/AP
BA1
BA0
WE*
RAS*
S0*
VDD8
VDD9
CAS*
NC/S1*
ODT0
NC/A13
VDD10
VDD11
NC/ODT1
VSS31
NC3
VSS32
DQ32
DQ33
DQ36
DQ37
VSS33
VSS34
DQS4*
DQS4
DM4
VSS35
VSS36
DQ38
DQ34
DQ35
DQ39
VSS37
VSS38
DQ44
DQ40
DQ41
DQ45
VSS39
VSS40
DM5
DQS5*
DQS5
VSS41
VSS42
DQ42
DQ43
DQ46
DQ47
VSS43
VSS44
DQ48
DQ49
DQ52
DQ53
VSS45
VSS46
NC_TEST
VSS47
CK1
CK1*
DQS6*
DQS6
VSS48
DM6
VSS49
VSS50
DQ50
DQ51
DQ54
DQ55
VSS51
VSS52
DQ56
DQ57
DQ60
DQ61
VSS53
VSS54
DM7
VSS55
DQS7*
DQS7
DQ58
DQ59
VSS56
DQ62
VSS57
DQ63
SDA
SCL
VSS58
SA0
VDDSPD
SA1
202
VSS0
DQ4
VSS5
DQ8
DQ9
516-0140
=PP1V8_S3_MEM
NC
65B6 29D3 29B2 28D6 28D3 28B2
28B2 28D3 28D6 29B2 29D6 65B6
2B
4B
MEM_B_DQ<9>
MEM_B_DQ<11>
6B
15C4
15C4
8B
10B
MEM_B_DM<1>
15D2
MEM_B_DQ<12>
MEM_B_DQ<8>
15C4
12B
14B
16B
15C4
18B
MEM_B_DQ<3>
MEM_B_DQ<6>
20B
22B
15D4
15D4
24B
26B
MEM_B_DM<0>
15D2
MEM_CLK_P<3>
MEM_CLK_N<3>
14D4
28B
30B
32B
14D4
34B
MEM_B_DQ<0>
MEM_B_DQ<5>
36B
38B
15D4
15D4
40B
42B
MEM_B_DQ<22>
MEM_B_DQ<18>
44B
46B
15C4
15C4
48B
50B
DIMM_OVERTEMP_L
MEM_B_DM<2>
52B
DDR2-SODIMM-DUAL
28C3 50D3
15D2
54B
56B
MEM_B_DQ<17>
MEM_B_DQ<16>
58B
15C4
15C4
60B
62B
MEM_B_DQ<26>
MEM_B_DQ<28>
64B
15C4
15C4
66B
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
68B
70B
15C2
15C2
72B
MEM_B_DQ<31>
MEM_B_DQ<30>
74B
76B
15C4
15C4
78B
MEM_CKE<3>
80B
14C4 30D6
82B
84B
MEM_B_A<15>
MEM_B_A<14>
86B
6D6
6D6
88B
MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<6>
90B
92B
94B
DDR2 Bypass Caps
15B2 30B6
15B2 30B6
(For return current)
15B2 30B6
96B
65B6 29D6 29D3 28D6 28D3 28B2
MEM_B_A<4>
MEM_B_A<2>
MEM_B_A<0>
98B
100B
102B
=PP1V8_S3_MEM
15B2 30B6
15C2 30B6
15C2 30B6
C2908
10UF
104B
106B
MEM_B_BS<1>
MEM_B_RAS_L
MEM_CS_L<2>
108B
110B
15D2 30A6
15B2 30A6
C2909
10UF
20%
20%
6.3V
X5R
603
C2910
6.3V
X5R
603
14C4 30D6
112B
MEM_ODT<2>
MEM_B_A<13>
114B
116B
14C4 30C6
15B2 30B6
118B
120B
NC
122B
MEM_B_DQ<32>
MEM_B_DQ<37>
124B
126B
C2911
0.1uF
1UF
10%
20%
10%
6.3V
CERM
402
C2914
10V
CERM
402
C2915
C2912
1UF
C2913
1UF
10%
6.3V
CERM
402
6.3V
CERM
402
15C4
15B4
128B
MEM_B_DM<4>
130B
15C2
132B
MEM_B_DQ<38>
MEM_B_DQ<39>
134B
136B
2
15B4
C2916
C2917
1UF
1UF
1UF
0.1uF
10%
10%
10%
20%
6.3V
CERM
402
C2918
6.3V
CERM
402
C2919
6.3V
CERM
402
10V
CERM
402
15B4
138B
MEM_B_DQ<44>
MEM_B_DQ<45>
140B
142B
15B4
15B4
144B
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
146B
148B
0.1uF
0.1uF
20%
20%
20%
10V
2 CERM
15C2
10V
2 CERM
402
15C2
C2920
0.1uF
402
C2921
0.1uF
20%
10V
2 CERM
402
10V
CERM
402
150B
MEM_B_DQ<46>
MEM_B_DQ<47>
152B
154B
15B4
15B4
156B
MEM_B_DQ<58>
MEM_B_DQ<63>
158B
160B
15B4
15A4
162B
MEM_CLK_P<2>
MEM_CLK_N<2>
164B
166B
14D4
14D4
168B
MEM_B_DM<7>
170B
15C2
172B
MEM_B_DQ<56>
MEM_B_DQ<57>
174B
176B
DDR2 SO-DIMM Connector B
15B4
15B4
178B
MEM_B_DQ<55>
MEM_B_DQ<50>
180B
182B
15B4
15B4
184B
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
186B
188B
15C2
=PPSPD_S0_MEM

28A6 29A6 65A3
15C2
190B
1
MEM_B_DQ<53>
MEM_B_DQ<48>
192B
194B
196B
15B4
198B
R2900
10K
15B4
Resistor prevents pwr-gnd short

2
5%
1/16W
MF-LF
402
SIZE
APPLE COMPUTER INC.
SODIMM_A_SA1
200B
DRAWING NUMBER
SHT
NONE
REV.
051-7150
SCALE
ADDR=0xA4(WR)/0xA5(RD)
NC
SYNC_DATE=(MASTER)
A.0.0
OF
29
84
One cap for each side of every RPAK, one cap for every two discrete resistors
Ensure CS_L and ODT resistors are close to SO-DIMM connector
IN
MEM_CS_L<3..0>
R3000
R3001
R3002
R3003
1
2
3
29C6 29C3 28C6 28C3 14C4
IN
MEM_CKE<3..0>
RP3032
RP3032
RP3058
RP3058
0
1
2
3
29B6 29B3 28B6 28B3 14C4
IN
MEM_ODT<3..0>
R3010
R3011
R3012
R3013
0
1
2
3
28C6 28C3 28B6 28B3 15C5 15B5
IN
MEM_A_A<13..0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
RP3034
RP3010
RP3034
RP3034
RP3034
RP3030
RP3032
RP3030
RP3032
RP3030
RP3036
RP3030
RP3005
RP3036
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
=PP0V9_S0_MEM_TERM
1
4
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
SM-LF
5%
1/16W
SM-LF
1/16W
SM-LF
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
IN
MEM_A_BS<2..0>
RP3036
RP3036
RP3005
0
1
2
56
56
56
5%
1/16W
5%
1/16W
SM-LF
5%
1/16W
SM-LF
IN
28B6 15D5
IN
28B6 15B5
IN
RP3010
RP3010
RP3010
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
56
56
56
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
29C6 29C3 29B6 29B3 15C2 15B2
IN
MEM_B_A<13..0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
RP3005
RP3050
RP3050
RP3052
RP3054
RP3052
RP3054
RP3054
RP3058
RP3058
RP3050
RP3056
RP3056
RP3052
56
56
56
56
56
56
56
56
56
56
56
56
56
56
2
1
3
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
IN
MEM_B_BS<2..0>
RP3056
RP3005
RP3056
0
1
2
56
56
56
IN
29B6 15D2
IN
29B6 15B2
IN
RP3050
RP3054
RP3052
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
56
56
56
20%
10V
CERM
402
C3032
20%
10V
CERM
402
C3034
20%
10V
CERM
402
C3036
20%
10V
CERM
402
C3038
20%
10V
CERM
402
C3050
20%
10V
CERM
402
C3052
20%
10V
CERM
402
20%
10V
CERM
402
C3011
20%
10V
CERM
402
C3031
0.1uF
20%
10V
CERM
402
C3033
0.1uF
2
20%
10V
CERM
402
C3035
0.1uF
20%
10V
CERM
402
C3037
0.1uF
20%
10V
CERM
402
C3039
0.1uF
20%
10V
CERM
402
C3051
0.1uF
2
20%
10V
CERM
402
C3053
0.1uF
20%
10V
CERM
402
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
C3054
0.1uF
20%
10V
CERM
402
C3056
SM-LF
20%
10V
CERM
402
C3055
0.1uF
0.1uF
2
29B3 15B2
C3030
C3007
0.1uF
2
0.1uF
29C6 29B6 29B3 15D2
0.1uF
2
5%
20%
10V
CERM
402
0.1uF
5%
C3010
20%
10V
CERM
402
0.1uF
2
0.1uF
0.1uF
SM-LF
5%
20%
10V
CERM
402
0.1uF
28B3 15B5
C3005
C3002
0.1uF
0.1uF
28C6 28B6 28B3 15D5
0.1uF
5%
20%
10V
CERM
402
0.1uF
5%
SM-LF
SM-LF
402
1/16W
C3000
0.1uF
5%
65D6
29B6 29B3 28B6 28B3 14C4
20%
10V
CERM
402
C3057
0.1uF
20%
10V
CERM
402
Memory Active Termination

5%
1/16W
SM-LF
5%
1/16W
SM-LF
5%
1/16W
SM-LF
C3058
C3059
0.1uF
0.1uF
20%
10V
CERM
402
20%
10V
CERM
402
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
30
84
8
Page Notes

- =PP5V_S0_MEMVTT
- =PP1V8_S0_MEMVTT
- =PP0V9_S0_MEMVTT_LDO
(NONE)
(NONE)
65A1
DDR2 Vtt Regulator
=PP5V_S0_MEMVTT
C3104
4.7UF
65B6
=PP1V8_S0_MEMVTT
C3101
20%
6.3V
CERM
603
10UF
If power inputs are not S0,

MEMVTT_EN can be used to
disable MEMVTT in sleep.
1 VDDQSNS MSOP
=PP0V9_S0_MEMVTT_LDO
65D8
VTT 3
CRITICAL
7 S3
VTTSNS 5
9 S5
THRML PGND
PAD
VTTREF 6 MEMVTT_VREF
GND
8
MEMVTT_EN
VIN
TPS51100
1K
VLDOIN
U3100
R31001
5%
1/16W
MF-LF
402
10
MEMVTT_EN_PU
11
20%
6.3V
X5R
603
1
1
C3102
0.1UF
Okay to turn off 5V and

leave 1.8V powered in S3.
20%
25V
X5R
402
C3105
22UF
20%
6.3V
2 X5R
805
C3106
22UF
20%
6.3V
2 X5R
805
Memory Vtt Supply
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
31
84
65C3
=PP3V3_S3_MEMVREF
MEMVREF_S3
C3200
R3202 1
0.1UF
20%
10V
CERM
402
65B6
100K
5%
1/16W
MF-LF
402
=PP1V8_S3_MEMVREF
R3205
U3200
10K
1%
1/16W
MF-LF
402 2
V+
MEMVREF_UNBUF
R3206 1
10K
1%
1/16W
MF-LF
402 2
CRITICAL
VOLTAGE=0.9V
MAX4236EUTT
SOT23-6-LF
1
5
V2
C3205
MEMVREF_OUT
28D6 29D6
14C2
14C2
MEMVREF_S0
R3203
220pF
5%
25V
CERM
402
MEM_VREF
MEM_VREF_NB_0
MEM_VREF_NB_1
VOLTAGE=0.9V
MAKE_BASE=TRUE
MEMVREF_SHDN_L
64C6 2
=MEMVREF_EN
IN
5%
1/16W
MF-LF
402
DDR2 VRef
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
32
84
L3302
FERR-120-OHM-1.5A
PP3V3_S0_CK410_VDD48_PCI
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm
=PP3V3_S0_CK410
33C7 33D8 34A8 65B3
0402-LF
1
C3308 1 C3309
0.1UF
10UF
10%
1UF
20%
2 6.3V
X5R
603
2 16V
X5R
402
C3310
10%
2 6.3V
CERM
402
D
L3301
65B3 34A8 33D3 33C7
FERR-120-OHM-1.5A
1
2
PP3V3_S0_CK410_VDD_CPU_SRC_A
=PP3V3_S0_CK410
VOLTAGE=3.3V
0402-LF
1
C3314
1UF
10%
6.3V
2 CERM
402
10UF
20%
2 6.3V
X5R
603
0.1UF
10%
2 16V
X5R
402
0.1UF
10%
16V
2 X5R
402
0.1UF
10%
2 16V
X5R
402
0.1UF
0.1UF
10%
16V
402
10%
2 16V
X5R
2 X5R
0.1UF
10%
16V
2 X5R
402
10%
2 16V
X5R
402
C3305 1 C3306 1 C3317

0.1UF
C3316 1 C3315 1 C3301 1 C3302 1 C3303 1 C3304
402
10UF
20%
2 6.3V
X5R
603
VOLTAGE=3.3V
C3312 C3311
1
10UF
20%
2 6.3V
X5R
603
0.1UF
5%
1/16W
MF-LF
402
C3307
0.1UF
10%
R3303
PP3V3_S0_CK410_VDD_REF
10%
2 16V
X5R
2 16V
X5R
402
402
C3389
12PF
5%
2 50V
CERM
402
C3390
35
17
28
U3301
CK410_XTAL_IN
CK410_XTAL_OUT
=PP3V3_S0_CK410
34B8
IN
SLG8LP436
R3301
(FW PCI 33MHZ) 34D8

10K
5%
(TPM LPC 33MHZ)
1/16W
MF-LF
(SMC LPC 33MHZ)
2402
34D8
(NO USED)
34A8 CK410_PCI5_FCTSEL1
IO
(PORT80 LPC 33MHZ)
(ICH7M PCI 33MHZ)
OUT
OUT
OUT
OUT
OUT
CK410_PCI1_CLK
CK410_PCI2_CLK
CK410_PCI3_CLK
CK410_PCI4_CLK
(INT PD)
CPU_STOP*
QFN
OMIT
51 XTAL_IN
50 XTAL_OUT
CK410_FSB_TEST_MODE
CK410_PCIF0_CLK
12
PCI_STOP*
402
5A7
OUT
49
5%
VDD_A
39 VSS_A
34D8
12PF
2 50V
CERM
38
65B3 34A8 33D8 33D3
(EACH POWER PIN PLACED ONE 0.1UF)

(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)
VDD_SRC
VDD_REF
61
VDD_PCI 67
VDD_48
5X3.2-SM
VDD_CPU
Y3301
14.31818
43
CRITICAL
CPU_0*
CPU_0
CRITICAL
44
45
CK410_CPU1_N
34D5 CK410_CPU1_P
OUT
CPU_ITP/SRC_11*
36
CPU_ITP/SRC_11
37
SRC_0/LCD_CLK*
SRC_0/LCD_CLK
11
10
SRC_1*
14
SRC_1
(INT PU) CLKREQ_1*
13
9
SRC_2*
SRC_2
16
34C5
15
34C5
SRC_3*
19
18
8 FS_B_TEST_MODE
64 PCI_4
65 PCI_5/FCT_SEL_1
IN
OUT
34D5
42
IN
CK410_CPU0_N
34D5 CK410_CPU0_P
41
57 PCI_1
58 PCI_2
63 PCI_3
PM_STPPCI_L
23C8 PM_STPCPU_L
23C8
34D5
CPU_1*
CPU_1
68 PCIF_0/ITP_EN
1 PCIF_1
CK410_PCIF1_CLK
56 (INT PU)
55 (INT PU)
CK410_CPU2_ITP_SRC10_N
34D5 CK410_CPU2_ITP_SRC10_P
34D5
CK410_LVDS_N
34B5 CK410_LVDS_P
34B5
CK410_SRC1_N
34B5 CK410_SRC1_P
34A4 CK410_SRC_CLKREQ1_L
34B5
CK410_SRC2_N
CK410_SRC2_P
OUT
OUT
(FROM ICH7 GPIO18 STPPCI* )

(FROM ICH7 GPIO20 STPCPU* )
(CPU HOST 133/167MHZ)
(GMCH HOST 133/167MHZ)
OUT
OUT
(ITP HOST 133/167MHZ)
OUT
OUT
OUT
(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)

(GPU PCI-E 100 MHZ )
OUT
IN
NEED TO DECIDE THE CLKREQ CONNECTION,TO GPIO?
OUT
OUT
(ICH7M DMI 100 MHZ )
(PULL UP PIN 68 TO ENABLE ITP HOST CLK)

(ICH SM BUS)
27D6
27D6
IN
IO
SMB_CK410_CLK
SMB_CK410_DATA
47 SCL
48 SDA
CK410_IREF
SRC_3
(INT PU) CLKREQ_3*
40 NC
SRC_4*
R3300
SRC_5*
24
SRC_5
(INT PU) CLKREQ_5*
23
60
SRC_6*
SRC_6
27
52 VSS_REF
31 VSS_SRC
(INT PU) CLKREQ_6*
25
SRC_7*
SRC_7
30
29
SRC_8*
32
SRC_8
(INT PU) CLKREQ_8*
33
34
VSS_48
1%
1/16W
MF-LF
2 402
62
66 VSS_PCI
69 THRML_PAD
OUT
34C5
34C5
CK410_SRC5_N
34C5 CK410_SRC5_P
14B6 CLK_NB_OE_L
34C5
26
34A4
34D5 CK410_SRC6_N
34D5 CK410_SRC6_P
CK410_SRC_CLKREQ6_L
34B5
34B5
CK410_SRC7_N
CK410_SRC7_P
CK410_SRC8_N
34C5 CK410_SRC8_P
34C5
DOT_96*/27M_SS*
DOT_96/27M
34B5
34B5
(INT PD) VTT_PWRGD*/PD
48M/FS_A
REF_0/FS_C/TEST_SEL
(INT PD)
REF_1/FCT_SEL_0
OUT
34C5
CK410_SRC4_N
CK410_SRC4_P
23C3 SB_CLK100M_SATA_OE_L
22
21
20
46 VSS_CPU
475
59
SRC_4
(INT PU) CLKREQ_4*
NO STUFF
1
CK410_SRC3_N
CK410_SRC3_P
34B5
54
53
OUT
OUT
IN
CK410_PD_VTT_PWRGD_L
CK410_USB48_FSA
CK410_CLK14P3M_TIMER
34A8 CK410_REF1_FCTSEL0
34C8
34B8
(ICH SATA 100 MHZ)
(FROM ICH7 GPIO35)
OUT
OUT
IN
(GMCH G_CLKIN 100 MHZ )

(FROM GMCH CLK_REQ*)
OUT
OUT
(WIRELESS PCI-E 100 MHZ )
IN
OUT
(NB CRT/TV GRAPHICS DOTCLK 100MHZ)
OUT
OUT
(GIGA LAN PCI-E 100 MHZ )
OUT
IN
CK410_DOT96_27M_N
CK410_DOT96_27M_P
26A8
(FOR PCI-E CARD)
IN
(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)
OUT
OUT
IN
OUT
OUT
(FROM CPU VCORE PWR GOOD)

(ICH7M USB 48MHZ)
(ICH7M,SIO,LPC REF. 14.318MHZ)
IO
CLOCKS
FCTSEL1
0
FCTSEL0
0
PIN 6
DOT96T
PIN 7
DOT96C
PIN 10
100MT_SST
PIN 11
100MC_SST
DOT96T
DOT96C
SRCT0
SRCC0
27M NON
SPREAD
27M
SPREAD
SRCT0
SRCC0
OFF LOW
TBD
SRCT0
SRCC0
SYNC_DATE=(MASTER)
* FOR INT. GRAPHIC SYSTEM

* FOR EXT. GRAPHIC SYSTEM

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
33
84
R3463
CK410_PCIF0_CLK
IN
33
5%
1/16W
MF-LF
402
33B6
CK410_PCIF1_CLK
IN
33
IN
CK410_PCI1_CLK
IN
CK410_PCI2_CLK
IN
CK410_PCI3_CLK
33
33B6
33B6
CK410_PCI4_CLK
IN
OUT
22A6
(TO ICH7M PCI 33MHZ)
PCI_CLK_FW
OUT
37B6
(TO FIREWIRE PCI 33MHZ)
PCI_CLK_TPM
OUT
58C6
(TO TPM PCI 33MHZ)
IN
33C4
33
33C4
5%
1/16W
MF-LF
402
PCI_CLK_SMC
5%
1/16W
MF-LF
402
OUT
49C7
IN
CK410_CPU0_N
IN
CK410_CPU1_P
33C4
NOSTUFF
1
15PF
PLACEMENT of these
caps should be close
as possible to the resistors
NOSTUFF
1
C3401
C3402
15PF
5%
50V
2 CERM
402
5%
50V
2 CERM
402
FSB_CLK_NB_P
MAKE_BASE=TRUE
CK410_CPU1_N
IN
CK410_CPU2_ITP_SRC10_P
FSB_CLK_NB_N
MAKE_BASE=TRUE
CPU_XDP_CLK_P
MAKE_BASE=TRUE
IN
CK410_CPU2_ITP_SRC10_N
IN
CK410_SRC6_P
CPU_XDP_CLK_N
C3403
15PF
15PF
15PF
5%
50V
2 CERM
402
5%
50V
2 CERM
402
5%
50V
2 CERM
402
33B4
CK410_USB48_FSA
IN
23D3
SB_CLK48M_USBCTLR
(TO ICH7M USB 48MHZ)
OUT
=PP1V05_S0_FSB_NB
33B4
PCIE_CLK100M_MINI_P
47C3 5B1
CK410_SRC6_N
IN
CK410_SRC5_P
PCIE_CLK100M_MINI_N
47C3 5B1
NB_CLK100M_GCLKIN_P
14C4
NOSTUFF
33B4
1K
NB_BSEL<0>
CK410_SRC5_N
IN
CK410_SRC2_P
OUT
33A4
(TO MCH FS_A)
33A4
R3450
CPU_BSEL_R<0>
NB_CLK100M_GCLKIN_N
14C4
OUT
MAKE_BASE=TRUE
SB_CLK100M_DMI_P
OUT
MAKE_BASE=TRUE
IN
CK410_SRC2_N
IN
CK410_SRC8_P
SB_CLK100M_DMI_N
MAKE_BASE=TRUE
ENET_CLK100M_PCIE_P
MAKE_BASE=TRUE
7B4
CPU_BSEL<0>
IN
5%
1/16W
MF-LF
402
R3469
33B4
IN
CK410_SRC8_N
IN
CK410_SRC4_P
ENET_CLK100M_PCIE_N
MAKE_BASE=TRUE
SB_CLK100M_SATA_P
MAKE_BASE=TRUE
33B4
IN
CK410_SRC4_N
IN
CK410_SRC3_P
SB_CLK100M_SATA_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=PP1V05_S0_FSB_NB
OUT
39C6
OUT
39C6
OUT
5A7 21B6
OUT
5A7 21B6
OUT
5B1 47B3
(ExpressCard Slot)
1
33B4
R3470
R3471
CK410_FSB_TEST_MODE
1K
5%
1/16W
MF-LF
402
1K
14C6 1
5%
1/16W
MF-LF
402
33A4 IN
NB_BSEL<1>
5%
1/16W
MF-LF
402
OUT
(TO MCH FS_B)
33A4
7B4
CPU_BSEL<1>
IN
(FROM CPU FS_B)
5%
1/16W
MF-LF
402
NOSTUFF
R3452
33B4
33B4
1K
CK410_DOT96_27M_P
CK410_27M_NONSPREAD
121
1%
1/16W
MF-LF
402
CK410_DOT96_27M_N
CK410_27M_SPREAD
R3405
71C2 34B2
IN
GPU_CLK27M
R3419
56
71C5 34B2
67A5
GPU_CLK27MSS_IN
71C5 34B4
OUT
GPU_CLK27MSS_IN
PEG_CLK100M_GPU_P
IN
CK410_SRC1_N
IN
CK410_LVDS_P
67A5
PEG_CLK100M_GPU_N
14B4
NB_CLK_DREFSSCLKIN_P
R3426
OUT
MAKE_BASE=TRUE
100K
IN
CK410_LVDS_N
14C4
NB_CLK_DREFSSCLKIN_N
MAKE_BASE=TRUE
NOSTUFF
R3454
33B4
(TO MCH FS_C)
OUT
33B4
R3453
0
1
7B4
CPU_BSEL<2>
IN
IN
IN
CK410_SRC7_P
CK410_SRC7_N
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
OUT
R3424
R3443
NB_BSEL<2>
5%
1/16W
MF-LF
402
NO STUFF
CPU_BSEL_R<2>
71.5
OUT
MAKE_BASE=TRUE
R3475
5%
1/16W
MF-LF
402
R3402
1
1NO STUFF
33B4
14C6 1
NO STUFF
OUT
MAKE_BASE=TRUE
(NB LVDS GRAPHICS 100MHZ)
1K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R3473
5%
1/16W
MF-LF
402
71.5
GPU_CLK27M
(GPU 27MHz Spread / Non-Spread)
5%
1/16W
MF-LF
402
CK410_SRC1_P
71C2 34B4
OUT
19A6 17C6
33B4
1K
R3474
5B1 47B3
(GPU PCI-E Graphics 100MHz)
5%
1/16W
MF-LF
2 402
=PP1V05_S0_FSB_NB
IN
R3451
1
OUT
MAKE_BASE=TRUE
MAKE_BASE=TRUE
1K
MAKE_BASE=TRUE
CPU_BSEL_R<1>
CK410_SRC3_N
R3418
R3472
IN
NEED TO CHECK THE BSEL PULLS
1K
CK410_CLK14P3M_TIMER
22C2
(ICH7M SATA 100MHZ)
5%
1/16W
MF-LF
402
33B4
33A4
OUT
(FROM CPU FS_A)
1K
IN
22C2
(Yukon PCI-E 100MHZ)
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
19D7 12C2 12B7 12A7

65D6 34C8 34C6
11B3 84C6
R3468
R3401
OUT
(ICH7M DMI 100MHZ)
14C6 1
33C6
OUT
11B3 84C6
OUT
MAKE_BASE=TRUE
R3480
5%
1/16W
MF-LF
2 402
19D7 12C2 12B7 12A7

65D6 34C6 34B8
12A6
OUT
MAKE_BASE=TRUE
IN
1K
2.2K
OUT
OUT
MAKE_BASE=TRUE
IN
12A7 12B7 12C2 19D7 34B8 34C8 65D6

33B4
12A6
(GMCH G_CLKIN 100MHZ)
5%
1/16W
MF-LF
402
OUT
(WIRELESS PCI-E MINI 100MHZ)
33B4
33A4
7C6
C3404
33B4
33
OUT
OUT
MAKE_BASE=TRUE
NOSTUFF
NOSTUFF
1
R3417
1
7C6
(ITP HOST 133/167MHZ)
MAKE_BASE=TRUE
C3400
FSB_CLK_CPU_N
MAKE_BASE=TRUE
IN
TP_CK410_PCI4_CLK
NOSTUFF
OUT
MAKE_BASE=TRUE
(TO SMC PCI 33MHZ)

33C4
FSB_CLK_CPU_P
(GMCH HOST 133/167MHZ)

33C4
CK410_CPU0_P
(CPU HOST 133/167MHZ)
TPM
R3433
33
PCI_CLK_SB
R3430
1
5C2
51C5
33C4
5%
1/16W
MF-LF
402
33B6
OUT
5%
1/16W
MF-LF
402
R3429
33B6
(PORT80 LPC 33MHZ)
PCI_CLK_PORT80_LPC
R3432
33B7
34B2 14C4
34B4 14C4
NB_CLK_DREFCLKIN_P
NO STUFF
R3444
1
(NB CRT/TV GRAPHICS DOTCLK 100MHZ)

34B2 14C4
NB_CLK_DREFCLKIN_P
34B4 14C4
NB_CLK_DREFCLKIN_N
OUT
5%
1/16W
MF-LF
402
NB_CLK_DREFCLKIN_N
R3425
(FROM CPU FS_C)
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
OUT
1K
5%
1/16W
MF-LF
402
R3476
33
1
SB_CLK14P3M_TIMER
5%
1/16W
MF-LF
402
65B3 33D8 33D3 33C7
FS_C FS_B FS_A

CPU
0
0
0
266M
#
0
0
1
133M
#
0
1
0
166M
0
1
1
200M
1
0
0
100M
1
0
1
333M
1
1
0
400M
1
1
1
RESERVED
# NAPA PLATFORM ONLY SUPPORT 133M/166M CPU SPEED
5%
1/16W
MF-LF
2 402
A
33A4
IO
CK410_PCI5_FCTSEL1
CK410_REF1_FCTSEL0
1
R3466
10K
5%
1/16W
MF-LF
2 402
(ICH7M 14.318MHZ)
NOSTUFF R3450,R3451,R3453 FOR MANUAL CPU FREQUENCY
R3467
10K
IO
23D3
=PP3V3_S0_CK410
1
33B6
OUT
Clock Termination
33B4
CK410_SRC_CLKREQ3_L
33B4
CK410_SRC_CLKREQ6_L
EXCARD_CLKREQ_L
SYNC_MASTER=M59_MG
5C1 47C6
MAKE_BASE=TRUE
MINI_CLKREQ_L
5C1 47C6
MAKE_BASE=TRUE

R3485
33B4
CK410_SRC_CLKREQ1_L
GPU CLK OE*
33A4
1K
5%
1/16W
MF-LF
402
CK410_SRC_CLKREQ8_L
Yukon CLK OE*

R3486
1
1K
SIZE
5%
1/16W
MF-LF
402
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
34
84
TPM Crystal Circuit

TPM
TPM
C3720
R3721
R3720 1
TPM
CRITICAL
Y3720
32.768K
10M
5%
1/16W
MF-LF
402 2
NC
NC
TPM
C3721
15pF
1
TPM_XTALI
58C6
SM-2
2
5%
50V
CERM
402
TPM_XTALO_R
5%
1/16W
MF-LF
402
NO STUFF
TPM_XTALO
15pF
1
58C6
2
5%
50V
CERM
402
SMC G3Hot Oscillator

L3750
65D3
FERR-EMI-100-OHM
=PP3V42_G3H_SMC_CLK
2
SM
PP3V42_G3H_SMC_CLK_F
VOLTAGE=3.425V
1
C3750
C3751
4.7uF
2
0.1uF
20%
6.3V
CERM
603
20%
10V
CERM
402
12
CRITICAL
VDD
U3750
32.768KHZ-9-3.6V
R3750
SG-3040LC-SM
1
VIO
OUT
NC0
NC4
NC1
NC2
NC5
NC6
4
5
NC3
NC7
11
SMC_CLK32K_SUSCLK_R
22
1
SMC_CLK32K_SUSCLK
SMC_SUS_CLK
49C5
MAKE_BASE=TRUE
NC
NC
NC
NC
10
5%
1/16W
MF-LF
402
NC
NC
NC
NC
GND
6
Mobile Clocking
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
35
84
IDE (ODD) Connector

65B3
=PP3V3_S0_IDE
65B1
=PP5V_S0_IDE
CRITICAL
Q3820
FDZ293P
BGA
B3
C3
B1
B2
A3
A2
C1
PP5V_S0_IDE_ODD
VOLTAGE=5V
NO STUFF
R3801 1
C2
4.7K
1
A1
10K
5%
1/16W
MF-LF
402 2
C3821
ODD_PWR_EN_L_RC
J3800
M-ST-SM1-LF
20%
6.3V
X5R
402
R3821 1
10K
5%
1/16W
MF-LF
402
22A6
IN
23C3 IN
21B5
21B5
ODD_PWR_EN_L
(UATA_CS0*)
IO
IO
IO
21B5
IO
21B5
IO
21B5
IO
21B6
21B6
21B6
IO
21B5
21C5
(UATA_STOP)
(UATA_HSTROBE)
IO
OUT
IN
OUT
21B5
IN
21B5
IN
21B5
IN
IDE_RESET_L
IDE_PDD<7>
IDE_PDD<6>
IDE_PDD<5>
IDE_PDD<4>
IDE_PDD<3>
IDE_PDD<2>
IDE_PDD<1>
IDE_PDD<0>
IDE_PDIOW_L
IDE_PDIOR_L
IDE_PDDACK_L
IDE_PDA<1>
IDE_PDCS1_L
IDE_PDA<2>
50
49
21B5
48
21B5
47
21B5
46
21B5
45
44
21B5
43
21B5
42
21B5
10
41
21B5
11
40
12
39
21B6
13
38
21B6
14
37
21B6
15
36 21B5
16
35
17
34 21B5
18
33
19
32
20
31
21
30
22
29
23
28
24
27
25
26
IDE_PDD<12>
IDE_PDD<13>
IDE_PDD<14>
IDE_PDD<15>
IDE_PDDREQ
IDE_PDIORDY
IDE_IRQ14
IDE_PDA<0>
5%
1/16W
MF-LF
402
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
(UATA_DSTROBE)
OUT
IN
IN
(UATA_CS1*)
NC
Indicates disk presence

SMC_ODD_DETECT
OUT
49B7
516S0335
15K
IDE_PDD<8>
IDE_PDD<9>
IDE_PDD<10>
IDE_PDD<11>
IDE_PDCS3_L
R3811 1
Counters 10K pull-up to 5V in
ODD to keep SB GPIO <= 3.3V
R3802
4.7K
5%
1/16W
MF-LF
402
2
21B5
R3810
33K
CRITICAL
0.22uF
R3820
5%
1/16W
MF-LF
402 2
R3803
6.2K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
23D2
SATA_C_DET_L
1
R3850
100
5%
1/16W
MF-LF
402
21B6
SATA_A_R2D_C_P
TP_SATA_A_R2DP
21B6
SATA_A_R2D_C_N
TP_SATA_A_R2DN
21B6
SATA_A_D2R_P
TP_SATA_A_D2RP
21B6
SATA_A_D2R_N
TP_SATA_A_D2RN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PATA Connector
MAKE_BASE=TRUE
SYNC_DATE=(MASTER)

21B6
21B6
SATA_RBIAS_P
SATA_RBIAS_N
SATA_RBIAS
MAKE_BASE=TRUE
1
Place within 12.7mm

from ball of SB
R3860
24.9
Placement note
2
1%
1/16W
MF-LF
402

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
36
84
65C3 37C3 37A7
=PP3V3_S3_FW
65C3
C3900
C3901
C3902
C3903
C3904
1uF
1uF
1uF
1uF
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
C3908
1uF
10%
10V
X5R
402
C3909
1uF
10%
10V
2 X5R
402
R3901 1
IO
22B7
IO
22B7
IO
22B7
IO
22B7
IO
22B7
IO
22B7
IO
22B7
IO
22B7
IO
22B7
IO
22B7
IO
22B7
IO
22B7
IO
22B7
IO
22B7
IO
22B7
IO
22B7
IO
22B7
IO
22B7
IO
22A7 6B7
IO
22A7
IO
22A7
IO
22A7
IO
22A7
IO
22A7
IO
22A7
IO
22A7
IO
22A7
IO
22A7
IO
22A7
IO
22A7
IO
22A7
IO
22B6
IO
22B6
IO
22B6
IO
22B6
IO
L12 PCI_AD0
N11 PCI_AD1
M11 PCI_AD2
N10 PCI_AD3
M10 PCI_AD4
PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>
5%
1/16W
MF-LF
402
VCCP
VCC
22B7
F11
E11
J11
J7
H11
J6
F5
D5
D8
D9
E5
4.7K
CRITICAL
U3900
K12 PCI_AD5
M9 PCI_AD6
N9 PCI_AD7
L8 PCI_AD8
M8 PCI_AD9
BGA
6B6
26D2
26D2
26D2
PCI_REQ_L F3
PCI_REQ64_L J13
PCI_RST_L D1
(2 OF 2)
26D2
26D2
PHY_D2 C13
PHY_D3 B9
PHY_D4 B10
G3 PCI_AD27
H1 PCI_AD28
F1 PCI_AD29
F2 PCI_AD30
G4 PCI_AD31
IO
IO
IN
OUT
IO
IO
OUT
OUT
PCI_RST_FW_L
22A6 PCI_SERR_L
22A6 PCI_STOP_L
22A6 PCI_TRDY_L
R3903
1
IO
34D6
22A6
R3900
PCI_C_BE0_L
PCI_C_BE1_L
PCI_C_BE2_L
PCI_C_BE3_L
IO
38B6
IO
38B6
IO
38B6
IO
IO
IO
65C3 37D7 37A7
IO
5%
1/16W
MF-LF
402
1K
2 FW_LKON
IO
1%
1/16W
MF-LF
402
IO
OUT
R3910
10K
IN
IN
5%
1/16W
MF-LF
402
FW_LLC_PP1V8LDO_EN_L
=PP1V8_S3_FW
1
FW_SCL
FW_SDA
C3910
10%
16V
X5R
402
MFUNC A1
65B6
C3911
0.1uF
10%
16V
X5R
402
FW_MFUNC
K10
J8
J9
J10
H10
H8
H9
37A5
H6
H7
F9
F7
F8
E9
E10
F6
E7
E8
E6
D6
D7
C8
C7
GND
Might use
MFUNC as a
GPIO
B
2
65C3 37D7 37C3
=PP3V3_S3_FW
R3904
OUT
38C3 38A3
G_RST_L E4
G10
22
IN
TP_FW_DATA<0>
TP_FW_DATA<1>
SCL C3
SDA C4
G8
G9
PCI_RST_L
THIS IS FROM ICH-7M
TP_FW_CTL<0>
TP_FW_CTL<1>
REG_EN_L C2
REG18_0 G11
REG18_1 G12
G7
=FW_PCI_IDSEL
22A6
F10
G6
6B6
IN
IO
0.1uF
From PCI clock generator via 33 Ohms
100
5%
1/16W
MF-LF
402
IO
PCI_ACK64_L
FW_DATA<2>
FW_DATA<3>
FW_DATA<4>
PHY_D5 C11 38B6 FW_DATA<5>
PHY_D6 B12 38B6 FW_DATA<6>
PHY_D7 A11 38B6 FW_DATA<7>
PHY_LCLK B7 38C5 CLKFW_PHY_LCLK
FW_PHY_LKON
PHY_LINKON B4
PHY_LPS A2 38C5 FW_LPS
D4
FW_LREQ
38C5
PHY_LREQ
PHY_PCLK B6 38C3 CLKFW_LINK_PCLK
PHY_PINT A3 38C3 FW_PINT
H4 PCI_AD24
J3 PCI_AD25
H2 PCI_AD26
D3 PCI_CLK
L2 PCI_IDSEL
N3 PCI_PAR
26D2
PHY_D0-D0 E13
PHY_D1-D1 E12
L1 PCI_AD21
J4 PCI_AD22
H3 PCI_AD23
PCI_DEVSEL_L
PCI_FRAME_L
=FW_PCI_GNT_L
22A7 INT_PIRQD_L
22A6 PCI_IRDY_L
22A6 PCI_PERR_L
22B5 PCI_PME_FW_L
6B6 =FW_PCI_REQ_L
PCI_REQ64_L
PHY_CTL0-CTL0 F13
PHY_CTL1-CTL1 F12
K3 PCI_AD16
N1 PCI_AD17
L4 PCI_AD18
M2 PCI_AD19
M1 PCI_AD20
PCI_CLK_FW
FW_PCI_IDSEL
PCI_PAR
5%
1/16W
MF-LF
402
26D2 22A7
PCI_ACK64_L N12
K2
26D2 22A6
K9 PCI_AD13
K8 PCI_AD14
M5 PCI_AD15
K5
PCI_PERR_L L6
PCI_PME_L F4
TSB83AA22AZAJ
4.7K
PCI_GNT_L E3
PCI_INTA_L B3
PCI_IRDY_L K4
PCI_SERR_L L7
PCI_STOP_L L5
PCI_TRDY_L J5
N8
M3
R3902
PCI_DEVSEL_L N2
PCI_FRAME_L L3
N6 PCI_AD10
M6 PCI_AD11
M7 PCI_AD12
PCI_C_BE_L<0>
PCI_C_BE_L<1>
PCI_C_BE_L<2>
PCI_C_BE_L<3>
=PP3V3_S3_PCI
1uF
2
R3980
R3990
1K
220
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R3991
220
5%
1/16W
MF-LF
402
FW_G_RST_L
IN
G_RST* is clamped to VCCP

It must not be taken high
when theres no power on VCCP
(OK if VCCP and VCC are
aliased to the same rail)
G_RST* assertion min 2ms
=PP3V3_S3_FW
Gated Platform Reset Option
RC Reset Option
1
R3977
10K
Q3970
2N7002
SOT23-LF
26B3
PLT_RST_BUF_L
3
S
5%
1/16W
MF-LF
R3879
2 402
1
FW_G_RST_L_R
0
5%
1/16W
MF-LF
402
37B2
IN
=SMC_FWRSTGATE_L 1
10K
SMC_RSTGATE_RC_L
5%
1/16W
MF-LF
402
OUT
C3977
1UF
R3979
6B6
FW_G_RST_L
10%
10V
X5R
402
FireWire Link (TSB83AA22)
C3979
SYNC_DATE=(MASTER)
0.001uF
2
10%
50V
CERM
402

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
37
84
PP3V3_FWPHY_AVDD
VOLTAGE=3.3V
R4000
=PP3V3_FWPHY
1
1
C4001
C4004
1uF
10%
10V
10%
10V
1uF
10%
10V
10%
10V
X5R
402
2 X5R
2 X5R
2 X5R
402
402
402
402
C4011
C4012
C4013
1uF
1uF
1uF
20%
16V
CERM
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
C4030
1uF
2 X5R
0.01uF
2
C4003
1uF
10%
10V
C4010
C4002
1uF
R4035
=PP1V95_FWPHY
1
5%
1/16W
MF-LF
402
6B6
C4031
PP1V95_FWPHY_PLLVDD
1uF
10%
10V
X5R
402
VOLTAGE=1.95V
5%
1/16W
MF-LF
402
C4035
2.2uF
10%
6.3V
2 CERM1
603
C4014
1uF
10%
10V
2 X5R
44B8 6C6
402
R4020
PP3V3_FWPHY_PLLVDD
FW_A_DS
FW_B_DS
CLKFW_PHY_LCLK
A6
DS0
B8
G13
DS1
LCLK
FW_LPS
N13
LPS
IN
FW_LREQ
K13
LREQ
IO
=FW_PC0
N4
PC0
M4
PC1
PC2
37C4 IN
1K
1K
5%
1/16W
MF-LF
402 2
PCLK
H13
PINT
M13
CNA
M12
LKON_DS2
L13
R4091
1K
R4061
470
5%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402
37C4
CLKFW_LINK_PCLK
OUT
C6
C5
K6
K7
J12
H12
U3900
TSB83AA22AZAJ
37C4
FW_PINT
OUT
38A3 37C3
FW_LKON
IO
(1 OF 2)
1K
37C4
IN
5%
1/16W
MF-LF
402 2
R4040
R4090 1
BGA
R40451
FW_B is BILINGUAL
CRITICAL
A8
FW_A is DS_ONLY
PLLVDD_CORE
5%
1/16W
MF-LF
402 2
A7
PLLVDD_3P3
1K
DVDD_CORE
AVDD_3P3
402
R4042 1
DVDD_3P3
10%
D12
1uF
2 10V
X5R
H5
C4021
D10
G5
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
D11
37C4
R4056
NC
10K
5%
1/16W
MF-LF
2 402
1
44B8
5%
1/16W
MF-LF
402
DUAL PORT DEVICES ARE POWER CLASS 4 (100)

SINGLE PORT DEVICES ARE POWER CLASS 0 (000)
IMPLEMENT 1K PULLUP OR PULLDOWN ON PORT PAGE
N5
K11
TPA0P
E1
TPA0N
E2
FW_A_TPA_P
44C7 FW_A_TPA_N
TPA1P
J2
44B7
PD
TPA1N
J1
FW_B_TPA_P
44B7 FW_B_TPA_N
TPB0P
C1
44C7
TPB0N
B1
FW_BMODE
L9
BMODE
FW_CPS
A5
CPS
1MA (MAX) BUS HOLDERS
R4055
=PPFW_FW_CPS
390K
5%
1/16W
MF-LF
402
IO
IO
IO
IO
IO
IO
FW_DATA<2>
37C4 FW_DATA<3>
37C4 FW_DATA<4>
37C4 FW_DATA<5>
37C4 FW_DATA<6>
37C4 FW_DATA<7>
37C4
FW_PHY_RESET_L
RESET PULSE WHEN PHY FIRST

RECEIVES POWER
IO
D2
D3
TPB1N
G1
FW_B_TPB_P
44B7 FW_B_TPB_N
D4
D5
TPBIAS0
TPBIAS1
D2
44D7
C12
K1
44D7
B13
D6
B11
D7
L10
RESET
D13
C9
C10
C4050
20%
6.3V
X5R
402
IO
IO
R4086
IO
FW_A_TPBIAS
FW_B_TPBIAS
=PP1V8_FWPHY_OSC
4.7
PP1V8_FWPHY_OSC
VOLTAGE=1.83V
5%
1/16W
MF-LF
402
IO
IO
OUT
OUT
R4062
TESTM
TESTW
R0
R1
SE
SM
44B7
XI
L11
N7
A12
A13
FW_TESTM
FW_TESTW
6.34K
FW_R0
FW_R1
CRITICAL
CLK98P304_FW_XI
A9
1%
1/16W
MF-LF
402
VCC
22
G4080
CLK98P304M_FW_XI_R
C4080
0.22uF
R4080
20%
6.3V
X5R
402
98P3040MHZ
5%
1/16W
MF-LF
402
A10
0.22uF
2
FW_A_TPB_P
44C7 FW_A_TPB_N
G2
B5
INTERNAL PULLUP PROVIDES
IO
TPB1P
A4
CAPACITOR IN CONJUCTION WITH
IO
6B6
PLLGND
65C1
44C7
SM
3
OUT
TRI-ST/NC
NC
GND
2
FW_LKON
37C3 38C3
NO STUFF
R4063 1
1K
1%
1/16W
MF-LF
402
FireWire PHY (TSB83AA22)
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
38
84
PLACE C4100-C4106 NEAR PINS AVDLL0-AVDLL6.
SCHEME MATCHES DOC MVL100258-01
40D5
L4100
FERR-120-OHM-1.5A
VOLTAGE=2.5V
PP2V5_S3_ENET_AVDD
=PP2V5_S3_ENET
65B6
0402-LF
1
C4100
0.1UF
1UF
2
C4101
10%
6.3V
CERM
402
C4102
C4103
0.1UF
10%
16V
X5R
402
0.1UF
10%
16V
X5R
402
C4105
0.1UF
10%
16V
X5R
402
C4104
C4106
0.001UF
10%
16V
X5R
402
10%
50V
CERM
402
C4107
0.001UF
0.1UF
10%
50V
CERM
402
10%
16V
X5R
402
PLACE C4107 NEAR U4101 AVDD
=PP3V3_S3_ENET
=PP1V2_S3_ENET
=PP3V3_S3_ENET
39A8 65D6
39D8 65D1
39A5 39B4
39B5 39B8
PLACE C4110 AND C4111 WITHIN

12 MIL OF U4101 PIN 49 AND 50
C4110
64C6
=ENET_VMAIN_AVLBL
VAUX_AVLBL
47
NC
11
VMAIN_AVLBL
SWITCH_VCC
NC
SWITCH_VAUX
CRITICAL
U4101
25
ENET_CTRL25
6D4 ENET_CTRL12
6D4
OUT
OUT
CTRL25
CTRL12
NC
59
NC
60
NC
62
NC
63
PCI EXPRESS
ANALOG
LED_ACT*
LED_LINK10/100*
TSTPT
46
TESTMODE
VDD25
TX_P
49
TX_N
50
RX_P
RX_N
54
55
REFCLKN
56
22D4
PCIE_A_D2R_P
OUT
22D4
PCIE_A_D2R_N
OUT
C4111
C4112
0.1UF
0.1UF
402
X5R
10%
16V
402
PCIE_A_R2D_P
PCIE_A_R2D_N
53
REFCLKP
1
1
ENET_CLK100M_PCIE_P
34C3 ENET_CLK100M_PCIE_N
34C3
PCIE_WAKE_L
26B1 ENET_RST_L
47C3 23C8 5B1
22D4
22D4
IN
C4113
IN
0.1UF
PCIE_A_R2D_C_P
PCIE_A_R2D_C_N
IN
IN
PLACE C4113 AND C4112 WITHIN

12 MIL OF U2100 E27 AND E28
402
X5R
16V
10%
OUT
IN
ENET_MDI_P<0>
ENET_MDI_N<0>
IO
ENET_MDI_P<1>
40A7 ENET_MDI_N<1>
IO
IO
27
ENET_MDI_P<2>
40C4 ENET_MDI_N<2>
30
40C4
ENET_MDI_P<3>
40B4 ENET_MDI_N<3>
IO
MDIP0
MDIN0
17
40D4
18
40C4 40B7
MDIP1
20
40C4
MDIN1
21
MDIP2
MDIN2
26
MDIP3
MDIN3
31
40C4
MEDIA
LED
LED_LINK1000*
LINK*
PCIE_A_D2R_C_N
10%
16V
X5R
WAKE*
PERST*
RSET
29
PCIE_A_D2R_C_P
88E8053
HSDACP
HSDACN
16
NO PULL-UP NEEDED
1%
1/16W
MF-LF
402
R4102
ENET_RSET
4.87K
OPTIONAL EXTERNAL LDO
24
NC
10%
16V
X5R
402
64
19
22
OMIT
QFN
NC
AVDDL0
28
32
51
AVDDL2
AVDDL1
52
AVDDL4
AVDDL3
57
AVDDL5
AVDD
AVDDL6
23
VDDO_TTL1
VDDO_TTL0
40
45
VDDO_TTL2
LOM_DISABLE*
12
VDDO_TTL4
VDDO_TTL3
61
VDD0
13
VDD2
VDD1
33
39
44
VDD3
48
VDD5
VDD4
VDD6
58
ENET_LOM_DIS_L 10
39B7
VDD7
0.1UF
ENET_VPD_CLK
ENET_VPD_DATA
38
TWSI
VPD_DATA
41
TEST
PU_VDDO_TTL0
PU_VDDO_TTL1
42
SPI_DI
35
NC
SPI_DO
SPI_CLK
34
NC
37
NC
SPI_CS
36
NC
XTALI
15
XTALO
14
SPI
MAIN CLK
IO
IO
40C4
VPD_CLK
TEST
39D6
39B5
39A5
39B4
39B8
65D1
IO
IO
39A2
39A2
ENET_PU_VDD_TTL0 39A6
ENET_PU_VDD_TTL1 39A6
43
ASF IS UNAVAILABLE ON 8053
INTERNAL PULL-UP
CRITICAL
ENET_XTALI
ENET_XTALO 3
1. KEEP ENET_XTALI AND ENET_XTALO
R4106
R4105
R4104
R4103
R4120
R4119
49.9
49.9
49.9
49.9
49.9
49.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R4118
49.9
R4117
49.9
1%
1/16W
MF-LF
402
TRACE LENGTH <12MIL
65
THRML_PAD
4
ENET_MDI0
2. DO NOT ROUTE UNDER CRYSTAL
ENET_MDI1
VOLTAGE=1.234V
Y4101
ENET_MDI2
VOLTAGE=1.234V
VOLTAGE=1.234V
ENET_MDI3
VOLTAGE=1.234V
SM-3.2X2.5MM
Setting attribute VOLTAGE

to arbitrary value
to help constraint manager
find correct topolgy
25.0000M
1
65D1 39D8 39D6 39B5 39B4 39A5
=PP3V3_S3_ENET
2
C4150
C4151
C4116
C4115
C4117
27pF
27pF
0.001UF
0.001UF
0.001UF
5%
50V
CERM
402
5%
50V
CERM
402
10%
50V
CERM
402
10%
50V
CERM
402
10%
50V
CERM
402
C4118
0.001UF
10%
50V
CERM
402
R41011
4.7K
5%
1/16W
MF-LF
402 2
PLACE RESISTORS CLOSE TO U4101

39C8
5%
1/16W
MF-LF
402 2
39C6
ENET_PU_VDD_TTL0
39B6
ENET_PU_VDD_TTL1
5%
1/16W
MF-LF
402
PLACE C4140 NEAR U4102 VCC

1
PLACE C4127-C4134 NEAR PINS VDD0-VDD7 ON U4101
=PP1V2_S3_ENET
65D1 39D8 39D6 39B8 39B5 39B4
10%
16V
X5R
402
OMIT
CRITICAL 8
VCC
3 E2
2 NC1
U4102 SDA
1 NC0
M24C08 SCL
7 WC*
SO8
PLACE C4135-C4139 NEAR VDDO_TTL0-VDD_TTL4 ON U4101
65D6 39D7
C4140
0.1UF
4.7K
5%
1/16W
MF-LF
402
10K
100K
4.7K
5%
1/16W
MF-LF
402
R4132
=PP3V3_S3_ENET
R4131
R4123
SOT23-LF
R4130
ENET_LOWPWR_EN
10K
6C4
39A5 39B4 39B8 39D6 39D8 65D1

65D1 39D8 39D6 39B8 39B5 39A5
2N7002
5%
1/16W
MF-LF
402
=PP3V3_S3_ENET
Q4100
R4122
ENET_LOM_DIS_L
3
ENET_VPD_DATA
39C6
ENET_VPD_CLK
39C6
VSS
=PP3V3_S3_ENET
4
1
1
C4126
0.1UF
10%
16V
X5R
402
C4127
0.1UF
2
10%
16V
X5R
402
C4128
0.1UF
2
10%
16V
X5R
402
C4129
0.1UF
2
10%
16V
X5R
402
C4130
0.1UF
2
10%
16V
X5R
402
C4131
0.001UF
2
10%
50V
CERM
402
C4132
0.001UF
2
10%
50V
CERM
402
C4133
0.001UF
2
10%
50V
CERM
402
C4134
0.001UF
2
C4135
0.1UF
10%
50V
CERM
402
10%
16V
X5R
402
C4136
0.1UF
2
10%
16V
X5R
402
C4137
0.1UF
2
10%
16V
X5R
402
C4138
10%
50V
CERM
402
ETHERNET CONTROLLER
0.001UF
0.001UF
2
C4139
10%
50V
CERM
402
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
39
84
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PROVIDED
BY
ETHERNET
PHY
SPACING
PHYSICAL
ENETCONN
ENET_100D
ENETCONN
ENET_100D
ENETCONN
ENET_100D
ENETCONN
ENET_100D
ENETCONN
ENET_100D
ENETCONN
ENET_100D
ENETCONN
ENET_100D
ENETCONN
ENET_100D
ENETCONN_P<0>
ENETCONN_N<0>
ENETCONN_P<1>
ENETCONN_N<1>
ENETCONN_P<2>
ENETCONN_N<2>
ENETCONN_P<3>
ENETCONN_N<3>
40D3
40C3
40C3
40C3
40C3
40C3
40C3
39D5 IN
40B3
PP2V5_S3_ENET_AVDD
Place one cap at each pin of transformer
Page Notes
C4200
1uF

- =PP2V5_ENET
- =GND_CHASSIS_ENET

(NONE)
C4201
C4202
1uF
10%
6.3V
CERM
402
1uF
10%
6.3V
CERM
402
1uF
10%
6.3V
CERM
402
C4203
10%
6.3V
CERM
402
1000BT-824-00275
CRITICAL
T4200

(NONE)
39C3
IO
XFR-SM
ENET_MDI_P<0>
16
14
15
40D7
ENETCONN_P<0>
ENET_CTAP0
ENET_MDI_N<0>
5
39C3
IO
ENET_MDI_P<1>
NC1
NC2
LINE
SIDE
40D7
J4200
ENETCONN_N<0>
JM36113-P2054-7F
13
NC4
NC3
IO
CHIP
SIDE
CRITICAL
40B7 39C3
11
F-RT-TH-RJ45
12
9
10
11
40D7
ENETCONN_P<1>
ENET_CTAP1
1
2
40A7 39C3
IO
ENET_MDI_N<1>
Transformers should be
mirrored on opposite
sides of the board
ENETCONN_N<1>
3
4
SYM_VER2
1000BT-824-00275
5
6
CRITICAL
T4201
40D7
39C3
IO
XFR-SM
ENET_MDI_P<2>
16
40D7
14
ENETCONN_P<2>
ENET_CTAP2
10
12
IO
ENET_MDI_N<2>
5
39C3
IO
ENET_MDI_P<3>
15
NC1
NC2
LINE
SIDE
CHIP
SIDE
39C3
40D7
ENETCONN_N<2>
514-0277
13
NC4
NC3
12
10
11
40D7
Short shielded RJ-45
ENETCONN_P<3>
NO STUFF
ENET_CTAP3
R4210
39C3
IO
ENET_MDI_N<3>
40D7
ENETCONN_N<3>
SYM_VER2
R4200 1
R4201 1
75
75
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R4202
75
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
65A3
R4227
C4220
R4220
68PF
1
ED_MDIN0_C
2.4K
R4223
392K
100K
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
EDET_MDIN_AMP
EDET_ACT
ED_MDIN1_C
2.4K
ED_MDIN_R
Q4220
MMDT3904XF
U4200
LMC7211
5%
1/16W
MF-LF
402
SM-LF
LAN_ENERGY_DET 23C3
V1
R4226
10K
MMDT3904XF
5%
1/16W
MF-LF
SOT-363-LF
Q4220
SOT-363-LF
4
NO STUFF
1
C4222
100pF

to arbitrary value
PLACE C4220 & C4221
10%
16V
X5R
402
VOLTAGE=1.234V
5%
50V
CERM
402-1
V+
R4221
68PF
1
OUT
5%
1/16W
MF-LF
402
C4221
ENET_MDI_N<1>
=GND_CHASSIS_ENET
0.1uF
R4224
3.3K
1%
1/16W
MF-LF
402
EDET_REF
40C4 39C3
6A6
C4223
R4228
470K
VOLTAGE=1.234V
5%
50V
CERM
402-1
2
10%
3KV
CERM
1808
B
1
ENET_MDI_N<0>
=PP3V3_S0_EDET
1
40C4 39C3
C4204
100pF
LAN ENERGY DETECT
Place close to connector
R4203
75
ENET_CTAP_COMMON
2
5%
1/16W
MF-LF
402
5%
50V
CERM
402
2 402
1
R4225
51.1K
1%
1/16W
MF-LF
2 402
NEAR ENET_MDI_N<0/1>
Ethernet Connector
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
40
84
Yukon Power Control

Allows powering Yukon down during battery sleep to save power
Q4300
FDG6332C_NL
SC70-6
P-CHN
=PP3V3_S3_P3V3S3AC
4
=PP3V3_S3AC_FET
D
65D3
65C3
G
5
PPVIN_S3_P2V5S3_SVIN
1
61D6
R4304
100K
5%
1/16W
MF-LF
402
=P2V5S3_EN
61D8
PM_SLP_S3BATT_L
MAKE_BASE=TRUE
3
D
Q4304
2N7002
SOT23-LF
S
2
65C1
=PPBUS_G3H_S3AC
1
P1V2S3_RUNSS
R4302
5D7 61B7
1.2V enable has pull-up to 3.3V
470K
5%
1/16W
MF-LF
402
Q4302
2N7002
PM_SLP_S3BATT
SOT23-LF
S
2
PM_SLP_S4_L
FDG6332C_NL
SC70-6
R4300
FWPWR_EN_L
Q4300
ENETPWR_S3AC
43C7
N-CHN
64B8 49C5 23C3
FWPWR_EN_L_OR_GND
ENETPWR_S3
5%
1/16W
MF-LF
402
R4301
0
B
2
5%
1/16W
MF-LF
402
When ENETPWR_S3AC BOMOPTION is active:

State
PM_SLP_S4_L
PM_SLP_S3BATT
PM_SLP_S3BATT_L
S0 AC
0V
3.3V
0V
(3.3V ON)
3.3V
3.3V
(2.5V ON)
3.3V (1.2V ON)
S0 Batt
0V
3.3V
0V
(3.3V ON)
3.3V
3.3V
(2.5V ON)
3.3V (1.2V ON)
S3 AC
0V
3.3V
0V
(3.3V ON)
3.3V
3.3V
(2.5V ON)
3.3V (1.2V ON)
PBUS
3.3V
PBUS (3.3V OFF)
0V
0V (2.5V OFF)
0V
(1.2V OFF)
0V
0V
PBUS (3.3V OFF)
0V
0V (2.5V OFF)
0V
(1.2V OFF)
S5 Batt
PBUS
0V
PBUS (3.3V OFF)
0V
0V (2.5V OFF)
0V
(1.2V OFF)
G3H Batt
PBUS
0V
PBUS (3.3V OFF)
0V
0V (2.5V OFF)
0V
(1.2V OFF)
S3 Batt
FWPWR_EN_L
S5 AC
P2V5S3_EN
P1V2S3_RUNSS
When ENETPWR_S3 BOMOPTION is active:

State
PM_SLP_S3BATT
PM_SLP_S3BATT_L
P2V5S3_EN
P1V2S3_RUNSS
S0
3.3V
0V
(3.3V ON)
3.3V
3.3V
(2.5V ON)
3.3V (1.2V ON)
S3
3.3V
0V
(3.3V ON)
3.3V
3.3V
(2.5V ON)
3.3V (1.2V ON)
S5
G3H
PM_SLP_S4_L
0V
0V
PBUS (3.3V OFF)

PBUS (3.3V OFF)
0V
0V
0V (2.5V OFF)
0V
0V (2.5V OFF)
0V
Yukon Power Control

(1.2V OFF)
SYNC_DATE=(MASTER)
(1.2V OFF)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
41
84
3.3V Supply for FWPHY

1.95V Supply for FW PHY
D4400
SC-59
65C1
=PPFW_P3V3FWPHY
42B6
PPBU_S0_FW
3 PP5VR33V_FWPHY3V3
SMD20E40C-X-F
6C6
CRITICAL
=PP3V3_FWPHY_CORE
C4400
10%
50V
X7R-CERM
1206
C4405
6
BOOST
3
VIN
4.7UF
U4400
165MA MAX LOAD
LT3470
NC
SHDN*
SW
CRITICAL BIAS
NC
FB
5
7
FWPHY3V3_SW
SWITCH_NODE=TRUE
33uH
1
=PP3V3_FWPHY_REG
NC
6C8
Vout = 3.316
(Regulator limit)
C4410
(Switcher limit)
5%
50V
CERM
402
1%
1/16W
MF-LF
2 402
PAD
7
1
C4420
C4421
10%
16V
CERM
402
C4422
2.2uF
0.01uF
1uF
10%
6.3V
CERM
402
324K
22pF
THRML
3
200mA max output

<Ra>
R4410
5 NC
GND
2
CDPH4D19F-SM
GND
4
OUT 1
NR 2 FWPHY_CORE_NR
L4400
TSOT23-8
SON
6 IN
4 EN
CRITICAL
6B8
Vout = 1.95V
400mA max output
TPS799195
0.22uF
20%
6.3V
X5R
402
=PP1V95_FWPHY_CORE_LDO
U4420
FWPHY3V3_BOOST
2
2
20%
4V
X5R
402
C4401
22UF
FWPHY3V3_FB
<Rb>
R4411
20%
6.3V
2 X5R
805
196K
1%
1/16W
MF-LF
2 402
Vout = 1.25V * (1 + Ra / Rb)
PBUS S0 FET
Q4450
IRLML6302PBF
=PPBUS_S0_PPBU_S0_FW
R4450
C4450
470K
0.0022UF
5%
1/16W
MF-LF
402 2
10%
50V
CERM 2
402
PPBU_S0_FW 42C8
VOLTAGE=12.6V
65C1
SOT23
PPBU_S0_FW_EN_DIV
1
R4451
330K
5%
1/16W
MF-LF
402 2
PPBU_S0_FW_EN
Q4451
2N7002
64C8 49C5 43B7 23C3
PM_SLP_S3_L
SOT23-LF
S
2
FW PHY Power Supply
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
42
84
Page Notes
- =PPBUS_S0_FWPWRSW (system supply for bus power)
- =PP3V3_S0_FWPORTPWRSW
- =FWPWR_PWRON (see related text note below)
(NONE)
Current Limit/Active Late-VG Protection

CRITICAL
Q4500
65C1
SI2318DS
=PPBUS_S5_FWPWRSW
SOT23-3
R4500
0.020
1%
0.25W
MF
805
PPBUS_S5_FW_R
VOLTAGE=12.6V
PPBUS_S5_FW_FET1
CRITICAL
VOLTAGE=12.6V
Q4501
6
SI7222DN
PWRPK-1212-8
Q4501 is a dual FET

for redundancy and
UL compliance for
single-point failure protection
FW_PWRCTRL_GATE2_1
5%
1/16W
MF-LF
402
Current Limit determined by R4500

0.020
0.025
0.030
0.033
FWPWR_LATEVG_EN
ohm
ohm
ohm
ohm
3
D
5
QSOP1
CRITICAL
LATEVG_EVENT_D_L
1K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402
8 ONQ1
Q4560
FW_PWRCTRL_GATE2_1_R
4
Q4502
MMDT3906XF
SOT-363
OUT 11
GATE1 14 FW_PWRCTRL_GATE1
GATE2 12
=PPBUS_S5_FW_FET
4 ILIM
SOT-363
6 OR_ADJ
IFAULT*
Q4502
NC
FWPWR_EN_L
NC 7
NC 10
NC 13
5 LATCH
D
1 ON
Q4561
2N7002DW-X-F
SMC_ADAPTER_EN
SOT-363
S
D
Enables port power when machine

is running or on AC.
64C8 49C5 42A8 23C3 PM_SLP_S3_L
C4560
Q4561
NC
R4503
R4504
100K
5%
1/16W
MF-LF
402 2
20%
16V
CERM
402
SOT-363
CRITICAL
Q4501
1K
SI7222DN
PWRPK-1212-8
5%
1/16W
MF-LF
402 2
FW_PWRCTRL_GATE2_2
0.01uF
2N7002DW-X-F
2
FW_PWRCTRL_GATE2_2_R
NC
50A2 49D5 47C6 5C1
NC
9 GND
VOLTAGE=12.6V
SOT-363
3 TIM
PPBUS_S5_FW_FET2
MMDT3906XF
1
41B6
65C3
FW_PWRCTRL_GATE2
6
2N7002DW-X-F
43A5
R4502
100K
15 SENSE
D
R4501
MAX5943
16 IN
SOT-363
2.4A
2A
1.66A (ideal)
1.5A
U4500
Q4560
2N7002DW-X-F
FWPWR_LATEVG_EN_L
=>
=>
=>
=>
200K
10K
R4561
R45601
5%
1/16W
MF-LF
402
C4500
1UF
10%
35V
2 X5R
603
Late-VG Event Detection

44D5 44B5 44A5
6B6
PP2V4_FWLATEVG
=PP3V3_FWLATEVG_ACTIVE
1
1
10K
R4512 1
5%
1/16W
MF-LF
402
10K
1%
1/16W
MF-LF
402
PP2V4_FWLATEVG_RC
V+
R4519
SM-LF
1
V-
2.0M
20%
10V
CERM
402
U4510
LMC7211
FWLATEGV_3V_REF
C4510
0.1UF
R4511
5%
1/16W
MF-LF
2 402
D4510
SOD-123
LATEVG_EVENT_L
LATEVG_EVENT_D_L
MBR0540XXG
R4513 1
80.6K
1%
1/16W
MF-LF
402
5%
50V
CERM
402
C4512
FireWire Port Power
0.33UF
C4511
100pF
43C7
10%
10V
CERM-X5R
603
SYNC_DATE=(MASTER)
R4510
1
200K
1%
1/16W
MF-LF
402
FWLATEVG_3V_REF Hysteresis:
2.95V when port power is on
2.81V on late Vg event and port power is off

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
43
84
NET_TYPE
PROVIDED
BY
PHY
PAGE
SPACING
PHYSICAL
FW
FW_110D
FW
FW_110D
FW
FW_110D
FW
FW_110D
FW
FW_110D
FW
FW_110D
FW
FW_110D
FW
FW_110D
FW_PORT1_TPA_P
FW_PORT1_TPA_N
FW_PORT1_TPB_P
FW_PORT1_TPB_N
FW_PORT2_TPA_FL_P
FW_PORT2_TPA_FL_N
FW_PORT2_TPB_FL_P
FW_PORT2_TPB_FL_N
AREF needs to be isolated from

all local grounds per 1394b spec
44B5 44C5
44B5 44C5
Cable Power
44B5 44C5
When a bilingual device is

connected to a beta-only device,
there is no DC path between them
(to avoid ground offset issue)
44B5 44C5
44B2
44B2
44B2
FERR-250-OHM
1
44B2
Page Notes
- =PPFW_PORT1
- =PP3V3_S5_FWLATEVG
- =GND_CHASSIS_FW_PORT1
44B5 44A5 43B7
PPFW_PORT1_VP
VOLTAGE=33V
C4624
0.001uF
PP2V4_FWLATEVG
DP4620
BAV99DW-X-F
C4621
10%
50V
X7R
402
Termination
20%
50V
CERM
402
SOT-363
1
5
0.01uF
PORT 1
BILINGUAL
Note:Trace PPFW_PORT1_VP should handle up to 5A
2
4
DP4620
BAV99DW-X-F
Place close to FireWire PHY
C4620
CRITICAL
SOT-363
1
2
J4620
0.01uF
TI PHYs require 1uF even though
38B3 FW_B_TPBIAS
38B3 FW_A_TPBIAS
2
SM
"Snapback" & "Late VG" Protection
BREF should be hard-connected to

logic ground for speed signaling
and connection detection currents
per 1394b V1.33

(NONE)
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.
L4620
65C1 =PPFW_PORT1_VP
10%
50V
X7R
402
FW spec calls out 0.33uF
1394B-UG31903
F-RT-SM1
10
1
1
C4650
C4660
1uF

(NONE)
44D7 44B5 FW_PORT1_TPB_N
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
(FW_PORT1_BREF)
(PPFW_PORT1_VP)
NC
(GND_FW_PORT1_VG)
VOLTAGE=1.234V
VOLTAGE=1.234V
44D7 44B5 FW_PORT1_TPA_N
FW_PORT1_AREF
1OMIT
1OMIT
L4660
L4661
44D7 44B5 FW_PORT1_TPA_P
5%
1/16W
MF-LF
1394b implementation based on Apple

FireWire Design Guide (FWDG 0.6, 5/14/03)
DP4621
5%
1/16W
MF-LF
2 402
C4629
56.2
56.2
1%
1/16W
MF-LF
2 402
R4660
10%
50V
X7R
402
56.2
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402 2
SOT-363
1
VP
NC
VG
TPA-
TPA<R>
TPA+
INPUT
FW_A_TPA_P
FW_PORT2_TPA_P
38B3
FW_A_TPA_N
FW_PORT2_TPA_N
38B3
FW_A_TPB_P
FW_PORT2_TPB_P
514S0133
0.01uF
2
20%
50V
CERM
603
Place C4629 close to

pin 5 of connector
5
1
C4623
10%
50V
X7R
402
44B4
MAKE_BASE=TRUE
NO STUFF
R4629
1M
0.01uF
38B3
10%
50V
X7R
603-1
BAV99DW-X-F
0.01uF
R4661 1
56.2
1%
1/16W
MF-LF
402 2
C4622
VOLTAGE=1.234V
VOLTAGE=1.234V
R4651 1
R4650
FW_B_TPA_L_N
C4625
0.1uF
DP4621
1
OUTPUT
TPB+
11
SOT-363
2
TPB<R>
BAV99DW-X-F
2 402
FW_B_TPA_L_P
TPB-
9
2
44D7 44B5 FW_PORT1_TPB_P

to arbitrary value
NOTE: FireWire TPA/TPB pairs are NOT

constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints
to apply to entire TPA/TPB XNets.
4
2
C4627
C4626
0.01uF
0.01uF
5%
1/16W
MF-LF
402
20%
16V
CERM
402
20%
16V
CERM
402
=GND_CHASSIS_FW_PORT1
44B4
6A6
MAKE_BASE=TRUE
44B4
MAKE_BASE=TRUE
38B3
FW_A_TPB_N
FW_PORT2_TPB_N
38B3
FW_B_TPA_P
FW_PORT1_TPA_P
38B3
FW_B_TPA_N
FW_PORT1_TPA_N
38B3
FW_B_TPB_P
FW_PORT1_TPB_P
44B4
MAKE_BASE=TRUE
44C5 44D7
MAKE_BASE=TRUE
44C5 44D7
Cable Power
MAKE_BASE=TRUE
44C5 44D7
65C1 =PPFW_PORT2_VP
"Snapback" & "Late VG" Protection
L4630
MAKE_BASE=TRUE
38B3
FW_B_TPB_N
FW_PORT1_TPB_N
44C5 44D7 44D5 44A5 43B7
FERR-250-OHM
PP2V4_FWLATEVG
MAKE_BASE=TRUE
38D7 6C6
=PP3V3_FWPHY
R4652
R4653
56.2
56.2
1%
1/16W
MF-LF
2 402
R4662
R4663
56.2
1%
1/16W
MF-LF
402 2
DP4630
BAV99DW-X-F
56.2
1%
1/16W
MF-LF
2 402
DP4630
1%
1/16W
MF-LF
402 2
C4630
FW_B_TPB_L_N
FW_B_TPB_L_P
VOLTAGE=1.234V
VOLTAGE=1.234V
10%
50V
X7R
402
FW_PC0
C4631
10%
50V
X7R
402
1OMIT
L4663
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
0.001uF
20%
50V
CERM
402
PORT 2
1394A
2
4
1OMIT
L4662
FW_PORT2_TPA_P
44C5 FW_PORT2_TPA_N
44C5
SYM_VER-2
FW_PORT2_TPB_C
FW_PORT1_TPB_C
VOLTAGE=1.234V
VOLTAGE=1.234V
R4654 1
C4654
4.99K
220pF
Note: The peaking inductors
were changed to resistors to allow
placement in an area restricted by
DFM rules for only Rs and Cs
1%
1/16W
MF-LF
402
5%
25V
CERM
402
C4664
J4630
1394A
1210-4SM1
90-OHM-100MA
SYM_VER-2
F-RT-TH-LF
44D7
44D7
R4664 1
1%
1/16W
MF-LF
402
FW_PORT2_TPA_FL_P
FW_PORT2_TPA_FL_N
44D7
4.99K
5%
25V
CERM
402
44C5
FW_PORT2_TPB_N
44D7
1210-4SM1
90-OHM-100MA
DP4631
DP4631
BAV99DW-X-F
BAV99DW-X-F
SOT-363
FL4631
CRITICAL
FW_PORT2_TPB_FL_P
FW_PORT2_TPB_FL_N
(PPFW_PORT2_VP)
QTY
152S0414
DESCRIPTION
REFERENCE DES
IND,18nH-15mA,0402
L4660,L4661,L4662,L4663
CRITICAL
BOM OPTION
10%
50V
X7R
402
(TPA-)
TPI
(TPB+)
TPI#
(TPB-)
VGND
514-0255
8
10
C4633
0.01uF
CRITICAL
(TPA+)
TPO#
(GND_FW_PORT2_VG)
7
C4632
TPO
VP
SOT-363
2
6
PART NUMBER
CRITICAL
44C5 FW_PORT2_TPB_P
220pF
2
FL4630
CRITICAL
PPFW_PORT2_VP
VOLTAGE=33V
C4634
SOT-363
0.01uF
BAV99DW-X-F
SOT-363
0.01uF
1
38B5 =FW_PC0
2
SM
0.01uF
10%
50V
X7R
402
1
4
C4635
C4636
0.01uF
0.01uF
20%
50V
CERM
603
20%
16V
CERM
402
=GND_CHASSIS_FW_PORT2L
6B6
=GND_CHASSIS_FW_PORT2U
6A6
Late-VG Protection Power

FireWire Ports
R4699
6C6
R4690
=PP3V3_FWLATEVG
1
332
PP2V4_FWLATEVG
1%
1/16W
MF-LF
402
PP2V4_FWLATEVG needs to be biased

to at least 2.1V for FW signal integrity
and should be biased to 2.4V for margin
R4690 should be 390 Ohms max for a 3.3V rail
43B7 44B5 44D5
VOLTAGE=2.4V
CRITICAL
C4691
D4690
0.01UF
10%
50V
X7R
402
0
5%
1/16W
MF-LF
402
ESD and late-VG rail

for snap-back diodes
(Common to all ports)
=GND_CHASSIS_FW_EMI_R

MMBZ5227B
2
SYNC_DATE=(MASTER)
6B6
SOT23
SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
44
84
Camera Connector
=PP5V_S3_CAMERA
L4930
5A4 65B1
FERR-220-OHM
1
1
PP5V_S3_CAMERA_F
45B5 6A6
=GND_CHASSIS_CAMERA
VOLTAGE=5V
0.01UF
10%
50V
2 X7R
402
0402
NO STUFF
C4931
CRITICAL
20%
50V
CERM
402
CAMERA-M1-CUS
Connector shield
F-RT-SM
7
Connector shield
CRITICAL
FL4935
90-OHM-100MA
1210-4SM1
SYM_VER-1
1
1
Twin-Ax Pair 1
(40 AWG)
Twin-Ax Pair 2
(40 AWG)
Standard wires
(28 AWG)
0.001uF
J4931
USB2_CAMERA_N_F
USB2_CAMERA_P_F
2
3
4
C4932
6C3
5A4
=USB2_CAMERA_N
IO
6D3
5A4
=USB2_CAMERA_P
IO
NC
NC
CRITICAL
L4931
FERR-220-OHM-2A
8
GND_CAMERA
2
0603
518S0371
CRITICAL
L4950
FERR-220-OHM-2A
45C5 6A6
=GND_CHASSIS_CAMERA
2
0603
Camera Connector
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
45
84
Right USB Port
Port Power Switch

CRITICAL
CRITICAL
U5290
65B1
L5205
TPS2051
=PP5V_S3_RTUSB
PP5V_S3_RTUSB_ILIM
MSOP
2
IN
OUT
IN
OUT 7
OUT
64A6
=RTUSB_EN
EN
GND
1
C5290
10uF
20%
6.3V
CERM
805-1
C5291
FERR-220-OHM-2A
OC*
THRML
VOLTAGE=5V
PP5V_S3_RTUSB_F
VOLTAGE=5V
0603
C5205
0.01uF
6D3
20%
16V
CERM
402
CRITICAL
=RTUSB_OC_L
L5200
OUT
J5200
UAR2X
F-RT-SM-USB-RGT1
5
6
90-OHM-100MA
1210-4SM1
PAD
CRITICAL
SYM_VER-1
USB2_RT_MUXED_N
C5295
0.1UF
10uF
20%
10V
CERM
402
20%
6.3V
CERM
805-1
USB2_RT_MUXED_P
20%
2 6.3V
POLY
B2
VBUS
2 D-
USB2_RT_F_N
USB2_RT_F_P
C5296
100UF
3 D+
4 GND
RTUSB_ESD
D5200
C5206
RCLAMP0502B
1
8
0.01uF
20%
16V
CERM
402
SC-75
CRITICAL
CRITICAL
514S0115
L5206
FERR-220-OHM-2A
1
USB/SMC Debug Mux

65D3
=GND_CHASSIS_RTUSB
6B6
GND_RTUSB
VOLTAGE=0V
Place L5200, L5205 and L5206 across moat
=PP3V42_G3H_SMCUSBMUX
C5250
2
0603
1
1
R5250
0.1UF
20%
10V
CERM 2
402
8
2
10K
5%
1/16W
MF-LF
2 402
VDD
IO
IO
IO
6D3
IO
6D3
SMC_TX_L
SMC_RX_L
12
11
0I0
1I0
=USB2_RT_N 10
=USB2_RT_P 9
0I1
1I1
U5250
Y0
Y1
TDFN
SEL
CRITICAL
PI3USB10
13
THRM_PAD
GND
3
4
USB_DEBUGPRT_EN_L
50B3
SEL=0 Choose SMC

SEL=1 Choose USB
7
5
1
51B4 50B3 50B2

49C7 5C2
External USB Connector
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
46
84
Place XW5500 at 5V switcher
5D1
(2 Amps)
PP5V_S0_AUDIO_PWR
XW5500
SM
1
=PP5V_S0_AUDIO_XW
65A1
VOLTAGE=5V
65D3 5D1
(Input from LIO)
65A8 5D1
65B1 5D1
=PP1V5_S0_LIO
=PP3V42_G3H_LIO
=PPDCIN_G3H_LIO
=PP5V_S5_LIO
5D1
(500 mA)
PP5V_S0_AUDIO
XW5505
SM
1
VOLTAGE=5V
CRITICAL
65C6 5D1
J5500
QT510806-L111-7F
F-ST-SM
NC
50B2 49B7 5C1
50A2 49D5 43B7 5C1
50A2 49D7 5C1
34A3 5C1
34A3 5C1
26C1 5C1
50B3 6C3 5C1

6D3 5C1
53C3 5C1
49B5 5C1
49B5 5C1
50A2 49D7 5C1
50A2 49B7 5C1
50A2 49C5 5C1
64C6 5C1
53C5 5C1
64A6 5C1
49B7 5C1
84B4 21C7 5C1

84B4 21C7 5C1
84B4 21C7 5C1
84B4 21C7 5C1
SYS_ONEWIRE
SMC_ADAPTER_EN
SMC_BATT_CHG_EN
EXCARD_CLKREQ_L
MINI_CLKREQ_L
LIO_PLT_RESET_L
EXCARD_OC_L
LTUSB_OC_L
LIO_BATT_ISENSE
SMC_SYS_ISET
SMC_BATT_ISET
SMC_EXCARD_CP
SMC_BC_ACOK
LIO_P3V3S0_EN_L
LIO_DCIN_ISENSE
LIO_P3V3S3_EN
SMC_EXCARD_PWR_EN
ACZ_SDATAOUT
ACZ_BITCLK
ACZ_SDATAIN<0>
ACZ_SYNC
NC
81
84
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
82
83
NC
PCIE_WAKE_L
=SMBUS_LIO_SMC_SDA
=SMBUS_LIO_SMC_SCL
=USB2_EXCARD_N
=USB2_EXCARD_P
=USB2_LT_N
=USB2_LT_P
=SMBUS_LIO_SB_SCL
=SMBUS_LIO_SB_SDA
PCIE_CLK100M_MINI_N
PCIE_CLK100M_MINI_P
=PCIE_MINI_D2R_N
=PCIE_MINI_D2R_P
=PCIE_MINI_R2D_N
=PCIE_MINI_R2D_P
=PCIE_EXCARD_D2R_N
=PCIE_EXCARD_D2R_P
=PCIE_EXCARD_R2D_N
=PCIE_EXCARD_R2D_P
ACZ_RST_L
5B1 23C8 39C6

5B1 27D1
5B1 27D1
5B1 6C3
5B1 6C3
5B1 6D3
5B1 6D3
5B1 27B6
5B1 27B6
5B1 34D4
5B1 34D4
5B1 48C6
5B1 48C6
5B1 48C6
5B1 48C6
5B1 34B3
5B1 34C3
5B1 48B6
5B1 48C6
5B1 48C6
5B1 48C6
5C1 21C7 84B4
NC
516S0361
5C1
(500 mA)
GND_AUDIO
XW5515
SM
1
VOLTAGE=0V
5C1
(2 Amps)
GND_AUDIO_PWR
XW5510
SM
1
VOLTAGE=0V
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
47
84
PCI-E x1 Port "A" = Ethernet (Yukon)
PCI-E x1 Port "B" = PCI-E Mini Card

C5710
0.1uF
47B3 5B1
=PCIE_MINI_R2D_P
PCIE_MINI_R2D_C_P
PCIE_B_R2D_C_P
22D4
MAKE_BASE=TRUE
10%
16V
X5R
402
47B3 5B1
=PCIE_MINI_R2D_N
C5711
0.1uF
PCIE_MINI_R2D_C_N
Place caps close to SB

PCIE_B_R2D_C_N
22D4
PCIE_B_D2R_P
22D4
PCIE_B_D2R_N
22D4
MAKE_BASE=TRUE
10%
16V
X5R
402
47C3 5B1
=PCIE_MINI_D2R_P
47C3 5B1
=PCIE_MINI_D2R_N
PCIE_MINI_D2R_P
MAKE_BASE=TRUE
PCIE_MINI_D2R_N
MAKE_BASE=TRUE
PCI-E x1 Port "C" = ExpressCard
C5720
0.1uF
47B3 5B1
=PCIE_EXCARD_R2D_P
PCIE_EXCARD_R2D_C_P
PCIE_C_R2D_C_P
22D4
MAKE_BASE=TRUE
10%
16V
X5R
402
47B3 5B1
=PCIE_EXCARD_R2D_N
PCIE_EXCARD_R2D_C_N
C5721
0.1uF
1
Place caps close to SB

PCIE_C_R2D_C_N
22D4
PCIE_C_D2R_P
22D4
PCIE_C_D2R_N
22D4
PCIE_D_R2D_C_P
22D4
PCIE_D_R2D_C_N
22D4
PCIE_D_D2R_P
22D4
PCIE_D_D2R_N
22D4
PCIE_E_R2D_C_P
22C4
PCIE_E_R2D_C_N
22C4
PCIE_E_D2R_P
22C4
PCIE_E_D2R_N
22C4
MAKE_BASE=TRUE
10%
16V
X5R
402
47B3 5B1
=PCIE_EXCARD_D2R_P
47B3 5B1
=PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
MAKE_BASE=TRUE
PCIE_EXCARD_D2R_N
MAKE_BASE=TRUE
PCI-E x1 Port "D" = Unused

TP_PCIE_D_R2DP
MAKE_BASE=TRUE
TP_PCIE_D_R2DN
MAKE_BASE=TRUE
TP_PCIE_D_D2RP
MAKE_BASE=TRUE
TP_PCIE_D_D2RN
MAKE_BASE=TRUE
PCI-E x1 Port "E" = Unused

TP_PCIE_E_R2DP
MAKE_BASE=TRUE
TP_PCIE_E_R2DN
MAKE_BASE=TRUE
TP_PCIE_E_D2RP
MAKE_BASE=TRUE
TP_PCIE_E_D2RN
MAKE_BASE=TRUE
PCI-E x1 Port "F" = Unused

TP_PCIE_F_R2DP
PCIE_F_R2D_C_P
22C4
PCIE_F_R2D_C_N
22C4
PCIE_F_D2R_P
22C4
PCIE_F_D2R_N
22C4
MAKE_BASE=TRUE
TP_PCIE_F_R2DN
MAKE_BASE=TRUE
TP_PCIE_F_D2RP
MAKE_BASE=TRUE
TP_PCIE_F_D2RN
MAKE_BASE=TRUE
PCI-E Connections
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
48
84
65D3 50D7 50B1 49D4 49C2
=PP3V3_S5_SMC
OMIT
OUT
SMC_P20
50C5 SMC_P21
50C5 SMC_P22
50C5 SMC_P23
OUT SMC_BATT_TRICKLE_EN_L
SMC_BATT_CHG_EN
OUT
50C5 SMC_P26
50C5 SMC_P27
50C5
50A2 47B6 5C1

50A2 47C6 5C1
58C6 51C4 21D4 5D2
IO
58C6 51C4 21D4 5C2
IO
58C6 51C5 21D4 5C2
IO
58C6 51C5 21D4 5C2

58C6 51C4 21C5 5C2
IN
26B1
IN
34D6
IN
58C6 51C5 23C8 5C2
50C5
OUT
OUT
50A8
OUT
27B3
IO
50B5
50C5
50D5
50D5
IO
OUT
OUT
OUT
OUT
55A6
OUT
51B4 50B3 50B2 46B5 5C2
OUT
51B5 50B3 50B2 46B5 5C2
IO
50A2
47C6 43B7 5C1
P15
P65/KIN5*
C15
P16
P17
P66/IRQ6*/KIN6*
P67/IRQ7*/KIN7*
J13
SMC_PM_G2_EN
SMC_ADAPTER_EN
22C6 SPI_ARB
22C6 SPI_SCLK
22C6 SPI_SI
22C6 SPI_SO
50D1 SMC_PROCHOT_3_3_L
50D5 SMC_CPU_INIT_3_3_L
D13
P20
P70/AN0
N12
53B7
D14
D15
P21
P71/AN1
P22
P23
P72/AN2
P73/AN3
R13
P13
P24
P25
P74/AN4
P75/AN5
P26
P76/AN6
P27
P77/AN7
A15
B14
B15
C14
D12
E12
E14
E15
E13
F14
D9
C9
A9
B9
D8
C8
A8
D7
P13
P14
54C1
R15
N13
P15
P82/CLKRUN*
B7
D6
P83/LPCPD*
P84/IRQ3*/TXD1
P35/LRESET*
P85/IRQ4*/RXD1
C6
A6
P86/IRQ5*/SCK1/SCL1
B6
P90/IRQ2*
K4
P40/TMIO
P91/IRQ1*
P41/TMO0
P42/SDA1
P92/IRQ0*
P93/IRQ12*
J2
J1
P43/TMI1/EXSCK1
P94/IRQ13*
P44/TMO1
P45
P95/IRQ14*
P96/EXCL
SMC_TX_L
SMC_RX_L
SMB_0_S0_CLK
G1
P50
P51
P97/IRQ15*/SDA0
J3
J4
H2
H1
G2
SMC_WAKE_SCI_L
50C5 SMC_TPM_GPIO
58C6
23C8 5C2 PM_CLKRUN_L
51B5
23C5 5C2 PM_SUS_STAT_L
50B5 SC_TX_L
50B5 SC_RX_L
27B3 SMB_BSB_CLK
23C1
A7
P33/LAD3
P34/LFRAME*
P36/LCLK
P37/SERIRQ
SMC_CPU_ISENSE
53D6 SMC_CPU_VSENSE
53B6 SMC_GPU_ISENSE
53C6 SMC_GPU_VSENSE
53C4 SMC_DCIN_ISENSE
53D2 SMC_PBUS_VSENSE
53C2 SMC_BATT_ISENSE
50D5 SMC_NB1V5_ISENSE
R14
P14
P32/LAD2
P46/PWX0/PWM0
G4
F2
54C1
K14
J12
C7
D3
C1
C2
54C7
K13
P80/PME*
P81/GA20
A5
B5
C3
B1
P63/KIN3*
P64/KIN4*
L15
K12
P30/LAD0
P31/LAD1
SMC_XDP_TMS
SMC_SYS_LED_16B
SMB_BSB_DATA
SMC_TPM_PP
SMC_XDP_TRST_L
SMC_XDP_TCK
SMC_SYS_LED
SMC_SYS_KBDLED
D5
BGA
(1 OF 4)
51C4
58C6
50A2
22UF
OUT
20%
6.3V
2 CERM
805
OUT
IN
0.1UF
C5804
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
C5805
0.1UF
C5806
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
IN
IN
SMC_VCL
IN
IN
IN
IN
LAYOUT NOTE:
PLACE R5899 AND C5820 NEAR SMC PIN N14,N15
C5807
0.47UF
VCL IS INTERNAL RAIL
10%
6.3V
2 CERM-X5R
402
IN
IN
IN
IN
65D3 50D7 50B1 49D3 49C2
=PP3V3_S5_SMC
PP3V3_AVREF_SMC
R5899
1
OUT
4.7
5%
1/16W
MF-LF
402
IO
IN
OUT
C5820
0.1UF
OMIT
IN
IN
50C8
IN
50C8
R5809
10K
5%
1/16W
MF-LF
2402
BGA
(3 OF 4)
IN
51B5 50D6 5C2 IN
SMC_RST_L
E3
RES*
SMC_XTAL
SMC_EXTAL
A2
XTAL
B2
EXTAL
=PP3V3_S5_SMC
SMC_H8S2116
GND_SMC_AVSS
IN
IN
65D3
49D4 49D3
50D7 50B1
U5800
IO
55C2 53D6 53C6 53C1 53B7 53B5 53B3 53B1 50B6 49B2
55C6
50B6
PP3V3_AVCC_SMC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM
20%
10V
2 CERM
402
IN
SMC_ONOFF_L
50A2 47B6 5C1 SMC_BC_ACOK
66B5 50B2 5D1 SMC_BS_ALRT_L
64C8
43B7 42A8 23C3 PM_SLP_S3_L
64B8 41B6 23C3 PM_SLP_S4_L
50A2 23C3 PM_SLP_S5_L
35B2 SMC_SUS_CLK
27D6 SMB_0_S0_DATA
C5803
LAYOUT NOTE:
PLACE C5807 NEAR PIN F1
IN
IN
78C2
50C6 50B2 5B2
IN
OUT
MD1
E2
MD2
K1
NMI
F4
R5801
10K
5%
1/16W
MF-LF
2402
SMC_MD1
5C2 51B4
KBC_MDE
51B5 5C2
SMC_NMI
IN
SMC_TRST_L
IN
IN
IO
P47/PWX1/PWM1
ETRST*
AVSS
P52/SCL0
VSS
D1
P4
27D6
IN
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
PCI_CLK_SMC
INT_SERIRQ
L14
VCL F1
23C3
OUT
P61/KIN1*
P62/KIN2*
AVREF M14
AVREF M15
59C7
OUT
64A8
SMC_H8S2116
B4
D2
23C1
IN
OUT
L13
P11
P12
A4
50A4
23C3
P60/KIN0*
C13
VCC J15
VCC A1
IN
U5800
B13
A13
64B1 26A5
C5802
P10
VCC P2
VCC P1
OUT
B12
R4
6D4 6B7
PM_LAN_ENABLE
SMC_RSTGATE_L
ALL_SYS_PWRGD
RSMRST_PWRGD
SMC_SB_NMI
PM_RSMRST_L
IMVP_VR_ON
PM_PWRBTN_L
F12
F13
OUT
AVCC N14
AVCC N15
23C3
8
UNUSED PINS HAVE THE FORMAT
SMC_XXX WHERE XXX IS THE PORT NUMBER.
THEY ARE SET BY SOFTWARE TO BE
DRIVEN OUTPUTS ALWAYS SO THEY
CAN BE LEFT NO-CONNECTED.
L1
P12
R12
51B4 5C2
NOSTUFF
1
R5898
10K
5%
1/16W
MF-LF
2402
R5803
0
5%
1/16W
MF-LF
2402
R5802
10K
5%
1/16W
MF-LF
2402
OMIT
21C3
51B4 22B3 5C2
26C5 23C5 5B2
50B5
50D5 14B7
23C8
IN
IN
OUT
IN
IO
50B2 47C6 5C1
IO
23C1
OUT
23B8
23C8
36C4
53A8 5A2
50A2 47B6 5C1
47B6 5C1
50B5
50B2
OUT
56B7
56B4
50D5
50D5
IN
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
56B7
IN
56B4
IN
50D5
IN
50D5
IN
57C3
IN
57C3
IN
57C3
IN
50D5 IN
50D5
IN
50A2
IN
55C7
IN
55D2
IN
U5800
SMC_RCIN_L
BOOT_LPC_SPI_L
PM_SYSRST_L
SMC_USB_DEBUG_MUX
PM_EXTTS_L
PM_THRM_L
SYS_ONEWIRE
PM_BATLOW_L
R3
P3
PA0/KIN8*/PA2DC
R2
PA2/KIN10*/PS2AC
PA3/KIN11*/PS2AD
SMC_EXTSMI_L
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
ISENSE_CAL_EN
SMC_EXCARD_CP
SMC_EXCARD_PWR_EN
SMC_EXCARD_OC_L
SMC_XDP_TDO_3_3
B10
SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_NB_ISENSE
SMC_MEM_ISENSE
ALS_LEFT
ALS_RIGHT
N3
R1
N2
M4
N1
A10
D10
A11
PA1/KIN9*/PA2DD
SMC_H8S2116
BGA
(2 OF 4)
PA4/KIN12*/PS2BC
PA5/KIN13*/PS2BD
PA6/KIN14*/PS2CC
PA7/KIN15*/PS2CD
PB0/LSMI*
PB1/LSCI
PE0
PE1*/ETCK
PE2*/ETDI
PE3*/ETDO
PE4*/ETMS
PF6/PWM6
PF7/PWM7
A12
PB5
PB6
PG0/EXIRQ8*/TMIX
D11
PB7
PG1/EXIRQ9*/TMIY
PG2/EXIRQ10*/SDA2
G14
G15
PC0/TIOCA0/WUE8*
PG3/EXIRQ11*/SCL2
H15
H13
H12
M11
P11
R11
N11
P10
R10
PC1/TIOCB0/WUE9*
PC2/TIOCC0/TCLKA/WUE10*
PG4/EXIRQ12*/EXSDAA
PG5/EXIRQ13*/EXSCLA
PC3/TIOCD0/TCLKB/WUE11*
PG6/EXIRQ14*/EXSDAB
PC4/TIOCA1/WUE12*
PC5/TIOCB1/TCLKC/WUE13*
PG7/EXIRQ15*/EXSCLB
PC6/TIOCA2/WUE14*
PC7/TIOCB2/TCLKD/WUE15*
PD0/AN8
51B4 50B2
R6
N6
PB3
PB4
G12
H14
L4
L2
PF2/IRQ10*/TMOY
PF5/PWM5
G13
51B5 50B2 5C2
M7
PB2
B11
C11
51B5 50B2 5C2
M1
PF0/IRQ8*/PWM2
PF1/IRQ9*/PWM3
PF3/IRQ11*/TMOX
PF4/PWM4
PH0/EXIRQ6*
PH1/EXIRQ7*
PH2/FWE
PH3/EXEXCL
PD1/AN9
PH4
PD2/AN10
PD3/AN11
PH5
SMC_CASE_OPEN
SMC_TCK
SMC_TDI
5C2 SMC_TDO
5C2 SMC_TMS
M3
M2
P6
M6
R5
P5
N5
P9
R9
N9
P8
R8
M8
P7
R7
E1
F3
K2
C4
D4
B3
50A2
51B4 50B2
SMC_PF0
50C5
SMC_PF1
50C5
78C3 50B2 SMC_LID
50B2 SMC_CPU_RESET_3_3_L
47B6 5C1 SMC_BATT_ISET
50D5 SMC_BATT_VSET
47C6 5C1 SMC_SYS_ISET
50D5 SMC_SYS_VSET
SPI_CE_L
50B2 SMC_XDP_TCK_3_3
27C3 SMB_BSA_DATA
27C3 SMB_BSA_CLK
27C6 SMB_A_S3_DATA
27C6 SMB_A_S3_CLK
27D3 SMB_B_S0_DATA
27D3 SMB_B_S0_CLK
54C7 22C6
SMC_PROCHOT
50C2 SMC_THRMTRIP
50B2 SMC_FWE
78C6 6D5 5B2 ALS_GAIN
50B2 23C3 SMS_INT_L
57C6 SMS_ONOFF_L
50C2
IN
XW5800
SM
IN
IN
OUT
GND_SMC_AVSS
49C4 50B6 53B1 53B3 53B5 53B7 53C1 53C6 53D6 55C2
55C6
IN
IN
IN
OUT
OUT
OUT
OUT
IO
IN
IO
IO
IO
IO
IO
IO
OUT
OUT
IN
OUT
OUT
OUT
PD4/AN12
N10
PD5/AN13
PD6/AN14
M10
PD7/AN15
OMIT
U5800
SMC_H8S2116
BGA
(4 OF 4)
G3
H3
K3
L3
N4
M5
N7
M12
M13
L12
NC0
NC12
NC1
NC2
NC13
NC14
NC3
NC15
NC4
NC5
NC16
NC17
NC6
NC7
NC18
NC19
NC8
NC20
K15
NC9
NC10
NC21
NC22
J14
NC11
SMC
F15
A14

C5
A3
B8

E4
H4
M9
SIZE
N8
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7150
SCALE
C12
C10
A.0.0
OF
49
84
49D5
SMC_CPU_INIT_3_3_L
49A7
SMC_NB_ISENSE
FWH_INIT_L
MAKE_BASE=TRUE
SMC Reset Button / Brownout Detect
5C2 21C4 51C5
65A3
SMC_P1V05S0_ISENSE
SMC 1.05V to 3.3V Level Shifting
=PP3V3_S0_SMC_LS
53B2
MAKE_BASE=TRUE
65D3 50B1 49D4 49D3 49C2
=PP3V3_S5_SMC
49D5
SMC_NB1V5_ISENSE
SMC_P1V5S0_NB_ISENSE
53B4
MAKE_BASE=TRUE
49B7 14B7
C5900
1
2
0.1uF
20%
10V
CERM
402
RN5VD30A-F
5%
1/16W
MF-LF
402
OMIT
1
R5901
51B5 49C3 5C2
C5901
0.01UF
5%
1/10W
MF-LF
603
SMC_SYS_LED
5%
1/16W
MF-LF
402 2
49A7
SMC_ANALOG_ID
TP_SMC_SYS_LED
OUT
49B5
SMC_BATT_VSET
MAKE_BASE=TRUE
CRITICAL
49B5
SMC_SYS_VSET
49B7
SMC_FAN_2_CTL
50C1 7C6
49B7
SMC_FAN_3_TACH
49C7
SMC_XDP_TCK
SM-LF
1
SMC_PROCHOT_3_3_L
49D5
V-
R5971 1
1K
5%
1/16W
MF-LF
402
TP_SMC_FAN_2_TACH
MAKE_BASE=TRUE
SMC_FAN_3_CTL
CPU_PROCHOT_L
TP_SMC_FAN_2_CTL
SMC_FAN_2_TACH
49B7
LMC7211
V+
TP_SMC_SYS_VSET
MAKE_BASE=TRUE
49B7
U5977
2
4
VOLTAGE=0.46V
TP_SMC_BATT_VSET
1.05V Mid-Reference
MAKE_BASE=TRUE
MAKE_BASE=TRUE
10%
16V
CERM
402
20%
10V
CERM
402
P0V46_SMC_LSREF
TP_SMC_ANALOG_ID
0.1uF
6.2K
MAKE_BASE=TRUE
SMC_RST_L
GND
Silk: "SMC RST"
NC
OUT
CD
NC
49C7
C5977
R5970 1
28C3 29C3
R5900
SOT23-5
SMC_MANUAL_RST_L
DIMM_OVERTEMP_L
1K
VDD
U5900
PM_EXTTS_L
MAKE_BASE=TRUE
TP_SMC_FAN_3_CTL
MAKE_BASE=TRUE
TP_SMC_FAN_3_TACH
MAKE_BASE=TRUE
TP_SMC_XDP_TCK
MAKE_BASE=TRUE
Debug Power Button
49C7
SMC_XDP_TMS
MAKE_BASE=TRUE
49C7
SMC_XDP_TRST_L
49D7
SMC_P20
TP_SMC_XDP_TRST_L
C5920
1
SMC_XTAL
SMC_ONOFF_L
OUT
20.00MHZ
5X3.2-SM
C5921
15pF
1
SMC_EXTAL
SMC_P21
49D7
SMC_P22
TP_SMC_P21
Q5995
2N7002DW-X-F
TP_SMC_P22
MAKE_BASE=TRUE
49D7
SMC_P23
49D7
SMC_P26
49B5
SMC_PROCHOT
SOT-363
TP_SMC_P23
MAKE_BASE=TRUE
TP_SMC_P26
MAKE_BASE=TRUE
49D7
SMC_P27
49B5
SMC_PF0
49B5
SMC_PF1
TP_SMC_P27
MAKE_BASE=TRUE
TP_SMC_PF0
PM_THRMTRIP_L
TP_SMC_PF1
Q5995
SMC_TPM_GPIO1
2N7002DW-X-F
R5990
49D5
49B5
SMC_TPM_GPIO
TPM_GPIO1
PP3V3_AVREF_SMC
SOT23-3
1
IN
OUT
SMC_TPM_PP
R5995
49C7
GND
SMC_TPM_PP
TPM_GPIO2
58C6
TPM_PP
58C6
5%
1/16W
MF-LF
402
C5967
0.01uF
58C6
C5965
C5966
0.47UF
10uF
10%
6.3V
CERM-X5R
402
20%
6.3V
X5R
603
20%
16V
CERM
402
65C3 58C2
65C3 57C6
R5992
49C5
SC_RX_L
SMC_RX_L
49B5 23C3
5C2 46B5 49C7 50B2 51B5
58B7
5%
1/16W
MF-LF
402
R5993
GND_SMC_AVSS
VOLTAGE=0V
49C5
SC_TX_L
SMC_TX_L
78C2 50C6 49C5 5B2

5C2 46B5 49C7 50B2 51B4
78C3 49B5
49B2 49C4 53B1 53B3 53B5 53B7 53C1 53C6 53D6 55C2
55C6
49B7
5%
1/16W
MF-LF
402
SMC_EXCARD_OC_L
R5994
0
1
49B5
EXCARD_OC_L
51B4 50B3 49C7 46B5 5C2

5C1 6C3 47C6
51B5 50B3 49C7 46B5 5C2
R5996
49B7
SMC_USB_DEBUG_MUX
5%
1/16W
MF-LF
402
USB_DEBUGPRT_EN_L
49B7 47C6 5C1
46B3
5%
1/16W
MF-LF
402
66B5 49C5 5D1

51B4 49B5 5C2
51B4 49B5 5C2
SMC PWRGD Circuit
51B5 49B5 5C2

51B5 49C5 5C2
Reports when 5V S5 and 3.3V S5 are in regulation
System (Sleep) LED Circuit
49B5
65C1
65D3
=PP5V_S3_SYSLED
PP5V_S5
=PP3V42_G3H_SMC_PWRGD
49B5
49B7
49D7 47B6 5C1
R5951 1
2.2K
5%
1/16W
MF-LF
402 2
C5960
R5950
R5961 1
100
10K
5%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402 2
R5963
49D7 47C6 5C1
0.1uF
16.2K
1%
1/16W
MF-LF
2 402
SYS_LED_ILIM
20%
10V
CERM
402
49D5 47C6 43B7 5C1
49C5
49C5 47B6 5C1
49B7 47B6 5C1
2
4
P1V71_SMC_REF
1.71V Reference
Q5950
P5VS5_COMP_POS
2N3906
78B4
5%
1/16W
MF-LF
402 2
R5962 1
SYS_LED_ANODE
58C6 51B5 49C5 23C5 5C2

49C5 23C3
64A8
1
5
10K
SM-LF
1
V-
SOT23-LF
R5952 1
U5960
LMC7211
V+
SYS_LED_L_VDIV
OUT
10K
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
49A7
OUT
R5932
R5933
R5934
R5935
R5936
SMC_ONOFF_L
SMC_LID
SMC_FWE
SMC_TX_L
SMC_RX_L
R5937
R5938
R5939
R5940
R5941
R5942
R5980
R5981
R5982
SYS_ONEWIRE
SMC_BS_ALRT_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_CPU_RESET_3_3_L
SMC_XDP_TCK_3_3
SMC_XDP_TDO_3_3
SMC_BATT_CHG_EN
SMC_ADAPTER_EN
SMC_CASE_OPEN
SMC_BC_ACOK
SMC_EXCARD_CP
PM_SUS_STAT_L
PM_SLP_S5_L
SMC_MEM_ISENSE
5%
1/16W
MF-LF
402
10K
10K
10K
10K
470K
10K
100K
100K
100K
Q5952
63C7
2N7002
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SMC Support
SYNC_DATE=(MASTER)

IN
=P3V3S5_PGOOD
49D7
RSMRST_PWRGD
MAKE_BASE=TRUE
ISL6269 undervoltage threshold 81-87% (2.67 - 2.87V)

NOTE: R5965 acts as 10K pull-up for PGOOD signal
SOT23-LF

OUT

C5969
0.0022uF
2
2
SIZE
10%
50V
CERM
402
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7150
SCALE
5%
2.0K
100K
10K
10K
10K
10K
10K
10K
10K
SMC_SYS_LED_16B
10K
100K
10K
10K
100K
R5965
5V Comp threshold set to 4.480V (89.6%)
IN
R5943
R5944
R5945
R5946
R5947
R5948
R5983
R5984
R5985
10K
10K
10K
R5964
10K
P5VS5_PGOOD
R5930
R5931
SMS_INT_L
SMC_TPM_RESET_L
SYS_LED_L
49C7
=PP3V3_S5_SMC
=PP3V3_S3_TPM
=PP3V3_S3_SMS
65D3 50D7 49D4 49D3 49C2
SOT-363
5%
1/16W
MF-LF
402
49D2
VOLTAGE=3.3V
R5991
VR5965
REF3133
SMC_TPM_GPIO2
5%
1/16W
MF-LF
402
CRITICAL
=PP3V42_G3H_SMCVREF
SMC_THRMTRIP
SMC AVREF Supply
65B1
7C6 14B6 21C2
MAKE_BASE=TRUE
MAKE_BASE=TRUE
65D3
7C6 50D3
MAKE_BASE=TRUE
5%
1/10W
MF-LF
603
5%
50V
CERM
402
49D7
R5910
0
Silk: "PWR BTN"
TP_SMC_P20
MAKE_BASE=TRUE
OMIT
Y5920
49C3
78C2 50B2 49C5 5B2
5%
50V
CERM
402
CRITICAL
CPU_PROCHOT_L
MAKE_BASE=TRUE
15pF
49C3
SMC 3.3V to 1.05V Level Shifting
TP_SMC_XDP_TMS
SMC Crystal Circuit
A.0.0
OF
50
84
CRITICAL
LPCPLUS
J6000
QT500306-L021-9F
M-ST-SM
NC
50D3 21C4 5C2
34D6 5C2
58C6 49C7 21D4 5C2

58C6 49C7 21D4 5C2
58C6 49C7 23C8 5C2

58C6 50A2 49C5 23C5 5C2
50B2 49B5 5C2
50B2 49C5 5C2
50D6 49C3 5C2
49C1 5C2
50B3 50B2 49C7 46B5 5C2
23C3 23B6 5C2
FWH_INIT_L
PCI_CLK_PORT80_LPC
LPC_AD<2>
LPC_AD<3>
INT_SERIRQ
PM_SUS_STAT_L
SMC_TDI
SMC_TCK
SMC_RST_L
SMC_NMI
SMC_RX_L
SV_SET_UP
(GPIO15)
NC
32
31
10
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
34
33
NC
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
LPC_AD<0>
LPC_AD<1>
LPC_FRAME_L
PM_CLKRUN_L
BOOT_LPC_SPI_L
SMC_TMS
DEBUG_RST_L
SMC_TRST_L
SMC_TDO
SMC_MD1
SMC_TX_L
5D2 65D3
5D2 65A1
5D2 21D4 49D7 58C6

5C2 21D4 49D7 58C6
5C2 21C5 49C7 58C6

5C2 23C8 49C5 58C6
5C2 22B3 49C7
5C2 49B5 50B2
5C2 26B1
5C2 49C1
5C2 49B5 50B2
5C2 49C1
5C2 46B5 49C7 50B2 50B3
NC
516S0384
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
51
84
GPU/Heat Pipe & Bottom Case Skin Thermal Sensor
M-RT-SM
3
65B3
R6100
=PP3V3_S0_REMTHMSNS
1
NC
XW6110
SM
Placement note:
5B2
RSFSTHMSNS_D_P
47
PP3V3_S0_GPUTHMSNS_R
VOLTAGE=3.3V
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
Place on left side of fan cutout
C6110
4
NC
10%
50V
CERM
402
5B2
VCC
U6100
XW6111
UMAX
REMTHMSNS_DXP1
REMTHMSNS_DXN
REMTHMSNS_DXP2
XW6120
CRITICAL
SM
J6120
5B2
HSTHMSNS_DX_P
Placement note:
Place in between VRAM
DXP2
ALERT*
NC
OT1*
OT2*
10
NC
NC
CRITICAL
C6120
NC
27D3
27D3
XW6121
10%
50V
CERM
402
SM
HSTHMSNS_DX_N
NC
GND
0.0022uF
5B2
=SMBUS_REMTHMSNS_SDA
=SMBUS_REMTHMSNS_SCL
SMBDATA
SMBCLK
DXP1
DXN
M-RT-SM
3
20%
10V
CERM
402
MAX6695AUB
SM
RSFSTHMSNS_D_N
C6100
0.1uF
0.0022uF
518S0452
(TG0H)
(Th1H)
(Th0H)
CRITICAL
J6160
Placement note:
Keep all 4 XWs as close
to U6100 as possible
518S0452
GPU Die Thermal Sensor

65A3
=PP3V3_S0_GPU_TDIODE
C6150
0.1UF
10%
16V
X5R
402
R61511
10K
5%
1/16W
MF-LF
402 2
R6152
10K
5%
1/16W
MF-LF
2 402
R6160
74A3
ATI_TDIODE_P
499
GPUTHMSNS_DXP
1%
1/16W
MF-LF
402
(TG0T)
ATI_TDIODE_N
499
ALERT*/ 6
RSTHMSNS_ALERT_L
THM2*
THM* 4 RSTHMSNS_THM_L
C6160
0.001UF
R6161
74A3
VDD
10%
50V
CERM
402
2 D+
3 D-
U6150
TMP401
MSOP
GPUTHMSNS_DXN
1%
1/16W
MF-LF
402
SCLK 8
SDATA 7
27D3
27D3
=SMBUS_GPU_TDIODE_SCL
=SMBUS_GPU_TDIODE_SDA
IO
IO
GND
5
Placement note:
Place U6150 near GPU
Thermal Sensors
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
52
84
CPU Voltage Sense / Filter

65D1 53A6 9D7 8D7 8B5
XW6209
=PPVCORE_S0_CPU
CPUVSENSE_IN
4.53K
49D5
1%
1/16W
MF-LF
402
Place short near U0700 center
PBUS Voltage Sense Enable & Filter
SMC_CPU_VSENSE
Q6215
OUT
FDG6332C_NL
SC70-6
C6209
P-CHN
0.22UF
20%
6.3V
X5R
402
PPBUS_G3H
65C1
PPBUS_G3H_VSENSE
VOLTAGE=12.6V
R6285 1
GND_SMC_AVSS
49B2 49C4 50B6 53B1 53B3 53B5 53B7 53C1 53C6 55C2
55C6
27.4K
Place RC close to SMC
1%
1/16W
MF-LF
402
PBUSVSENS_EN_L
6
Rthevanin = 4573 ohms
49D5
64B6
=PBUSVSENS_EN
N-CHN
GPU Voltage Sense / Filter

XW6259
=PPVCORE_S0_GPU
R6259
SM
1
GPUVSENSE_IN
4.53K
Enables PBUS VSense divider when high.
49D5
R6286 1
FDG6332C_NL
SC70-6
1%
1/16W
MF-LF
402
0.22UF
20%
6.3V
X5R
402
2
2
OUT
C6259
49B2 49C4 50B6 53B1 53B3 53B5 53B7 53C6 53D6 55C2
55C6
0.22UF
2
OUT
C6285
5.49K
GND_SMC_AVSS
1%
1/16W
MF-LF
402
Place short near U8400 center
SMC_GPU_VSENSE
SMC_PBUS_VSENSE
Q6215
S
74A7 69D8 65A6 53A5
R6209
SM
1
20%
6.3V
X5R
402
GND_SMC_AVSS
49B2 49C4 50B6 53B1 53B3 53B5 53B7 53C1 53D6 55C2
55C6
C
DCIN Current Sense Filter
Battery Current Sense Filter
R6280
47B6 5C1
LIO_DCIN_ISENSE
IN
4.53K
R6290
49D5
1%
1/16W
MF-LF
402
SMC_DCIN_ISENSE
47C6 5C1
OUT
IN
LIO_BATT_ISENSE
0.22UF
R6270
1
2
1%
1/16W
MF-LF
402
49D5
SMC_CPU_ISENSE
68D1
OUT
IN
1
1%
1/16W
MF-LF
402
C6270
0.22UF
49D5
SMC_GPU_ISENSE
50D3
SMC_P1V5S0_NB_ISENSE
20%
6.3V
X5R
402
GND_SMC_AVSS
63B1
OUT
P1V05S0_IOUT
4.53K
1
20%
6.3V
X5R
402
50D3
49B2 49C4 50B6 53B1 53B3 53B5 53B7 53C1 53C6 53D6
55C2 55C6
OUT
C6240
20%
6.3V
X5R
402
GND_SMC_AVSS
49B2 49C4 50B6 53B1 53B3 53B5 53B7 53C1 53C6 53D6
55C2 55C6
SMC_P1V05S0_ISENSE
0.22UF
2
GND_SMC_AVSS
49B2 49C4 50B6 53B1 53B3 53B7 53C1 53C6 53D6 55C2
55C6
IN
1%
1/16W
MF-LF
402
C6235
0.22UF
1.05V S0 (NB) Current Sense Filter
0.22UF
20%
6.3V
X5R
402
GND_SMC_AVSS
49B2 49C4 50B6 53B1 53B3 53B5 53C1 53C6 53D6 55C2
55C6
2
1%
1/16W
MF-LF
402
0.22UF
2
OUT
C6290
R6240
4.53K
P1V5S0_NB_IOUT
IN
C6275
20%
6.3V
X5R
402
GND_SMC_AVSS
60A6
OUT
SMC_BATT_ISENSE
R6235
4.53K
GPUVCORE_IOUT
49B2 49C4 50B6 53B1 53B3 53B5 53B7 53C1 53C6 53D6
55C2 55C6
1.5V S0 (NB) Current Sense Filter
R6275
4.53K
CPUVCORE_IOUT
IN
49D5
GND_SMC_AVSS
59A5
20%
6.3V
X5R
402
GPU Current Sense Filter
4.53K
1%
1/16W
MF-LF
402
C6280
CPU Current Sense Filter
49B2 49C4 50B6 53B1 53B3 53B5 53B7 53C1 53C6 53D6
55C2 55C6
Current Sense Calibration Circuit

Switches in fixed load on power supplies to calibrate current sense circuits
Q6229
FDG6332C_NL
SC70-6
65D1 53D7 9D7 8D7 8B5
65A1 5A2
R6229 1
5%
1/16W
MF-LF
402
470K
ISENSE_CAL_EN_LS5V
470K
R6228
5%
1/16W
MF-LF
402
1.00
1%
1/4W
MF-LF
1206
=PP1V05_S0_REG
FDM6296
1.05A / 1.1W
CRITICAL
FDM6296
MICROFET3X3
Current & Voltage Sensing
Q6223
4
S
1

100K
5%
1/16W
MF-LF
402
SYNC_DATE=(MASTER)
MICROFET3X3
S
1
P1V05S0_ISENSE_CAL
Q6221
4
SC70-6
1%
1/4W
MF-LF
1206
CRITICAL
MICROFET3X3
FDG6332C_NL
1.00
1.2A / 1.44W
FDM6296
R6223 1
GPUVCORE_ISENSE_CAL
CRITICAL
Q6220
Q6229
R6227 1
R6221
1%
1/4W
MF-LF
1206
D
N-CHN
ISENSE_CAL_EN
65D8 63A2 5B2
1.00
CPUVCORE_ISENSE_CAL
IN
=PPVCORE_S0_GPU
49B7 5A2
74A7 69D8 65A6 53C7
R6220
ISENSE_CAL_EN_L
=PPVCORE_S0_CPU
P-CHN
=PP5V_S0_ISENSECAL

2

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
53
84
65C3
=PP3V3_S5_ROM
1
0.1UF
R63021 R63011
3.3K
20%
2 10V
CERM
3.3K
5%
1/16W
MF-LF
402 2
402
5%
1/16W
MF-LF
402 2
C6312
R6308
8
10K
OMIT
5%
1/16W
MF-LF
402
VDD
U6301
16MBIT
R6307
1
SPI_CE_L
22pF
5%
50V
402
NOSTUFF
1
C6308 R6309
22pF
10K
5%
2 50V
CERM
402
SI
SCK
SPI_SI_R
SST25VF016B
SPI_WP_L
SPI_HOLD_L
C6309
2 CERM
R6306
SOI
SPI_SCLK_R
5%
1/16W
MF-LF
402
49B5 22C6
SPI_SCLK
3
7
CE*
WP*
HOLD*
47
SPI_SI
22C6 49D5
SPI_SO
22C6 49D5
5%
R6303 1/16W
MF-LF
SO
SPI_SO_R
47
5%
1/16W
MF-LF
402
VSS
402
C6301
22pF
5%
2 50V
CERM
C6311
22pF
402
5%
1/16W
MF-LF
402
5%
2 50V
CERM
402
49D5 22C6
47
CRITICAL
R6309 IS NOT NEEDED WHEN SHARING SPI FLASH WITH

ICH7M AND TEKOA(LAN CHIP)
R6307 AND R6306 SHOULD BE PLACED LESS THAN 100 MILS FORM ICH7M
R6303 SHOULD BE PLACED LESS THAN 100 MILS FORM FLASH ROM
SPI BOOTROM
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
54
84
Right ALS Circuit

65C3
=PP3V3_S3_RTALS
C6405
0.1UF
20%
10V
CERM
402
Left ALS Filter
CRITICAL
U6405
4
V+
RTALS_PHOTODIODE
R6430
78C6 5B2
LTALS_OUT
3.48K
1%
1/16W
MF-LF
402
49A7
ALS_LEFT
OUT
20%
6.3V
X5R
402
GND_SMC_AVSS
R6400
BS520EOF
0.22UF
2
RTALS_OP_IN
5%
1/16W
MF-LF
402
4.53K
49A7
C6400
ALS_RIGHT
OUT
C6410
0.22UF
20%
6.3V
X5R
402
GND_SMC_AVSS
0.01UF
2
1%
1/16W
MF-LF
402
V-
5.1M
TH
R6410
ALS_RT_OUT
1%
1/16W
MF-LF
402
CRITICAL
PD6400
C6430
1K
MAX4236EUTT
SOT23-6-LF
1
R6401
Left ALS circuit has 1K series-R
20%
16V
CERM
402
C6406
20%
6.3V
X5R
402
49B2 49C4 50B6 53B1 53B3 53B5 53B7 53C1 53C6 53D6
55C6
R6406
120K
0.22UF
49B2 49C4 50B6 53B1 53B3 53B5 53B7 53C1 53C6 53D6
55C2
RTALS_OP_IN and RTALS_OP_COMP need to be matched
2
2
5%
1/16W
MF-LF
402
RTALS_OP_COMP
R6408 1
1K
1%
1/16W
MF-LF
402
R6407
15.0K
1%
1/16W
MF-LF
402
RTALS_GAIN_L
3
Q6408
2N7002
6D4
IN
=RTALS_GAIN
SOT23-LF
S
2
Keyboard LED Driver
B
CRITICAL
L6450
65A1
22uH
=PP5V_S0_KBDLED
1
KBDLED_SW
3.8x3.8x1.5MM
65B3
=PP3V3_S0_KBDLED
KBDLED_NOT
R6451 1
C6450
10%
6.3V
CERM
402
5%
1/16W
MF-LF
402 2
49C7
IN
1
1
1uF
10K
VDD
2
CRITICAL
SW
U6450
MM3120
LLP
VOUT
78C3
KBDLED_ANODE
FB
78C3
KBDLED_RETURN
THRML_PAD
CNTRL
NC
SMC_SYS_KBDLED
NC
KBDLED_HAS
R6452 1
1
1
10K
5%
1/16W
MF-LF
402
NC
PGND
5
AGND
2
C6455
0.22uF
20%
25V
X5R
603
OUT
IN
R6455
25.5
1%
1/8W
MF-LF
2 805
ALS Support
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
55
84
Left Fan
65A1 5D2
65A3
Right Fan
=PP5V_S0_FAN_LT
=PP3V3_S0_FAN_LT
65A1
65A3
=PP5V_S0_FAN_RT
=PP3V3_S0_FAN_RT
CRITICAL
CRITICAL
J6550
R6550
5%
1/16W
MF-LF
402
R6555
SMC_FAN_0_TACH
47K
5D2
NC
49B7
SMC_FAN_0_CTL
2N7002DW-X-F
SOT-363
SMC_FAN_1_TACH
5D2
47K
5D2
NC
2
3
4
R6561 1
NC
100K
5%
1/16W
MF-LF
402
518S0369
FAN_LT_PWM
49B7
SMC_FAN_1_CTL
2N7002DW-X-F
SOT-363
Q6560
2
1
M-RT-SM
5
FAN_RT_TACH
5%
1/16W
MF-LF
402
Q6560
2
4
49B7
100K
5%
1/16W
MF-LF
402
R6565
NC
SM04B-ACH
47K
R6551 1
5
R6560
M-RT-SM
5
FAN_LT_TACH
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
J6560
SM04B-ACH
47K
49B7
5D2
518S0369
FAN_RT_PWM
Fan Connectors
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
56
84
65C3 50B1
APN:338S0354
=PP3V3_S3_SMS
1
13
14
R66201
10K
5%
1/16W
MF-LF
402
C6620
0.1uF
2
VDD
20%
10V
CERM
402
U6620
KXPS5-2050
49A5
2
3
5
6
12
SMS_ONOFF_L
LGA
X
CRITICAL
Y
CS*
Z
ADDR/SDI
SCL/SCLK
FF/MOT
ENABLE
SDA/SDO
MOT_ENABLE
7
8
9
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
11
4
49B7
49B7
49A7
TP_SMS_FF
10
GND
1
C6605
0.033UF
0.033UF
20%
10V
X7R
402
20%
10V
X7R
402
Desired orientation when
placed on board top-side:
placed on board bottom-side:
+Y
+Z (up)
C6606
0.033UF
20%
10V
X7R
402
Top-through View
+Y
+X
Desired orientation when
Package Top
C6604
+X
+Z (dn)
M59 placement: Bottom-side
Sudden Motion Sensor (SMS)
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
57
84
=PP3V3_S0_TPM
TPM
1
TPM
C6700
0.1UF
10%
16V
2 X5R
402
C6701
0.1UF
10%
16V
2 X5R
402
TPM
1
NOSTUFF
C6702
R6705
10%
16V
2 X5R
402
5%
1/8W
MF-LF
2 805
OMIT
65B3 58D4
51C4 49D7 21D4 5D2
IO
51C4 49D7 21D4 5C2
IO
51C5 49C7 21D4 5C2
=PP3V3_S0_TPM
51C5 49C7 21D4 5C2
NOSTUFF
34D6
R6700
LAYOUT NOTE:
PLACE WHERE ACCESSIBLE
50B3
IO
IO
IN
51C4 49C7 21C5 5C2
IN
51B5 50A2 49C5 23C5 5C2
IN
26
LAD0
23
20
LAD1
TPM
VDD
TSSOP
VDD
17
LAD2
LAD3
PCI_CLK_TPM
LPC_FRAME_L
21
LCLK
PM_SUS_STAT_L
INT_SERIRQ
PM_CLKRUN_L
28
27
51C5 49C7 23C8 5C2
IO
51C4 49C5 23C8 5C2
IO
22
16
15
TPM_GPIO1
NC
50C3
10
19
24
TPM
R6704
VNC
LFRAME*
TPM_GPIO2
NC
12
NC
TPM_XTALI
TPM_XTALO
TPM
VOLTAGE=3.3V
NC
VBAT
LRESET*
LPCPD*
0.1UF
SERRIRQ
CLKRUN/GPIO*
R6702
PP/GPIO
GPIO_EXPRESS_00
5%
1/16W
MF-LF
2 402
(INT PD)
PP
XTALI/32K_IN
14
XTALO
=PP3V3_S3_TPM
50B1 65C3
BASE ADDR = 0X4E/4F
GPIO
13
5%
1/8W
MF-LF
805
10K
6
1
GPIO/SM_DAT
NC
GPIO/SM_CLK
C6703
10%
16V
2 X5R
402
TPM
NC
PP3V3_TPM_3VSB
VSB
TESTBI/BADD/GPIO
TESTBI/BADD
TESTI
9
8
LAYOUT NOTE:
PLACE R6702-03 WHERE ACCESSIBLE
TPM_BADD
NOSTUFF
1
GND
4 GND0
11 GND1
18 GND2
25 GND3
35D5
3V2
VDD
GPIO2
35C5
3V1
CLKRUN*
TPM_PP
50C3
3V0
3VSB
5%
1/16W
MF-LF
2 402
U6700
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
NOTE:
SINCE CURRENT OF VSB IS NOT YET ON SPEC,
1/8W (R6704/R6705) IS USED FOR NOW
0.1UF
65B3 58C7
R6703
10K
5%
1/16W
MF-LF
2 402
BASE ADDR = 0X2E/2F
TPM
R6798
26B1
IN
TPM_LRESET_L
5%
1/16W
MF-LF
402
TPM_RST_L
NOSTUFF
R6799
50B2
IN
SMC_TPM_RESET_L
5%
1/16W
MF-LF
402
TPM
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
58
84
65C1 59D7
=PPVIN_S0_IMVP6
These caps for Q7500
R7530
10
1
CRITICAL
VOLTAGE=5V
10
10
1
5%
1/16W
MF-LF
402
C7531
499
10%
16V
X5R
402
C7528
R7544
10%
16V
X5R
603
C7546
0.01uF
470K
10%
16V
CERM
402
402
7A3
64B2
R7547
26A7
49D7
4.02K
C7532
R7532
26B5 14B6
147K
0.015uF
10%
16V
X7R
402
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
22
5C7
41
40
39
38
37
VDD
VID6
820pF
46
45
2
3
47
44
1
5
6
(GND_IMVP6_SGND)
IMVP6_SOFT
IMVP6_RBIAS
(GND_IMVP6_SGND)
IMVP6_VDIFF
VID4
U7530
ISL9504CRZ
QFN
VID3
UGATE1
VID2
2
2
5C7
R7536
1%
1/16W
MF-LF
402
1.82K
CCM
1-Phase
CCM
1-Phase
DCM
1-Phase
DCM
PHASE1 34
VID0
LGATE1
20%
25V
X5R
603
32
2
5C7
5%
1/16W
MF-LF
402 2
Q7501
RJK0301DPB
LFPAK
RJK0301DPB
(GND)
IMVP6_ISEN1
DPRSLPVR
2
20%
6.3V
X5R
402
NO STUFF
C7501
0.0022UF
2
1 2 3
R7506
C7502
0.0022UF
10%
50V
CERM
402
1%
1/10W
MF-LF
603
10%
50V
CERM
402
(IMVP6_ISEN1)
PSI*
PGD_IN
UGATE2
PHASE2
27
IMVP6_UGATE2
28
IMVP6_PHASE2
30
IMVP6_LGATE2
3V3
CLK_EN*
LGATE2
VR_ON
PGND2 29
VR_TT*
ISEN2
CRITICAL
(GND)
Q7550
PGOOD
RJK0305DPB
LFPAK
23
IMVP6_ISEN2
19
IMVP6_VSUM
5C7 IMVP6_OCSET
IMVP6_VO
59A2 IMVP6_DROOP
NTC
CRITICAL
VSUM
SOFT
VO 18
RBIAS
16
R7540
IMVP6_DFB
VSEN 14
10
COMP
10%
50V
CERM
402
C7580
10%
25V
CERM
402
NC
1%
1/16W
MF-LF
402
RTN 15
VW
R7541
TPAD
R7557 1
1
CRITICAL
5%
50V
CERM
402
5%
1/16W
MF-LF
402 2
Q7551
RJK0301DPB
LFPAK
R7542
C7555
R7555
13.7K
180pF
1%
1/16W
MF-LF
2 402
2
SM-IHLP
4
1
C7540
1K
0.001uF
3.01K
1
FB2
FB
0.36UH-30A-1.2M-OHM
(IMVP6_PHASE2)
NO STUFF
C7542
5C7
L7555
1 2 3
VDIFF
GND
CRITICAL
1%
1/16W
MF-LF
402
Q7552
10K
0.22UF
1
1%
1/16W
MF-LF
402
RJK0301DPB
1 2 3
LFPAK
(IMVP6_VO)
C7543
470pF
R7543
R7548
11K
R7556
3.65K
NO STUFF
1
5.23K
1%
1/16W
MF-LF
402
2
10%
16V
CERM
402
2
20%
6.3V
X5R
402
49
21
GND_IMVP6_SGND
10%
50V
CERM
402
3.65K
IMVP6_LGATE1
ISEN1 24
0.22UF
1%
1/16W
MF-LF
402
1
0.0068uF
C7535
C7505
10K
1
Q7502
LFPAK
NO STUFF
PGND1 33
IMVP6_PHASE1
0.01uF
10%
50V
CERM
402
R7507
CRITICAL
0.22uF
20%
25V
X5R
603
65D3
SM-IHLP
IMVP6_UGATE1
(IMVP6_FB)
820pF
=PPVOUT_S0_IMVP6_REG
2
DPRSTP*
R7533
C7534
L7505
C7500
CRITICAL
(Inductors limit)
(IMVP6_PHASE2)
IMVP6_VDIFF_RC
1%
1/16W
MF-LF
402
0.22uF
301
1%
1/16W
MF-LF
402 2
10%
16V
X5R
603
VID1
11
C7550
IMVP6_BOOT1
IMVP6_BOOT2
35
DFB 17
25
R7535 1
36
BOOT2 26
DROOP
13
12
IMVP6_FB2
5C7 IMVP6_FB
5D7 IMVP6_COMP
IMVP6_VW
2.0K
10%
50V
CERM
402
2-Phase
1 2 3
BOOT1
OMIT
VID5
0.36uH-30A-1.2M-OHM
PVCC
NO STUFF
C7533
31
OCSET
5D7
20%
16V
POLY
CASED2E-SM
R7505
42
OUT VR_PWRGD_CK410_L
IN IMVP_VR_ON
OUT VR_PWRGOOD_DELAY
IMVP6_VR_TT
IMVP6_NTC
20%
16V
POLY
CASED2E-SM
C7561
1uF
33uF
CRITICAL
43
IN CPU_DPRSTP_L
84C6 IMVP_DPRSLPVR
IN CPU_PSI_L
IN IMVP_PWRGD_IN
C7560
33uF
36A max output
48
1
20
IMVP6_NTC_R
1
21C4 7B3
10%
16V
X5R
603
CRITICAL
1
C7515
Vout = Variable
CRITICAL
R7546
20%
16V
POLY
CASED2E-SM
1 2 3
VIN
(IMVP6_NTC)
1uF
9C1 IMVP6_VID<6>
9C1 IMVP6_VID<5>
9C1 IMVP6_VID<4>
9C1 IMVP6_VID<3>
9C1 IMVP6_VID<2>
9C1 IMVP6_VID<1>
9C1 IMVP6_VID<0>
RJK0305DPB
1uF
1%
1/16W
MF-LF
402
C7511
LFPAK
R7545
PM_DPRSLPVR
Q7500
20%
6.3V
CERM
603
0.1uF
1%
1/16W
MF-LF
402
2
IN
CRITICAL
DPRSLPVR DPRSTP* PSI* Operation Mode
VOLTAGE=12V
499
84C6 23C3 14B7
33uF
C7529
PPVIN_S0_IMVP6_R
VOLTAGE=3.3V
1
C7510
CRITICAL
1uF
PP3V3_S0_IMVP6_R
C7530
10%
6.3V
CERM
402
5%
1/16W
MF-LF
402
R7528
=PP3V3_S0_IMVP6
R7531
=PPVIN_S0_IMVP6
4.7uF
PP5V_S0_IMVP6_VDD
2
5%
1/16W
MF-LF
402
65B3
These caps for Q7550
=PP5V_S0_IMVP6
5
65C1 59D4
1%
1/16W
MF-LF
402 2
NO STUFF
C7551
0.0022UF
2
1 2 3
C7552
0.0022UF
10%
50V
CERM
402
1%
1/10W
MF-LF
603
10%
50V
CERM
402
IMVP6_VO_R
IMVP6_COMP_RC
(IMVP6_VW)
CRITICAL
R7534 1
C7537
107K
1%
1/16W
MF-LF
402 2
5%
50V
CERM
402
R7537
R7549
C7544
4.42K
47pF
2
1%
1/16W
MF-LF
402
2
10KOHM-5%
0.22uF
20%
6.3V
X5R
402
R7581
0603-LF
2
(IMVP6_ISEN2)
(IMVP6_COMP)
CPU_VCCSENSE_P
8B6 84B6
5%
1/16W
MF-LF
402
(IMVP6_VSUM)
(IMVP6_VO)
84B6
R7582
IMVP6_VSEN_P
84B6 IMVP6_VSEN_N
0
1
NO STUFF
C7541
0.22UF
XW7530
SM
2
20%
6.3V
X5R
402
C7582
0.01uF
2
10%
16V
CERM
402
CPU VCore Current Sense
C7581
0.01uF
10%
16V
CERM
402
<Ra>
C7598
65A3
=PP3V3R5V_S0_CPUISENS
CPU_VCCSENSE_N
8B6
84B6
R7594
30.1K
CPUISENS_NEG
2
5%
1/16W
MF-LF
402
<Rb>
R7593
470pF
1
CPUISENS_NEG_RC
0
1
C7595
<Rc>
10%
50V
CERM
402
1uF
10%
6.3V
CERM
402
1%
1/16W
MF-LF
402
R7598
1
1M
NO STUFF
1
2
1%
1/16W
MF-LF
402
CRITICAL
5%
1/16W
MF-LF
402
C7594
0.1uF
20%
10V
CERM
402
IMVP6 CPU VCore Regulator
U7595
HPA00141AIDCKR
SC70-5
53B8
Vout
OUT
CPUVCORE_IOUT
V+
SYNC_DATE=(MASTER)
V-
= Gain * ((2.1 mV/A * Iload) + Voffset)
Voffset = (Vdrp_offset * Kdroop) + Vamp_offset
<Rc>

<Ra + Rb>
Gain
R7592
= Rc / (Ra + Rb)
1
1M
R7591
CPUISENS_POS
30.1K
Voffset worst-case ~2.3mV (+/- ~1A offset)
C7592
Vout @ 36A = 2.44V-2.60V
470pF
1
IMVP6_DROOP
59C6
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
SIZE
APPLE COMPUTER INC.

10%
50V
CERM
402
65A1
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
59
84
7
65C1
=PPVIN_S5_P5VP1V5
CRITICAL
1
CRITICAL
1
C7640
1uF
20%
16V
POLY
CASED2E-SM
C7641
33uF
20%
16V
POLY
CASED2E-SM
5%
1/16W
MF-LF
402
C7681
1uF
33uF
10
10%
16V
X5R
603
C7680
R7600
10%
16V
X5R
603
D
0.1uF
2
60B3
60D3
PP5V_S5_P5VP1V5_INTVCC
C7620
10%
16V
X5R
402
1
R7629
CRITICAL
1%
1/16W
MF-LF
402
=PP5V_S5_REG
C7624
CRITICAL
0.1uF
L7620
2.0UH
(Q7621 limit)
1
20%
10V
CERM
402
C7650
150UF
20%
6.3V
CERM
805
20%
6.3V 2
POLY
CASE-C3
P5VS5_TG
P5VS5_BOOST
BOOST1
P5VS5_SW
SW1
26
TG1
P5VS5_BG
Q7621
C7622
G
MICROFET3X3
C7651
10%
50V
CERM
402
NO STUFF
1
P5VS5_SNS_P
P5VS5_SNS_N
0.001uF
20%
6.3V
CERM
805
C7621
1000pF
30
P5VS5_VOSNS
P5VS5_ITH
P5VS5_RUNSS
C7627
C7626
47PF
1%
1/16W
MF-LF
402 2
U7600
LTC3728LXC
C7625
47pF
5%
50V
2 CERM
402
PLLIN
PLLFLTR
SENSE1+
SENSE2+
SENSE2-
VOSENSE1
VOSENSE2
ITH2
ITH1
28
10%
50V
CERM
402
21
15
P1V5S0_SW
P1V5S0_BG
P5VP1V5_FSEL
11
9
P1V5S0_VOSNS
P1V5S0_ITH
SGND
R7625
C7628
33K
0.1uF
5%
1/16W
MF-LF
2 402
10%
25V
X7R
402
C7630
20%
10V
CERM
402
27
INTVCC
20
NC1
10
NC2
16
NC3
NC4
29
=PP1V5_S0_REG
MICROFET3X3
C7664
0.1uF
20%
10V
CERM
402
CRITICAL
8A max output
L7660
2.2uH-14A
(L7660 & Q7660 limit)
2
IHLP2525CZ-SM
CRITICAL
1
CRITICAL
1
C7662
C7690
0.001uF
2
Q7661
C7691
SO-8
P1V5S0_RUNSS
10%
25V
X7R
402
C7666
470pF
2
NC
NC
NC
NC
20%
6.3V
CERM
805
5%
50V
CERM
402
C7667
100pF
10%
50V
CERM
402
22UF
C7665
20%
2 2.5V
POLY
CASE-D2E-LF
NO STUFF
C7661
C7692
330UF
20%
6.3V
CERM
805
IRF7832Z
10%
50V
CERM
402
5A2 65C8
Vout = 1.49V
60B3
32
1%
1/16W
MF-LF
402
FDM6296
NC
PGOOD
1.21K
CRITICAL
22UF
P1V5S0_SNS_R_P
P1V5S0_SNS_R_N
12
EXTVCC
1000pF
2
P1V5S0_BOOST
3_3VOUT
10K
1%
1/16W
MF-LF
402 2
P1V5S0_TG
13
FCB
33
NO STUFF
1
14
18
10%
16V
X5R
402
17
RUN_SS2
470pF
5%
50V
CERM
402
RUN_SS1
P5VS5_ITH_RC
<Rb>
1
R7628
SW2
BG2
SENSE1-
52.3K
BOOST2
0.1uF
2
2
Q7660
5%
1/16W
MF-LF
402
1000pF
10%
25V
X7R
402
TG2
CRITICAL
BG1
NC
<Ra>
R7627 1
1%
1/16W
MF-LF
402
R7669 1
R7664
0
VIN
22UF
2
5%
1/16W
MF-LF
402 2
C7660
FDM6296
1
1M
CRITICAL
R7670 1
5%
1/16W
MF-LF
2 402
22UF
P1V5S0_BOOST_RC
R7630
QFN
SM-IHLP
CRITICAL
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1M
Q7620
MICROFET3X3
11.5A max output
R7624 1
FDM6296
Vout = 4.98V
C7652
23.7K
65B3
3.65K
CMDSH-3
10%
16V
X5R
603
P5VS5_BOOST_RC
R7660 1
SOD-323
1uF
2
909
2
60B3
60D6
D7664
C7600
CMDSH-3
1%
1/16W
MF-LF
402
R7663
CRITICAL
1
1
SOD-323
4.53K
2
VOLTAGE=12V
D7624
R7620
0.1uF
PPVIN_S5_P5VP1V5_R
CRITICAL
0.1uF
10%
16V
X5R
402
PGND
C7663
10%
16V
X5R
402
10%
50V
CERM
402
<Ra>
R7667
34.0K
470pF
2
1%
1/16W
MF-LF
2 402
P1V5S0_ITH_RC
C7670
R7665
C7668
10K
0.1uF
20%
10V
CERM
402
NO STUFF
<Rb>
R7668
39.2K
1000pF
5%
1/16W
MF-LF
402 2
10%
25V
X7R
402
1%
1/16W
MF-LF
2 402
GND_P5VP1V5_SGND
VOLTAGE=0V
XW7600
C7607
Connect to RUNSS pins to control outputs.

If unconnected, powers up with VIN.
NOTE: Be aware of pull-ups to VIN on these signals.
Vout = 0.8V * (1 + Ra / Rb)
=P5VP1V5_PGOOD
SM
0.01uF
64C2
10%
16V
CERM
402
60D3 60D6
VOLTAGE=5V
5V S0 FET
P5VP1V5_SKIP
1
C7601
0
5%
1/16W
MF-LF
402
4.7uF
20%
6.3V
CERM
603
R7603
65B1
5%
1/16W
MF-LF
402
P5VP1V5_FSEL
=PP5V_S5_P5VP1V5_VCC
C7605
5%
1/16W
MF-LF
402
1uF
10%
6.3V
CERM
402
6 7
CRITICAL
Q7615
R7615
1
R7607
0
60C4
P5VP1V5_CONT
1
=PP5V_S0_P5VS0
30K
P5VP1V5_FCB
65B1
R7604
C7602
10K
1uF
5%
1/16W
MF-LF
402
10%
6.3V
CERM
402
64C6
C7604
=P5VS0_EN_L
IRF7707PBF
P5VS0_EN_L_RC
TSSOP
5%
1/16W
MF-LF
402
0.01uF
2
100K
10%
16V
CERM
402
=PP5V_S0_FET
1 5
1
65C6
=PP1V5_S0_NB1V5_SENSE
R7675
0.002
1%
1/4W
MF-LF
1206
=PP1V5_S0_NB
C7672
22UF
20%
2 6.3V
CERM
805
NB1V5_ISENSE_VCC
C7671
C7675
22UF
0.1UF
20%
2 6.3V
CERM
805
=PP3V3_S0_NB1V5ISENS
C7615
C7616
NB1V5_ISENSE_R1_N
1 R1-
V+
R7672
2.0K
1%
1/16W
MF-LF
2 402
NB1V5_ISENSE_R1_P
8 R1+
3
V-
65B1
SM-LF
=PP5V_S3_P5VS3
=PP5V_S3_FET
65B3
6
5
P1V5S0_NB_IOUT
53B5
5V / 1.5V Power Supply
CRITICAL
U7670
MSOP
3
R7674
C7610
0.0022uF
100K
1%
1/16W
MF-LF
402
SYNC_DATE=(MASTER)
INA326EA-250
NB1V5_ISENSE_R2
R7610
C7674
0.001UF
64B6
=P5VS3_EN_L
10%
50V
CERM
402
100K
5%
1/16W
MF-LF
402
P5VS3_EN_L_RC

10%
50V
CERM
402

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7150
SCALE
20%
6.3V
CERM
805
CRITICAL
PLACE C7675 NEAR U7670 PIN 7
R2
C7617
FDC638P
Q7610
Placement Note:
7
22UF
1%
1/16W
MF-LF
402
20%
6.3V
CERM
805
5V S3 FET
R7671
10
10%
16V
X5R
402
22UF
10%
50V
2 CERM
402
65A3
65B3
0.0022uF
65C8
19D7
65C6
R7606
1
C7623
THRML_PAD
4.02K
1%
1/16W
MF-LF
402
19
R7623
A.0.0
OF
60
84
2.5V S0 FET
Q7720
2.5V S3 Regulator
65A6 61C3
FDC637AN
=PP2V5_S0_P2V5S0
=PP2V5_S0_FET
65A8
SOT23
C7720
=PPVIN_S3_P2V5S3
1
1
22uF
20%
6.3V
CERM
805
41C3
PPVIN_S3_P2V5S3_SVIN
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
10%
50V
CERM
402
C7701
0.1uF
2
41C3
=P2V5S0_EN
100K
AVINPVIN
6
5
EN
2.2uH-1.9A-23M-OHM
CRITICAL
P2V5S3_SW
SW
U7700
TPS62510
BQA
OVT
MODE
<Ra>
1
R7707
10pF
5%
50V
CERM
402
(U7700 limit)
1%
1/16W
MF-LF
2 402
C7709
22UF
<Rb>
1
R7708
C7711
Q7721
22UF
20%
6.3V
CERM
805
65A6 61D3
20%
FDC637AN
=PP2V5_S0_P2V5S0
805
65A8
2
1
C7710
C7721
22UF
1%
1/16W
MF-LF
2 402
=PP2V5_D3C_FET
SOT23
2 6.3V
CERM
200K
=P2V5S3_PGOOD
2.5V D3Cold FET
1.5A max output
634K
11
AGND PGND THRM_PAD

3
65B8
Vout = 2.50V
PG
=PP2V5_S3_REG
P2V5S3_VFB
FB
2
SM-MSS5131
C7706
7
P2V5S0_EN_RC
5%
1/16W
MF-LF
402
CRITICAL
L7700
10%
16V
X5R
402
=P2V5S3_EN
64B8
R7720
64D5
6
2
C7700
0.0022uF
R7700
10
65C3
0.0022uF
20%
6.3V
CERM
805
10%
50V
CERM
402
C7722
0.01UF
3
2
10%
50V
X7R
402
R7721
64D5
160K
=P2V5D3C_EN
P2V5D3C_EN_RC
5%
1/16W
MF-LF
402
Vout = 0.6V * (1 + Ra / Rb)
1.2V S3 Regulator
65C3
=PPVIN_S3_P1V2S3
1M
5%
1/16W
MF-LF
402 2
41C4 5D7
P1V2S3_RUNSS
C7751
LTC3412
P1V2S3_RT
5
7
P1V2S3_ITH
P1V2S3_MODE
3
6
PGOOD 2
P1V2S3_ITH_RC
C7754
0.0022uF
2
10%
50V
CERM
402
C7757
10%
50V
CERM
402
22pF
5%
50V
CERM
402
22UF
65D6
L7750
14
1.0UH-3.48A
P1V2S3_SW
=PP1V2_S3_REG
17
65D8
65C8
2
5
Vout = 1.205V
SM-LF
<Ra>
R7750 1
1%
1/16W
MF-LF
402 2
C7755
1
C7750
22pF
5%
50V
CERM
402
XW7750
C7758
C7770
2.5A max output
22UF
22UF
0.0022uF
20%
6.3V
CERM
805
20%
6.3V
CERM
805
10%
50V
CERM
402
2
1
C7756
22UF
SM
20%
6.3V
CERM
805
(Switcher limit)
2
1
C7759
R7770
22UF
20%
64D5
2 6.3V
CERM
=P1V2D3C_EN
100K
1
P1V2D3C_EN_RC
5%
1/16W
MF-LF
402
805
VOLTAGE=0V
=PP1V2_D3C_FET
SOT23
47.0K
Q7770
=PP1V2_S0_P1V2S0
FDC637AN
11
R7754
1%
1/16W
MF-LF
2 402
GND_P1V2S3_SGND
1.2V D3Cold FET
64B8
309K
470pF
20%
6.3V
CERM
805
CRITICAL
15
13
5%
1/16W
MF-LF
402
1
C7753
=P1V2S3_PGOOD
THERM
SGND PGND PAD
10
VFB
12
Burst
1%
1/16W
MF-LF
402 2
R7756
C7752
CRITICAL
ITH
SYNC/MODE
SW
8.25K
TSSOP-LF
RT
RUN/SS
R7753 1
20%
6.3V
CERM
805
U7750
5D7
22UF
SVIN PVIN
5%
1/16W
MF-LF
2 402
Connect RUNSS off-page to control

If unconnected, powers up with PVIN.
NOTE: Be aware of pull-up on this signal.
CRITICAL
R7755
Continuous
16
NO STUFF
1
R7757
P1V2S3_VFB
<Rb>
R7751 1
61.9K
1%
1/16W
MF-LF
402
P1V2S3_VFB_DIV
<Rc>
R7752 1
30.9K
1%
1/16W
MF-LF
402
2.5V & 1.2V Regulators
SYNC_MASTER=M59_MG
Vout = 0.8V * (1 + Ra / (Rb + Rc))

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
61
84
D
65C1
=PP5V_S3_P1V8S3
C7800
C7802
10%
6.3V
CERM
402
1
1
1uF
1UF
10%
16V
X5R
603
65B1
=PPVIN_S3_P1V8S3
C7830
20%
16V
POLY
CASED2E-SM
C7831
C7832
1uF
33uF
2
1uF
10%
16V
X5R
603
10%
16V
X5R
603
R7801
10
1%
1/16W
MF-LF
402
P1V8S3_V5FILT
C7801
VOLTAGE=5V
4.7UF
20%
6.3V
CERM
603
CRITICAL
U7800
R78031
182K
1%
1/16W
MF-LF
402 2
C7803
THRM_PAD
0.1UF
10%
16V
X5R
402
GND
DRVH 13
DRVL 9
Q7820
P1V8S3_DRVH
RJK0305DPB
LFPAK
LL 12
CRITICAL
VOUT 3
L7820
1 2 3
1.2UH
1
P1V8S3_LL
PGOOD 6
SWITCH_NODE=TRUE
PGND
2
FDA1055
=PP1V8_S3_REG
5A2 65B8
=P1V8S3_EN
64A6
15
4 V5FILT
10 V5DRV TPS51117RGY_QFN14
QFN
1 EN_PSV
P1V8S3_TON
2 TON
CRITICAL
P1V8S3_TRIP 11 TRIP
P1V8S3_VBST14 VBST
5 VFB
CRITICAL
Q7821
P1V8S3_DRVL
RJK0303DPB
LFPAK
1%
1/16W
MF-LF
402 2
CRITICAL
Q7822
R7804
1 2 3
RJK0303DPB
<Rb>
R7822 1
LFPAK
12.1K
C7842
1%
1/16W
MF-LF
2 402
C7820
1 2 3
P1V8S3_FB
(L7820 limit)
20%
2.5V 2
POLY
CASE-D2E-LF
47PF
5%
50V
CERM
402
15K
5%
1/16W
MF-LF
402 2
18A max output
330UF
21.5K
Vout = 1.825V
<Ra>
R7821 1
C7841
22UF
2
(P1V8S3_FB)
C7843
330UF
20%
6.3V
CERM
805
20%
2 2.5V
POLY
CASE-D2E-LF
Vout = 0.75V * (1 + Ra / Rb)
B
=P1V8S3_PGOOD
64C2
1.8V D3Cold FET

CRITICAL
Q7845
=PP1V8_D3C_FET
FDM6296
MICROFET3X3
65B6
65C1
=PP1V8_S0_P1V8S0
=PPBUS_S0_P1V8S0
2
5
R7846
5%
1/16W
MF-LF
402
=P1V8D3C_EN
C7845
0.0047UF
470K
64D5
65B8
R7845
2
1
150K
10%
25V
CERM
402
P1V8D3C_EN_RC
S
G
4
C7846
22UF
20%
6.3V
CERM
805
C7847
22UF
20%
6.3V
CERM
805
1.8V Supply
SYNC_MASTER=M59_MG
5%
1/16W
MF-LF
402

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
62
84
Q7947
3.3V S0 FET
FDC638P
65B1
SM-LF
=PP3V3_S0_FET
65B5
65C1
3.3V S5 Regulator
=PP5V_S5_P3V3S5
=PPVIN_S5_P3V3S5
3.3V S3 FET
=PP3V3_S0_P3V3S0
Q7945
5
4
2
C7901
1uF
10%
16V
X5R
603
FDC638P
C7900
C7947
64D5
100K
=P3V3S0_EN_L
P3V3S0_EN_L_RC
C7902
NO STUFF
R7949
2.2UF
R7904
20%
6.3V
CERM1
603
5%
1/16W
MF-LF
402
5D7 5B7
12
PVCC
VCC
R7909
ISL6269BCRZ
P3V3S5_FSET
QFN
VIN
CRITICAL
UG
14
5B7
5B7
5%
1/16W
MF-LF
402
P3V3S5_EN_RC
P3V3S5_FCCM
4
3
50A5 =P3V3S5_PGOOD
16
5D7
5B7
C7906
10%
16V
CERM
402
2
2
1%
1/16W
MF-LF
402
R7908
5B7
5B7
C7907
51.1K
Q7948
P3V3S5_FB
470pF
1%
1/16W
MF-LF
402
10%
50V
CERM
402
=PP3V3_D3C_FET
65A5
=PP3V3_S0_P3V3S0
5
2
C
1
VO
R7905
C7948
C7908
0.022uF
LG
11
PGND
5%
1/16W
MF-LF
402
FDM6296
CRITICAL
L7920
1
4.7uH
R7910
1
5.62K
=PP3V3_S5_REG
CRITICAL
FDM6296
C7949
20%
6.3V
CERM
805
<Rb>
1
R7922
C7942
150UF
20%
2 6.3V
POLY
CASE-C3
1
5%
1/16W
MF-LF
402
C7941
22UF
732
20%
6.3V
CERM
805
0.1%
1/16W
MF-LF
402 2
SM
1
(L7920 limit)
22UF
R7920
1000pF
10%
25V
X7R
402
C7940
P3V3S5_FB_RC
5B7
20%
16V
CERM
402
10%
25V
CERM
402
MICROFET3X3
C7921
4.5A max output
C7920
0.0047uF
0.1%
1/16W
MF-LF
402 2
Q7921
P3V3S5_LG
3.32K
10
Vout = 3.32V
<Ra>
R7921 1
1%
1/16W
MF-LF
402
65D5
2
IHLP
NO STUFF
GND_P3V3S5_SGND
10%
50V
CERM
402
MICROFET3X3
P3V3S5_BOOT
P3V3S5_ISEN
5B7
P3V3S3_EN_L_RC
2
5%
1/16W
MF-LF
402
SWITCH_NODE=TRUE
Q7920
G
100K
=P3V3S3_EN_L
CRITICAL
XW7900
10%
2 25V
CERM
402
64B6
20%
6.3V
X5R
402
4
0.01uF
10%
16V
CERM-X5R
402
2
2
R7945
0.22uF
P3V3S5_PHASE
15
17
C7909
THRML
PAD
0.0047uF
=P3V3D3C_EN_L
13
P3V3S5_COMP_R
64D5
FB
P3V3S5_UG
NO STUFF
SM-LF
150K
FDC638P
R7948
BOOT
PHASE
ISEN
5B7
63D8
65C3
EN
FCCM
PGOOD
COMP
R7906
57.6K
0.01UF
P3V3S5_COMP
FSET
C7945
0.0022uF
0
5%
1/16W
MF-LF
402
U7900
3.3V D3Cold FET
D
3
P3V3S5_BOOT_R
64A6 =P3V3S5_EN
5
4
1
5B7
10%
25V
CERM
402
5%
1/16W
MF-LF
402
=PP3V3_S3_P3V3S3
65C3
20%
2 16V
POLY
CASED2E-SM
65C5
33UF
0.0047uF
R7947
=PP3V3_S3_FET
C7930
20%
6.3V
CERM1
603
SM-LF
1 CRITICAL
2.2UF
65C3 63C8
P3V3D3C_EN_L_RC
5%
1/16W
MF-LF
402
Vout = 0.6V * (1 + Ra / Rb)
1.05V Current Sense

CRITICAL
C7980
P1V05ISENS_NTC
33uF
20%
16V
POLY
CASED2E-SM
1.05V S0 Regulator
=PP5V_S0_P1V05S0
65C1 =PPVIN_S0_P1V05S0
65B1
C7951
0603-LF
2.2UF
20%
6.3V
CERM1
603
C7990
C7952
20%
6.3V
CERM1
603
5%
1/16W
MF-LF
402
P1V05S0_FSET
VCC
PVCC
2
5%
1/16W
MF-LF
402
ISL6269BCRZ
QFN
VIN
CRITICAL
FSET
UG
14
5B7
=P1V05S0_EN
P1V05S0_FCCM
64B5
=P1V05S0_PGOOD
3
16
5D7 5C7
C7956
10%
16V
CERM
402
BOOT
PHASE
ISEN
R7956
1
1%
1/16W
MF-LF
2 402
R7958
C7957
30.9K
15PF
1%
1/16W
MF-LF
2 402
5C7
5B7
5%
50V
CERM
402
P1V05S0_FB
6
8
FB
13
15
5B7
LG
11
PGND
10
THRML
PAD
17
2.8K
IRF7832Z
R7991
1
20.0K
CRITICAL
L7970
OUT
1M
2
1%
1/16W
MF-LF
402
C7992
470pF
2
10%
50V
CERM
402
R7970
2
5B7
(L7970 limit)
20%
6.3V
CERM
805
20%
2 2.5V
POLY
CASE-D2E-LF
NO STUFF
C7970
C7986
0.0022uF
(P1V05S0_FB)
C7989
330UF
P1V05S0_FB_RC
10%
50V
CERM
402
2
10A max output
C7985
22UF
5%
1/16W
MF-LF
402
4.42K
1%
1/16W
MF-LF
402
5B2 53A4 65D8
Vout = 1.05V
NO STUFF
<Rb>
R7972 1
53B3
1.8UH
P1V05S0_IOUT
V-
1000pF
SC70-5
R7992
P1V05ISENS_POS
1%
1/16W
MF-LF
402
SM
1%
1/16W
MF-LF
402
XW7950
GND_P1V05S0_SGND
V+
3.32K
SO-8
HPA00141AIDCKR
0.22UF
<Ra>
R7971 1
Q7971
4
10%
25V
X7R
402
CRITICAL
U7995
5
C7991
P1V05ISENS_RC
10%
6.3V
CERM
402
=PP1V05_S0_REG
CRITICAL
P1V05S0_LG
P1V05ISENS_NEG
C7995
1uF
1%
1/16W
MF-LF
402
0.01uF
20%
16V
CERM
402
20.0K
1
SM-IHLP
R7960
1
1%
1/16W
MF-LF
402
R7993
1%
1/16W
MF-LF
402
NO STUFF
C7958
5%
1/16W
MF-LF
402
P1V05S0_PHASE
P1V05S0_COMP_R
R7955
1%
1/16W
MF-LF
402
P1V05S0_BOOT
P1V05S0_ISEN
5B7
1%
1/16W
MF-LF
402
649
VO
R7990
MICROFET3X3
SWITCH_NODE=TRUE
CRITICAL
FDM6296
10%
6.3V
CERM-X5R
402
Q7970
G
C7971
1
20%
6.3V
X5R
402
P1V05S0_UG
1M
10%
50V
CERM
402
R7998
1
0.22uF
5B7
57.6K
0.01UF
P1V05S0_COMP
EN
FCCM
PGOOD
COMP
C7959
5C7
64C6
4.7
U7950
1
5D7 5B7
R7959
10%
6.3V
CERM-X5R
402
12
2.2UF
R7954
0
1K
0.47UF
P1V05S0_BOOT_R
NO STUFF
R7994
1
470pF
Keep C7990, C7991,

R7990, R7994 and R7997
close to inductor
5C7
C7998
Placement Note:
10KOHM-5%
NO STUFF
C7950
=PP3V3R5V_S0_P1V05ISENS
R7997
1K
1%
1/16W
MF-LF
402
65A3
CRITICAL
R7996 1
1uF
10%
16V
X5R
603
1
2
22UF
2
20%
6.3V
CERM
805
3.3V / 1.05V Power Supplies

SYNC_MASTER=M59_MG

Vout = 0.6V * (1 + Ra / Rb)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
63
84
Power Control Signals

65B1 64B8
State
SMC_PM_G2_ENABLE
PM_SLP_S4_L
PM_SLP_S3_L
Run (S0)
Sleep (S3)
Soft-Off (S5)
Battery Off (G3Hot)
3.425V "G3Hot" Supply
=PP5V_S5_PWRCTL
Supply needs to guarantee 3.31V delivered to SMC VRef generator
R8050 1
68C8
IN
R8051 1
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R8068 1
R8052
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
GPU requires 1.2V, 1.8V, 2.5V and

3.3V rise after VCore is up.
R8069
10K
65A6
=PPVIN_G3H_P3V42G3H
5%
1/16W
MF-LF
402
P3V42G3H5_BOOST
C8000
=GPUVCORE_PGOOD
P1V2R2V5D3C_EN_LS5V
Need to ensure that

ISL6269 PGOOD does not
deassert while GPU
PowerPlay is changing
GPU core voltage.
=P2V5D3C_EN
=P1V2D3C_EN
MAKE_BASE=TRUE
P3V3D3C_EN_L
10%
25V
X5R
1206-1
61B3
20%
6.3V
X5R
402
LT3470
63C8
=P1V8D3C_EN
62A6
1.8V Enable has pull-up to PBUS
SHDN*
SW
BIAS
Q8055
SOT-363
NC
L8010
33uH
FB
P3V42G3H_SW
SWITCH_NODE=TRUE
PM_SLP_S3_LS5V_L
SOT-363
MAKE_BASE=TRUE
P3V3S0_EN_L
=P2V5S0_EN
61D3
=P3V3S0_EN_L
63D8
C8010
5%
50V
CERM
402
Q8050
2N7002DW-X-F
2
(Switcher limit)
348K
5D7
1%
1/16W
MF-LF
2 402
SOT-363
20%
6.3V
CERM
805
200K
1%
1/16W
MF-LF
2 402
1
4
C8015
22UF
<Rb>
R8011
2N7002DW-X-F
5
P3V42G3H_FB
Q8058
SOT-363
<Ra>
R8010
22pF
MAKE_BASE=TRUE
Vout = 3.425
200mA max output
GND
2N7002DW-X-F
65D5
2
CDPH4D19F-SM
=PP3V42_G3H_REG
CRITICAL
Q8056
2N7002DW-X-F
2
NC
CRITICAL
2
TSOT23-8
=P3V3D3C_EN_L
MAKE_BASE=TRUE
0.22uF
BOOST
U8000
P1V8D3C_EN
C8005
VIN
10UF
61C3
MAKE_BASE=TRUE
Q8058
2N7002DW-X-F
PM_SLP_S3_LS5V
65D3 64A8
MAKE_BASE=TRUE
=PP3V42_G3H_PWRCTL
=P5VS0_EN_L
LIO_P3V3S0_EN_L
P1V5S0_RUNSS
3
1
Q8050
SOT-363
S
2
R8054
IN
Reports when 1.5V S0 and 1.05V S0 are in regulation
65C3
=PP3V3_S5_P1V5PG
65C6
PP1V5_S0
60B3
62B4
65C3
R8061 1
=PP3V3_S3_PWRCTL
(PM_SLP_S3_L)
MAKE_BASE=TRUE
1
R8081
10%
16V
CERM
402
=PP5V_S5_PWRCTL
R8055
SB_GPUVCORE_DISABLE_L
MC74VHC1G08
SC70
4
GPUVCORE_EN
=GPUVCORE_EN
68C8
10K
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
=P3V3S3_EN_L
=P5VS3_EN_L
63B8
=P1V05S0_PGOOD
IN
59C7
P1V5P1V05S0_PGOOD
MAKE_BASE=TRUE
=PP3V3_S0_ALLSYSPG
65A3 79D5
B
5
Other S0 Rails PWRGD Circuit
MC74VHC1G08
U8080
Does not include D3C rails for GPU!!

79A2
SC70
4
ALL_SYS_PWRGD
OUT
26A5 49D7
PGOOD_MUXED_S0_OR_S0D3C
Q8055
65C3
SOT-363
65B1
65A6
2.5V S3 and 1.2V S3 supplies are controlled

by ethernet power control circuit.
100K
65D6
PP3V3_S0
PP5V_S0
PP2V5_S0
PP0V9_S0
C8080
C8070
(PM_SLP_S4_L)
MAKE_BASE=TRUE
62C8
46C7
R8074
R8072
(P5VS5_PGOOD)
365K
845K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
5C1 47B6
=P3V3S5_EN
63D7
P5VS5_RUNSS
5D7 60C5
R8070
68.1K
=PP3V42_G3H_PWRCTL
P5VS5_PGOOD
20%
10V
CERM
402
0.1uF
1
=P1V8S3_EN
=RTUSB_EN
LIO_P3V3S3_EN
0.1UF
5%
1/16W
MF-LF
402 2
IN
OUT
ISL6269 undervoltage threshold 81-87% (0.85 - 0.91V)

NOTE: R8065 acts as 10K pull-up for PGOOD signal
60A4
R8057 1
50A4
5%
1/16W
MF-LF
2 402
IMVP_PWRGD_IN
63D3
2N7002DW-X-F
65D3 64C8
R8065
10K
R8064
1.5V Comp threshold set to 1.32V (88%)
The SB can turn off the GPUVcore (and by

extension all D3Cold rails) by driving
GPIO38 low.
MAKE_BASE=TRUE
10K
PM_SLP_S4_L
P1V5S0_PGOOD
V-
MAKE_BASE=TRUE
PM_SLP_S4_LS5V
IN
SM-LF
1
MAKE_BASE=TRUE
10K
5%
1/16W
MF-LF
402
U8081
TP_SB_GPIO38
LMC7211
P1V5S0_COMP_POS
R8062
0.047UF
20%
10V
CERM
402
5%
1/16W
MF-LF
402 2
TP_P1V8S3_PGOOD
U8060
V+
0.1uF
PM_SLP_S3_L_GPUVCORE_EN
C8053
P1V0_P1V5PG_REF
0.89V Reference
C8081
10K
5%
1/16W
MF-LF
2 402
MAKE_BASE=TRUE
65B1 64D8
R8053
20%
10V
CERM
402
1%
1/16W
MF-LF
2 402
2
=P1V8S3_PGOOD
0.1uF
R8063
4.99K
1%
1/16W
MF-LF
402 2
10K
TP_P2V5S3_P1V2S3_PGOOD
This signal was used as an option previously

to test for 2v5 and 1v2 S3 valid for GPUVCORE_EN.
But was disconnected for C8053 placement.
41B6 23C3
49C5
27.4K
=P1V05S0_EN
63B8
=ENET_VMAIN_AVLBL
39C8
=MEMVREF_EN
32B3
=PBUSVSENS_EN
53C3
65A3 =PP3V3_S0_PWRCTL
TP_P5V_P1V5_PGOOD
MAKE_BASE=TRUE
C8060
=P5VP1V5_PGOOD
MAKE_BASE=TRUE
=P2V5S3_PGOOD
=P1V2S3_PGOOD
Unused PGOOD Signals
SOT-363
5%
1/16W
MF-LF
402 2
IN
1.5V / 1.05V PWRGD Circuit
Q8057
SOT-363
100K
IN
5B7 5D7 60C4
2N7002DW-X-F
5
61B5
5C1 47B6
Q8057
PM_SLP_S3_L
R8056 1
61C8
2N7002DW-X-F
2
PM_SLP_S3
Vout = 1.25V * (1 + Ra / Rb)
60B3
5%
1/16W
MF-LF
402
42A8 23C3
49C5 43B7
1.5V Enable has pull-up to PBUS
100K
2N7002DW-X-F
SOT-363
20%
10V
CERM
402
2
1
CRITICAL
S0PGOOD_5V_DIV
V2
S0PGOOD_2V5_DIV
V3
S0PGOOD_0V9_DIV
V4
MAKE_BASE=TRUE
R8076
10K
5%
1/16W
MF-LF
2 402
V1
U8070
LTC2903
TSOT-23
RST* 6
S0PGOOD_PWROK
79A4 79D5
GND
1
R8059
5V Enable has pull-up to PBUS
470K
SMC_PM_G2_EN_L
Q8059
IN
SMC_PM_G2_EN
C8075
0.1UF
20%
10V
2 CERM
402
R8073
100K
1%
1/16W
MF-LF
402
C8073
R8071
100K
0.1UF
2
1%
1/16W
MF-LF
402
20%
10V
2 CERM
402
C8071
0.1UF
2
20%
10V
2 CERM
402
3.3V G3Hot Supply & Power Control
2N7002DW-X-F
5
SOT-363
SYNC_MASTER=M59_MG
Q8059

LTC2903 guaranteed threshold is 93.5% (3.055V, 4.725V, 2.325V, 0.840V)
2N7002DW-X-F
49D5
100K
R8075
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SOT-363

1
R8058 1
100K
5%
1/16W
MF-LF
402
SIZE
2
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
64
84
7
PP0V9_S0
31C2
=PP0V9_S0_MEMVTT_LDO
PP3V42_G3H
30D5
64D2
=PP3V42_G3H_REG
PP1V05_S0
VOLTAGE=1.05V
MAKE_BASE=TRUE
63A2 53A4 5B2
=PP1V05_S0_REG
=PP1V05_S0_CPU
=PP1V05_S0_FSB_NB
=PP1V05_S0_NB_CRT
=PP1V05_S0_NB_VTT
=PPVCORE_S0_NB
=PPVCORE_S0_SB
PP1V2_S3
7B5 7B6 7D5 8C7 9B7 11B3 11C5

12A7 12B7 12C2 19D7 34B8 34C6 34C8
19D6 19D7
17D3 19C8 19D7
21C1 24C3 25C4
16C8 16D3 19C8 19D2 19D7
=PP1V2_S3_REG
61B3
=PP3V3_S5_REG
79D7
=PP1V2_S0_GPU_VDDPLL
=PP1V2_S0_PCIE_GPU
=PP1V2_S0_PCIE_GPU_PVDD
=PP1V2_S0_PCIE_GPU_VDDR
74B8
67A1
67C7
67C7
PP1V5_S0
64C5
VOLTAGE=0
MAKE_BASE=TRUE
=PP1V5_S0_REG
=PP1V5_S0_CPU
=PP1V5_S0_NB1V5_SENSE
=PP1V5_S0_SB
=PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V5_S0_LIO
=PP1V5_S0_ITPMOUNT
8B7 9B7
60A8
24A3 25C2
24B5 25D6
63D1
=PP3V3_S3_FET
24A5 25C6
24A3 25B2
24B5 25D6
24A5 25B6
5D1 47D6
11C4
VOLTAGE=0
MAKE_BASE=TRUE
=PP1V5_S0_NB
=PP1V5_S0_NB
=PP1V5_S0_NB_3G
=PP1V5_S0_NB_3GPLL
=PP1V5_S0_NB_PCIE
=PP1V5_S0_NB_PLL
=PP1V5_S0_NB_TVDAC
=PP1V5_S0_NB_VCCAUX
19D7 60A7 65C8
19B5 19D7
17C6 19A5
63D6
=PP3V3_S0_FET
19D2 19D6 19D7

16D1 17B6 19C4 19D7
17C6 19D7
28B2 28D3 28D6 29B2 29D3 29D6

14C2 16B6 19D7
32C6
31C5
62A6
37B2
79D7
VOLTAGE=1.8V
MAKE_BASE=TRUE
62A4
=PP1V8_D3C_FET
=PP1V8R2V0_S0_FB_GPU
=PP1V8_S0_FB_VDD
=PP1V8_S0_FB_VDDQ
69B8 70A5 70A8 70B5 70B8

72D5 72D8 73D5 73D8
72D5 72D8 73D5 73D8
PP2V5_S3
VOLTAGE=2.5V
MAKE_BASE=TRUE
61D4
=PP2V5_S3_REG
=PP2V5_S3_ENET
=PP2V5_S0_P2V5S0
39D3
61C3 61D3
PP2V5_S0
64B5
VOLTAGE=2.5V
MAKE_BASE=TRUE
61D1
=PP2V5_S0_FET
=PP2V5_S0_NB_DPLL
=PP2V5_S0_LVDS_MUX
PP2V5_D3C
17D6 19C5 19D7

17D6 19A6 19D7
17C6 19A4
19A8
79C5 79D3
79D7
VOLTAGE=0
MAKE_BASE=TRUE
61C1
=PP2V5_D3C_FET
=PP2V5_S0_GPU
=PP2V5_S0_GPU_PVDD
=PP2V5_S0_GPU_VDD25
=PP2V5_S0_GPU_VDDC_CT
75C8
74A8
74C6
63C7
=PP3V3_D3C_FET
VOLTAGE=1.2V
MAKE_BASE=TRUE
=PPVCORE_S0_GPU_REG
=PPVCORE_S0_GPU
=PPVCORE_S0_GPU_BBP
PPDCIN_G3H
53A5 53C7 69D8 74A7

68B7
VOLTAGE=18.5V
MAKE_BASE=TRUE
47C6 5D1
=PPDCIN_G3H_LIO
=PPVIN_G3H_P3V42G3H
GND
64D5
VOLTAGE=0V
78D3
68A2
=PNVOUT_S0_GPUBBN_REG
=PNBB_S0_GPU
69D2
49C2 49D3 49D4 50B1 50D7
5D2 51C4
PPBB_S0_GPU
46B5
=PPVOUT_S0_GPUBBP_LDO
=PP3V3_S5_SB
=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA
=PP3V3_S5_SB_IO
=PP3V3_S5_SB_PM
=PP3V3_S5_SB_USB
=PP3V3_S5_ROM
=PP3V3_S5_P1V5PG
=PP3V3_S3_P3V3S3
=PPVIN_S3_P2V5S3
=PP3V3_S0_LCD
=PP3V3_S0_P3V3S0
PP3V3_S3
=PP3V3_S3_P3V3S3AC
=PP3V3_S3_RTALS
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_TPM
=PP3V3_S3_SMS
=PP3V3_S3_TOPCASE
=PP3V3_S3_LTALS
=PP3V3_S3_MEMVREF
=PP3V3_S3_FW
=PP3V3_S3_PCI
=PPVIN_S3_P1V2S3
=PP3V3_S3_PWRCTL
=PP3V3_S0_DDC_LCD
=PP3V3_S0_CK410
=PP3V3_S0_IDE
=PP3V3_S0_IMVP6
=PP3V3_S0_INVERTER
=PP3V3_S0_NB
=PP3V3_S0_NB_VCC_HV
=PP3V3_S0_SB
=PP3V3_S0_SB_3V3_1V5_VCCHDA
=PP3V3_S0_SB_GPIO
=PP3V3_S0_SB_PCI
=PP3V3_S0_SB_PM
=PP3V3_S0_SB_VCC3_3
=PP3V3_S0_SB_VCCLAN3_3
=PP3V3_S0_TPM
=PP3V3_S0_KBDLED
=PP3V3_S0_THRM_SNR
=PP3V3_S0_REMTHMSNS
=PP3V3_S0_SMBUS_SB
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_SMC_BSB
=PP3V3_S0_RSTBUF
=PP3V3_S0_SMC_LS
=PP3V3_S0_ALLSYSPG
=PP3V3_S0_FAN_LT
=PP3V3_S0_FAN_RT
=PP3V3R5V_S0_CPUISENS
=PP3V3R5V_S0_GPUISENS
=PP3V3R5V_S0_P1V05ISENS
=PPSPD_S0_MEM
=PP3V3_S0_EDET
=PP3V3_S0_LVDS_MUX
=PP3V3_S0_NB1V5ISENS
=PP3V3_S0_GPU_TDIODE
=PP3V3_S0_PWRCTL
PP3V3_D3C
=PP3V3_S0_GPU
=PP3V3_S0_GPUBBP
=PP3V3_S0_GPUBBN
=PP3V3_S0_GPU_VDDR3
=PP3V3_D3C_GPU_GPIOS
=PP1V8R3V3_S0_GPU_VDDR4
=PP3V3_D3C_DDC_DVI
=PP3V3_D3C_VGASYNC
=PP3V3_D3C_GPU_LVDS_DDC
=PP3V3_D3C_GPU
=PPBB_S0_GPU
69D6
PPVCORE_S0_CPU
5A2
VOLTAGE=1.1V
MAKE_BASE=TRUE
23A7 23B7 23D4 23D8 25C8

24C3
22C6
59D1
=PPVOUT_S0_IMVP6_REG
=PPVCORE_S0_CPU
8B5 8D7 9D7

53A6 53D7
11B5 23D1 26C5

22D8
PPBUS_G3H
24A5 24B3 25B6 25D2
54D4
64C5
53D3
VOLTAGE=12.6V
MAKE_BASE=TRUE
24B3 25D2
66C4 5A1
=PPBUS_G3H_LIO_CONN
=PPBUS_G3H_S3AC
=PPVIN_S5_P5VP1V5
=PPVIN_S0_IMVP6
=PPVIN_S5_P3V3S5
=PPBUS_S5_FWPWRSW
=PPVIN_S3_P1V8S3
=PPVIN_S0_P1V05S0
=PPVIN_S0_GPUVCORE
=PPBUS_S0_INVERTER
=PPBUS_S0_P1V8S0
=PPBUS_S0_PPBU_S0_FW
63D2
61D8
76D5
63C8 63D8
41C5
55D4
27C5
60D7
59D4 59D7
63D6
43D7
62D7
63B7
68D7
76B7
62A6
42B8
PPBUS_S5_FW_FET
50B1 57C6
VOLTAGE=33V
MAKE_BASE=TRUE
78D3
5B2 78C5
64C6
=PPFW_PORT1_VP
=PPFW_PORT2_VP
=PPFW_FW_CPS
=PPFW_P3V3FWPHY
PP5V_S5
64B5
VOLTAGE=5V
MAKE_BASE=TRUE
32C5
43C1
=PPBUS_S5_FW_FET
37A7 37C3 37D7

37D5
61B7
60C8
=PP5V_S5_REG
44D3
44B3
38B7
42C8
50B5
=PP5V_S5_SB
=PP5V_S5_P3V3S5
=PP5V_S5_P5VP1V5_VCC
=PP5V_S5_LIO
=PP5V_S5_PWRCTL
=PP5V_S3_P5VS3
=PP5V_S3_P1V8S3
=PP5V_S3_RTUSB
=PP5V_S0_P5VS0
=PP5V_S0_GPUVCORE
=PP5V_S0_P1V05S0
76D3
33C7 33D3 33D8 34A8
36D6
59D8
76A8
14C7 14D6 19C7 20A4 20B4
17C6 19C6 19C7
22B5 25D8
24C3 25C4
25C8
63D6
60B6
5D1 47C6
64B8 64D8
60A4
62C8
46C7
60B2
68D7
63B7
21C3 21D3 23B3 23D5
PP5V_S3
26D1
VOLTAGE=5V
MAKE_BASE=TRUE
26B6 26B8
24B5 25B8 25C6
24C3 25B4
60A2
=PP5V_S3_FET
=PP5V_S3_SYSLED
=PP5V_S3_CAMERA
=PP5V_S3_IR
=PP5V_S3_TOPCASE
24B3 25A4
24D3 25D3
58C7 58D4
50B8
5A4 45C3
78B5
78D3
55B6
PP5V_S0
10C5
VOLTAGE=5V
MAKE_BASE=TRUE
52D4
27D8
27D5
64B5
60B1
=PP5V_S0_FET
=PP5V_S0_DVI_DDC
=PP5V_S0_IDE
=PP5V_S0_HDD
=PP5V_S0_IMVP6
=PP5V_S0_INVERTER
=PP5V_S0_MEMVTT
=PP5V_S0_SB
=PP5V_S0_FAN_LT
=PP5V_S0_FAN_RT
=PP5V_S0_KBDLED
=PP5V_S0_GPUBBCTL
=PP5V_S0_LPCPLUS
=PP5V_S0_AUDIO_XW
=PP5V_S0_ISENSECAL
=PP5V_S0_SB_HPD
27D3
27C3
26B4
50D3
64B1 79D5
56C7
56C4
59A5
68D2
63B3
28A6 29A3 29A6
40B6
79A4 79B3 79C6
60A6
77B5
36D6
78B5
59D7
76B8
31C5
25D8
5D2 56C7
56C4
55B5
68A6
5D2 51C4
47D3
5A2 53A8
77A1
52B5
Power Aliases
64B6
79D7
SYNC_MASTER=M59_MG

68C4 74D2

68B8
68A4
74C6
71D6
74B7
74B7
SIZE
77B2
77D5
APPLE COMPUTER INC.
79A7
DRAWING NUMBER
D
SCALE
SHT
71B2
REV.
051-7150
NONE
41C6
50B1 58C2
VOLTAGE=3.3V
MAKE_BASE=TRUE
74C6
PPVCORE_D3C_GPU
68C1
PNBB_S0_GPU
5D1 47D6
68B5
PP3V3_S0
19B8 19D7
=PP1V8_S3_MEM
=PP1V8_S3_MEM_NB
=PP1V8_S3_MEMVREF
=PP1V8_S0_MEMVTT
=PP1V8_S0_P1V8S0
=PP1V8_S3_FW
PP1V8_D3C
39A5 39B4 39B5

39B8 39D6 39D8
VOLTAGE=-0.7V
MAKE_BASE=TRUE
35B7
VOLTAGE=3.3V
MAKE_BASE=TRUE
13D2 19D7
VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP1V8_S3_REG
=PP3V3_S3_ENET
19B5 19D7
PP1V8_S3
62C1 5A2
=PP3V3_S3AC_FET
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
25A8 25C8
PP1V5_S0_NB
65C6 60A7 19D7
41C4
50B5
VOLTAGE=3.3V
MAKE_BASE=TRUE
39A8 39D7
VOLTAGE=1.2V
MAKE_BASE=TRUE
60C1 5A2
64A8 64C8
26D6
VOLTAGE=1.9V
MAKE_BASE=TRUE
63D1
=PP1V2_D3C_FET
27C3
PP3V3_S5
=PP1V2_S3_ENET
=PP1V2_S0_P1V2S0
PP1V2_D3C
61B1
PP3V3_S3AC
VOLTAGE=3.3V
MAKE_BASE=TRUE
50B7
24D3 25D3
VOLTAGE=1.2V
MAKE_BASE=TRUE
61B3
=PP3V42_G3H_SMCVREF
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SB_RTC
=PP3V42_G3H_SMC_PWRGD
=PP3V42_G3H_SMC_CLK
=PP3V42_G3H_LIO
=PP3V42_G3H_LIDSWITCH
=PP3V3_S5_SMC
=PP3V3_S5_LPCPLUS
=PP3V42_G3H_SMCUSBMUX
"S3AC" rail is ON in S3 on AC, OFF in S3 on battery
VOLTAGE=3.425V
MAKE_BASE=TRUE
=PP0V9_S0_MEM_TERM
5
64B5
VOLTAGE=0.9V
MAKE_BASE=TRUE
A.0.0
OF
65
84
Left I/O Power Connector

CRITICAL
J8200
87438-0663
M-RT-SM
=PPBUS_G3H_LIO_CONN
5A1 65C3
1
2
3
4
5
6
518S0458
C
Battery Connector (Digital Signals)
CRITICAL
J8250
SM04B-ACH
M-RT-SM
5
NC
5D1
27C1
5D1
27C1
5D1
NC
GND_BATT
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
SMC_BS_ALRT_L
IO
IO
OUT
R8250
10
518S0369
2
5%
1/16W
MF-LF
402
PBus-In,Batt. & 3G Pwr Connectors
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
66
84
OMIT
U8400
M56P
13C3
13B3
13C3
D
13B3
13C3
13B3
13B3
13B3
13B3
13B3
13B3
13B3
13B3
65C6
65C6
=PP1V2_S0_PCIE_GPU_VDDR
=PP1V2_S0_PCIE_GPU_PVDD
13B3
13B3
IN
IN
IN
IN
PEG_R2D_C_N<2>
IN
IN
IN
IN
IN
IN
IN
C8423
PEG_R2D_C_N<1>
IN
IN
C8422
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
IN
C8421
PEG_R2D_C_N<0>
IN
IN
C8420
PEG_R2D_C_P<0>
C8424
C8425
C8426
PEG_R2D_C_P<3>
C8427
PEG_R2D_C_N<3>
C8428
PEG_R2D_C_P<4>
C8429
PEG_R2D_C_N<4>
C8430
PEG_R2D_C_P<5>
C8431
PEG_R2D_C_N<5>
C8432
PEG_R2D_C_P<6>
C8433
PEG_R2D_C_N<6>
C8434
PEG_R2D_C_P<7>
C8435
PEG_R2D_C_N<7>
L8400
0402
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
IN
PEG_R2D_C_P<8>
C8436
0.1uF
13B3
IN
PEG_R2D_C_N<8>
C8437
0.1uF
13B3
U8400
2
M56P
13B3
BGA
(2 OF 7)
OMIT
N23
W29
P23
PCIE_PVDD_12
(1.2V)
Y24
Y26
C8402
1uF
10%
6.3V
CERM
402
U23
V23
C8401
1uF
2
10%
6.3V
CERM
402
C8400
VOLTAGE=1.2V
13B3
20%
6.3V
CERM
805
13B3
13B3
N25
Y30
N26
N27
C8407
AA25
N28
1uF
AA26
N29
AL29
10%
6.3V
CERM
402
C8406
1uF
2
10%
6.3V
CERM
402
13B3
C8405
AB23
20%
6.3V
CERM
805
13B3
13A3
AL32
AB27
AM27
1uF
AB29
AM28
AC23
AM29
10%
6.3V
CERM
402
AC24
AM30
AC26
AM31
C8413
C8412
1uF
2
10%
6.3V
CERM
402
C8411
1uF
2
10%
6.3V
CERM
402
13B3
C8410
PCI EXPRESS POWER & GROUND
AC30
AD25
AD26
AD29
AD31
AE26
PCIE_VSS
AE27
AE29
AF26
AF28
AF29
AF30
AG25
PCIE_PVSS
20%
6.3V
CERM
805
13A3
13A3
W23
IN
C8440
PEG_R2D_C_P<10>
C8441
PEG_R2D_C_N<10>
0.1uF
0.1uF
IN
C8442
PEG_R2D_C_P<11>
IN
IN
C8443
PEG_R2D_C_N<11>
C8444
PEG_R2D_C_P<12>
0.1uF
0.1uF
0.1uF
IN
C8445
PEG_R2D_C_N<12>
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
AK27
AJ27
PEG_D2R_C_P<0>
PEG_D2R_C_N<0>
IN
IN
IN
C8446
PEG_R2D_C_P<13>
C8447
PEG_R2D_C_N<13>
0.1uF
0.1uF
13B3
N24
IN
13A3
P25
IN
PEG_R2D_P<1>
PEG_R2D_N<1>
AH30
AG30
PCIE_RX1P
PCIE_RX1N
10%
16V
X5R
402
10%
16V
X5R
402
PEG_R2D_P<2>
PEG_R2D_N<2>
AG32
PCIE_TX1P
PCIE_TX1N
AF32
PCIE_RX2P
PCIE_RX2N
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
PEG_R2D_P<3>
PEG_R2D_N<3>
AF31
AE31
PCIE_RX3P
PCIE_RX3N
PEG_R2D_P<4>
PEG_R2D_N<4>
AE30
AD30
PCIE_RX4P
PCIE_RX4N
PEG_R2D_P<5>
PEG_R2D_N<5>
AD32
AC32
PCIE_RX5P
PCIE_RX5N
2
10%
16V
X5R
402
10%
16V
X5R
402
P26
13B3
P28
IN
10%
16V
X5R
402
10%
16V
X5R
402
AJ25
AH25
PEG_D2R_C_P<1>
PEG_D2R_C_N<1>
10%
16V
X5R
402
10%
16V
X5R
402
C8459
0.1uF
C8460
0.1uF
10%
PCIE_TX2P
PCIE_TX2N
AH28
AG28
10%
PEG_D2R_C_P<2>
PEG_D2R_C_N<2>
PEG_R2D_P<6>
PEG_R2D_N<6>
AC31
AB31
PCIE_RX6P
PCIE_RX6N
PCIE_TX3P
PCIE_TX3N
AG27
AF27
0.1uF
C8462
0.1uF
C8463
0.1uF
C8464
0.1uF
C8465
0.1uF
C8466
0.1uF
C8467
0.1uF
C8468
0.1uF
C8469
0.1uF
C8470
0.1uF
C8471
0.1uF
34B4
R23
34B4
PCIE_TX4P
PCIE_TX4N
AF25
AE25
PEG_D2R_C_P<4>
PEG_D2R_C_N<4>
IN
IN
T24
PCIE_VSS
2
10%
PCIE_TX5P
PCIE_TX5N
AE28
AD28
PEG_D2R_C_P<5>
PEG_D2R_C_N<5>
10%
10%
PCIE_TX6P
PCIE_TX6N
AD27
AC27
PEG_D2R_C_P<6>
PEG_D2R_C_N<6>
PEG_R2D_P<7>
PEG_R2D_N<7>
AB30
AA30
PCIE_RX7P
PCIE_RX7N
PCIE_TX7P
PCIE_TX7N
AC25
AB25
10%
PEG_D2R_C_P<7>
PEG_D2R_C_N<7>
10%
16V
X5R
402
10%
16V
X5R
402
PEG_R2D_P<8>
PEG_R2D_N<8>
AA32
Y32
PCIE_RX8P
PCIE_RX8N
PCIE_TX8P
PCIE_TX8N
AB28
10%
AA28
PEG_D2R_C_P<8>
PEG_D2R_C_N<8>
PEG_R2D_P<9>
PEG_R2D_N<9>
Y31
W31
PCIE_RX9P
PCIE_RX9N
PCIE_TX9P
PCIE_TX9N
AA27
Y27
PEG_D2R_C_P<9>
PEG_D2R_C_N<9>
C8472
0.1uF
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
PEG_R2D_P<10>
PEG_R2D_N<10>
W30
V30
PCIE_RX10P
PCIE_RX10N
PCIE_TX10P
PCIE_TX10N
Y25
W25
C8473
0.1uF
C8474
0.1uF
C8475
0.1uF
C8476
0.1uF
10%
10%
PEG_D2R_C_P<10>
PEG_D2R_C_N<10>
10%
PEG_R2D_P<11>
PEG_R2D_N<11>
V32
U32
PCIE_RX11P
PCIE_RX11N
PCIE_TX11P
PCIE_TX11N
W28
V28
C8477
0.1uF
C8478
0.1uF
C8479
0.1uF
C8480
0.1uF
C8481
0.1uF
C8482
0.1uF
C8483
0.1uF
C8484
0.1uF
10%
PEG_D2R_C_P<11>
PEG_D2R_C_N<11>
10%
PEG_R2D_P<12>
PEG_R2D_N<12>
U31
T31
PCIE_RX12P
PCIE_RX12N
PCIE_TX12P
PCIE_TX12N
V27
U27
PEG_D2R_C_P<12>
PEG_D2R_C_N<12>
10%
10%
2
10%
16V
X5R
402
10%
16V
X5R
402
PEG_R2D_P<13>
PEG_R2D_N<13>
T30
R30
PCIE_RX13P
PCIE_RX13N
PCIE_TX13P
PCIE_TX13N
U25
T25
PEG_D2R_C_P<13>
PEG_D2R_C_N<13>
10%
PEG_R2D_C_N<14>
10%
16V
X5R
402
PEG_R2D_P<14>
PEG_R2D_N<14>
R32
P32
PCIE_RX14P
PCIE_RX14N
PCIE_TX14P
PCIE_TX14N
T28
R28
PEG_D2R_C_P<14>
PEG_D2R_C_N<14>
10%
1
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
PEG_R2D_P<15>
PEG_R2D_N<15>
P31
N31
PCIE_RX15P
PCIE_RX15N
PCIE_TX15P
PCIE_TX15N
R27
P27
PEG_D2R_C_P<15>
PEG_D2R_C_N<15>
C8485
0.1uF
C8486
0.1uF
10%
10%
PEG_CLK100M_GPU_P
PEG_CLK100M_GPU_N
AL28
AK28
PCIE_REFCLKP
PCIE_REFCLKN
X5R
402
16V
X5R
402
13C3
13D3
16V
X5R
402
16V
X5R
402
16V
X5R
402
13C3
13D3
13C3
X5R
13D3
16V
X5R
402
16V
X5R
402
13C3
13D3
16V
X5R
402
16V
X5R
402
13C3
13D3
16V
X5R
402
16V
X5R
402
13C3
13D3
16V
X5R
X5R
16V
X5R
402
16V
X5R
402
OUT
PEG_D2R_N<1>
OUT
PEG_D2R_P<2>
OUT
PEG_D2R_N<2>
OUT
PEG_D2R_P<3>
OUT
PEG_D2R_N<3>
OUT
PEG_D2R_P<4>
OUT
PEG_D2R_N<4>
OUT
PEG_D2R_P<5>
OUT
PEG_D2R_N<5>
OUT
PEG_D2R_P<6>
OUT
PEG_D2R_N<6>
OUT
PEG_D2R_P<7>
OUT
16V
X5R
402
16V
X5R
402
13D3
13C3
13D3
16V
X5R
402
16V
X5R
402
13C3
13C3
16V
X5R
402
16V
X5R
402
13C3
13C3
16V
X5R
402
16V
X5R
402
13C3
13C3
16V
X5R
402
16V
X5R
402
13C3
13C3
X5R
PEG_D2R_N<7>
OUT
13C3
PEG_D2R_P<8>
OUT
PEG_D2R_N<8>
OUT
PEG_D2R_P<9>
OUT
PEG_D2R_N<9>
OUT
PEG_D2R_P<10>
OUT
PEG_D2R_N<10>
OUT
PEG_D2R_P<11>
OUT
PEG_D2R_N<11>
OUT
PEG_D2R_P<12>
OUT
PEG_D2R_N<12>
OUT
PEG_D2R_P<13>
OUT
PEG_D2R_N<13>
OUT
402
13C3
16V
X5R
402
16V
X5R
402
16V
X5R
402
13C3
13C3
13C3
16V
PEG_D2R_P<1>
402
13D3
16V
OUT
402
13C3
16V
OUT
PEG_D2R_N<0>
402
2
10%
10%
16V
10%
10%
13D3
16V
PEG_D2R_P<0>
402
2
10%
X5R
X5R
PEG_D2R_P<14>
OUT
PEG_D2R_N<14>
OUT
PEG_D2R_P<15>
OUT
PEG_D2R_N<15>
OUT
402
65C6
R8495
2.0K
R26
AG31
10%
R24
R31
10%
R25
R29
=PP1V2_S0_PCIE_GPU
P30
AG29
10%
PEG_D2R_C_P<3>
PEG_D2R_C_N<3>
13C3
16V
C8461
P29
AG26
10%
0.1uF
0.1uF
C8451
C8458
10%
0.1uF
PEG_R2D_C_N<15>
C8457
0.1uF
10%
0.1uF
10%
C8449
0.1uF
C8448
C8450
0.1uF
10%
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>
0.1uF
C8456
10%
N30
P24
C8455
10%
402
X5R
PCIE_TX0P
PCIE_TX0N
16V
10%
26B1
AH24
IN
0.1uF
10%
AH31
PCIE_RX0P
PCIE_RX0N
22UF
13B3
AC29
C8439
PEG_R2D_C_N<9>
402
X5R
AJ31
AL31
AB26
AC28
IN
22UF
AL30
PCIE_VDDR_12
(1.2V)
0.1uF
16V
2000mA
Y29
AA23
AA31
C8438
PEG_R2D_C_P<9>
22UF
2
Y28
AA29
IN
10%
PEG_R2D_P<0>
PEG_R2D_N<0>
PP1V2_S0_PCIE_GPU_PVDD_F
100mA
W27
0.1uF
200-OHM-EMI
0.1uF
PCI-EXPRESS BUS INTERFACE
13B3
BGA
(1 OF 7)
IN
PEG_RESET_L
AF24
PERST*
PERST*_MASK
AA24
PCIE_TEST
AG24
NC
PCIE_CALRP
PCIE_CALRN
AD24
AE24
GPU_PCIE_CALRP
GPU_PCIE_CALRN
PCIE_CALI
AB24
GPU_PCIE_CALI
1%
1/16W
MF-LF
402
T26
AH26
T27
AH27
T29
AH29
U24
AJ26
U26
AJ28
U28
R8497 1
1.47K
1%
1/16W
MF-LF
402
R8496
562
1%
1/16W
MF-LF
402
ATI M56 PCI-E

AJ29
U29
AJ30
U30
AJ32
V24
AK26
V25
AK29
V26
AK30
V29
AK31
V31
SYNC_DATE=(MASTER)

AK32
W24
AL27
W26
SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
67
84
2
3
GPU VCore Current Sense
GPUISENS_NTC
1
1K
1
2.2UF
20%
6.3V
CERM1
603
GPUVCORE_BOOT_R
C8590
2.2UF
20%
6.3V
CERM1
603
0
5%
1/16W
MF-LF
402
5D7
Stuff 4.7ohm for

decreased slew rate
12
PVCC
VCC
U8500
5C7
ISL6269BCRZ
1
GPUVCORE_FSET
QFN
VIN
=GPUVCORE_EN
GPUVCORE_FCCM
64D8
=GPUVCORE_PGOOD
16
5D7
GPUVCORE_COMP
UG
R8508
C8507
150K
C8506
6
8
5%
50V
CERM
402
4.7
5%
1/16W
MF-LF
402
0.22UF
20%
6.3V
X5R
402
C8530
EN
NO STUFF
C8508
R8505
FCCM
PGOOD
COMP
FB
15
5C7
LG
11
PGND
10
5C7
1%
1/16W
MF-LF
402
GPUVCORE_LG
10%
50V
CERM
402
5%
1/16W
MF-LF
402
RJK0301DPB
C8522
SM
1000pF
GND_GPUVCORE_SGND
XW8500
XW8502
SM
SM
10%
25V
X7R
402
1M
1%
1/16W
MF-LF
402
C8592
470pF
2
LFPAK
1 2 3
18A max output
330UF
(L8520 limit)
20%
2.5V 2
POLY
CASE-D2E-LF
NO STUFF
C8520
10%
50V
CERM
402
1%
1/16W
MF-LF
402 2
10%
25V
X7R
402
C8542
0.0022uF
5.11K
1000pF
2
20%
6.3V
CERM
805
GPUVCORE_FB_RC
5C7
C8521
22UF
5%
1/16W
MF-LF
2 402
<Rb>
R8522 1
NO STUFF
C8540
R8520
0
1 2 3
RJK0301DPB
65A8
Vout = 1.10V / 0.95V
NO STUFF
1
3.01K
1%
1/16W
MF-LF
402 2
Q8522
53B6
R8592
GPUISENS_POS
<Ra>
R8521 1
Q8521
NO STUFF
OUT
=PPVCORE_S0_GPU_REG
CRITICAL
17
XW8501
GPUVCORE_IOUT
10%
50V
CERM
402
LFPAK
V-
THRML
PAD
SC70-5
FDA1055
5.11K
HPA00141AIDCKR
1.2UH
R8510
1
20.0K
L8520
GPUVCORE_PHASE
GPUVCORE_ISEN
R8591
1
CRITICAL
2
10%
6.3V
CERM
402
CRITICAL
V+
1%
1/16W
MF-LF
402
SWITCH_NODE=TRUE
VO
1 2 3
13
470pF
1uF
U8595
1
649
1%
1/16W
MF-LF
402
GPUISENS_NEG
GPUISENS_RC
R8590 1
10%
6.3V
CERM-X5R
402
RJK0305DPB
BOOT
PHASE
ISEN
Q8520
LFPAK
1%
1/16W
MF-LF
402
C8595
0.22UF
CRITICAL
1
C8591
GPUVCORE_COMP_R
1%
1/16W
MF-LF
2 402
1M
1%
1/16W
MF-LF
402
10%
6.3V
CERM-X5R
402
20%
16V
POLY
CASED2E-SM
GPUVCORE_BOOT
FSET
20.0K
CRITICAL
4
GPUVCORE_UG
57.6K
0.01UF
10%
16V
CERM
402
R8506
GPUVCORE_FB
15pF
1%
1/16W
MF-LF
402
5C7
R8598
1
R8593
0.47UF
CRITICAL
14
5C7
C8509
1%
1/16W
MF-LF
402
33uF
CRITICAL
64B5
10%
50V
CERM
402
R8509
R8504
Keep C8590, C8591

R8590, R8594 and R8597
close to inductor
R8594
C8500
0603-LF
NO STUFF
C8502
470pF
Placement Note:
1uF
10%
16V
X5R
603
C8598
10KOHM-5%
C8541
22UF
2
2
(GPUVCORE_FB)
C8543
330UF
20%
6.3V
CERM
805
20%
2 2.5V
POLY
CASE-D2E-LF
GND_GPUVCORE_PGND
<Rc>
R8523
12.4K
1
Vout(low)
Back-Bias Positive Supply
= 0.6V * (1 + Ra / Rb)
Vout(high) = 0.6V * (1 + Ra / Req)
Back-bias positive supply provides VDDC + 0.5V when active.

When inactive, provides VDDC to BBP pins.
NOTE: BBP tracks VDDC based on GPU voltage GPIO.
R8526
Req = Rb || Rc
Q8575
5%
1/16W
MF-LF
402
1
2
65A6
=PPVCORE_S0_GPU_BBP
68A5
68A8
10K
4
68A6 68A4
GPUBB_EN
VIN
PG
EN
ADJ
20%
6.3V
CERM1
603
10%
16V
CERM
402
2
5D7
C8556
24.9K
0.01UF
20%
6.3V
CERM
805
R8524
5%
1/16W
MF-LF
402
(LDO limit)
16.2K
1%
1/16W
MF-LF
2 402
2N7002
GPU_VCORE_HIGH
SOT23-LF
SOT-363
Back-bias negative supply provides VSS - 0.55V when active.

When inactive, provides VSS to BBN pins.
65A3
Vout(low)
=PP3V3_S0_GPUBBN
= 0.59V * (1 + Ra/Rb)
C8580
Vout(high) = 0.59V * (1 + Ra/Req)
20%
6.3V
X5R
603
65A1
68B8 68A6
=PP5V_S0_GPUBBCTL
1%
1/16W
MF-LF
402
A
GPU_GENERICD
0
1
D
1
2
5%
1/16W
MF-LF
402
Q8570
SOT23-LF
SHDN_L
IN
Vout = -Vin * Rb / Ra
<Rb>
R8588 1
CAP+
U8580
11.3K
2.2uF
MAX1673
1%
1/16W
MF-LF
402
20%
6.3V
CERM1
603
SOI
CRITICAL
GPUBBN_CAPN
6 5C7 GPUBBN_FB
C8581
CAP-
OUT
Recommended values:
Ra = Vin / 50 uA
Rb = -Vout / 50 uA
GPU (M56) Core Supplies
=PNVOUT_S0_GPUBBN_REG
1
C8570
0.0022uF
2N7002
68A4 68B8
68B7
NO STUFF
1
GPUBBN_CAPP
GPU_BB_CTL
1%
1/16W
MF-LF
402
FB
GPUBB_EN_L
68.1K
2
SI3446DV max Vgs is 1.6V

Vin must be > 2.8V
4.7K
For proper M56 power sequence, this

pull-up must be powered before VCore
GPUBB_EN
GPUBB_EN
Pull-up voltage must be high enough to

satisfy BBP FET Vgs (where Vs = 1.2V)
R8570 1
R8561
<Ra>
R8587 1
10uF
Req = Rb || Rc
74C3
Back-Bias Negative Supply
20%
6.3V
CERM
805
GPUBBP_ADJ_LOW
68B4
10%
16V
CERM-X5R
402
C8557
22UF
1%
1/16W
MF-LF
2 402
<Rc>
NO STUFF
R8554
174K
Q8554
SOT-363
10K
<Rb>
R8556
NO STUFF
GPUBBP_ADJ
1
GPU_VCORE_LOW
180mA max output
22UF
1%
1/16W
MF-LF
2 402
71C5
65D3
Vout = (1.58V /) 1.50V
<Ra>
R8555
C8555
2.2uF
C8523
0.022uF
2N7002DW-X-F
=PPVOUT_S0_GPUBBP_LDO
VOUT
GND
C8551
2N7002DW-X-F
GPU_VCORE_HIGH_RC
Q8523
U8550
FAN2558
SOT23-6-LF
1
2
5%
1/16W
MF-LF
402
Q8523
R8525
2
1
=PP3V3_S0_GPUBBP
GPU_VCORE_HIGH
CRITICAL
65A3
GPUBB_EN_L
GPUVCORE_FB_LOW
10K
SI3446DV
TSOP-LF
2
1%
1/16W
MF-LF
402
=PP3V3_S0_GPU
74D2 65A3
LIN/SKIP_L
GND
7
10%
50V
CERM
402
C8589
20%
6.3V
CERM
805
SYNC_DATE=(MASTER)
65D3
Vout = -0.55V
22UF
2

125mA max output

(Regulator limit)
R8560 1
10K
5%
1/16W
MF-LF
402 2
SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7150
SCALE
C8501
=PP3V3R5V_S0_GPUISENS
R8597
1K
1%
1/16W
MF-LF
402
65A3
CRITICAL
R8596 1
GPU VCore Supply
=PP5V_S0_GPUVCORE
65C1 =PPVIN_S0_GPUVCORE
65B1
A.0.0
OF
68
84
8
Page Notes

- =PP1V5_GPU_VDD15
- =PP1VR1V3_GPU_VCORE
(NONE)
(NONE)
U8400
M56P
BGA
(7 OF 7)
OMIT
=PPBB_S0_GPU
100mA (Preliminary)
C8691
C8692
22UF
1uF
0.1uF
20%
6.3V
CERM
805
10%
6.3V
CERM
402
10%
16V
X5R
402
20%
6.3V
CERM
805
V10
BBP
BBN
AC14
C8601
C8604
C8606
C8607
C8608
C8609
C8610
100mA (Preliminary)
P14
R19
22UF
22UF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
T16
20%
6.3V
CERM
805
20%
6.3V
CERM
805
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
T17
T18
U15
U16
U17
C8611
1uF
2
10%
6.3V
CERM
402
C8612
1uF
2
C8613
1uF
10%
6.3V
CERM
402
C8614
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C8615
1uF
2
10%
6.3V
CERM
402
C8616
V14
1uF
V15
10%
6.3V
CERM
402
5%
1/10W
MF-LF
603
VDDC
(1.0V/1.2V)
V16
R8630 1
70B8 70B5 70A8 70A5 65B6
=PNBB_S0_GPU
65D1
M6
M7
M8
M9
M24
M28
M32
N3
N7
N8
P1
P5
P6
P7
P15
V18
P17
W14
R3
W15
R6
W19
R14
AC11
R16
AC12
T10
AD11
T15
PPVCORE_S0_GPU_VDDCI
VOLTAGE=1.2V
AC17
R17
C8605
Y23
C8695
22UF
R18
C8600
10%
6.3V
CERM
402
R15
14.2A @ 445/452MHz Core/Mem Clk for VDDC+VDDCI
1uF
10%
16V
X5R
402
P19
=PPVCORE_S0_GPU
C8696
0.1uF
R10
P18
74A7 65A6 53C7 53A5
K15
M23
C8690
C8697
K18
MEMORY & CORE POWER / GROUND
65D1
T19
C8630
C8631
C8632
C8633
K14
U1
C8634
P16
U5
T14
22UF
1uF
1uF
1uF
1uF
20%
6.3V
CERM
805
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
T23
U19
U6
U7
VDDCI
(1.0V/1.2V)
U8
W10
U9
W17
U10
U14
2.0A @ 500MHz 1.8V GDDR3

A3
U18
A9
C8650
22UF
20%
6.3V
CERM
805
C8651
22UF
2
20%
6.3V
CERM
805
C8652
22UF
2
20%
6.3V
CERM
805
C8653
22UF
2
20%
6.3V
CERM
805
C8655
1uF
2
C8656
1uF
10%
6.3V
CERM
402
C8661
10%
6.3V
CERM
402
C8662
C8657
1uF
2
10%
6.3V
CERM
402
C8663
C8658
1uF
2
10%
6.3V
CERM
402
C8664
C8659
1uF
2
10%
6.3V
CERM
402
C8665
V3
C8660
A12
K23
F18
V6
1uF
A15
A2
F19
V17
A18
A8
F21
V19
A21
A11
F22
A24
A13
F24
A30
A16
F27
Y1
C1
A19
F30
Y5
10%
6.3V
CERM
402
C8666
1uF
1uF
1uF
1uF
1uF
C32
A22
G13
Y6
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
F32
A25
G16
Y7
H13
A31
G19
AA4
H19
B1
G20
AA6
C8667
C8668
C8669
C8670
C8671
B32
G21
AC9
J10
C4
G22
AC10
C8672
J11
C5
G25
AD6
J13
C6
H1
AD7
J18
C9
H5
AD8
J19
C10
H7
AD9
J20
C15
H16
AD10
C18
H20
AD13
C20
H21
C21
H28
1uF
1uF
1uF
1uF
1uF
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
J32
1
W18
1uF
J1
W16
VSS
C8673
C8674
C8675
C8676
C8677
C8678
K11
VSS
VDDR1
(1.8V/2.0V)
AD14
1uF
1uF
1uF
1uF
1uF
1uF
K13
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
K19
C24
H32
K20
C27
J3
AD17
K21
D11
J6
AE8
K24
D30
J9
AE14
C8679
C8680
C8681
C8682
E5
J12
AE15
L24
E8
J16
AE16
L32
E9
J21
AE17
1uF
1uF
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
AD16
L23
1uF
2
AD15
VSS
C8683
1uF
2
M1
E12
J24
AF14
M10
E13
J28
AF16
N9
E16
J30
AG11
N10
E19
K10
AG16
P8
E25
K12
AG23
P9
E28
K16
AH10
P10
E30
K17
AH11
R1
E32
K27
AH16
R9
F3
K30
AJ10
V1
F6
L1
AK16
Y8
F10
L6
AL1
AL13
Y9
F13
L7
Y10
F15
L29
AA1
F16
M3
ATI M56 Core Power

SYNC_DATE=(MASTER)
AM2

AM13

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
69
84
IO
72B6
IO
72B6
IO
72B6
IO
72B6
IO
72B6
IO
72B6
IO
72B6
IO
72B6
IO
72B6
IO
72B6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72A6
IO
72B3
IO
72B3
B
1
40.2
1%
1/16W
MF-LF
402
R8712
IO
72B3
IO
72B3
IO
72B3
IO
72B3
IO
72B3
IO
1%
1/16W
MF-LF
402
IO
72B3
IO
72B3
IO
72B3
IO
72A3
IO
72A3
IO
72A3
IO
72A3
IO
72A3
IO
72A3
IO
72A3
IO
72A3
IO
72A3
IO
72A3
IO
72A3
IO
72A3
IO
72A3
IO
72A3
IO
72A3
IO
72A3
IO
72A3
IO
72A3
IO
40.2
IO
72B3
72B3
IO
72A6
72A3
IO
72A3
IO
FB_A_DQ<0>
FB_A_DQ<1>
FB_A_DQ<2>
FB_A_DQ<3>
FB_A_DQ<4>
FB_A_DQ<5>
FB_A_DQ<6>
FB_A_DQ<7>
FB_A_DQ<8>
FB_A_DQ<9>
FB_A_DQ<10>
FB_A_DQ<11>
FB_A_DQ<12>
FB_A_DQ<13>
FB_A_DQ<14>
FB_A_DQ<15>
FB_A_DQ<16>
FB_A_DQ<17>
FB_A_DQ<18>
FB_A_DQ<19>
FB_A_DQ<20>
FB_A_DQ<21>
FB_A_DQ<22>
FB_A_DQ<23>
FB_A_DQ<24>
FB_A_DQ<25>
FB_A_DQ<26>
FB_A_DQ<27>
FB_A_DQ<28>
FB_A_DQ<29>
FB_A_DQ<30>
FB_A_DQ<31>
FB_A_DQ<32>
FB_A_DQ<33>
FB_A_DQ<34>
FB_A_DQ<35>
FB_A_DQ<36>
FB_A_DQ<37>
FB_A_DQ<38>
FB_A_DQ<39>
FB_A_DQ<40>
FB_A_DQ<41>
FB_A_DQ<42>
FB_A_DQ<43>
FB_A_DQ<44>
FB_A_DQ<45>
FB_A_DQ<46>
FB_A_DQ<47>
FB_A_DQ<48>
FB_A_DQ<49>
FB_A_DQ<50>
FB_A_DQ<51>
FB_A_DQ<52>
FB_A_DQ<53>
FB_A_DQ<54>
FB_A_DQ<55>
FB_A_DQ<56>
FB_A_DQ<57>
FB_A_DQ<58>
FB_A_DQ<59>
FB_A_DQ<60>
FB_A_DQ<61>
FB_A_DQ<62>
FB_A_DQ<63>
GPU_MVREFD0
GPU_MVREFS0
R8711 1
C8711
100
1%
1/16W
MF-LF
402
100
0.1uF
10%
16V
X5R
402
R8713
2
2
M30
L31
L30
H30
G31
G30
F31
M27
M29
L28
L27
J27
H29
G29
G27
M26
L26
M25
L25
J25
G28
H27
H26
F26
G26
H25
H24
H23
H22
J23
J22
E23
D22
D23
E22
E20
F20
D19
D18
B19
B18
C17
B17
C14
B14
C13
B13
D17
E18
E17
F17
E15
E14
F14
D13
H18
H17
G18
G17
G15
G14
H14
J14
C31
C30
A27
C8713
A28
0.1uF
1%
1/16W
MF-LF
402
M31
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15
MVREFD_0
MVREFS_0
(1.8V/
VDDRH0 2.0V)
VSSRH0
72B6
DQMA_0*
72B6
DQMA_1*
72B6
DQMA_2*
72B6
DQMA_3*
72B3
DQMA_4*
72B3
DQMA_5*
72B3
DQMA_6*
72B3
DQMA_7*
QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
QSA_0*
QSA_1*
QSA_2*
QSA_3*
QSA_4*
QSA_5*
QSA_6*
QSA_7*
CLKA0
CLKA0*
CSA0_0*
CSA0_1*
D26
F28
72B8
72B5
72B8
72B5
D25
72B8
72B5
72B8
72B5
E24
72B8
72B5
D28
E26
D27
F25
C26
B26
72B8
72B5
72B8
72B5
72B8
72B5
72B8
72B5
72B8
72B5
B27
72B8
72B5
72B8
72B5
E27
71C1
E29
72A8
72A5
B25
72A8
72A5
C25
72A8
72A5
D29
FB_A_MA<0>
FB_A_MA<1>
FB_A_MA<2>
FB_A_MA<3>
FB_A_MA<4>
FB_A_MA<5>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<8>
FB_A_MA<9>
FB_A_MA<10>
FB_A_MA<11>
TP_FB_A_MA12
FB_A_BA<2>
FB_A_BA<0>
FB_A_BA<1>
FB_A_DQM_L<0>
FB_A_DQM_L<1>
FB_A_DQM_L<2>
FB_A_DQM_L<3>
FB_A_DQM_L<4>
FB_A_DQM_L<5>
FB_A_DQM_L<6>
FB_A_DQM_L<7>
H31
J29
J26
G23
E21
B15
D14
J17
K25
F23
D20
B16
D16
H15
K31
72A8
K28
72A8
K26
72A8
G24
72A8
D21
72A5
C16
72A5
D15
72A5
J15
72A5
D31
72B8
E31
72B8
72B8
FB_A_WDQS<0>
FB_A_WDQS<1>
FB_A_WDQS<2>
FB_A_WDQS<3>
FB_A_WDQS<4>
FB_A_WDQS<5>
FB_A_WDQS<6>
FB_A_WDQS<7>
FB_A_CLK_P<0>
FB_A_CLK_N<0>
FB_A_CS_L<0>
IO
73A6
IO
73A6
IO
OUT
OUT
OUT
OUT
OUT
73A6
IO
73A6
IO
73A6
IO
73B6
IO
73B6
IO
OUT
73B6
IO
OUT
73B6
IO
OUT
73B6
IO
OUT
73B6
IO
OUT
73B6
IO
73B6
IO
OUT
OUT
73B6
IO
IO
73B6
IO
IO
73B6
IO
IO
73B6
IO
IO
73A6
IO
IO
73A6
IO
IO
73A6
IO
IO
73A6
IO
IO
73A6
IO
73A6
IO
IN
73A6
IO
IN
73A6
IO
IN
73A6
IO
IN
73A6
IO
IN
73A6
IO
IN
73A6
IO
IN
73A3
IO
IN
73A3
IO
OUT
73A3
IO
OUT
73A3
IO
73A3
IO
73A3
IO
73A3
IO
73A3
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
73A3
IO
73A3
IO
73A3
IO
73B3
IO
73B3
IO
73B3
IO
73B3
IO
73B3
IO
73B3
IO
73B3
IO
NC
72B8
FB_A_CKE<0>
OUT
B28
72A8
FB_A_RAS_L<0>
OUT
CASA0*
C29
72A8
FB_A_CAS_L<0>
OUT
WEA0*
B31
72A8
FB_A_WE_L<0>
OUT
TP_FB_A_ODT<0>
ODTA0
F29
CLKA1
CLKA1*
B20
72B5
C19
72B5
72B5
FB_A_CLK_P<1>
FB_A_CLK_N<1>
FB_A_CS_L<1>
OUT
OUT
OUT
70A8 70A5 69B8 65B6

70B8
OUT
NC
R8720
40.2
CKEA1
C22
72B5
FB_A_CKE<1>
RASA1*
B24
72A5
FB_A_RAS_L<1>
CASA1*
B22
72A5
FB_A_CAS_L<1>
OUT
WEA1*
B21
72A5
FB_A_WE_L<1>
OUT
ODTA1
D24
TP_FB_A_ODT<1>
OUT
OUT
OUT
1%
1/16W
MF-LF
402
73B3
IO
73B3
IO
73B3
IO
73B3
IO
73B3
IO
73A3
IO
73A3
IO
73A3
IO
73A3
IO
73A3
IO
73A3
IO
73A3
IO
73A3
IO
40.2
1%
1/16W
MF-LF
402
GPU_MVREFD1
GPU_MVREFS1
R8721 1
C8721
100
1%
1/16W
MF-LF
402
10%
16V
X5R
402
R8722
100
0.1uF
10%
16V
X5R
402
R8723
2
2
PP1V8R2V0_S0_GPU_VDDRH1
C8723
L8715
10%
16V
X5R
402
GPU_TEST_MCLK
GPU_TEST_YCLK
GPU_MEMTEST
70B8 70B5 70A8 69B8 65B6
FERR-220-OHM
PP1V8R2V0_S0_GPU_VDDRH0
0402
XW8715
SM
1
5%
1/16W
MF-LF
402
VOLTAGE=1.8V
1
0402
C8715
C8716
C8725
C8726
1uF
1uF
1uF
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
XW8725
SM
GND_GPU_VSSRH0
VOLTAGE=0V
C12
B11
C11
C8
B7
C7
B6
F12
D12
E11
F11
F9
D8
D7
F7
G12
G11
H12
H11
H9
E7
F8
G8
G6
G7
H8
J8
K8
L8
K9
L9
K5
L4
K4
L5
N5
N6
P4
R4
P2
R2
T3
T2
W3
W2
Y3
Y2
T4
R5
T5
T6
V5
W5
W6
Y4
R8
T8
R7
T7
V7
W7
W8
W9
B3
C3
F1
AA5
AA2
AA7
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
MAB_15
G4
73B8
73B5
E6
73B8
73B5
E4
73B8
73B5
73B6
DQMB_0*
73B6
DQMB_1*
73B6
DQMB_2*
73B6
DQMB_3*
73B3
DQMB_4*
73B3
DQMB_5*
73B3
DQMB_6*
73B3
DQMB_7*
B8
QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7
B9
MVREFD_1
MVREFS_1
(1.8V/
VDDRH1 2.0V)
VSSRH1
TEST_MCLK
TEST_YCLK
MEMTEST
FB_B_MA<0>
FB_B_MA<1>
FB_B_MA<2>
73B8
73B5 FB_B_MA<3>
73B8
73B5 FB_B_MA<4>
73B8
73B5 FB_B_MA<5>
73B8
73B5 FB_B_MA<6>
73B8
73B5 FB_B_MA<7>
73B8
73B5 FB_B_MA<8>
73B8
73B5 FB_B_MA<9>
73B8
73B5 FB_B_MA<10>
73B8
73B5 FB_B_MA<11>
71C1 TP_FB_B_MA12
73A8
73A5 FB_B_BA<2>
73A8
73A5 FB_B_BA<0>
73A8
73A5 FB_B_BA<1>
H4
J5
G5
F4
H6
G3
G2
D4
F2
F5
D5
H2
H3
D9
G9
K7
M5
V2
W4
T9
4.7K
5%
1/16W
MF-LF
402
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
V8
FB_B_RDQS<0>
73A8 FB_B_RDQS<1>
73A8 FB_B_RDQS<2>
73A8 FB_B_RDQS<3>
73A5 FB_B_RDQS<4>
73A5 FB_B_RDQS<5>
73A5 FB_B_RDQS<6>
73A5 FB_B_RDQS<7>
QSB_0*
QSB_1*
QSB_2*
QSB_3*
QSB_4*
QSB_5*
QSB_6*
QSB_7*
B10
73A8
V9
FB_B_WDQS<0>
73A8 FB_B_WDQS<1>
73A8 FB_B_WDQS<2>
73A8 FB_B_WDQS<3>
73A5 FB_B_WDQS<4>
73A5 FB_B_WDQS<5>
73A5 FB_B_WDQS<6>
73A5 FB_B_WDQS<7>
CLKB0
CLKB0*
B4
73B8
B5
FB_B_CLK_P<0>
73B8 FB_B_CLK_N<0>
CSB0_0*
CSB0_1*
D2
73B8
FB_B_CS_L<0>
D10
H10
K6
N4
U2
U4
E10
G10
J7
M4
U3
V4
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
NC
E3
CKEB0
C2
73B8
FB_B_CKE<0>
OUT
RASB0*
E2
73A8
FB_B_RAS_L<0>
OUT
CASB0*
D3
73A8
FB_B_CAS_L<0>
OUT
WEB0*
B2
73A8
FB_B_WE_L<0>
OUT
ODTB0
D6
TP_FB_B_ODT<0>
OUT
CLKB1
CLKB1*
N2
P3
FB_B_CLK_P<1>
73B5 FB_B_CLK_N<1>
CSB1_0*
CSB1_1*
K2
73B5
FB_B_CS_L<1>
73B5
OUT
OUT
OUT
NC
K3
CKEB1
L3
73B5
FB_B_CKE<1>
RASB1*
J2
73A5
FB_B_RAS_L<1>
CASB1*
L2
73A5
FB_B_CAS_L<1>
OUT
WEB1*
M2
73A5
FB_B_WE_L<1>
OUT
ODTB1
J4
TP_FB_B_ODT<1>
OUT
DRAM_RST
OUT
73A8
AA3
73A8
73A5 72A8
72A5
OUT
FB_DRAM_RST
OUT
OUT
R8733
4.7K
2
1
R8730
OUT
FB_B_DQM_L<0>
FB_B_DQM_L<1>
FB_B_DQM_L<2>
FB_B_DQM_L<3>
FB_B_DQM_L<4>
FB_B_DQM_L<5>
FB_B_DQM_L<6>
FB_B_DQM_L<7>
4.7K
L8725
VOLTAGE=1.8V
FERR-220-OHM
B12
E1
0.1uF
1%
1/16W
MF-LF
402
R8731
70B8
70A5
65B6
69B8
70B5
FB_B_DQ<0>
FB_B_DQ<1>
FB_B_DQ<2>
FB_B_DQ<3>
FB_B_DQ<4>
FB_B_DQ<5>
FB_B_DQ<6>
FB_B_DQ<7>
FB_B_DQ<8>
FB_B_DQ<9>
FB_B_DQ<10>
FB_B_DQ<11>
FB_B_DQ<12>
FB_B_DQ<13>
FB_B_DQ<14>
FB_B_DQ<15>
FB_B_DQ<16>
FB_B_DQ<17>
FB_B_DQ<18>
FB_B_DQ<19>
FB_B_DQ<20>
FB_B_DQ<21>
FB_B_DQ<22>
FB_B_DQ<23>
FB_B_DQ<24>
FB_B_DQ<25>
FB_B_DQ<26>
FB_B_DQ<27>
FB_B_DQ<28>
FB_B_DQ<29>
FB_B_DQ<30>
FB_B_DQ<31>
FB_B_DQ<32>
FB_B_DQ<33>
FB_B_DQ<34>
FB_B_DQ<35>
FB_B_DQ<36>
FB_B_DQ<37>
FB_B_DQ<38>
FB_B_DQ<39>
FB_B_DQ<40>
FB_B_DQ<41>
FB_B_DQ<42>
FB_B_DQ<43>
FB_B_DQ<44>
FB_B_DQ<45>
FB_B_DQ<46>
FB_B_DQ<47>
FB_B_DQ<48>
FB_B_DQ<49>
FB_B_DQ<50>
FB_B_DQ<51>
FB_B_DQ<52>
FB_B_DQ<53>
FB_B_DQ<54>
FB_B_DQ<55>
FB_B_DQ<56>
FB_B_DQ<57>
FB_B_DQ<58>
FB_B_DQ<59>
FB_B_DQ<60>
FB_B_DQ<61>
FB_B_DQ<62>
FB_B_DQ<63>
IO
73A3
B30
C23
IO
OUT
CKEA0
B23
IO
73A6
OUT
RASA0*
CSA1_0*
CSA1_1*
73A6
73A6
FB_A_RDQS<0>
72A8 FB_A_RDQS<1>
72A8 FB_A_RDQS<2>
72A8 FB_A_RDQS<3>
72A5 FB_A_RDQS<4>
72A5 FB_A_RDQS<5>
72A5 FB_A_RDQS<6>
72A5 FB_A_RDQS<7>
K29
C28
OUT
72A8
J31
B29
OUT
IO
72B6
BGA
(4 OF 7)
MEMORY INTERFACE A
72B6
M56P
BGA
(3 OF 7)
READ STROBE
R8710
OMIT
U8400
WRITE STROBE

(NONE)
70B5
69B8 65B6
70A8 70A5
OMIT
U8400
M56P

(NONE)
MEMORY INTERFACE B

- =PP1V8R2V0_S0_FB_GPU
READ STROBE
WRITE STROBE
8
Page Notes
5%
1/16W
MF-LF
402
R8732
243
1%
1/16W
MF-LF
402
ATI M56 Frame Buffer I/F
GND_GPU_VSSRH1
VOLTAGE=0V
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
70
84
ROMCFGID[3..0]
=PP3V3_D3C_GPU_GPIOS
NO STUFF
R8800 1
Misc
GPU_GPIO_0
74D3
GPU_GPIO_1
74D3
GPU_GPIO_2
74D3
GPU_GPIO_3
74D3
GPU_GPIO_4
74D3
GPU_GPIO_5
74D3
GPU_GPIO_6
74D3
GPU_GPIO_7
74D3
GPU_GPIO_8
74C3
GPU_GPIO_9
74C3
GPU_GPIO_10
74C3
GPU_GPIO_11
74C3
GPU_GPIO_12
TESTIN[0]
TX_PWRS_ENb
IPD
TESTIN[1]
TX_DEEMPH_EN
TESTIN[2]
Reserved
TESTIN[3]
Reserved
TESTIN[4]
DEBUG_ACCESS
TESTIN[5]
Reserved
TESTIN[6]
Reserved
GPU_MEM_256M
R8812 1
10K
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R8801
NO STUFF
1
R8803
NO STUFF
1
R8805
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
GPU_MEM_64M
1
R8808
10K
R8813
R8824 1
10K
5%
1/16W
MF-LF
402
Straps
IPD
GPU_MEM_256M
R8809 1
10K
2
74D3
NO STUFF
R8806 1
5%
1/16W
MF-LF
402
GPU_DEEPMH_EN
TestBus
NO STUFF
R8804 1
128MB
256MB
64MB
Reserved
10K
Serial ROM
NO STUFF
R8802 1
=
=
=
=
NO STUFF
1
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
GPU_MEM_NOT_SAM
R8811
R8827
10K
5%
1/16W
MF-LF
402
Renamed signals
34B4 34B2
VDD_VCL
IPD
GPU_CLK27M
GPU_XTALIN
Unused signals
NC_GPU_XTALOUT
MAKE_BASE=TRUE
IPD
TESTIN[7]
ROMSO
TESTWR
MAKE_BASE=TRUE
GPU_BLON
ROMSI
MAKE_BASE=TRUE
IPD
TESTOUT[9]
ROMIDCFG[0]
IPD
TESTOUT[10]
ROMIDCFG[1]
IPD
TESTOUT[11]
ROMIDCFG[2]
Required for debug access
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_GPU_VGA_R
GPU_GPIO_13
74C3
GPU_GPIO_14
MAKE_BASE=TRUE
NC_GPU_GPIO_14
74C3
GPU_GPIO_15
74C3
GPU_GPIO_16
TESTIN[9]
PWRCNTL
GPU_VCORE_LOW
MAKE_BASE=TRUE
GPU_CLK27MSS_IN
TP_GPU_VGA_HSYNC
34B2 34B4
TP_GPU_VGA_VSYNC
Thm Mon Int
GPU_GPIO_17
NC_GPU_GPIO_17
NO_TEST=TRUE
NC_GPU_TV_Y
MAKE_BASE=TRUE
GPU_GPIO_18
74D5
GPU_GPIO_19
74D5
GPU_GPIO_20
74D5
GPU_GPIO_21
74D5
GPU_GPIO_22
74D5
GPU_GPIO_23
74D5
GPU_GPIO_24
74D5
GPU_GPIO_25
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_LVDS_U_DATAP<3>
NC_GPU_GPIO_21
NC_LVDS_U_DATAN<3>
MAKE_BASE=TRUE
74D5
GPU_GPIO_26
GPU_GPIO_27
75B3
GPU_TV_C
75B3
GPU_TV_COMP
75B3
LVDS_U_DATA_P<3>
75B3
LVDS_U_DATA_N<3>
75B3
LVDS_L_DATA_P<3>
75A3
LVDS_L_DATA_N<3>
75A3
ATI_DVPCLK
74C3
ATI_DVPCNTL<2..0>
74B3 74C3
ATI_DVPDATA<15..0>
74B3
NO_TEST=TRUE
NC_GPU_GPIO_22
NC_LVDS_L_DATAP<3>
NC_GPU_GPIO_23
NC_LVDS_L_DATAN<3>
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
GPU_MEM_256M
NO_TEST=TRUE
NC_ATI_DVPCLK
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_ATI_DVPCNTL<2..0>
MAKE_BASE=TRUE
NC_GPU_GPIO_26
NO_TEST=TRUE
NC_ATI_DVPDATA<15..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
75B3
GPU_TV_Y
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
74D5
75B3
GPU_VGA_VSYNC
NO_TEST=TRUE
NC_GPU_GPIO_20
NC_GPU_GPIO_25
MAKE_BASE=TRUE
NO_TEST=TRUE
75C3
GPU_VGA_HSYNC
NO_TEST=TRUE
NC_GPU_TV_COMP
NC_GPU_GPIO_19
MAKE_BASE=TRUE
NO_TEST=TRUE
75C3
GPU_VGA_B
NO_TEST=TRUE
NC_GPU_TV_C
NC_GPU_GPIO_18
MAKE_BASE=TRUE
NO_TEST=TRUE
GPU_VGA_G
MAKE_BASE=TRUE
MAKE_BASE=TRUE
74D5
75C3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
74C3
74C3
GPU_VGA_R
NO_TEST=TRUE
68B4
MAKE_BASE=TRUE
SS_IN
74C3
GPU_GENERICC
NO_TEST=TRUE
NC_GPU_VGA_B
NO_TEST=TRUE
MAKE_BASE=TRUE
74C3
GPU_GENERICB
NO_TEST=TRUE
NC_GPU_VGA_G
TESTIN[8]
GPU_GENERICA
NO_TEST=TRUE
MAKE_BASE=TRUE
74C3
70D1
NO_TEST=TRUE
NC_GPU_GENERICC
70D5
TP_FB_B_MA12
NO_TEST=TRUE
NC_GPU_GENERICB
TP_GPU_GPIO_10
TP_FB_A_MA12
NO_TEST=TRUE
NC_GPU_GENERICA
ROMIDCFG[3]
TESTOUT[8]
74A3
NO_TEST=TRUE
NC_FB_B_MA12
MAKE_BASE=TRUE
ROMSCK
74A5
TP_ATI_ROMCS_L
NO_TEST=TRUE
MAKE_BASE=TRUE
79A4
MAKE_BASE=TRUE
Reserved
GPU_XTALOUT
NO_TEST=TRUE
NC_ATI_ROMCS_L
NC_FB_A_MA12
ENA_BL
74A5
MAKE_BASE=TRUE
MAKE_BASE=TRUE
GPU_MEMID
NO_TEST=TRUE
MAKE_BASE=TRUE
74D5
GPU_GPIO_28
74C5
GPU_GPIO_29
74C5
GPU_GPIO_30
74C5
GPU_GPIO_31
74C5
GPU_GPIO_32
74C5
GPU_GPIO_33
74C5
GPU_GPIO_34
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_29
NC_GPU_GPIO_30
TP_ATI_DVPDATA<23..16>
ATI_DVPDATA<23..16>
74A3
74B3
MAKE_BASE=TRUE
NC_GPU_GPIO_31
Also required: GPIO10 - GPIO13
NC_GPU_GPIO_32
NC_GPU_GPIO_33
65A3
=PP3V3_D3C_GPU
NC_GPU_GPIO_34
MAKE_BASE=TRUE
NO_TEST=TRUE
R8890 1
R8891 1
4.7K
5%
1/16W
MF-LF
402
75A3
75A3
4.7K
5%
1/16W
MF-LF
402
NC_GPU_GPIO_28
MAKE_BASE=TRUE
NO_TEST=TRUE
65A3
0000
0010
0100
0110
GPU_DDC_B_CLK
GPU_DDC_B_DATA
GPU Straps
SYNC_MASTER=M59_MG

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
71
84
22UF
20%
6.3V
CERM
805
C8901
C8902
C8903
C8904
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
F1
PP1V8_S0_FB_A0_VDDA0
VOLTAGE=1.8V
0402
L8915
FERR-220-OHM
1
M1
VDD3
VDD4
M12
VDD5
V2
VDD6
VDD7
V11
FERR-220-OHM
VDD1
VDD2
F12
L8910
1
VDD0
VOLTAGE=1.8V
0402
C8910
C8915
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
U8900.J1
22UF
20%
6.3V
CERM
805
C8921
C8922
C8924
C8925
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
R8932
2.37K
2.37K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
VSSA1
J12
R8931
R8933
5.49K
FERR-220-OHM
1
VDDQ3
VDDQ4
VSSQ3
VSSQ4
B12
VDDQ5
VSSQ5
D4
VDDQ6
VDDQ7
VSSQ6
VSSQ7
D9
E9
VDDQ8
VSSQ8
G2
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
VSSQ9
VSSQ10
G11
J9
VDDQ11
VSSQ11
L11
F1
L8965
C8960
C8965
0.1uF
VOLTAGE=1.8V
0402
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
U8900.J1
IN
M1
VDD3
VDD4
M12
VDD5
V2
VDD6
VDD7
22UF
20%
6.3V
CERM
805
C8971
C8972
C8973
C8974
C8975
C8976
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
VDDQ3
VDDQ4
VSSQ3
VSSQ4
B12
C9
C12
VDDQ5
VSSQ5
D4
E1
VDDQ6
VDDQ7
VSSQ6
VSSQ7
D9
E4
E9
VDDQ8
VSSQ8
G2
G11
J9
VDDQ11
VSSQ11
L11
N1
VDDQ12
VDDQ13
VSSQ12
VSSQ13
P1
VDDQ14
VDDQ15
VSSQ14
VSSQ15
P9
N12
R1
VDDQ16
VSSQ16
T1
R4
VDDQ17
VDDQ18
VSSQ17
VSSQ18
T4
R9
R12
VDDQ19
VSSQ19
T12
V1
VDDQ20
VDDQ21
VDDQ16
VSSQ16
T1
2.37K
R12
VDDQ19
VSSQ19
T12
V1
VDDQ20
VDDQ21
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
H1
VREF0
H12
VREF1
R8982
FB_A1_VREF0
V12
FB_A1_VREF1
D12
VSSQ9
VSSQ10
R1
2.37K
D1
VDDQ9
VDDQ10
VSSQ14
VSSQ15
H1
VREF0
H12
VREF1
B9
J4
VDDQ14
VDDQ15
R8980
J12
B4
N12
T9
J1
VSSA1
VSSQ1
VSSQ2
N9
T4
VSSA0

(NONE)
V10
VDDQ1
VDDQ2
N4
VSSQ17
VSSQ18
V3
A12
P9
VDDQ17
VDDQ18
L12
VSS6
VSS7
B1
P4
R9
VSS5

(NONE)
L1
VSSQ0
P1
G12

- =PP1V8_S0_FB_VDD
- =PP1V8_S0_FB_VDDQ
G1
VDDQ0
VSSQ12
VSSQ13
VSS3
VSS4
A1
VDDQ12
VDDQ13
P12
A10
VDDA1
E12
1
A3
VSS1
VSS2
VDDA0
=PP1V8_S0_FB_VDDQ
C8970
L2
FBGA
(2 OF 2)
VSS0
K1
C4
U8900.J12
U8950
K12
C1
Connect to designated pin, then GND

73D8 73D5 72D8 65B6
VDDQ9
VDDQ10
VDD1
VDD2
F12
VOLTAGE=1.8V
0402
D12
J4
C8954
0.1uF
10%
16V
X5R
402
D1
E4
C8953
0.1uF
VDD0
L2
P4
P12
T9
5.49K
1%
1/16W
MF-LF
402 2
C8952
10%
16V
X5R
402
1
0.1uF
A2
A11
V11
B9
V12
FB_A0_VREF1
J1
B4
FB_A0_VREF0
FERR-220-OHM
VSSA0
C8951
L8960
VSSQ1
VSSQ2
R4
V10
L1
VDDQ1
VDDQ2
N9
R8930
V3
20%
6.3V
CERM
805
A12
N1
L12
VSS6
VSS7
22UF
B1
N4
VSS5
C8950
VSSQ0
C9
C8926
G12
G1
VDDQ0
C12
C8923
VSS3
VSS4
A1
E12
1
A10
VDDA1
=PP1V8_S0_FB_VDDQ
C8920
A3
VSS1
VSS2
K12
E1
72D5 65B6
73D8 73D5 IN
VSS0
VDDA0
C4
FBGA
(2 OF 2)
CRITICAL
OMIT
=PP1V8_S0_FB_VDD
K1
C1
U8900.J12
U8900
K4J52324QC-BC20
C8900
A2
A11
IN
1
Page Notes
73D8 73D5 72D8 65B6
K4J52324QC-BC20
CRITICAL
OMIT
=PP1V8_S0_FB_VDD
16MX32-GDDR3-500MHZ
72D5 65B6
73D8 73D5 IN
16MX32-GDDR3-500MHZ
1%
1/16W
MF-LF
402 2
C8931
C8933
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
R8981
R8983
5.49K
5.49K
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
C8981
C8983
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
NOTE: U8900 DQ0-7 MUST connect to GPU
IN
72B5 70D5
IN
72B5 70D5
IN
72B5 70D5
IN
72B5 70D5
IN
72B5 70D5 IN
72B5 70D5
IN
72B5 70D5
IN
72B5 70D5
IN
72B5 70D5
IN
72B5 70D5
IN
72B5 70D5
IN
70B5
IN
70B5
IN
70B5
IN
70B5
70B5
IN
IN
70B5 IN
70B5
IN
121
R8945
60.4
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
2
121
72A5 70A1
73A8 73A5 IN
70C5
70C5
70C5
70C5
OUT
OUT
OUT
OUT
70C5 IN
70C5
IN
70C5
IN
70C5
IN
72A5 70D5
IN
72A5 70D5
72A5 70D5
IN
IN
A0
U8900
DM0
E3
70D5
IN
72B8 70D5
IN
A1
FBGA
DM1
E10
70C5
IN
72B8 70D5
IN
A2
A3
(1 OF 2)
DM2
DM3
N10
70C5
IN
72B8 70D5
IN
IN
72B8 70D5
IN
72B8 70D5
DQ0
B2 70D7
IN
H2
A4
A5
K3
A6
L4
A7
A8/AP
K2
M4
B11
J11
70D7
DQ9
B10
J10
CK
CK*
70D7
DQ10
C11
F4
CS*
70D7
DQ11
C10
H4
70D7
DQ12
70D7
DQ13
E11
F9
WE*
CAS*
H10
RAS*
70D7
DQ14
F11
70D7
DQ15
70C7
DQ16
G10
A9
ZQ
MF
V4
SEN
70D7
DQ17
L10
RESET
70C7
DQ18
N11
70D7
DQ19
M10
70C7
DQ20
70C7
DQ21
R11
R8949
243
100
1%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402
2
RDQS0
RDQS1
RDQS2
RDQS3
F10
M11
R10
70C7
DQ22
T11
T10
D2
WDQS0
70C7
DQ23
DQ24
D11
WDQS1
DQ25
L3 70C7
P11
DQ26
DQ27
N2 70C7
P2
WDQS2
WDQS3
R2 70C7
BA0
DQ28
G9
DQ29
DQ30
R3 70C7
DQ31
T3 70C7
G4
R8948
F2 70D7
F3 70D7
G3 70D7
P3
NC
NC
DQ6
DQ7
P10
DQ4
DQ5
E2 70D7
70D7
DQ8
D10
C3 70D7
CKE
D3
FB_A_BA<0>
FB_A_BA<1>
FB_A_BA<2>
C2 70D7
H9
V9
FB_A_WDQS<0>
FB_A_WDQS<1>
FB_A_WDQS<2>
FB_A_WDQS<3>
DQ3
B3 70D7
L9
A4
FB_A_RDQS<0>
FB_A_RDQS<1>
FB_A_RDQS<2>
FB_A_RDQS<3>
A9
DQ1
DQ2
N3
A10
A11
K11
FB_DRAM_RST
FB_A_DQM_L<0>
FB_A_DQM_L<1>
FB_A_DQM_L<2>
70C5 FB_A_DQM_L<3>
K9
K10
K4
FB_A0_ZQ
FB_A0_MF
FB_A0_SEN
5%
1/16W
MF-LF
402
2
H11
M9
BA1
H3
BA2
J2
RFU1
J3
RFU2
R8991
1K
CRITICAL
OMIT
1%
1/16W
MF-LF
402
2
FB_A_CKE<0>
FB_A_CLK_P<0>
FB_A_CLK_N<0>
FB_A_CS_L<0>
FB_A_WE_L<0>
FB_A_CAS_L<0>
FB_A_RAS_L<0>
2
1
R8947
FB_A_MA<0>
FB_A_MA<1>
FB_A_MA<2>
FB_A_MA<3>
FB_A_MA<4>
FB_A_MA<5>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<8>
FB_A_MA<9>
FB_A_MA<10>
FB_A_MA<11>
1%
1/16W
MF-LF
402
M2 70C7
M3 70C7
T2 70C7
FB_A_DQ<0>
FB_A_DQ<1>
FB_A_DQ<2>
FB_A_DQ<3>
FB_A_DQ<4>
FB_A_DQ<5>
FB_A_DQ<6>
FB_A_DQ<7>
FB_A_DQ<8>
FB_A_DQ<9>
FB_A_DQ<10>
FB_A_DQ<11>
FB_A_DQ<15>
FB_A_DQ<14>
FB_A_DQ<12>
FB_A_DQ<13>
FB_A_DQ<19>
FB_A_DQ<16>
FB_A_DQ<18>
FB_A_DQ<17>
FB_A_DQ<23>
FB_A_DQ<21>
FB_A_DQ<20>
FB_A_DQ<22>
FB_A_DQ<24>
FB_A_DQ<25>
FB_A_DQ<26>
FB_A_DQ<27>
FB_A_DQ<29>
FB_A_DQ<30>
FB_A_DQ<28>
FB_A_DQ<31>
IO
IO
IO
IO
IO
IO
IO
72B8 70D5
IN
72B8 70D5
IN
72B8 70D5
IN
72B8 70D5
IN
72B8 70D5
IN
72B8 70D5
IN
72B8 70D5
IN
2
1
R8996 1
60.4
1%
1/16W
MF-LF
402
2
1
R8993
121
R8995
60.4
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
2
R8997
121
CRITICAL
OMIT
1%
1/16W
MF-LF
402
FB_A_MA<0>
FB_A_MA<1>
FB_A_MA<2>
FB_A_MA<3>
FB_A_MA<4>
FB_A_MA<5>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<8>
FB_A_MA<9>
FB_A_MA<10>
FB_A_MA<11>
A0
U8950
DM0
E3
70C5
IN
A1
FBGA
DM1
E10
70C5
IN
K10
A2
A3
(1 OF 2)
DM2
DM3
N10
70C5
DQ0
B2 70C7
DQ1
DQ2
B3 70C7
DQ3
C3 70C7
DQ4
DQ5
E2 70C7
DQ6
F2 70C7
M9
H2
A4
A5
K3
A6
L4
A7
A8/AP
K4
K2
M4
A9
IO
IN
IO
70B5
IN
IO
70B5
IN
IO
70B5
IO
70B5
IO
70B5 IN
IO
70B5
IN
IN
IN
FB_A_CKE<1>
FB_A_CLK_P<1>
FB_A_CLK_N<1>
FB_A_CS_L<1>
FB_A_WE_L<1>
FB_A_CAS_L<1>
FB_A_RAS_L<1>
FB_A1_ZQ
FB_A1_MF
FB_A1_SEN
IO
IO
IO
IO
IO
IO
IO
IO
73A5 72A8 70A1

73A8 IN
70C5
70C5
70C5
70C5
OUT
OUT
OUT
OUT
DQ7
G3 70C7
CKE
70C7
DQ8
B11
J11
70C7
DQ9
B10
J10
CK
CK*
70C7
DQ10
C11
F4
CS*
70C7
DQ11
C10
H4
70B7
DQ12
70B7
DQ13
E11
F9
WE*
CAS*
H10
RAS*
70B7
DQ14
F11
70B7
DQ15
70B7
DQ16
G10
A9
ZQ
MF
V4
SEN
70B7
DQ17
L10
RESET
70B7
DQ18
N11
70B7
DQ19
M10
70B7
DQ20
70B7
DQ21
R11
70B7
DQ22
T11
T10
D3
D10
P10
P3
RDQS0
RDQS1
RDQS2
RDQS3
70C5 IN
IO
70C5
IO
70C5
IN
IO
70C5
IN
72A8 70D5
IN
IO
IO
IO
72A8 70D5
72A8 70D5
IN
IN
IN
FB_A_WDQS<4>
FB_A_WDQS<5>
FB_A_WDQS<6>
FB_A_WDQS<7>
FB_A_BA<0>
FB_A_BA<1>
FB_A_BA<2>
R8998
R8999
243
100
1%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402
2
NC
NC
R10
WDQS0
D11
WDQS1
DQ25
L3 70B7
P11
DQ26
DQ27
N2 70B7
P2
WDQS2
WDQS3
R2 70B7
BA0
DQ28
G9
DQ29
DQ30
R3 70B7
DQ31
T3 70B7
BA1
H3
BA2
J2
RFU1
J3
RFU2
IO
1
M11
D2
G4
F10
70B7
DQ23
DQ24
IO
IO
F3 70C7
H9
V9
FB_A_RDQS<4>
FB_A_RDQS<5>
FB_A_RDQS<6>
FB_A_RDQS<7>
C2 70C7
L9
A4
FB_DRAM_RST
N3
A10
A11
K11
IO
70B5
FB_A_DQM_L<4>
FB_A_DQM_L<5>
FB_A_DQM_L<6>
70C5 FB_A_DQM_L<7>
K9
H11
K4J52324QC-BC20
5%
1/16W
MF-LF
402
2
R8943
GDDR3 vendor/device identification scheme.
121
1%
1/16W
MF-LF
402
MFHIGH
1K
R8994 1
121
1%
1/16W
MF-LF
402
16MX32-GDDR3-500MHZ
R8941
R8992 1
121
MFHIGH
R8990 1
how these bits are mapped for GPU to support
K4J52324QC-BC20
1%
1/16W
MF-LF
402
16MX32-GDDR3-500MHZ
60.4
1%
1/16W
MF-LF
402
MFHIGH
121
1%
1/16W
MF-LF
402
MFHIGH
121
1%
1/16W
MF-LF
402
Bits can be swapped
within byte-lane, but software must know
R8946 1
121
72B5 70D5
R8944 1
MFHIGH
R8942 1
MFHIGH
DQA0-7 or DQA8-15.
R8940 1
M2 70B7
M3 70B7
T2 70B7
FB_A_DQ<32>
FB_A_DQ<34>
FB_A_DQ<33>
FB_A_DQ<35>
FB_A_DQ<36>
FB_A_DQ<37>
FB_A_DQ<38>
FB_A_DQ<39>
FB_A_DQ<40>
FB_A_DQ<41>
FB_A_DQ<42>
FB_A_DQ<43>
FB_A_DQ<46>
FB_A_DQ<44>
FB_A_DQ<47>
FB_A_DQ<45>
FB_A_DQ<48>
FB_A_DQ<49>
FB_A_DQ<50>
FB_A_DQ<51>
FB_A_DQ<52>
FB_A_DQ<55>
FB_A_DQ<54>
FB_A_DQ<53>
FB_A_DQ<60>
FB_A_DQ<59>
FB_A_DQ<61>
FB_A_DQ<57>
FB_A_DQ<62>
FB_A_DQ<56>
FB_A_DQ<63>
FB_A_DQ<58>
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GDDR3 Frame Buffer A
IO
IO
IO
IO
SYNC_DATE=(MASTER)
IO

IO
IO

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
72
84
C9003
C9004
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
F1
F12
L9010
PP1V8_S0_FB_B0_VDDA0
VOLTAGE=1.8V
0402
L9015
FERR-220-OHM
1
M12
VDD5
V2
VDD6
VDD7
V11
FERR-220-OHM
1
M1
VDD3
VDD4
VOLTAGE=1.8V
0402
C9010
C9015
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
U9000.J1
22UF
20%
6.3V
CERM
805
C9021
C9022
C9024
C9025
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
R9032
2.37K
2.37K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
FERR-220-OHM
B9
VDDQ3
VDDQ4
VSSQ3
VSSQ4
B12
VDDQ5
VSSQ5
D4
C
R9031
R9033
5.49K
VDDQ6
VDDQ7
VSSQ6
VSSQ7
D9
E9
VDDQ8
VSSQ8
G2
R9040 1
VSSQ9
VSSQ10
G11
J9
VDDQ11
VSSQ11
L11
VOLTAGE=1.8V
0402
IN
22UF
20%
6.3V
CERM
805
C9071
C9072
IN
73B5 70D1
IN
73B5 70D1
IN
73B5 70D1
IN
73B5 70D1
IN
73B5 70D1
IN
73B5 70D1
IN
73B5 70D1
IN
70B1
IN
70B1
IN
70B1
IN
70B1
IN
70B1
IN
70B1
IN
70B1
IN
70C1
70C1
70C1
70C1
OUT
OUT
OUT
OUT
70C1 IN
70C1
IN
70C1
IN
70C1
IN
73A5 70D1
IN
73A5 70D1
73A5 70D1
IN
IN
10%
16V
X5R
402
121
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
10%
16V
X5R
402
FB_B_CKE<0>
FB_B_CLK_P<0>
FB_B_CLK_N<0>
FB_B_CS_L<0>
FB_B_WE_L<0>
FB_B_CAS_L<0>
FB_B_RAS_L<0>
VDDQ3
VDDQ4
VSSQ3
VSSQ4
B12
C9
C12
VDDQ5
VSSQ5
D4
E1
VDDQ6
VDDQ7
VSSQ6
VSSQ7
D9
E4
E9
VDDQ8
VSSQ8
G2
VDDQ17
VDDQ18
VSSQ17
VSSQ18
T4
R9080
T9
2.37K
2.37K
R12
VDDQ19
VSSQ19
T12
V1
VDDQ20
VDDQ21
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
H1
VREF0
H12
VREF1
R9082
FB_B1_VREF0
FB_B1_VREF1
D12
VSSQ9
VSSQ10
G11
J9
VDDQ11
VSSQ11
L11
N1
VDDQ12
VDDQ13
VSSQ12
VSSQ13
P1
VDDQ14
VDDQ15
VSSQ14
VSSQ15
P9
N12
R1
VDDQ16
VSSQ16
T1
R4
VDDQ17
VDDQ18
VSSQ17
VSSQ18
T4
R9
R12
VDDQ19
VSSQ19
T12
V1
VDDQ20
VDDQ21
V12
D1
VDDQ9
VDDQ10
H1
VREF0
H12
VREF1
B9
J4
T1
R9
J12
B4
VSSQ16
J1
VSSA1
VSSQ1
VSSQ2
VDDQ16
VSSA0

(NONE)
V10
VDDQ1
VDDQ2
R1
P12
V3
A12
VSSQ14
VSSQ15
R9081
R9083
5.49K
1%
1/16W
MF-LF
402 2
R9092 1
DM0
E3
70C1
IN
73B8 70D1
IN
FBGA
DM1
E10
70C1
IN
73B8 70D1
IN
(1 OF 2)
DM2
DM3
N10
70C1
IN
73B8 70D1
IN
IN
73B8 70D1
IN
73B8 70D1
DQ0
B2 70D3
IN
H2
K3
A6
L4
A7
A8/AP
DQ3
B3 70D3
C2 70D3
C3 70D3
DQ4
DQ5
E2 70D3
DQ6
F2 70D3
F3 70D3
L9
DQ7
G3 70D3
H9
CKE
70C3
DQ8
B11
J11
70D3
DQ9
B10
J10
CK
CK*
70C3
DQ10
C11
F4
CS*
70D3
DQ11
C10
H4
70C3
DQ12
70C3
DQ13
E11
F9
WE*
CAS*
H10
RAS*
70C3
DQ14
F11
70C3
DQ15
70C3
DQ16
G10
A9
ZQ
MF
V4
SEN
70C3
DQ17
L10
RESET
70C3
DQ18
N11
70C3
DQ19
M10
70C3
DQ20
70C3
DQ21
R11
P10
P3
RDQS0
RDQS1
RDQS2
RDQS3
F10
M11
R10
70C3
DQ22
T11
T10
D2
WDQS0
70C3
DQ23
DQ24
D11
WDQS1
DQ25
L3 70D3
P11
DQ26
DQ27
N2 70D3
P2
WDQS2
WDQS3
R2 70D3
BA0
DQ28
G9
DQ29
DQ30
R3 70D3
DQ31
T3 70D3
G4
NC
NC
A9
DQ1
DQ2
N3
A10
A11
D10
FB_B_BA<0>
FB_B_BA<1>
FB_B_BA<2>
FB_B_DQM_L<1>
FB_B_DQM_L<2>
FB_B_DQM_L<3>
70D1 FB_B_DQM_L<0>
U9000
A2
A3
D3
FB_B_WDQS<1>
FB_B_WDQS<2>
FB_B_WDQS<3>
FB_B_WDQS<0>
5%
1/16W
MF-LF
402
2
A1
A4
A5
BA1
H3
BA2
J2
RFU1
J3
RFU2
R9091
1K
A0
V9
FB_B_RDQS<1>
FB_B_RDQS<2>
FB_B_RDQS<3>
FB_B_RDQS<0>
M2 70D3
M3 70D3
T2 70D3
FB_B_DQ<15>
FB_B_DQ<12>
FB_B_DQ<14>
FB_B_DQ<13>
FB_B_DQ<8>
FB_B_DQ<9>
FB_B_DQ<11>
FB_B_DQ<10>
FB_B_DQ<18>
FB_B_DQ<17>
FB_B_DQ<19>
FB_B_DQ<16>
FB_B_DQ<20>
FB_B_DQ<22>
FB_B_DQ<23>
FB_B_DQ<21>
FB_B_DQ<29>
FB_B_DQ<30>
FB_B_DQ<28>
FB_B_DQ<31>
FB_B_DQ<27>
FB_B_DQ<24>
FB_B_DQ<26>
FB_B_DQ<25>
FB_B_DQ<1>
FB_B_DQ<6>
FB_B_DQ<0>
FB_B_DQ<5>
FB_B_DQ<3>
FB_B_DQ<7>
FB_B_DQ<2>
FB_B_DQ<4>
IO
IO
IO
IO
IO
IO
IO
73B8 70D1
IN
73B8 70D1
IN
73B8 70D1
IN
73B8 70D1
IN
73B8 70D1
IN
73B8 70D1
IN
73B8 70D1
IN
5.49K
1%
1/16W
MF-LF
402 2
K9
A4
FB_DRAM_RST
5%
1/16W
MF-LF
402
2
L12
VSS6
VSS7
B1
VDDQ14
VDDQ15
K10
M4
100
VSS5

(NONE)
L1
VSSQ0
N12
H11
K11
1%
1/16W
MF-LF
402 2
G12

- =PP1V8_S0_FB_VDD
- =PP1V8_S0_FB_VDDQ
G1
VDDQ0
N9
CRITICAL
OMIT
1%
1/16W
MF-LF
402
2
K2
243
C9076
VSS3
VSS4
A1
N4
K4
R9049
A10
VDDA1
P9
R9047
M9
R9048
C9075
A3
VSS1
VSS2
VDDA0
P4
FB_B_MA<0>
FB_B_MA<1>
FB_B_MA<2>
FB_B_MA<3>
FB_B_MA<4>
FB_B_MA<5>
FB_B_MA<6>
FB_B_MA<7>
FB_B_MA<8>
FB_B_MA<9>
FB_B_MA<10>
FB_B_MA<11>
0.1uF
2
1
C9081
L2
P4
P12
T9
C9083
0.1uF
0.1uF
10%
16V
X5R
402
10%
16V
X5R
402
R9094 1
1%
1/16W
MF-LF
402
C9074
FBGA
(2 OF 2)
VSS0
K1
P1
R9090 1
FB_B0_ZQ
FB_B0_MF
FB_B0_SEN
72A5 70A1
73A5 72A8 IN
0.1uF
10%
16V
X5R
402
K4J52324QC-BC20
73B5 70D1
0.1uF
16MX32-GDDR3-500MHZ
IN
10%
16V
X5R
402
121
1%
1/16W
MF-LF
402
2
C9073
0.1uF
1%
1/16W
MF-LF
402
60.4
U9000.J12
U9050
K12
C4
10%
16V
X5R
402
121
1%
1/16W
MF-LF
402
2
VDD6
VDD7
C1
0.1uF
1%
1/16W
MF-LF
402
121
10%
16V
X5R
402
10%
16V
X5R
402
121
R9045
VDD5
V2
VSSQ12
VSSQ13
R9046 1
0.1uF
2
0.1uF
1%
1/16W
MF-LF
402
R9043
M12
E12
C9070
L2
60.4
M1
VDD3
VDD4
=PP1V8_S0_FB_VDDQ
1%
1/16W
MF-LF
402
R9041
C9033
MFHIGH
IN
73B5 70D1
MFHIGH
IN
73B5 70D1
C9031
F1
F12
C9065
10%
16V
X5R
402
U9000.J1
121
C9060
0.1uF
1%
1/16W
MF-LF
402
VDD1
VDD2
VDDQ12
VDDQ13
MFHIGH
IN
73B5 70D1
R9044 1
121
5%
1/16W
MF-LF
402
2
73B5 70D1
1%
1/16W
MF-LF
402 2
R9042 1
1%
1/16W
MF-LF
402
1K
10%
16V
X5R
402
121
0.1uF
10%
16V
X5R
402
L9065
73D8 72D8 72D5 65B6
VDDQ9
VDDQ10
C9054
0.1uF
VOLTAGE=1.8V
0402
D12
J4
C9053
10%
16V
X5R
402
VDD0
5.49K
1%
1/16W
MF-LF
402 2
0.1uF
1
C9052
10%
16V
X5R
402
D1
E4
V12
FB_B0_VREF1
0.1uF
A2
A11
V11
B4
FB_B0_VREF0
J12
VSSQ1
VSSQ2
R4
VSSA1
VDDQ1
VDDQ2
N9
R9030
A12
N1
J1
B1
N4
FERR-220-OHM
VSSA0
C9051
L9060
VSSQ0
C9
C9026
V10
L1
VDDQ0
C12
C9023
V3
20%
6.3V
CERM
805
A1
E12
1
L12
VSS6
VSS7
22UF
VDDA1
=PP1V8_S0_FB_VDDQ
C9020
VSS5
C9050
K12
E1
72D5 65B6
73D5 72D8 IN
G12
G1
VDDA0
C4
VSS3
VSS4
K1
C1
U9000.J12
FBGA
(2 OF 2)
A10
1
Page Notes
C9002
10%
16V
X5R
402
A3
VSS1
VSS2
R9096 1
60.4
1%
1/16W
MF-LF
402
2
1
R9093
121
R9095
60.4
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
2
R9097
121
CRITICAL
OMIT
1%
1/16W
MF-LF
402
FB_B_MA<0>
FB_B_MA<1>
FB_B_MA<2>
FB_B_MA<3>
FB_B_MA<4>
FB_B_MA<5>
FB_B_MA<6>
FB_B_MA<7>
FB_B_MA<8>
FB_B_MA<9>
FB_B_MA<10>
FB_B_MA<11>
A0
U9050
DM0
E3
70C1
IN
A1
FBGA
DM1
E10
70C1
IN
K10
A2
A3
(1 OF 2)
DM2
DM3
N10
70C1
DQ0
B2 70B3
DQ1
DQ2
B3 70B3
DQ3
C3 70B3
DQ4
DQ5
E2 70B3
DQ6
F2 70B3
M9
H2
A4
A5
K3
A6
L4
A7
A8/AP
K4
K2
M4
A9
IO
IN
IO
70B1
IN
IO
70B1
IN
IO
70B1
IO
70B1
IO
70B1 IN
IO
70B1
IN
IN
IN
FB_B_CKE<1>
FB_B_CLK_P<1>
FB_B_CLK_N<1>
FB_B_CS_L<1>
FB_B_WE_L<1>
FB_B_CAS_L<1>
FB_B_RAS_L<1>
FB_B1_ZQ
FB_B1_MF
FB_B1_SEN
IO
IO
IO
IO
IO
IO
IO
IO
72A8 72A5 70A1

73A8 IN
70C1
70C1
70C1
70C1
OUT
OUT
OUT
OUT
DQ7
G3 70B3
CKE
70B3
DQ8
B11
J11
70B3
DQ9
B10
J10
CK
CK*
70B3
DQ10
C11
F4
CS*
70B3
DQ11
C10
H4
70C3
DQ12
70C3
DQ13
E11
F9
WE*
CAS*
H10
RAS*
70C3
DQ14
F11
70C3
DQ15
70C3
DQ16
G10
A9
ZQ
MF
V4
SEN
70C3
DQ17
L10
RESET
70C3
DQ18
N11
70C3
DQ19
M10
70C3
DQ20
70C3
DQ21
R11
70C3
DQ22
T11
T10
D3
D10
P10
P3
RDQS0
RDQS1
RDQS2
RDQS3
70C1
IO
70C1
IO
70C1
IN
IO
70C1
IN
73A8 70D1
IN
IO
IO
IO
73A8 70D1
73A8 70D1
IN
IN
IN
IN
FB_B_WDQS<6>
FB_B_WDQS<5>
FB_B_WDQS<4>
FB_B_WDQS<7>
FB_B_BA<0>
FB_B_BA<1>
FB_B_BA<2>
R9098
R9099
243
100
1%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402
2
NC
NC
R10
WDQS0
D11
WDQS1
DQ25
L3 70B3
P11
DQ26
DQ27
N2 70B3
P2
WDQS2
WDQS3
R2 70B3
BA0
DQ28
G9
DQ29
DQ30
R3 70B3
DQ31
T3 70B3
BA1
H3
BA2
J2
RFU1
J3
RFU2
IO
1
M11
D2
G4
F10
70C3
DQ23
DQ24
IO
IO
F3 70B3
H9
V9
FB_B_RDQS<6>
FB_B_RDQS<5>
FB_B_RDQS<4>
FB_B_RDQS<7>
C2 70B3
L9
A4
FB_DRAM_RST
N3
A10
A11
K11
IO
70B1
FB_B_DQM_L<6>
FB_B_DQM_L<5>
FB_B_DQM_L<4>
70C1 FB_B_DQM_L<7>
K9
H11
K4J52324QC-BC20
0.1uF
VSS0
MFHIGH
C9001
U9000
16MX32-GDDR3-500MHZ
20%
6.3V
CERM
805
VDD1
VDD2
CRITICAL
OMIT
=PP1V8_S0_FB_VDD
MFHIGH
22UF
VDD0
K4J52324QC-BC20
C9000
A2
A11
IN
K4J52324QC-BC20
73D8 72D8 72D5 65B6
16MX32-GDDR3-500MHZ
CRITICAL
OMIT
=PP1V8_S0_FB_VDD
16MX32-GDDR3-500MHZ
72D5 65B6
73D5 72D8 IN
MFHIGH
M2 70B3
M3 70B3
T2 70B3
FB_B_DQ<54>
FB_B_DQ<53>
FB_B_DQ<52>
FB_B_DQ<55>
FB_B_DQ<50>
FB_B_DQ<48>
FB_B_DQ<49>
FB_B_DQ<51>
FB_B_DQ<44>
FB_B_DQ<47>
FB_B_DQ<45>
FB_B_DQ<46>
FB_B_DQ<43>
FB_B_DQ<41>
FB_B_DQ<42>
FB_B_DQ<40>
FB_B_DQ<37>
FB_B_DQ<32>
FB_B_DQ<39>
FB_B_DQ<34>
FB_B_DQ<36>
FB_B_DQ<35>
FB_B_DQ<38>
FB_B_DQ<33>
FB_B_DQ<63>
FB_B_DQ<61>
FB_B_DQ<62>
FB_B_DQ<60>
FB_B_DQ<56>
FB_B_DQ<59>
FB_B_DQ<58>
FB_B_DQ<57>
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GDDR3 Frame Buffer B
IO
IO
IO
IO
SYNC_DATE=(MASTER)
IO

IO
IO

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
73
84

- =PP3V3_GPU_GPIOS
- =PP2V5_PVDD
- =PP1V8_GPU_LVDS_PLL
68C4 65A3

- =I2C_GPU_TMDS_SDA - I2C data line for
external TMDS transmitters
- =I2C_GPU_TMDS_SCL - I2C clock line for
external TMDS transmitters
=PP3V3_S0_GPU
OMIT
U8400
BGA
(6 OF 7)

(NONE)
71B8
71B8
71B8
71B8
71B8
71B8
71B8
71B8
71B8
71B8
71B8
71B8
71B8
71B8
71B8
71B8
71B8
65A3
GPU_GPIO_18
GPU_GPIO_19
GPU_GPIO_20
GPU_GPIO_21
GPU_GPIO_22
GPU_GPIO_23
GPU_GPIO_24
GPU_GPIO_25
GPU_GPIO_26
GPU_GPIO_27
GPU_GPIO_28
GPU_GPIO_29
GPU_GPIO_30
GPU_GPIO_31
GPU_GPIO_32
GPU_GPIO_33
GPU_GPIO_34
AE13
AF13
AF9
AG7
AE10
AE9
AF7
AF8
AH6
AF10
AG10
AH9
AJ8
AH8
AG9
AH7
AG8
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
=PP3V3_S0_GPU_VDDR3
Typically <50mA
AA9
AB9
C9100
22UF
20%
6.3V
CERM
805
C9101
1uF
2
C9102
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C9103
AB10
1uF
AC19
10%
6.3V
CERM
402
AC20
R9190
499
M56P
GENERAL PURPOSE I/O
VREFG
AC8
ATI_VREFG
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7_BLON
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
AD4
GPU_GPIO_0
GPU_GPIO_1
GPU_GPIO_2
GPU_GPIO_3
GPU_GPIO_4
GPU_GPIO_5
GPU_GPIO_6
GPU_GPIO_7
GPU_GPIO_8
GPU_GPIO_9
GPU_GPIO_10
GPU_GPIO_11
GPU_GPIO_12
GPU_GPIO_13
GPU_GPIO_14
GPU_GPIO_15
GPU_GPIO_16
GPU_GPIO_17
AD2
AD1
AD3
AC1
AC2
AC3
AB2
AC6
AC5
AC4
AB3
AB4
AB5
AD5
AB8
AA8
AB7
GENERICA
GENERICB
GENERICC
GENERICD
AK22
PANEL
DIGON
CONTROL VARY_BL
AE11
VDDR3
(3.3V)
AD18
AD19
GPU_GENERICA
GPU_GENERICB
GPU_GENERICC
GPU_GENERICD
AF23
AE23
AD23
71D8
C9191
71C8
0.1uF
71C8
71C8
10%
16V
X5R
402
1%
1/16W
MF-LF
402
D
R9191
499
2
2
1%
1/16W
MF-LF
402
71C8
71C8
71C8
71C8
71C8
71C8
71C8
71C8
8
Page Notes
71C8
71C8
71C8
71C8
71C8
71C8
71C1
71C1
71C1
68A7
AD20
65A6
=PP2V5_S0_GPU_VDD25
70mA total for VDD25
K22
GPU_DIGON
GPU_VARY_BL
AD12
79A4 79B6
79A4
L10
C9110
22UF
1uF
20%
6.3V
CERM
805
22UF
65A3
VOLTAGE=3.3V
C9120
22UF
L9125
AC18
NC0
AB6
NC
NC_DVOVMODE_0
NC_DVOVMODE_1
AK4
NC
NC
DVPCLK
AG1
ATI_DVPCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
AF2
ATI_DVPCNTL<0>
ATI_DVPCNTL<1>
ATI_DVPCNTL<2>
10%
6.3V
CERM
402
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
AG2
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
AE6
C9117
1uF
10%
6.3V
CERM
402
C9121
10%
6.3V
CERM
402
C9122
0.1uF
AJ5
10%
16V
X5R
402
AK5
AL5
PP1V8R3V3_S0_GPU_VDDR5_F
VDDR4
(1.8V/3.3V)
VOLTAGE=3.3V
AE2
AE3
C9125
22UF
20%
6.3V
CERM
805
L9130
C9126
1uF
10%
6.3V
CERM
402
C9127
AE4
0.1uF
AE5
10%
16V
X5R
402
VDDR5
(1.8V/3.3V)
200-OHM-EMI
1
PP1V2_S0_GPU_VDDPLL
VOLTAGE=1.2V
0402
20mA
C9130
22UF
20%
6.3V
CERM
805
C9131
AC15
1uF
2
10%
6.3V
CERM
402
C9132
(PP2V5_S0_GPU_PVDD_F)
(GND_GPU_PVSS)
1uF
2
10%
6.3V
CERM
402
AJ14
AH14
(PP1V0R1V2_S0_GPU_MPVDD)
(GND_GPU_MPVSS)
L9135
A6
A5
VDDPLL (1.2V)
PVDD
PVSS
MPVDD
MPVSS
(2.5V)
(2.5V)
FERR-220-OHM
=PP2V5_S0_GPU_PVDD
PP2V5_S0_GPU_PVDD_F
VOLTAGE=2.5V
0402
71C1
100mA
71C1
C9135
22UF
20%
6.3V
CERM
805
C9136
1uF
2
10%
6.3V
CERM
402
GPU_XTALIN
GPU_XTALOUT
C9137
NC
0.1uF
2
10%
16V
X5R
402
XTALIN
XTALOUT
AG14
PLLTEST
XW9135
1
AL4
AF1
AF3
ATI_DVPDATA<0>
ATI_DVPDATA<1>
ATI_DVPDATA<2>
ATI_DVPDATA<3>
ATI_DVPDATA<4>
ATI_DVPDATA<5>
ATI_DVPDATA<6>
ATI_DVPDATA<7>
ATI_DVPDATA<8>
ATI_DVPDATA<9>
ATI_DVPDATA<10>
ATI_DVPDATA<11>
AG3
AH2
AH3
AJ2
AJ1
AK2
AK1
AK3
AL2
AL3
AM3
ATI_DVPDATA<12>
ATI_DVPDATA<13>
ATI_DVPDATA<14>
ATI_DVPDATA<15>
ATI_DVPDATA<16>
ATI_DVPDATA<17>
ATI_DVPDATA<18>
ATI_DVPDATA<19>
ATI_DVPDATA<20>
ATI_DVPDATA<21>
ATI_DVPDATA<22>
ATI_DVPDATA<23>
AF4
AF5
AG4
AJ3
AH4
AJ4
AG5
AH5
AF6
AE7
AG6
THERMAL
DIODE
DPLUS
DMINUS
AG12
AH12
ATI_TDIODE_P
ATI_TDIODE_N
ROM
ROMCS*
AC7
TP_ATI_ROMCS_L
TEST
TESTEN
AG22
ATI_TESTEN
1
SM
GND_GPU_PVSS
FERR-220-OHM
2
1
2
0402
PPVCORE_S0_GPU_MPVDD
VOLTAGE=1.2V
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
71B1
52B6
52B6
71C1
R9195
1K
VOLTAGE=0V
L9140
=PPVCORE_S0_GPU
AM26
AL26
PLL & XTAL
=PP1V2_S0_GPU_VDDPLL
69D8 65A6 53C7 53A5
VDD25
(2.5V)
AC16
AM5
0402
65A6
AC13
10%
16V
X5R
402
Typically <50mA
FERR-220-OHM
1
65C6
1uF
20%
6.3V
CERM
805
AA10
0.1uF
PP1V8R3V3_S0_GPU_VDDR4_F
2
0402
65A3
C9112
Typically <50mA
FERR-220-OHM
1
C9116
1uF
20%
6.3V
CERM
805
L9120
=PP2V5_S0_GPU_VDDC_CT
C9115
10%
6.3V
CERM
402
VIP HOST / EXTERNAL TMDS
65A6
C9111
5%
1/16W
MF-LF
402
ATI M56 GPIO/DVO/Misc
20mA
C9140
22UF
20%
6.3V
CERM
805
C9141
1uF
2
10%
6.3V
CERM
402
C9142
SYNC_DATE=(MASTER)
0.1uF
10%
16V
X5R
402
XW9140

SM
GND_GPU_MPVSS
VOLTAGE=0V

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
74
84
Page Notes
- =PP2V5_S0_GPU
- =PP1V8R2V5_S0_GPU_LVDDR
(NONE)
(NONE)
L9300
FERR-220-OHM
2
PP2V5_S0_GPU_TPVDD
OMIT
20mA peak
VOLTAGE=2.5V
0402
U8400
C9300
L9305
C9301
1uF
1uF
20%
6.3V
CERM
805
10%
6.3V
CERM
402
10%
6.3V
CERM
402
M56P
C9302
22UF
BGA
(5 OF 7)
AM8
AL8
FERR-220-OHM
1
PP2V5_S0_GPU_TXVDDR
150mA peak
VOLTAGE=2.5V
0402
AK6
C9305
20%
6.3V
CERM
805
L9310
C9306
1uF
2
10%
6.3V
CERM
402
C9307
AL6
0.1uF
AM6
10%
16V
X5R
402
AK7
AK8
PP2V5_S0_GPU_AVDD
65mA peak
VOLTAGE=2.5V
0402
C9310
C9311
1uF
10%
6.3V
CERM
402
C9312
0.1uF
AL25
10%
16V
X5R
402
AM25
L9315
20mA peak
C9316
C9317
22UF
1uF
0.1uF
20%
6.3V
CERM
805
10%
6.3V
CERM
402
10%
16V
X5R
402
AK23
AVSSQ
0402
AK25
AVSS
L9320
AL23
VDD1DI (2.5V)
VSS1DI
AL22
RSET
AM23
130mA peak
75A8
ATI_RSET
C9320
PP2V5_S0_GPU_A2VDD
VOLTAGE=2.5V
C9322
AL16
22UF
1uF
0.1uF
20%
6.3V
CERM
805
10%
6.3V
CERM
402
10%
16V
X5R
402
AM16
C9321
A2VDD
(2.5V)
AL17
L9325
AM17
A2VSS
FERR-220-OHM
NC
VOLTAGE=2.5V
AK13
0402
20mA peak
C9325
20%
6.3V
CERM
805
C9326
1uF
22UF
2
10%
6.3V
CERM
402
C9327
75A8
ATI_R2SET
NC_A2VDDQ
A2VSSQ
AJ17
VDD2DI (2.5V)
VSS2DI
AK14
R2SET
AE19
LPVDD (2.5V)
LPVSS
AJ16
L9330
0.1uF
2
AL14
PP2V5_S0_GPU_LPVDD
20mA peak
VOLTAGE=2.5V
0402
AE18
C9330
20%
6.3V
CERM
805
C9331
1uF
22UF
10%
6.3V
CERM
402
C9332
1uF
AC21
10%
6.3V
CERM
402
AC22
AD21
L9345
AD22
FERR-220-OHM
1
0402
AE20
PP2V5_S0_GPU_LVDDR
VOLTAGE=2.5V
200mA peak
AE21
LVDDR
(2.5V)
AE22
C9340
22UF
20%
6.3V
CERM
805
C9345
20%
6.3V
CERM
805
1uF
22UF
2
C9341
10%
6.3V
CERM
402
C9342
0.1uF
2
10%
16V
X5R
402
C9346
0.1uF
2
10%
16V
X5R
402
C9347
AF19
0.1uF
AF20
10%
16V
X5R
402
AF17
AF18
AG17
AG19
LVSSR
AH17
AH19
AJ19
R9350
75B5
R9351
499
715
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
75B5
77A1
IN
GPU_HPD
AF11
HPD1
MONITOR
IDENTIFICATION
AK17
AM11
AL11
AM12
AL12
AJ9
84A4
77B8
76C7
AK9
AJ11
AK11
AJ12
AK12
R
G
B
HSYNC
VSYNC
AJ23 71C1
AM24 71C1
AL24 71C1
AJ22 71C1
77C3
R2
G2
B2
AK15 76D7
H2SYNC
V2SYNC
AF15 77C5
TMDS_CLK_P
TMDS_CLK_N
OUT
OUT
TMDS_DATA_P<0>
TMDS_DATA_N<0>
TMDS_DATA_P<1>
TMDS_DATA_N<1>
TMDS_DATA_P<2>
TMDS_DATA_N<2>
OUT
OUT
OUT
OUT
OUT
OUT
TMDS_DATA_P<3>
TMDS_DATA_N<3>
TMDS_DATA_P<4>
TMDS_DATA_N<4>
TMDS_DATA_P<5>
TMDS_DATA_N<5>
OUT
OUT
OUT
OUT
OUT
OUT
GPU_VGA_R
GPU_VGA_G
GPU_VGA_B
OUT
OUT
OUT
GPU_VGA_HSYNC
GPU_VGA_VSYNC
77C3
AM15 76D7
77C3
AL15 76D7
OUT
OUT
AG15 77D5
GPU_R2
GPU_G2
GPU_B2
OUT
OUT
OUT
GPU_H2SYNC
GPU_V2SYNC
OUT
OUT
Y
C
AJ15 71C1
AJ13 71B1
GPU_TV_Y
GPU_TV_C
COMP
AH15 71B1
GPU_TV_COMP
TXCLK_UP
TXCLK_UN
AJ21 76D7
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
AG18 76D7
TXCLK_LP
TXCLK_LN
AM18 76D7
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
AF22
ATI_RSET
ATI_R2SET
AK10
AK24 71C1
AF21
84A4
77D8
AL10 76C7
OUT
Composite/S-Video
VGA
Component
OUT
Y
C
G
R
Y
Pr
OUT
Comp
Pb
FERR-220-OHM
10%
16V
X5R
402
LVDS
84B4
77B8
76C7
AL9
FERR-220-OHM
0402
PP2V5_S0_GPU_VDD2DI
DAC (CRT)
C9315
AVDD
(2.5V)
AM9
AJ24
FERR-220-OHM
VOLTAGE=2.5V
TX0P
TX0M
TX1P
TX1M
TX2P
TX2M
TX3P
TX3M
TX4P
TX4M
TX5P
TX5M
AM7
20%
6.3V
CERM
805
TXVSSR
TXCP
TXCM
AL7
22UF
PP2V5_S0_GPU_VDD1DI
TXVDDR
(2.5V)
AJ7
FERR-220-OHM
1
TPVDD (2.5V)
TPVSS
AJ6
22UF
INTEGRATED TMDS
=PP2V5_S0_GPU
DAC2 (TV/CRT2)
65A6
Sum of peak currents on this page: 605mA
DDC1CLK
77B1
DDC1DATA
77B1
79C3
79C3
AK21 76D7
79C3
79C3
AH18 76D7
79C3
AK20 76D7
79C3
AJ20 76D7
79B3
AG20 76D7
79C3
AH20 76D7
AH21 71B1
AG21 71B1
79C3
79C3
AL18 76D7
79C3
AL19 76D7
79C3
AK19 76D7
79C3
AM20 76D7
79C3
AL20 76D7
79C3
AM21 76D7
79C3
AL21 76D7
AJ18 71B1
AK18 71B1
AH23
AH22
71A2
DDC2CLK
71A2
DDC2DATA
AG13
79A7
DDC3CLK
79A7
DDC3DATA
AF12
AH13
AE12
LVDS_U_CLK_P
LVDS_U_CLK_N
OUT
OUT
LVDS_U_DATA_P<0>
LVDS_U_DATA_N<0>
LVDS_U_DATA_P<1>
LVDS_U_DATA_N<1>
LVDS_U_DATA_P<2>
LVDS_U_DATA_N<2>
LVDS_U_DATA_P<3>
LVDS_U_DATA_N<3>
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
LVDS_L_CLK_P
LVDS_L_CLK_N
OUT
OUT
LVDS_L_DATA_P<0>
LVDS_L_DATA_N<0>
LVDS_L_DATA_P<1>
LVDS_L_DATA_N<1>
LVDS_L_DATA_P<2>
LVDS_L_DATA_N<2>
LVDS_L_DATA_P<3>
LVDS_L_DATA_N<3>
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
GPU_DDC_A_CLK
GPU_DDC_A_DATA
ATI M56 Video Interfaces
IO
IO
GPU_DDC_B_CLK
GPU_DDC_B_DATA
IO
GPU_DDC_C_CLK
GPU_DDC_C_DATA
IO
SYNC_DATE=(MASTER)
IO

IO

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
75
84
SPACING
VGA
VGA
VGA
VGA
VGA
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LCD (LVDS) INTERFACE
PHYSICAL
VGA
NET_TYPE
GPU_R2
GPU_G2
GPU_B2
75B3 77C3
65C3
=PP3V3_S0_LCD
75B3 77C3
75B3 77C3
C9400
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
0.0022uF
R9400 1
75B3 79C3
5%
1/16W
MF-LF
402
75B3 79C3
10%
50V
CERM
402
LCD_PWREN_L_RC
R9401
100K
75A3 79C3
5%
1/16W
MF-LF
402
75A3 79C3
75A3 79C3
79B6
PP3V3_LCD_SW
VOLTAGE=3.3V
LCD_PWREN_L
C9401
20%
50V
CERM
402
Q9400
Q9401
6B1 76C2 79C1 79D1
0.001uF
TSOP-LF D
SI3443DV
6B1 76B2 76C2 79C1 79D1
SM
6B1 76B2 79C1
6A6
=GND_CHASSIS_LCD2
6A6
=GND_CHASSIS_LCD1
CRITICAL
2N7002
6B1 76C2 79C1
79A2
LVDS_PANEL_EN
SOT23-LF
C9420
6B1 76C2 79C1
65B3
20%
50V
CERM
402
100K
6A1 76C2 79C1
5%
1/16W
MF-LF
402
75C3 77B8 84B4

75C3 77C8 84B4
100K pull-ups are for

no-panel case (development).
Panel has 2K pull-ups
75C3 77A8 77B8 84A4

75C3 77A8 77B8 84A4
J9400
MSC-RB30-5-FA
0.001uF
=PP3V3_S0_DDC_LCD
R9494 1
6A1 6B1 76C2 79C1
TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA_P<5..3>
TMDS_DATA_N<5..3>
TMDS_DATA_P<2..0>
TMDS_DATA_N<2..0>
6B1 76B2 79C1
LVDS_L_CLK_CONN_P
LVDS_L_CLK_CONN_N
LVDS_L_DATA_CONN_P<2..0>
LVDS_L_DATA_CONN_N<2..0>
L9400
FERR-250-OHM
S
G
75A3 79C3
LVDS_U_CLK_CONN_P
LVDS_U_CLK_CONN_N
LVDS_U_DATA_CONN_P<2..0>
LVDS_U_DATA_CONN_N<2..0>
100K
75B3 79B3 79C3
LVDS_L_CLK_P
LVDS_L_CLK_N
LVDS_L_DATA_P<2..0>
LVDS_L_DATA_N<2..0>
LVDS
LVDS
75B3 79C3
F-RT-SM
34
2
1
R94101
100K
5%
1/16W
MF-LF
402 2
R9411
100K
5%
1/16W
MF-LF
2 402
PP3V3_LCD_CONN
VOLTAGE=3.3V
3
4
5
NC
79A5 LVDS_CONN_DDC_CLK
79A5 LVDS_CONN_DDC_DATA
75C3 77C8 77D8 84A4

75C3 77C8 77D8 84A4
7
8
6B1 LVDS_L_DATA_CONN_P<0>
79C1 76D7 6A1
C9410
79C1 76D7
0.001uF
20%
50V
CERM
402
6A6
LVDS_U_CLK_P
LVDS_U_CLK_N
LVDS_U_DATA_P<2..0>
LVDS_U_DATA_N<2..0>
=GND_CHASSIS_LCD3
10
79C1 76D7 6A1

79C1 76D7 6A1
11
12
13
14
6A1 LVDS_L_DATA_CONN_P<2>
79C1 76D7 6A1

79C1 76D7
15
16
17
LVDS_L_CLK_CONN_N
6B1 LVDS_L_CLK_CONN_P
79C1 76D7 6B1

79C1 76D7
18
19
79D1 76D7 6B1

79D1 76D7 6B1
20
21
22
79C1 76D7 6B1

79C1 76D7 6B1
23
24
25
26
6B1 LVDS_U_DATA_CONN_P<2>
79D1 76D7 6B1

79C1 76D7
27
28
29
LVDS_U_CLK_CONN_N
6B1 LVDS_U_CLK_CONN_P
79C1 76D7 6B1
INVERTER INTERFACE
79C1 76D7
0.001uF
2
FERR-220-OHM-2A
=PPBUS_S0_INVERTER
5A4
Q9450
=PP5V_S0_INVERTER
FDG6332C_NL
R9450 1
SC70-6
L9452
P-CHN
400-OHM-EMI
D
5%
1/16W
MF-LF
402
VOLTAGE=5V
G
2
C9450
2
2
J9450
SM04B-ACH
20%
6.3V
X5R
603
NC
N-CHN
Q9450
1
FDG6332C_NL
SC70-6
C9452
NC
0.001uF
L9454
2
400-OHM-EMI
100K
5%
1/16W
MF-LF
402
PP5V_INVERTER_SW
VOLTAGE=5V
R9489
2
5A4
M-RT-SM
5
INVERTER_BKLTON
=GND_CHASSIS_LCD4
CRITICAL
10UF
FP_PWR_EN_L
79A2
6A6
20%
50V
CERM
402
SM-1
C9451
518S0289
0.001uF
PP5V_INVERTER_SW_F
100K
1
20%
50V
CERM
402
PPBUS_S0_INVERTER
VOLTAGE=12.8V
0603
65A1
33
C9421
CRITICAL
L9450
65C1
30
20%
50V
CERM
402
5A4
SM-1
518S0369
INVERTER_PWM
GND_INVERTER
5A4
C9454
CRITICAL
0.001uF
20%
50V
CERM
402
65B3
=PP3V3_S0_INVERTER
6A6
5
6C4
=INVERTER_PWM_PLT_RST_L
INVERTER_PWM_UNBUF
FERR-220-OHM-2A
0603
=GND_CHASSIS_INVERTER
MC74VHC1G08
SC70
U9453
79A2
L9455
INVERTER_PWM_F
INVERTER EXPECTS ACTIVE HIGH PWM SIGNAL
Internal Display Connectors
SYNC_MASTER=M59_MG
C9453
20%
10V
CERM
402
0.1uF


SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
76
84
NET_TYPE
TMDS Filtering
VGA SYNC BUFFERS
Place termination components close to GPU, common mode chokes near connector.
77D5 65A3
84A4 76C7 75C3
=PP3V3_D3C_VGASYNC
TMDS_DATA_N<0>
CRITICAL
TMDS_DATA_RL<0> R9762 1
VOLTAGE=0V
1%
1/16W
MF-LF
402
L9743
L9700
182
NO_TEST=TRUE
SC70
90-OHM-100MA
1210-4SM1
U9750
SYM_VER-1
TMDS_DATA_F_N<0>
75B3
GPU_V2SYNC
TMDS_DATA_F_P<0>
PHYSICAL
TMDS
TMDS
TMDS
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDS_CLK_R_P
TMDS_CLK_R_N
77B7
77C7
TMDS_CLK_F_P
TMDS_CLK_F_N
77B5 77B6 84A4

77A5 77C6 84A4
TMDS_DATA_F_P<5..0>
TMDS_DATA_F_N<5..0>
77A6 77B3 77B5 77B6 77C6 77D6 84A4

77A6 77B3 77B5 77B6 77C6 77D6 84A4
77A3
5%
1/16W
MF-LF
402
0.1uF
77B5 77D1 84A4
20%
10V
CERM
402
TMDS_DATA_N<1>
VGA_VSYNC
C9750
2
84A4 76C7 75C3
0402
TMDS_DATA_P<0>
33
VGA_VSYNC_R
77B5 77D1 84A4
47nH
84A4 76C7 75C3
R9750
MC74VHC1G08
SPACING
TMDS
ANALOG FILTERING
VOLTAGE=0V
1
NO_TEST=TRUE
R9766 1
L9701
182
1%
1/16W
MF-LF
402
L9744
PLACE CLOSE TO CONNECTOR
PLACE U9750 & U9751 CLOSE TO DVI CONNECTOR
90-OHM-100MA
1210-4SM1
77D5 65A3
SYM_VER-1
TMDS_DATA_F_N<1>
CRITICAL
=PP3V3_D3C_VGASYNC
SM-220MHZ-LF
47nH
76D7 75B3
0402
5
TMDS_DATA_F_P<1>
77B3 77D1 84A4
U9751
75B3
VGA_HSYNC
R9740
77A5
1%
1/16W
MF-LF
402
TMDS_DATA_RL<2>
VOLTAGE=0V
NO_TEST=TRUE
L9702
R9770 1
L9745
TMDS_DATA_F_N<2>
TMDS_DATA_F_P<2>
R9741
77B3 77D1 84A4
76D7 75B3
77B3 77D1 84A4
77D1
370-OHM
SM
SM-220MHZ-LF
TMDS_CLK_F_N
77A5 77D1 84A4
TMDS_CLK_F_P
77B5 77D1 84A4
65B1
=PP5V_S0_DVI_DDC
1
77D1
C
1
TMDS_CLK_R_P
PP5V_S0_DDC_F
VOLTAGE=5V
VOLTAGE=5V
3V LEVEL SHIFTERS
D9710
33
6A6
TMDS_DATA_N<3>
R9778
L9746
84A4 77D6 77D1
CRITICAL
SOD-123
1
2
PP5V_S0_DDC_PULLUPS
R9710 1
31
84A4 77D6 77D1
90-OHM-100MA
1210-4SM1
17
TMDS_DATA_F_N<0>
TMDS_DATA_F_N<2>
TMDS_DATA_F_N<1>
TMDS_DATA_F_P<2>
TMDS_DATA_F_P<1>
18
TMDS_DATA_F_P<0>
2
10
SYM_VER-1
19
TMDS_DATA_F_N<3>
77C6 77D1 84A4
TMDS_DATA_F_P<3>
TMDS_DATA_F_N<5>
20
TMDS_DATA_F_P<5>
21
TMDS_DATA_F_N<4>
TMDS_DATA_F_N<3>
TMDS_DATA_F_P<4>
TMDS_DATA_F_P<3>
DVI_DDC_CLK_R
12
77B3 77D1 84A4

84A4 77D1 77A6
5
13
TMDS_DATA_N<4>
22
6
14
84A4 77D1 77B6
TMDS_DATA_RL<4>
VOLTAGE=0V
NO_TEST=TRUE
L9747
23
TMDS_CLK_F_P
77A6 77D1
84A4
77B6 77D1
84A4
77A6 77D1
84A4
77B6 77D1
84A4
100
84A4 77D1 77C6
R9782 1
24
TMDS_CLK_F_N
16
VGA_VSYNC
DVI_HPD_R
C1
VGA_R
100
77C1
CRITICAL
2
C3
VGA_B
C5B
L9704
77C3
90-OHM-100MA
1210-4SM1
0402
C9713
100
SOT-363
R9714
1
TMDS_DATA_P<4>
TMDS_DATA_F_N<4>
VGA_HSYNC
C2
34
77B3 77D1 84A4
2N7002DW-X-F
DVI_HPD
S 4
1 S
R9722
5%
1/16W
MF-LF
402
GPU_HPD
VGA_G
GPU_HPD_BILAT
TMDS_DATA_F_P<4>
77B3 77D1 84A4
6B6
=GND_CHASSIS_DVI2
77C1
C9710
32
514-0278
R9730
20%
50V
CERM
603
=GND_CHASSIS_DVI4
=GND_CHASSIS_DVI3
=GND_CHASSIS_DVI5
6A6
6A6
S 1
SB_DVI_HPD
MAKE_BASE=TRUE
SYNC_MASTER=M59_MG

SYM_VER-1
TMDS_DATA_F_N<5>
77B5 77D1 84A4
TMDS_DATA_F_P<5>
77B5 77D1 84A4
SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
SHT
NONE
REV.
051-7150
SCALE
22A6
6B6
CRITICAL
TMDS_DATA_P<5>
SB_GPIO4
External Display Connector

2
90-OHM-100MA
1210-4SM1
0402
5%
1/16W
MF-LF
402
20K
5%
1/16W
MF-LF
402
L9705
47nH
R9715 1
PLACE NEAR 3, 11 & 19
L9748
SOT-363
6
65A1
R9723
2N7002DW-X-F
5%
50V
CERM
402
75A5
270K
Q9715
C9714
100pF
1
5%
1/16W
MF-LF
402
182
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
0
2
R9786
0
2
R9731
=PP5V_S0_SB_HPD
1
0.01uF
TMDS_DATA_N<5>
75A3
270K
Q9714
SOT-363
5%
1/16W
MF-LF
402
C5A
C4
PLACE NEAR C5A & C5B
84A4 76C7 75C3
GPU_DDC_A_DATA
2N7002DW-X-F
77C1
NO_TEST=TRUE
S 1
Q9714
5%
50V
CERM
402
=GPU_HPD_ENABLE
SYM_VER-1
VOLTAGE=0V
5%
1/16W
MF-LF
2 402
DVI_DDC_DATA
26A1
R9721
182
1%
1/16W
MF-LF
402
47nH
TMDS_DATA_RL<5>
SOT-363
5%
1/16W
MF-LF
402
75A3
10K
2N7002DW-X-F
100pF
77D3
GPU_DDC_A_CLK
1
R9713
5%
1/16W
MF-LF
402
S 4
Q9711
5%
50V
CERM
402
DVI_DDC_CLK
5%
1/16W
MF-LF
402
C9711
(PP5V_S0_DDC)
DVI_DDC_DATA_R
10K
G
SOT-363
R9711
15
R9720
2N7002DW-X-F
1
77C6 77D1
84A4
77C6 77D1
84A4
Q9711
77C6 77D1 84A4
11
84A4 77D1 77A6
84A4 76C7 75C3
5%
1/16W
MF-LF
2 402
100pF
0402
TMDS_DATA_P<3>
R9712
77B3 77D1 84A4
=PP3V3_D3C_DDC_DVI
4.7K
5%
1/16W
MF-LF
402 2
47nH
84A4 76C7 75C3
4.7K
=GND_CHASSIS_DVI1
65A3
VOLTAGE=5V
B0530WXF
L9703
182
1%
1/16W
MF-LF
402
0.25%
50V
CERM
402
Isolation required for DVI power switch
J9700
VOLTAGE=0V
3.3pF
PP5V_S0_DDC
SM-1
F-RT-TH-DVI
NO_TEST=TRUE
C9742
L9710
2
QH11121-RIG02-4F
TMDS_DATA_RL<3>
77A3
400-OHM-EMI
0.5AMP-13.2V
R9773
0
TMDS_CLK_P
VGA_R
CRITICAL
F9710
1%
1/16W
MF-LF
402
CRITICAL
0.25%
50V
CERM
402
(55mA requirement per DVI spec)
SM-LF
84A4 76C7 75C3
DVI DDC CURRENT LIMIT
SYM_VER-1
5%
1/16W
MF-LF
402
84A4 76C7 75C3
C9741
L9706
TMDS_CLK_R_N
5%
1/16W
MF-LF
402
R9774
77A3
3.3pF
FL9742
LCFILTER
1%
1/16W
MF-LF
402 2
DVI INTERFACE
182
CRITICAL
75
VGA_G
TMDS_DATA_P<2>
GPU_R2
R9742
R9772
84A4 76C7 75C3
0.25%
50V
CERM
402
(DAC2 C)
CRITICAL
84B4 76C7 75C3
SM-220MHZ-LF
C9740
3.3pF
FL9741
LCFILTER
1%
1/16W
MF-LF
402 2
TMDS_CLK_N
77A5
0402
84B4 76C7 75C3
CRITICAL
75
4
47nH
84A4 76C7 75C3
GPU_G2
SYM_VER-1
VGA_B
(DAC2 Y)
90-OHM-100MA
1210-4SM1
182
1%
1/16W
MF-LF
402
76D7 75B3
20%
10V
CERM
402
CRITICAL
75
5%
1/16W
MF-LF
402
0.1uF
TMDS_DATA_N<2>
VGA_HSYNC_R
C9751
84A4 76C7 75C3
33
GPU_H2SYNC
TMDS_DATA_P<1>
GPU_B2
(DAC2 Comp)
R9751
MC74VHC1G08
SC70
84A4 76C7 75C3
FL9740
LCFILTER
77B3 77D1 84A4
TMDS_DATA_RL<1>
CRITICAL
A.0.0
OF
77
84
Top-Case Connector
Left ALS Connector
65C3
65D3
CRITICAL
65B1
=PP3V3_S3_TOPCASE
=PP3V42_G3H_LIDSWITCH
=PP5V_S3_TOPCASE
CRITICAL
J6430
J4900
BM04B-ACH
M-RT-SM
5
QT500206-L020
=PP3V3_S3_LTALS
5B2 65C3
50B2 49B5
OUT
SMC_LID
1
2
49B5
6D5 5B2
55C7 5B2
55A4
ALS_GAIN
LTALS_OUT
IN
55A4
OUT
OUT
KBDLED_RETURN
KBDLED_ANODE
OUT
NC
6D3
IO
6D3
IO
=USB_TRACKPAD_P
=USB_TRACKPAD_N
CRITICAL
50C6
50B2
49C5 5B2
6C3
6C3
10
11
12
13
14
27C3
IO
15
16
27C3
IO
17
18
19
20
SMC_ONOFF_L
M-ST-SM
NC
OUT
=USB_BT_N
=USB_BT_P
IO
IO
=SMBUS_TOPCASE_SDA
=SMBUS_TOPCASE_SCL
27C6 =I2C_TRACKPAD_SCL
27C6 =I2C_TRACKPAD_SDA
IO
IO
D4900
518S0469
SC-75
1
white colored version of 518S0369
516S0412
3
2
RCLAMP0502B
SATA HDD & IR & SIL Flex Connector

65B1
65B1
=PP5V_S3_IR
=PP5V_S0_HDD
CRITICAL
CRITICAL
J4960
FL4960
QT500206-L020
M-ST-SM
0.0047uF
SYM_VER-1
C4965
0.0047uF
CRITICAL
FL4965
90-OHM-100MA
1210-4SM1
SYM_VER-1
21B6
OUT
SATA_C_D2R_P
SATA_C_D2R_UF_P
C4966
21B6
OUT
SATA_C_D2R_N
0.0047uF
SATA_C_D2R_UF_N
10%
25V
CERM
402
SATA_C_D2R_C_P
SATA_C_D2R_C_N
10
11
12
13
14
15
16
17
18
19
20
SATA_C_R2D_UF_N
SATA_C_R2D_N
SATA_C_R2D_P
2
=USB_IR_N
6C3 =USB_IR_P
6C3
50A7
SYS_LED_ANODE
2
10%
25V
CERM
402
SATA_C_R2D_UF_P
21B6
SATA_C_R2D_C_N
IN
21B6
SATA_C_R2D_C_P
IN
C4960
0.0047uF
1
IO
10%
25V
CERM
402
IO
10%
25V
CERM
402
C4961
90-OHM-100MA
1210-4SM1
IN
PLACEMENT_NOTE=Place C4960 close to southbridge

PLACEMENT_NOTE=Place C4961 next to C4960
PLACEMENT_NOTE=Place C4965 close to J4960

PLACEMENT_NOTE=Place C4966 next to C4965
516S0412
NOTE: _UF_ nets cross DDR2 signals and pick
up significant noise. Common-mode chokes
are to remove this noise from SATA signals.
M59 Specific Connectors
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
78
84

LVDS I/F Mux
13C5
65A6
65B6
LVDS_PD
5%
1/16W
SM-LF
RP9900
65D6
13C5
64B1
65A3
6A3
LVDS_PD
C9990
6A3
D3CPGOOD_ALL
1
R9994
1%
1/16W
MF-LF
402
RP9900
LVDS_PD
5%
1/16W
SM-LF
R9995
1%
1/16W
MF-LF
402
RP9901
D3CPGOOD_ALL
D3CPGOOD_ALL
1
R9993
C9995
100K
0.1UF
1%
1/16W
MF-LF
402
20%
2 10V
CERM
402
8.2K
CRITICAL
V1
D3CPGOOD_ALL
3
4
V2
V3
U9990
64A2
79A4
TSOT-23
RST* 6
V4
2
13C5
NB LVDS I/F
13C5
13C5
LTC2903
13C5
S0PGOOD_PWROK
MC74VHC1G08
13C5
S0D3CPGOOD_PWROK
79A4
13C5
D3CPGOOD_PWROK
D3CPGOOD_ALL
R9991
C9993
100K
0.1UF
1%
1/16W
MF-LF
402
20%
2 10V
CERM
402
GND
D3CPGOOD_ALL
1
D3CPGOOD_ALL
1
C9992
470K
0.1UF
2
D3CPGOOD_3V3
R9996
D3CPGOOD_ALL 2
20%
2 10V
CERM
402
LVDS_B_DATA_P<1>
LVDS_B_DATA_N<1>
A7 DA14
A5 DA15
B4 DA16
13C5
LVDS_B_CLK_N
LVDS_B_CLK_P
LVDS_B_DATA_P<2>
A2 DA17
B1 DA18
D1 DA19
13C5
10%
2 6.3V
CERM
402
13C5
LVDS_U_DATA_N<2>
LVDS_U_DATA_N<0>
LVDS_U_DATA_P<0>
G1 DB0*
J1 DB1*
76D7 75B3
76D7 75B3
LTC2903 guaranteed threshold is 93.5% (3.055V, 2.325V, 1.685V, 1.120V)
76D7 75B3
RP9901
8.2K
6B3
=LVDS_PD_L_CLK_P
76D7 75A3
76D7 75A3
LVDS_PD
5%
1/16W
SM-LF
RP9901
LVDS Mux Selection Qualification
8.2K
6B3
=LVDS_PD_L_CLK_N
6
5%
1/16W
SM-LF
LVDS_PD
8.2K
RP9902
1
LVDS_PD
79B3 79A4 65A3
=PP3V3_S0_LVDS_MUX
C9985
=PP2V5_S0_LVDS_MUX
C9980
76D7 75B3
LVDS_L_DATA_N<0>
LVDS_L_DATA_P<0>
LVDS_L_DATA_P<2>
LVDS_L_DATA_N<2>
LVDS_L_DATA_N<1>
LVDS_L_DATA_P<1>
LVDS_U_DATA_P<1>
LVDS_U_DATA_N<1>
76D7 75B3
20%
10V
CERM 2
402
76D7 75B3
LVDS_U_CLK_N
LVDS_U_CLK_P
LVDS_U_DATA_P<2>
C10 DA11
A10 DA12
A8 DA13
DH0 F2
DH1 H2
DH2 J2
DH3 J3
NC
LVDS_L_CLK_CONN_P
LVDS_L_CLK_CONN_N
DH4 J5
DH5 J6
DH6 J8
DH10 E9
DH11 C9
DH12 B9
K2 DB2*
J4 DB3*
K5 DB4*
K7 DB5*
DH13 B8
DH14 B6
NC
LVDS_U_CLK_CONN_N
LVDS_U_CLK_CONN_P
DH18 C2
DH19 E2
F10 DB9*
D10 DB10*
B10 DB11*
SEL E3
6B1 76C2 76D7

6B1 76C2 76D7
6B1 76C2 76D7
NC
DH15 B5
DH16 B3
DH17 B2
K8 DB6*
K10 DB7*
H10 DB8*
6B1 76C2 76D7
6B1 76C2 76D7
NC
DH7 J9
DH8 H9
DH9 F9
6A1 76C2 76D7

6B1 76C2 76D7
6A1 76C2 76D7
6A1 76C2 76D7
6A1 76C2 76D7
6A1 76C2 76D7
6B1 76C2 76D7

6B1 76C2 76D7
6B1 76B2 76D7
6B1 76B2 76D7

6B1 76B2 76D7
LVDS_MUX_SEL_GPU_L
A9 DB12*
B7 DB13*
A6 DB14*
NOTE: SEL = LOW selects port B
A4 DB15*
A3 DB16*
A1 DB17*
C1 DB18*
E1 DB19*
GND
H6
H5
LVDS_PD
76D7 75B3
0.1UF
20%
10V
CERM 2
402
5
5%
1/16W
SM-LF
79D3 65A6
0.1UF
8.2K
4
76D7 75A3
LVDS_L_CLK_P
LVDS_L_CLK_N
8
5%
1/16W
SM-LF
RP9902
76D7 75A3
76D7 75B3
8.2K
6B3
GPU LVDS I/F
LVDS_PD
5%
1/16W
SM-LF
6B3
76D7 75A3
Enables the GPU LVDS path in the mux with the qualification
that the GPU has turned on panel power and that the
panel power has risen to (near) 3.3V. This should
eliminate need for LVDS pulldowns
RP9902
6B3
SYM_VER-3
K9 DA7
J10 DA8
G10 DA9
E10 DA10
C9996
1UF
5%
1/16W
MF-LF
402
BGA-LF
LVDS_A_DATA_N<0>
LVDS_A_DATA_P<0>
LVDS_A_DATA_P<2>
LVDS_A_DATA_N<2>
LVDS_A_DATA_N<1>
LVDS_A_DATA_P<1>
SC70
8
5%
1/16W
SM-LF
LVDS_PD
5%
1/16W
MF-LF
2 402
U9950
CBTV4020
J7 DA6
13C5
13C5
D3CPGOOD_ALL
1
LVDS_PD
20%
10V
CERM
402
U9991
100K
K3 DA3
K4 DA4
K6 DA5
0.1uF
R9997
10K
1%
1/16W
MF-LF
402
D3CPGOOD_1V8_DIV
7
5%
1/16W
SM-LF
8.2K
6A3
D3CPGOOD_1V2_DIV
RP9901
C9991
D3CPGOOD_2V5_DIV
8.2K
6A3
365K
LVDS_PD
5%
1/16W
SM-LF
6A3
R9990
237K
1%
1/16W
MF-LF
402
20%
10V
CERM
402
D3CPGOOD_ALL
1
R9992
124K
8.2K
4
13D5
LVDS_A_CLK_P
LVDS_A_CLK_N
0.1uF
D3CPGOOD_ALL
1
7
5%
1/16W
SM-LF
RP9900
13C5
D3CPGOOD_ALL
1
8.2K
2
=PP3V3_S0_ALLSYSPG
20%
10V
CERM 2
402
8.2K
1
0.1UF
RP9902
C6
C5
VDD
F1 DA0
H1 DA1 CRITICAL
K1 DA2
D2
6B3
PP3V3_D3C
PP2V5_D3C
PP1V8_D3C
PP1V2_D3C
LVDS_B_DATA_N<2>
LVDS_B_DATA_N<0>
LVDS_B_DATA_P<0>
G2
D9
13C5
65A3
C9950
E8
D3CPGOOD_ALL BOM option stuffs LTC2903 circuit to monitor all D3C rails to qualify D3CPGOOD.
D3CPGOOD_3V3 BOM option uses only PP3V3_D3C to qualify D3CPGOOD.
F3
F8
PGOOD Monitor for GPU Rails
LVDS_PD
RP9900
=PP2V5_S0_LVDS_MUX
79C5 65A6
G9
NOTE: These parts are to counter an invalid state caused by the

M56 part. Bias voltage is present on LVDS interface pins even
when they should be tri-stated to meet panel power sequence
requirements. Resulting pump-up in LCD panel can cause startup
and long-term reliability issues. Pull-down resistors reduce
the pump-up in the panel, though some voltage will still be seen
on LVDS signals when they should be 0V.
8.2K
6B3
LVDS_PD
5%
1/16W
SM-LF
RP9903
79A4 74C3
79A4 79A3
SC70
4
76D3
PP3V3_LCD_SW
8.2K
6B3
=LVDS_PD_U_CLK_P
SC70-5
2
U9980
PANEL_PWR_ON
R9981
13.3K
Panel/Backlight Control Mux
LVDS_PD
5%
1/16W
SM-LF
RP9903
79C6 79A4 65A3
8.2K
6B3
10K
1%
1/16W
MF-LF
2 402
RP9903
5%
1/16W
MF-LF
402
5%
1/16W
SM-LF
LVDS_PD
SN74LVC1G132
R9980
RP9903
5
1
8.2K
6B3
CRITICAL
GPU_DIGON_AND_SELECTED
=LVDS_MUX_SEL_GPU
LVDS_PD
5%
1/16W
SM-LF
MC74VHC1G08
U9985
8.2K
6B3
GPU_DIGON
=LVDS_PD_U_CLK_N
=PP3V3_S0_LVDS_MUX
Divider set to rise to 1.88V nom/1.74V min when panel power is

at 3.3V/3.315V. Schmitt trigger voltage max is 1.70V (@2.625V Vcc).
R9981 can also be used as pad for cap, creating an RC filter.
6
5%
1/16W
SM-LF
C9960 1
0.1UF
20%
10V
CERM 2
402
GPU DDC Pass FETs
CRITICAL
=GPU_DDC_ENABLE
65A3
=PP3V3_D3C_GPU_LVDS_DDC
U9960
13D5
79B6 74C3
R9970
13D5
15.8K
71C5
1%
1/16W
MF-LF
402 2
79C6 79B3 65A3
Q9970
2N7002DW-X-F
13D5
1 S
GPU_DDC_C_CLK
=PP3V3_S0_LVDS_MUX
C9961
SOT-363
75A3
13D5
74C3
0.1UF
LVDS_CONN_DDC_CLK
MAKE_BASE=TRUE
79D5 64A2
20%
10V
CERM 2
402
76C3
79C4
R99711
15.8K
79B6 79A3
1%
1/16W
MF-LF
402 2
75A3
3
5
6
11
10
14
13
1
LVDS_MUX_SEL_GPU_MUXED
5
26C3 22A6
GPU_DDC_C_DATA
LVDS_VDDEN
GPU_DIGON
LVDS_BKLTEN
GPU_BLON
LVDS_BKLTCTL
GPU_VARY_BL
S0PGOOD_PWROK
S0D3CPGOOD_PWROK
15
NOTE: S = HIGH selects xB2
LVDS_DDC_CLK
16
VCC
26A1
PLT_RST_L
=LVDS_MUX_SEL_GPU 2
U9961
NO STUFF
3
R9960
10K
GND
8
LVDS_PANEL_EN
76D4
INVERTER_BKLTON
76B8
INVERTER_PWM_UNBUF
76A8
12
PGOOD_MUXED_S0_OR_S0D3C 64B2
THRML
PAD
17
SYNC_MASTER=M59_MG
5%
1/16W
MF-LF
2 402
LVDS_CONN_DDC_DATA
MAKE_BASE=TRUE
R9962

5%
1/16W
MF-LF
2 402
76C3
SOT-363
3
5%
1/16W
MF-LF
402 2
S
OE*
2N7002DW-X-F
D
100K
SC70
Q9970
G
4 S
R99611
MC74VHC1G08
74CBTLV3257
QFN
1B1 SYM_VER-2
1A
1B2
2B1
2A
2B2
3B1
3A
3B2
4A
4B1
4B2

13D5
SIZE
LVDS_DDC_DATA
21D5
TP_SB_GPIO23
LVDS_MUX_SEL_GPU
=LVDS_MUX_SEL_GPU 79A4 79B6
MAKE_BASE=TRUE
NOTE: SB_GPIO23 has internal 20K PU to default selection to GPU
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
79
84
8
Date
- Radar # - Description
5
Date
Date
DMS Release #01000

2006/05/26 - 4508681 - Release for Proto
DMS Release #04000

2006/06/30 - 4566939 - Release for EVT
DMS Release #07000

2006/08/07 - 4607952 - Release for DVT
DMS Release #0A000
2006/09/19 - 4726575 - Release for PVT
Revision History
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
80
84
FSB (Front-Side Bus) Constraints
PCI-Express / DMI Bus Constraints

TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
FSB_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCIE_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
DMI_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
TABLE_SPACING_RULE_ITEM
FSB_ADDR
=3:1_SPACING
FSB_DATA
FSB_ADDR2ADDR
=2:1_SPACING
FSB_ADSTB
=3:1_SPACING
FSB_DATA2DATA
=2:1_SPACING
FSB_DSTB
=3:1_SPACING
WEIGHT
PCIE
20 MIL
DMI
20 MIL
FSB_ADDR2ADSTB
=3:1_SPACING
=3:1_SPACING
FSB_DATA2DSTB
=3:1_SPACING
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 7.2, 9.2 & 10.5.2
SPACING_RULE_SET
LAYER
WEIGHT
Disk Interface Constraints
FSB_COMMON
=2:1_SPACING
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
IDE_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SATA_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
FSB_ADDR
FSB_ADDR
FSB_ADDR2ADDR
FSB_ADDR
FSB_ADSTB
FSB_ADDR2ADSTB
FSB_DATA
FSB_DATA
FSB_DATA2DATA
WEIGHT
FSB_DATA
FSB_DSTB
IDE
=1.8:1_SPACING
SATA
20 MIL
FSB_DATA2DSTB
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 10.6 & 10.7.2
Audio Interface Constraints

Design Guide recommends each strobe/signal group is routed on the same layer.
Design Guide recommends FSB signals be routed only on internal layers.
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
AUDIO_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1.
NOTE: Design Guide allows closer spacing if signal lengths can be shortened.
WEIGHT
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 4.2 & 4.3
AUDIO
CPU Signal Constraints
=1.8:1_SPACING
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1

PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
USB 2.0 Interface Constraints
CPU_27P4S
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=STANDARD
=STANDARD
CPU_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
USB2_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
SPACING_RULE_SET
LAYER
WEIGHT
CPU_2TO1
WEIGHT
=2:1_SPACING
CPU_COMP
DG recommends at least 25 mils, >50 mils preferred
25 MIL
USB2
=4:1_SPACING
USB2_2CLK
25 MIL
CPU_GTLREF
DG says minimum spacing 50 mils to clocks
25 MIL
CPU_ITP
=2:1_SPACING
CPU_VCCSENSE
25 MIL
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.10.1.2

Internal Interface Constraints

Most CPU signals with impedance requirements are 55-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
SMB_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 4.4, 4.6.2, & 5.8.2.4
DDR2 Memory Bus Constraints
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
WEIGHT
DIFFPAIR NECK GAP

SMB
=3:1_SPACING
SPI
=1.8:1_SPACING
MEM_45S
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
MEM_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
MEM_70D
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.17.1.1
MEM_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
Clock Signal Constraints

SPACING_RULE_SET
LAYER
WEIGHT
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
MEM_CLK2MEM
MEM_CLK
MEM_CLK
MEM_CLK2MEM
=2:1_SPACING
MEM_CTRL2MEM
=3:1_SPACING
MEM_CLK
MEM_CTRL
MEM_CLK2MEM
MEM_CLK
MEM_CMD
MEM_CLK2MEM
MEM_CLK
MEM_DATA
MEM_CLK2MEM
MEM_CMD2MEM
=3:1_SPACING
=1.5:1_SPACING
MEM_CTRL
MEM_CLK
MEM_DQS
MEM_CLK2MEM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
CLK_FSB_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
CLK_PCIE_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
CLK_MED_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CLK_SLOW_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
MEM_CTRL2MEM
MEM_CTRL
MEM_CTRL
MEM_CTRL2CTRL
MEM_CTRL
MEM_CMD
MEM_CTRL2MEM
MEM_CTRL
MEM_DATA
MEM_CLK
SPACING_RULE_SET
=1.5:1_SPACING
MEM_DATA2DATA
AREA_TYPE
NET_SPACING_TYPE2
MEM_CMD2CMD
NET_SPACING_TYPE1
=4:1_SPACING
MEM_CTRL2CTRL
SPACING_RULE_SET
MEM_CTRL2MEM
All FSB signals with impedance requirements are 55-ohm single-ended.

Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs.
Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs.
DSTB complementary pairs are spaced 3:1, even in constraint areas.
MEM_CTRL
MEM_DQS
MEM_CTRL2MEM
MEM_DATA2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CMD
MEM_CLK
MEM_CMD2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DATA
MEM_CLK
MEM_DATA2MEM
CLK_FSB
25 MIL
CLK_PCIE
20 MIL
CLK_MED
20 MIL
CLK_SLOW
10 MIL
=3:1_SPACING
MEM_CMD
MEM_2OTHER
WEIGHT
=3:1_SPACING
MEM_DQS2MEM
MEM_CTRL
MEM_CMD2MEM
MEM_DATA
MEM_CTRL
MEM_DATA2MEM
25 MIL
MEM_CMD
MEM_CMD
MEM_CMD2CMD
MEM_DATA
MEM_CMD
MEM_CMD
MEM_DATA
MEM_CMD2MEM
MEM_CMD
MEM_DQS
MEM_CMD2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS
MEM_CLK
MEM_DQS2MEM
MEM_DQS
MEM_CTRL
MEM_DQS2MEM
MEM_DQS
MEM_CMD
MEM_DQS2MEM
MEM_DQS
MEM_DATA
MEM_DQS2MEM
Need to support MEM_*-style wildcards!
MEM_DATA2MEM
MEM_DATA
MEM_DATA
MEM_DATA2DATA
MEM_DATA
MEM_DQS
MEM_DATA2MEM
Napa Platform Constraints

NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
MEM_2OTHER
MEM_CTRL
MEM_2OTHER
MEM_CMD
MEM_2OTHER
MEM_DATA
MEM_2OTHER
SYNC_DATE=(MASTER)


MEM_DQS
MEM_2OTHER

MEM_DQS
MEM_DQS
MEM_DQS2MEM
SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 6.2
REV.
051-7150
A.0.0
OF
81
84
GDDR3 (Frame Buffer) Memory Bus Constraints
High-Speed I/O Interface Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
ENET_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
FW_110D
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
SPACING_RULE_SET
LAYER
FB_35S_TO_55S
=35_OHM_SE
=55_OHM_SE
=35_55_OHM_SE
=STANDARD
=STANDARD
FB_40S
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
FB_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
FB_75D
=75_OHM_DIFF
=75_OHM_DIFF
=75_OHM_DIFF
=75_OHM_DIFF
=75_OHM_DIFF
WEIGHT
ENET
=3:1_SPACING
FW
=3:1_SPACING
SPACING_RULE_SET
LAYER
WEIGHT
FB_ADCTRL
=2.5:1_SPACING
FB_CLK
=2.5:1_SPACING
note
FB_DATA
=2.5:1_SPACING
PCI Bus Constraints

ADDR/CTRL lines should route 35-ohms to T, then 55-ohms to each VRAM device.
CTRL lines are 55-ohm single-ended impedence.
DQ/DQM/DQS lines are 40-ohm single-ended impedence.
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
PCI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
NOTE: CLK lines are specified in Layout Guide as 40-ohm single-ended. We treat as 75-ohm differential.
NOTE: Layout Guide does not specify LVDS/TMDS spacing to other traces other than "do not run close"
WEIGHT
SOURCE: ATI Layout Guide, Rev 0.5 (DSG-216MOBRADEON-05), Sections 7 & 8.1.2.
PCI
=2:1_SPACING
Video Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
LVDS_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TMDS_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
VGA_75S
=75_OHM_SE
=75_OHM_SE
=75_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
LVDS
=3:1_SPACING
LVDS_PAIR2PAIR
25 MIL
TMDS_PAIR2PAIR
25 MIL
TMDS
WEIGHT
=3:1_SPACING
VGA
15 MIL
C
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
LVDS
LVDS
LVDS_PAIR2PAIR
TMDS
TMDS
TMDS_PAIR2PAIR
LVDS and TMDS signals are 100-ohm +/- 10% differential impedence.
LVDS and TMDS pairs should be kept at least 25 mils apart.
Ground shields can be used around each pair if spacing cannot be met.
VGA should be routed as close to 75-ohms single-ended impedence as possible.
VGA signals should be kept at least 15 mils from other traces.
Ground shields recommended around VGA signals.
NOTE: Layout Guide does not specify LVDS/TMDS spacing to other traces other than "do not run close"
SOURCE: ATI Layout Guide, Rev 0.5 (DSG-216MOBRADEON-05), Sections 7 & 8.1.2.
More System Constraints
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
82
84
M59 Board-Specific Spacing & Physical Constraints

TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
SPACING_RULE_SET
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA
MM
15.2
DEFAULT
LAYER
WEIGHT
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
BGA
BGA_P1MM
MEM_CLK
BGA
BGA_P2MM
CLK_FSB
BGA
BGA_P2MM
CLK_PCIE
BGA
BGA_P2MM
CLK_MED
BGA
BGA_P2MM
CLK_SLOW
BGA
BGA_P2MM
0.1 MM
STANDARD
=DEFAULT
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
DEFAULT
=55_OHM_SE
=55_OHM_SE
30 MM
0 MM
0 MM
STANDARD
=DEFAULT
=DEFAULT
12.7 MM
=DEFAULT
=DEFAULT
BGA_P1MM
=DEFAULT
BGA_P2MM
=DEFAULT
BGA_P3MM
=DEFAULT
PHYSICAL_RULE_SET
55_OHM_SE
LAYER
TOP,BOTTOM
ALLOW ROUTE
ON LAYER?
Y
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

0.100 MM
FB_CLK
BGA
BGA_P2MM
FSB_DSTB
FSB_DSTB
BGA
BGA_P3MM
0.100 MM
55_OHM_SE
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
50_OHM_SE
TOP,BOTTOM
0.124 MM
0.124 MM
Allow 0.1 MM on blind-to-buried via dogbones (layers 2 & 11)
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
0.090 MM
0.090 MM
=STANDARD
=STANDARD
=STANDARD
1.5:1_SPACING
0.15 MM
1.5:1_SPACING
ISL2,ISL11
1.8:1_SPACING
PHYSICAL_RULE_SET
45_OHM_SE
LAYER
TOP,BOTTOM
ALLOW ROUTE
ON LAYER?
Y
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
0.18 MM
1.8:1_SPACING
ISL2,ISL11
2:1_SPACING
0.2 MM
2.5:1_SPACING
0.25 MM
0.105 MM
0.105 MM
=STANDARD
=STANDARD
MINIMUM LINE WIDTH
ISL2,ISL11
0.1 MM
2:1_SPACING
ISL2,ISL11
0.1 MM
2.5:1_SPACING
ISL2,ISL11
0.1 MM
CLK_MED
ISL2,ISL11
0.1 MM
CLK_SLOW
ISL2,ISL11
0.1 MM
CPU_COMP
ISL2,ISL11
0.1 MM
CPU_GTLREF
ISL2,ISL11
0.1 MM
CPU_VCCSENSE
ISL2,ISL11
0.1 MM
DMI
ISL2,ISL11
0.1 MM
LVDS_PAIR2PAIR
ISL2,ISL11
0.1 MM
MEM_2OTHER
ISL2,ISL11
0.1 MM
PCIE
ISL2,ISL11
0.1 MM
SATA
ISL2,ISL11
0.1 MM
TMDS_PAIR2PAIR
ISL2,ISL11
0.1 MM
VGA
ISL2,ISL11
0.1 MM
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=STANDARD
3:1_SPACING
LAYER
CLK_PCIE
0.150 MM
0.3 MM
3:1_SPACING
PHYSICAL_RULE_SET
0.1 MM
0.1 MM
ALLOW ROUTE
ON LAYER?
ISL2,ISL11
DIFFPAIR NECK GAP
45_OHM_SE
CLK_FSB
0.150 MM
0.1 MM
ISL2,ISL11
DIFFPAIR NECK GAP
4:1_SPACING
0.1 MM
0.4 MM
4:1_SPACING
ISL2,ISL11
0.1 MM
40_OHM_SE
TOP,BOTTOM
0.185 MM
0.185 MM
40_OHM_SE
0.131 MM
0.100 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
35_OHM_SE
TOP,BOTTOM
0.230 MM
0.230 MM
35_OHM_SE
0.165 MM
0.165 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
27P4_OHM_SE
TOP,BOTTOM
0.335 MM
0.335 MM
27P4_OHM_SE
0.240 MM
0.240 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

Rules for "Topology #3" for FSB signals, Napa DG tables 4-7 & 4-12.
=STANDARD
=STANDARD
SPACING_RULE_SET
=STANDARD
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
TABLE_SPACING_RULE_OVERRIDE
FSB_ADDR
WEIGHT
=2:1_SPACING
FSB_DATA
=2:1_SPACING
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
OVERRIDE
DIFFPAIR NECK GAP
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
FSB_ADDR2ADDR
35_55_OHM_SE
TOP,BOTTOM
0.230 MM
0.100 MM
35_55_OHM_SE
0.165 MM
0.076 MM
OVERRIDE
OVERRIDE
FSB_DATA2DATA
OVERRIDE
OVERRIDE
=STANDARD
=STANDARD
OVERRIDE
OVERRIDE
=STANDARD
OVERRIDE
=STANDARD
FSB_ADSTB
OVERRIDE
FSB_DSTB
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
=2:1_SPACING
OVERRIDE
Unsupported rule
FSB_ADDR2ADSTB
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
75_OHM_SE
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
OVERRIDE
FSB_DATA2DSTB
OVERRIDE
OVERRIDE
=2:1_SPACING
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
SPACING_RULE_SET
LAYER
WEIGHT
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
TABLE_PHYSICAL_ASSIGNMENT_ITEM
LVDS
LVDS_100D
TMDS
TMDS_100D
OVERRIDE
=2:1_SPACING
OVERRIDE
OVERRIDE
=2:1_SPACING
OVERRIDE
OVERRIDE
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
MEM_2OTHER
OVERRIDE
OVERRIDE
0.5 MM
OVERRIDE
PCI_2PCI
OVERRIDE
OVERRIDE
0.1 MM
OVERRIDE
OVERRIDE
OVERRIDE
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
70_OHM_DIFF
0.149 MM
0.149 MM
=STANDARD
0.125 MM
0.125 MM
70_OHM_DIFF
TOP,BOTTOM
0.185 MM
0.185 MM
0.125 MM
0.125 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
75_OHM_DIFF
0.131 MM
0.131 MM
=STANDARD
0.125 MM
0.125 MM
75_OHM_DIFF
TOP,BOTTOM
0.161 MM
0.161 MM
0.125 MM
0.125 MM
TMDSCONN
TMDS_100D
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
PCI
PCI
PCI_2PCI
VGA
VGA_75S
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
ENETCONN
ENET
TMDSCONN
TMDS
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
80_OHM_DIFF
0.115 MM
0.111 MM
=STANDARD
0.125 MM
0.125 MM
"Stale" physical / spacing types
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
FSB_ANALOG
FSB_COMMON
80_OHM_DIFF
TOP,BOTTOM
0.140 MM
0.140 MM
0.125 MM
0.125 MM
FSB_P2MM
FSB_COMMON
I2C
SMB
GND
STANDARD
MEM_PP1V8_S3
STANDARD
FB_PP1V8
STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

85_OHM_DIFF
0.101 MM
0.101 MM
85_OHM_DIFF
TOP,BOTTOM
0.125 MM
0.125 MM
=STANDARD
0.125 MM
0.125 MM
0.125 MM
0.125 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
PHYSICAL_RULE_SET
50_OHM_SE
DIFFPAIR NECK GAP

90_OHM_DIFF
0.102 MM
0.102 MM
90_OHM_DIFF
TOP,BOTTOM
0.130 MM
0.130 MM
=STANDARD
0.220 MM
0.220 MM
0.220 MM
0.220 MM
FSB_ANALOG
FSB_P2MM
I2C
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
100_OHM_DIFF
0.080 MM
0.080 MM
=STANDARD
0.200 MM
0.200 MM
GND
MEM_PP1V8_S3
FB_PP1V8
100_OHM_DIFF
TOP,BOTTOM
0.099 MM
0.099 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
0.200 MM
0.200 MM
DIFFPAIR NECK GAP
PCI
PCI_55S
M59 Spacing & Physical Constraints

MAXIMUM NECK LENGTH
PHYSICAL_RULE_SET
110_OHM_DIFF
0.077 MM
0.077 MM
=STANDARD
0.330 MM
LAYER
0.330 MM
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
110_OHM_DIFF
TOP,BOTTOM
0.089 MM
0.089 MM
0.330 MM
0.330 MM
MEM_45S
OVERRIDE
OVERRIDE
*
OVERRIDE
0.100 MM
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
MEM_70D
OVERRIDE
SYNC_DATE=(MASTER)
DIFFPAIR NECK GAP

0.100 MM

MEM_85D
OVERRIDE
OVERRIDE
0.100 MM

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
83
84
NET_TYPE
PHYSICAL
SPACING
MEM_CLK
FSB_55S
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_55S
FSB_COMMON
FSB_55S
FSB_DATA
FSB_55S
FSB_DATA
FSB_55S
FSB_DSTB
FSB_55S
FSB_DSTB
FSB_55S
FSB_ADDR
FSB_55S
FSB_ADDR
FSB_55S
FSB_ADSTB
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_55S
CPU_2TO1
CPU_55S
CPU_2TO1
CPU_55S
CPU_2TO1
CPU_55S
CPU_GTLREF
CPU_55S
CPU_COMP
CPU_27P4S
CPU_COMP
CPU_55S
CPU_COMP
CPU_27P4S
CPU_COMP
CPU_55S
CPU_ITP
CLK_FSB_100D
CPU_ITP
CLK_FSB_100D
CPU_ITP
CPU_55S
CPU_ITP
CPU_55S
CPU_2TO1
CPU_55S
CPU_2TO1
THERM
CPU_27P4S
CPU_VCCSENSE
THERM
CPU_27P4S
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
FSB_BREQ0_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DPWR_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_RS_L<2..0>
FSB_TRDY_L
FSB_CPURST_L
FSB_D_L<63..0>
FSB_DINV_L<3..0>
FSB_DSTBP_L<3..0>
FSB_DSTBN_L<3..0>
FSB_A_L<31..3>
FSB_REQ_L<4..0>
FSB_ADSTB_L<3..0>
FSB_IERR_L
FSB_FERR_L
CPU_PWRGD
CPU_INTR
CPU_NMI
CPU_A20M_L
CPU_DPSLP_L
CPU_IGNNE_L
CPU_INIT_L
CPU_SMI_L
CPU_STPCLK_L
CPU_THERMTRIP_L
PM_DPRSLPVR
IMVP_DPRSLPVR
CPU_GTLREF
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>
XDP_BPM_L<5..0>
CPU_XDP_CLK_P
CPU_XDP_CLK_N
ITPRESET_L
CPU_VID<6..0>
CPU_VID<6..0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_VSEN_P
IMVP6_VSEN_N
MEM_70D
5D5 7D6 12C4
MEM_CTRL
MEM_45S
5D5 7D6 12C4
MEM_CMD
MEM_55S
7D6 12C4
MEM_DATA
MEM_55S
5D5 7D6 12C4
MEM_DQS
MEM_85D
5D5 7D6 12B4
FB_CLK
FB_75D
FB_ADCTRL
FB_35S_TO_55S
FB_ADCTRL
FB_55S
FB_DATA
FB_40S
5D5 7D6 12B4
LVDS
LVDS_100D
5D5 7D6 12B4
TMDS
TMDS_100D
7D6 12A4
VGA
VGA_75S
PCIE
PCIE_100D
DMI
DMI_100D
SATA
SATA_100D
IDE
IDE_55S
USB2
USB2_90D
ENET
ENET_100D
FW
FW_110D
SMB
SMB_55S
SPI
SPI_55S
CLK_FSB
CLK_FSB_100D
7B3 21C4
CLK_PCIE
CLK_PCIE_100D
7C8 21C4
CLK_MED
CLK_MED_55S
7C8 21C4
CLK_SLOW
CLK_SLOW_55S
7D6 12B4
7B3 12B4
5D5 7D6 12B4
5D5 7D6 12B4
7D6 12A4
7D6 11B5 12C4
5D5 7B3 7B4 7C3 7C4 12B6 12C6 12D6

5D5 7B3 7B4 7C3 7C4 12B4
5D5 7B3 7B4 7C3 7C4 12B4
5D5 7B3 7B4 7C3 7C4 12B4
5D5 7C8 7D8 12C4 12D4

5D5 7D8 12A4 12B4
5D5 7C8 7D8 12C4
7D6
7C8 21C4
7B3 21C4
7C8 21C4
7D6 21C4
7C8 21C4
7C8 21C4
14B7 23C3 59C8
59C7
7B4
7B3
7B3
7B3
7B3
7C6 11B3
11B3 34D3
11B3 34D3
11B3
8B7 9C2 84B6

8B7 9C2 84B6
8B6 59B1
8B6 59A1
59A3
59A3
AUDIO_55S
AUDIO
AUDIO_55S
AUDIO
AUDIO_55S
AUDIO
AUDIO_55S
AUDIO
AUDIO_55S
AUDIO
AUDIO_55S
AUDIO
AUDIO_55S
AUDIO
AUDIO_55S
AUDIO
AUDIO_55S
AUDIO
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
I70
TMDS
TMDS
I71
TMDS
TMDS
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
TMDSCONN
I72
TMDSCONN
TMDSCONN
I73
TMDSCONN
TMDSCONN
SB_ACZ_BITCLK
ACZ_BITCLK
SB_ACZ_SYNC
ACZ_SYNC
SB_ACZ_RST_L
ACZ_RST_L
ACZ_SDATAIN<0>
SB_ACZ_SDATAOUT
ACZ_SDATAOUT
21C6
5C1 21C7 47B6
21C6
5C1 21C7 47B6
21C6
5C1 21C7 47B3
5C1 21C7 47B6
21C6
5C1 21C7 47B6
TMDS_CLK_P
TMDS_CLK_N
TMDS_DATA_P<5..3>
TMDS_DATA_N<5..3>
TMDS_DATA_P<2..0>
TMDS_DATA_N<2..0>
TMDS_CLK_F_P
TMDS_CLK_F_N
TMDS_DATA_F_P<5..3>
TMDS_DATA_F_N<5..3>
TMDS_DATA_F_P<2..0>
TMDS_DATA_F_N<2..0>
75C3 76C7 77B8

75C3 76C7 77C8
75C3 76C7 77A8 77B8
75C3 76C7 77A8 77B8
75C3 76C7 77C8 77D8
75C3 76C7 77C8 77D8
77B5 77B6 77D1
77A5 77C6 77D1
77A6 77B3 77B5 77B6 77D1
77A6 77B3 77B5 77B6 77D1
77B3 77B5 77C6 77D1 77D6
77B3 77B5 77C6 77D1 77D6
M59 Net Properties
SYNC_DATE=(MASTER)

SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
D
SCALE
SHT
NONE
REV.
051-7150
A.0.0
OF
84
84

LB 820-2054

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8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

System Block Diagram

Power Block Diagram

Functional / ICT Test

Signal Aliases/Misc Comps

CPU Decoupling & VID

CPU MISC1-TEMP SENSOR

CPU ITP700FLEX DEBUG

NB PEG / Video Interfaces

DDR2 SO-DIMM Connector A

DDR2 SO-DIMM Connector B

Memory Active Termination

Memory Vtt Supply

FireWire Link (TSB83AA22)

FireWire PHY (TSB83AA22)

Yukon Power Control

FW PHY Power Supply

FireWire Port Power

External USB Connector

Left I/O Board Connector

LPC+ Debug Connector

Current & Voltage Sensing

Sudden Motion Sensor (SMS)

IMVP6 CPU VCore Regulator

5V / 1.5V Power Supply

2.5V & 1.2V Regulators

3.3V / 1.05V Power Supplies

3.3V G3Hot Supply & Power Control

PBus-In,Batt. & 3G Pwr Connectors

ATI M56 PCI-E

GPU (M56) Core Supplies

ATI M56 Core Power

ATI M56 Frame Buffer I/F

GDDR3 Frame Buffer A

GDDR3 Frame Buffer B

ATI M56 GPIO/DVO/Misc

ATI M56 Video Interfaces

Internal Display Connectors

External Display Connector

M59 Specific Connectors

LVDS Interface Pull-downs

Napa Platform Constraints

More System Constraints

M59 Spacing & Physical Constraints

M59 Net Properties

DIMENSIONS ARE IN MILLIMETERS

Apple Computer Inc.

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

DO NOT SCALE DRAWING

THIRD ANGLE PROJECTION

LAST_MODIFIED=Mon Sep 25 10:45:58 2006

"Factory Slot" Connector

Right USB 2.0

Left I/O &

NOTICE OF PROPRIETARY PROPERTY

System Block Diagram

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY