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A1181 Macbook Pro

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The document appears to be a bill of materials (BOM) listing various electronic components along with their designators and packages.

The BOM lists resistors, capacitors, integrated circuits, connectors, and other electronic components.

Designators include letters and numbers to identify components on schematics and printed circuit boards (PCB), such as U1234 for an IC and R9876 for a resistor.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.


2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

1
CK
APPD

M42C MLB

REV

ZONE

ECN

ENG
APPD

DESCRIPTION OF CHANGE
DATE

474680 PRODUCTION RELEASED

DATE

11/27/06 ?

11/27/2006 POST RAMP WITH LOCKED BOOTROM


D

D
(.csa)

Page
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TABLE_TABLEOFCONTENTS_ITEM

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61

Contents

DRI

Table of Contents
SYSTEM BLOCK DIAGRAM
Power Block Diagram
CONFIGURATION OPTIONS
FUNC TEST 1 OF 2
SIGNAL ALIAS /RESET
CPU 1 OF 2-FSB
CPU 2 OF 2-PWR/GND
CPU DECAPS & VID<>
CPU MISC1-TEMP SENSOR
CPU ITP700FLEX DEBUG
NB CPU Interface
NB PEG / Video Interfaces
NB Misc Interfaces
NB DDR2 Interfaces
NB Power 1
NB Power 2
NB Grounds
NB (GM) Decoupling
NB Config Straps

RX
RX
MK
RX
RX
RX
RX
MK
MK
ES
RX
MK
DK
RX
LT
DK
DK
DK
DK
DK
RX
RX
RX
RX
RX
SB Misc
RX
M42 SMBUS CONNECTIONS
ES
DDR2 SO-DIMM Connector A
LT
DDR2 SO-DIMM Connector B
LT
Memory Active Termination
LT
Memory Vtt Supply
LT
CLOCKS
DK
CLOCK TERMINATION
DK
PATA CONNECTOR
ES
SATA CONNECTOR
ES
ES
ETHERNET CONTROLLER
ETHERNET CONNECTOR
ES
FIREWIRE CONTROLLER
ES
FIREWIRE PORT
ES
CONNECTOR MISC
ES
IR CONTROLLER
ES
ES
ES
MK
BLUETOOTH INTERFACE
SMC
MK
SMC SUPPORT
LD
MK
LPC+ Debug Connector
CPU Current & Voltage Sense ES

Page

Sync

TABLE_TABLEOFCONTENTS_HEAD

N/A

N/A

TABLE_TABLEOFCONTENTS_ITEM

5/23/05

MASTER

TABLE_TABLEOFCONTENTS_ITEM

06/30/2005

POWER

TABLE_TABLEOFCONTENTS_ITEM

07/18/2005

SMC

TABLE_TABLEOFCONTENTS_ITEM

07/25/2005

TP

TABLE_TABLEOFCONTENTS_ITEM

08/19/2005

ENET

TABLE_TABLEOFCONTENTS_ITEM

05/03/2005

MASTER
MASTER

TABLE_TABLEOFCONTENTS_ITEM

08/19/2005

SMC

TABLE_TABLEOFCONTENTS_ITEM

08/19/2005

ENET

TABLE_TABLEOFCONTENTS_ITEM

5/23/05

MASTER

TABLE_TABLEOFCONTENTS_ITEM

07/25/2005

NB

TABLE_TABLEOFCONTENTS_ITEM

07/25/2005

NB

TABLE_TABLEOFCONTENTS_ITEM

08/15/2005

NB

TABLE_TABLEOFCONTENTS_ITEM

07/25/2005

NB

TABLE_TABLEOFCONTENTS_ITEM

07/25/2005

NB

TABLE_TABLEOFCONTENTS_ITEM

07/25/2005

NB

TABLE_TABLEOFCONTENTS_ITEM

07/25/2005

NB

TABLE_TABLEOFCONTENTS_ITEM

06/22/2005

NB

TABLE_TABLEOFCONTENTS_ITEM

06/28/2005

NB

TABLE_TABLEOFCONTENTS_ITEM

08/05/2005

SB

TABLE_TABLEOFCONTENTS_ITEM

11/16/2005

ENET

TABLE_TABLEOFCONTENTS_ITEM

11/28/2005

ENET

TABLE_TABLEOFCONTENTS_ITEM

08/05/2005

SB

TABLE_TABLEOFCONTENTS_ITEM

06/28/2005

SB

TABLE_TABLEOFCONTENTS_ITEM

07/26/2005

NB

TABLE_TABLEOFCONTENTS_ITEM

08/30/2005

ENET

TABLE_TABLEOFCONTENTS_ITEM

06/20/2005

MEMORY

TABLE_TABLEOFCONTENTS_ITEM

06/20/2005

MEMORY

TABLE_TABLEOFCONTENTS_ITEM

06/20/2005

MEMORY

62

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50
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68
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75
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77
78

63
65
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68
72
73
74
75
76
77
78
79
80
81
82
83
94
95
98
99

100
101
102
103
104
105

106

107

06/03/2005

CLOCK
06/06/2005

CLOCK

11/01/2005

ENET

11/14/2005

ENET

12/06/2005

ENET

11/14/2005

ENET

08/30/2005

ENET

11/16/2005

ENET

11/16/2005

ENET

11/09/2005

ENET

11/01/2005

ENET

08/19/2005

ENET

DESCRIPTION

RX
ES
MK
RX
DK
DK
DK
DK
MK
MK
MK
MK
MK
MK
MK
MK
MK
ES
DK
DK

Sync
11/09/2005

ENET
5/23/05

MASTER
11/10/2005

ENET
08/23/2005

SMC
07/18/2005

SMC
08/05/2006

M42AUDIO
08/05/2006

M42AUDIO

08/05/2006

M42AUDIO

08/05/2006

M42AUDIO

07/13/2005

POWER

07/13/2005

POWER

12/06/2005

ENET

07/13/2005

POWER

07/13/2005

POWER

08/30/2005

ENET

11/16/2005

ENET

08/29/2005
08/18/2005

08/19/2005

SMC

06/06/2005

GRAPHIC

06/06/2005

GRAPHIC

05/21/05

EUGENE

08/23/2005

SMC

06/30/2005

RX-RAYMOND XU
DK-DINESH KUMAR
RC-RAY CHANG
MK-MARC KLINGELHOFER
LT-LAWRENCE TAN
ES-ERIC SMITH

NB

08/30/2005

ENET

REFERENCE DESIGNATOR(S)

LD-LINDA DUNN

BOM OPTION

DIMENSIONS ARE IN MILLIMETERS

SCHEM,MACBOOK,MLB

SCH

820-1889

PCBF,MACBOOK,MLB

PCB

Apple Computer Inc.

METRIC

XX

X.XX
DRAFTER

NOTICE OF PROPRIETARY PROPERTY

DESIGN CK

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

X.XXX
ENG APPD

MFG APPD

QA APPD

DESIGNER

RELEASE

SCALE

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

ANGLES

TITLE

DO NOT SCALE DRAWING

SCHEM,MLB,MACBOOK
NONE

TABLE_5_ITEM

SIZE

ABBREV=DRAWING
LAST_MODIFIED=Mon Nov 27 14:57:31 2006

THIRD ANGLE PROJECTION

EE DRIS:

SMC

051-7173
DRAWING

07/13/2005

POWER

TABLE_5_ITEM

TITLE=U230

y
r

ENET

TABLE_5_HEAD

QTY

Contents

TEMPERATURE SENSE
SPI BOOTROM
Fan
SMS
TPM
AUDIO: CODEC
AUDI0: SPEAKER AMP
AUDIO: JACK
AUDIO: JACK TRANSLATORS
IMVP6 CPU VCore Regulator
5V / 3.3V Power Supply
2.5V/1.2V Regulator
1.8V Supply
1.5V / 1.05V Power Supply
S3/S0 FETS, G3H SUPPLY
Power Conn / Alias
DC-In & Battery Connectors
PBUS Supply/Battery Charger
INVERTER,LVDS,TMDS
EXTERNAL TMDS
MINI-DVI CONNECTOR
Cross Reference Page
Cross Reference Page
Cross Reference Page
Cross Reference Page
Cross Reference Page
Cross Reference Page
Cross Reference Page
Cross Reference Page
Cross Reference Page

Date

TABLE_TABLEOFCONTENTS_ITEM

(MASTER)

(MASTER)

Schematic / PCB #s
PART#

DRI

a
n
i
m
i
l
e
TABLE_TABLEOFCONTENTS_ITEM

05/03/2005

r
P

TABLE_TABLEOFCONTENTS_ITEM

(.csa)

Date

MATERIAL/FINISH
NOTED AS
APPLICABLE

DRAWING NUMBER

REV.

051-7173
SHT

C
OF

108

INVERTER
CONNECTOR

P.67

CPU
THERMAL
SENSOR
P.10

LCD Panel

P.67

CLOCKING
Config
AND SPECTRUM

PROCESSOR
479 BGA

J2800

P.32-33

y
r

P.7-9

MINI DVI &


CRT CONNECTOR

DDR2 SDRAM DIMM A

P.69

SO-DIMM Connector

FSB

P.28
ETHERNET
CONNECTOR

LVDS
TV+CRT

P.37

TMDS

FW CONNECTOR

1466UFCBGA

P.39

FW

P.12-20

FW CONTROLLER

P.38
5V

HDD
Connector
P.35

SO-DIMM Connector

DMIX4

USB

PCIEX1
PCI

m
il

CHIPSET-SB

USB

ODD
Connector
P.34

USB

IR CONTROLLER
P.41

PATA

66MHZ
16BITS

TP CONNECTOR
P.40
AUDIO

USB

P.54-57

P
SPI FLASH
BOOTROM
P.50

SMBUS

P.27

A
FAN
CONNECTOR

P.31

P.43

BLUETOOTH

CONNECTOR

P.44

SB MISC.

P.21-26

SPI
AZALIA

609 BGA

e
r

INTERNAL KB

REGULATOR

TO WIRELESS
CARD

PCIEX1

SATA

IR_RX_OUT

DDR2 VTT

P.29

P.36

P.42

DDR2 SDRAM DIMM B

CH.B

ENET CONTROLLER

USB 2.0
CONNECTOR

a
n
i

CHIPSET-NB
SDVO

TMDS

P.68

ENET

J2900

CH.A

SMC

P.26

LPC 33MHZ

POWER SUPPLY

TPM

P.53

LPC
DEBUG
CONNECTOR

P.58~P.66

P.47
SMS

CONNECTOR TO

SYSTEM BLOCK DIAGRAM

BATTERIES
& Charger

P.52

SYNC_MASTER=MASTER

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

SMBUS

P.45

P.64

P.51

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7173

SCALE

SYNC_DATE=5/23/05

NOTICE OF PROPRIETARY PROPERTY

C
OF

108

M42A POWER SYSTEM ARCHITECTURE


02
3.425V G3HOT
LT3470
U8090
(PAGE 62)

PBUSB_VSENSE

7A FUSE
PPVBAT_S5_CHGR_REG

ENABLES

AC
ADAPTER
IN

ISL6255

PP3V42_G3H_REG

VIN

16

1V5S0_RUNSS
(S0)

16

1V05S0_RUNSS
(S0)

U8300

1.5V
ENA1

ENA2

SMC_BATT_ISENSE

SMC_DCIN_ISENSE

PP1V5_S0
(6A MAX CURRENT)

VOUT1

PP1V05_S0
(8A MAX CURRENT)

VOUT2

PGOOD

02

1V51V05S0_PGOOD

VIN

Q8000

CPUVCORE

13

PGD_IN

VOUT

PP5V_S3

12

IMVP_VR_ON
(S0)

P5VS3_EN_L_RC
(S3)
Q8005

CLKEN#

PP5V_S0

2
06

07

Q8059

Q8060

SMC_PM_G2_ENABLE
P60

(S5)

07

VIN

5VS5_RUNSS
(S5)

ENA2

3V3S5_RUNSS
(S5)

ENA1

Q8059
P25

LOGIC

Q8031

PP5VS3_EN_L_RC

(S3)

P3V3S3_EN_L_RC
(S3)

VIN
ENA

2.5V

(S3)

e
r
Q8015

SLP_S3_L

(S0)

15

17

PP3V3_S0

16

VIN

ENA

P3V3S0_EN_RC

Q8061
SOFT
START

Q8062

1V5S0_RUNSS
(S0)

(S0)

16

1V05S0_RUNSS
(S0)

16

08

PP3V3_S5

DELAY

Q8030

R=10k
P5VS0_EN_RC
c=0.1uf (S0)

16

DELAY

R=100k
P3V3S0_EN_RC
c=0.1uf (S0)

P1V2S0_EN

16
16

P1V8S0_EN_L_RC
R=100k
c=0.01uf (S0)

P
2

DELAY

Q8031

2.5V
MAX8887
U7701

16

12

VIN

PM_SLP_S4_L ENA
(S3)

1.8V

PGOOD

14

PP2V5_S0

18

VIN

MCH DPLL 1.5V


ENA

PP1V5_S0_DPLL

18_1

TPS73115
U1900
(PAGE 19)

PWROK

RESET*

MCH

28

PWROK

HCPURST*

FSB_CPURST_L

10
U8080

SMC

19

RSMRST_OUT(P15) PM_RSMRST_L

ALL_SYS_PWRGD

09

PWRGD(P12)

RSMRST_PWRGD

99ms DLY

PP1V8_S0

V1(2.5V)

P17(BTN_OUT)

BATTERY ONLY: 05

S0PWRGD_OK
RST*

RST*

ADAPTER IN

V1(1.8V)

PLT_RST*
PWR_BUTTON(P90)

V1(3.3V)

17

PM_PWRBTN_L
SMC_RST_L

: 08-1

VADJ1(1.2V)
VADJ2(0.9V)

LTC2908
U8070
(PAGE 62)

SLP_S5_L
SLP_S4_L

SIGNAL DELAY TIME


IMVP_VR_ON
S0PWRGD_OK
VR_PWRGOOD_DELAY

SLP_S3_L

SLP_S5_L(P95)
SLP_S4_L(P94)
SLP_S3_L(P93)

99ms
200ms
7ms

U5800
(PAGE 44)

STEP
01-04
01,05-09
10-13
14-18
17,19-24
25-27

Power Block Diagram

STEP 06 (S5 POWER STATUS)TRUTH TABLE


NO AC/BATTERY
BATTERY ONLY
ACIN WITH/WITHOUT BATTERY
BATTERY ONLY,PRESS PWR BUTTON

18

BD3535FVM
U3100
(PAGE 31)

L(S5
L(S5
H(S5
H(S5

OFF)
OFF)
ON)
ON)

SYNC_MASTER=POWER

SYNC_DATE=06/30/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

PP1V2_S3_ENET

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

MAX8516
U7720
(PAGE 59)

Q8063
PP1V2_S0

SIZE

17
APPLE COMPUTER INC.

DRAWING NUMBER

16

P1V2_S0_EN

SHT
NONE

REV.

051-7173

SCALE

21

RSMRST_IN(P13)

SMC_ONOFF_L

19

V1(5V)

IMVP_VR_ON

IMVP_VR_ON(P16)

13
VOUT

POWER ON SEQUENCE LIST

(8A MAX CURRENT)

PP0V9_S0

VOUT

26

PWRGOOD

VIN

0.9V

CPU_PWRGD

CPUPWRGD(GPIO49)

CPU

17-1

PWR/RST STATUS
G3H POWER ON
S5 POWER ON
S3 POWER ON
S0 SYSTEM POWER ON
S0 CPU POWER ON
PLATFORM,CPU RESET

P1V8S0_EN_L_RC16
(S0)

VIN

1.2V

VOUT1

Q8025

PP5V_S0_MEMVTTENA

ENA

RSMRST*

PM_SB_PWROK

VOUT

PP2V5_S0_NB_DISP_PLL

17

27
PLT_RST_L

PLTRST*

25

U2601

(0.3A MAX CURRENT)

PP1V8_S3_REG

VOUT

ISL6269
U7800
(PAGE 60)

VRMPWRGD

(0.3A MAX CURRENT)

(PAGE 59)

PPBUS_S5_FWPWRSW

Q8061
SOFT
START

Q8030

VOUT

23

6-1

PWRBTN*

PP4V5_AUDIO_ANALOG

VOUT

TPS79501
VR6800
(PAGE 68)

PP2V5_S3

MAX8887
U7700
(PAGE 59)

SLP_S4_L

ENA

(S0)

12

AUDIO 4.5V

PP3V3_S0_AUDIO

17

13

ICH

17-1

MM157
U1901
(PAGE 19)

08

CY28445-5
U3301
(PAGE 33)

U2603
VR_PWRGD_CK410

(36A MAX CURRENT)

PWRGD

PP3V3_S0_NB_TVDAC

VIN

PP3V3_S3

12

TV 3.3VVOUT

m
il

RSMRST_PWRGD

ENA

PP5V_S5

11

SLP_S5_L

SLP_S3_L

(4A MAX
CURRENT)

Q8010

5V3V3S5_PGOOD

DELAY

SLP_S4_L

VOUT1

12

R=100k PP3V3S3_EN_L_RC
c=0.01uf (S3)

ICH

3.3V

VIN

P5VS0_EN_RC
(S0)

16

PGOOD

DELAY

R=10k
c=2.2nf

VOUT2

LTC3728
U7600
(PAGE 58)

CHGR_EN

U5800
(PAGE 44)

5V

PP5V_S5_REG
(5A MAX CURRENT)
PP3V3_S5_REG

22

PPVCORE_CPU_S0

24

PPBUSB_G3H

SMC

SMC_CPU_VSENSE

VR_PWRGOOD_DELAY

ISL6262 PGOOD
U7500
(PAGE 57)

17

3S2P / 3S3P

VR_PWRGD_CK410_L

VR_ON

21

CK410_PD_VTT_PRGD_L

18

SMC_CPU_ISENSE

BATT_POS_F

17

a
n
i

U6100
01
BATTERY

17

CLOCK

1.05V

LTC3728
U7900
(PAGE 61)

U8375

(PAGE 65)

y
r

02
VIN

BATTERY CHARGER

U8370

DCIN

VOUT

Q6150

PBUS CONVERTER/

01
6A FUSE

V
PPBUSA_G3H

SMC_RST_L

03

ENABLE

U8310

04

SMC PWRGD
MC33465N_30ATR
U5900
(PAGE 45)

CHGR_EN
(S5)

C
OF

108

PAGE_BORDER=TRUE

Page Notes

BOM OPTION

Power aliases required by this page:


(NONE)

BOMOPTION

M42A GOOD
ST MICRO
630-7795
EVT

M42A BETTER
ST MICRO
630-7796
EVT

M42A BEST
KIONIX
630-7799
EVT

>

>

>

>

>

>

>>

>>

>>

>

>

>

>

> >

> >

> >

> >

> >

> > >

> > > >

> > >

> > >

5V3V3S3_CONT

(NONE)

5V3V3S3_SKIP
ACCEL_KIONIX

> >

> >

> >

ACCEL_ST
INVERTER_BUF

>>

ITP
LEMENU
MEMVTT_EN_PU
NBCFG_DMI_REVERSE

BOARD STACK-UP AND CONSTRUCTION

NBCFG_DMI_X2
NBCFG_DYN_ODT_DISABLE

a
n
i

NBCFG_PEG_REVERSE

MLB STACKUP
LAYER

CONFORMAL_COAT

0.018

L1

0.047

SIGNAL(TOP)

L1-L2
GROUND

U5800

M42A_PGM

L12

TABLE_5_ITEM

U5100

IC,PSOC+W/USB,56P,MLF,CY8C24794

M42A_PGM

TOTAL

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

POST-RAMP-DIMM35

0.07
0.047

0.1
M42

0.018

M42A

1.276

>

PVT-DIMM

0.1

0.014

>

CONFORMAL_COAT

TABLE_5_ITEM

341S1890

SIGNAL(BOTTOM)

TPM

>

IC,SMC,176P BGA,HS8/2116

BETTER-KIONIX
BEST-ST

>

> > >

341S1946

TABLE_5_ITEM

>

M42A_PGM

>

M42A_PGM

U4102

>

U6301

IC,EEPROM,SERIAL IIC,8KBIT,SO8

> > >

IC, 16MBIT 8-PIN SPI SERIAL FLASH,SOIC8

GOOD-KIONIX

0.1

>

341S1797

BEST-KIONIX

>

341S1942

0.1

>

L11-L12

TABLE_5_ITEM

GOOD-ST

BETTER-ST

>

BOM OPTION

FET_STL8NH3LL

---

>

REFERENCE DESIGNATOR(S)

FET_FDN6296

>

DESCRIPTION

GROUND

STANDOFF

>

QTY

---

>

PART#

FANCY

>

P
L11

TABLE_5_HEAD

0.076

NORMAL

>

L10-L11

TABLE_5_ITEM

> >

LEMENU

>

U3301

>

IC,SLG8LP436,CLOCK GEN,68PIN QFN

0.014

>

SIGNAL

>

359S0109

L10

TABLE_5_ITEM

> >

LEMENU

3V3_IND_3MM

---

>

LEMENU

U4101

> >

U4400

IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO

>

IC,FW32306,1394A LINK,BGA,129P

>

338S0270

>

TABLE_5_ITEM

338S0268

0.156

>

BOM OPTION

> >

REFERENCE DESIGNATOR(S)

ONEWIRE_ALWAYSON

>

DESCRIPTION

---

> > >

QTY

0.014

>

L9-L10

TABLE_5_HEAD

PART#

0.076

SIGNAL

>

L9

>

L8-L9

BEST

> > >

U0700

IC,MEROM,CPU B2 DC 2.0GHZ,479 PGA

ONEWIRE_PWRCTL

>

> >

337S3389

>

ONEWIRE_PU_ACOK

e
r

BETTER
TABLE_5_ITEM

0.031

0.014

>

U0700

IC,MEROM,CPU B2 DC 2.0GHZ,479 PGA

GROUND

>

ONEWIRE_PU_PROT

>

337S3389

0.079

m
il

0.031

0.07

>

POWER

L7-L8
L8

0.014

0.076

GOOD
TABLE_5_ITEM

0.014

0.07
POWER

> >

BOM OPTION
TABLE_5_ITEM

U0700

ONEWIRE_PULLUP_OLD

3V3_IND_2MM8

L5-L6

> >

GND

>

L5

ONEWIRE_PULLUP

>

REFERENCE DESIGNATOR(S)

IC,MEROM,CPU B2 DC 1.83GHZ,479 PGA

M42A_PGM

0.079

0.014

>

DESCRIPTION

0.014

0.076

TABLE_5_HEAD

GOOD

>

SIGNAL

L6-L7
QTY

BETTER

0.156

L4-L5

L7

---

BEST

L3-L4

L6

USB_E_OC_PU

0.076
SIGNAL

L4

USB_D_OC_PU

0.1

> >

L3

NO_REBOOT_MODE

>

L2

NBCFG_VCC_1V5

USB_C_OC_PU

0.07

L2-L3

Speed)
Speed)

NBCFG_SDVO_AND_PCIE

TRACE WIDTH
(MM)

> > >

Speed)
Speed)

THICKNESS
(MM)

> > > >

SIGNAL
GROUND
SIGNAL(High
SIGNAL(High
GROUND
POWER
POWER
GROUND
SIGNAL(High
SIGNAL(High
GROUND
SIGNAL

>

y
r

INVERTER_UNBUF

PART#

M42A BEST
ST MICRO
630-7797
EVT

>

1V51V05S0_SKIP

BOM options provided by this page:

337S3387

M42A BETTER
KIONIX
630-7736
EVT

>

(NONE)

M42A GOOD
KIONIX
630-7798
EVT

1V51V05S0_CONT

Signal aliases required by this page:

Top
2
3
4
5
6
7
8
9
10
11
BOTTOM

---

TABLE_5_ITEM

826-4393

LBL,P/N LABEL,PCB,28MMX6MM

EEE:WES

CRITICAL

GOOD-ST

826-4393

LBL,P/N LABEL,PCB,28MMX6MM

EEE:WET

CRITICAL

BETTER-ST

826-4393

LBL,P/N LABEL,PCB,28MMX6MM

EEE:WEW

CRITICAL

BEST-KIONIX

826-4393

LBL,P/N LABEL,PCB,28MMX6MM

EEE:WEV

CRITICAL

GOOD-KIONIX

CONFIGURATION OPTIONS

TABLE_5_ITEM

TABLE_5_ITEM

SYNC_MASTER=SMC

SYNC_DATE=07/18/2005

TABLE_5_ITEM

NOTICE OF PROPRIETARY PROPERTY

TABLE_5_ITEM

826-4393

LBL,P/N LABEL,PCB,28MMX6MM

EEE:W6V

CRITICAL

BETTER-KIONIX

826-4393

LBL,P/N LABEL,PCB,28MMX6MM

EEE:WEU

CRITICAL

BEST-ST

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

TABLE_5_ITEM

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

108

Functional Test Points


Power Supply NO_TESTs

Fan Connectors

NO_TEST
IMVP6_RBIAS
IMVP6_COMP

I93
I94
I95
I96

I101
I102
I103
I104
I106
I105
I107

TRUE
TRUE
TRUE
TRUE
TRUE

5VS5_RUNSS
1V5S0_RUNSS
1V8S3_COMP
1V8S3_FSET
3V3S5_COMP
3V3S5_FSET
1V05S0_COMP
1V05S0_FSET
P3V42G3H_FB

58

I12
I15

59 63

I16
62 63

I157
61

I158
61

I159

I19
I18
I17

I113
I115
I114
I116
I117
I118
I119
I120
I121
I122
I123
I124

I125
I183
I184
I185
I186
I187
I188
I189
I190
I191
I192
I193
I194
I195
I196
I197
I198

CK410_CPU0_N
32 33
CK410_CPU0_P
32 33
CK410_CPU1_N
32 33
CK410_CPU1_P
32 33
CK410_CPU2_ITP_SRC10_N 32 33
CK410_CPU2_ITP_SRC10_P 32 33
CK410_DOT96_27M_N
32 33
CK410_DOT96_27M_P
32 33
CK410_LVDS_N
32 33
CK410_LVDS_P
32 33
CK410_PCI4_CLK_SPN
CK410_PCIF1_CLK
32 33
CK410_SRC1_N_SPN
6
CK410_SRC1_P_SPN
6
CK410_SRC2_N
32 33
CK410_SRC2_P
32 33
CK410_SRC3_N_SPN
6
CK410_SRC3_P_SPN
6
CK410_SRC4_N
32 33
CK410_SRC4_P
32 33
CK410_SRC5_N
32 33
CK410_SRC5_P
32 33
CK410_SRC6_N
32 33
CK410_SRC6_P
32 33
CK410_SRC7_N_SPN
6
CK410_SRC7_P_SPN
6
CK410_SRC8_N
32 33
CK410_SRC8_P
32 33
CK410_SRC_CLKREQ1_L_SPN 6
CK410_SRC_CLKREQ3_L_SPN 6
CK410_SRC_CLKREQ8_L
32 33

I71
I72

I74
I75
I76
I77
I78
I79
I80
I81
I82
I83
I84
I85
I86
I87
I88
I89

I91
I90

NO_TEST
I200
I201

I202
I203
I204
I205
I206
I207
I208

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

FW_B_TPA_N_SPN
FW_B_TPA_P_SPN
FW_B_TPBIAS_SPN
FW_B_TPB_N_SPN
FW_B_TPB_P_SPN
FW_C_TPA_N_SPN
FW_C_TPA_P_SPN
FW_C_TPBIAS_SPN
FW_C_TPB_N_SPN
FW_C_TPB_P_SPN

m
il

e
r

6
6
6
6
6
6
6
6
6
6

LVDS NO_TESTS

NO_TEST
I209
I210
I211
I212
I213
I214
I215

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

LVDS_B_CLK_N_SPN
LVDS_B_CLK_P_SPN
LVDS_B_DATA_N0_SPN
LVDS_B_DATA_N1_SPN
LVDS_B_DATA_N2_SPN
LVDS_B_DATA_P1_SPN
LVDS_B_DATA_P2_SPN

6
6
6
6
6
6
6

ETHERNET NO_TESTS
NO_TEST
I216
I217

I218

TRUE
TRUE
TRUE

ENET_MDI_TRAN_P<2>
ENET_MDI_TRAN_N<2>
ENET_MDI_TRAN_P<3>

I1

51

I3

51

I4

51 64

I2

45 51

I177

45 51

I180

37
37
37

=PP3V42_G3H_LPCPLUS
=PP5V_S0_LPCPLUS

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

LPC_AD<0>
LPC_AD<1>
LPC_FRAME_L
PM_CLKRUN_L
BOOT_LPC_SPI_L
SMC_TMS
DEBUG_RST_L
SMC_TRST_L
SMC_TDO
SMC_MD1
SMC_TX_L
FWH_INIT_L
PCI_CLK_PORT80_LPC
LPC_AD<2>
LPC_AD<3>
INT_SERIRQ
PM_SUS_STAT_L
SMC_TDI
SMC_TCK
SMC_RST_L
SMC_NMI
SMC_RX_L
SV_SET_UP

I10

47 64

I21
I22

21 45 47 53

I24

21 45 47 53

I23

21 45 47 53

I25

23 38 45 47 53

I92

I182

I45

45 46 47

26 47

I29

45 47

I32

45 46 47

I31

45 47

I33

45 46 47

I36

6 21 47

I38

I151

SMBUS_SMC_MLB_SCL

TRUE

SMBUS_SMC_MLB_SDA

21 45 47 53
21 45 47 53

I44

23 45 47 53

I47

23 45 46 47 53

I46

45 46 47

I220

TRUE
TRUE

SMC_FAN_3_TACH
ALS_LEFT

65

Audio FUNC_TEST
PP5V_S0_AUDIO_PWR
TRUE
PP5V_S0_AUDIO
TRUE
GND_AUDIO_PWR
TRUE
GND_AUDIO_CODEC
TRUE

64
64

ACZ_SDATAIN<0>
ACZ_SDATAOUT
ACZ_BITCLK
ACZ_RST_L
ACZ_SYNC

TRUE
TRUE
TRUE
TRUE
TRUE

21 54
21 54
21 54
21 54 57
21 54

Battery FUNC_TEST
SMC_BATT_ISET
TRUE
SMC_BATT_CHG_EN
TRUE
SMC_BC_ACOK
TRUE
SMC_PS_ON
TRUE
SMC_BATT_TRICKLE_EN_L
TRUE
SYS_ONEWIRE
TRUE

45 66
45 46 66
45 46 65 66
39 45 46 65
45 46 66
45 46 65

I48

USB FUNC_TEST
TP_USBP_E
TRUE
TP_USBN_E
TRUE
TP_USBP_F
TRUE
TP_USBN_F
TRUE

6
6

45 46 47
45 46 47
45 47

DC-JACK FUNC_TEST

45 46 47
23 47

I57

62 64

65

PPVBAT_G3H_CHGR_OUT

TRUE

66

INVERTER CONNECTOR FUNC_TEST


I60
I59

27

ACIN_ENABLE_GATE

TRUE

Battery charger FUNC_TEST


I58

I61
I63

PPBUS_ALL_INV_CONN
INV_GND
PP5V_INV_F
INV_BKLIGHT_PWM_L

TRUE
TRUE
TRUE
TRUE

67
67
67
67

27

FIREWIRE FUNC_TEST
I152

TRUE

PPFW_SWITCH

39

SLEEP LED FUNC_TEST


I155

TRUE

SYS_LED_ANODE

35 46

SMC FUNC_TEST
I153
I154
I156

TRUE
TRUE
TRUE

SMC_LID
SMC_MANUAL_RST_L
SMC_CPU_VSENSE

40 45 46 65
46
45 48

Power Supply FUNC_TEST


I160
I161
I162
I163
I164
I165
I169
I166
I167
I168
I170
I174
I171
I172
I173
I175
I176
I179
I178
I181

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

ALL_SYS_PWRGD
PPVCORE_CPU_S0
PP1V05_S0
PP1V5_S0
PP1V8_S0
PP2V5_S0
PP3V3_S0
PP5V_S0
PP1V2_S3
PP1V8_S3
PP2V5_S3
PP3V3_S3
PP5V_S3
PP3V3_S5
PP5V_S5
PP3V42_G3H
PPBUSA_G3H
PPBUSB_G3H
PP18V5_G3H
PP0V9_S0

26 45 63
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64

64
64

FUNC TEST 1 OF 2

64

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

NO_TEST
I219

65

65

33 47

SMBus FUNC_TEST
TRUE

65

22 45 47

FUNC_TEST

=PP1V05_S0_REG

45 46 65

47 64

Other Func Test Points


TRUE

SMC_BS_ALRT_L
SMBUS_BATT_SCL_F
SMBUS_BATT_SDA_F
BATT_IN
BATT_POS
BATT_NEG

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

y
r
I11

TRUE
TRUE

a
n
i
I73

FIREWARE NO_TESTS
I199

51 64

I9

NO_TEST
I112

FUNC_TEST
=PP5V_S0_FAN_RT
FAN_RT_PWM
FAN_RT_TACH
=PP3V3_S0_FAN_RT
SMC_FAN_1_CTL
SMC_FAN_1_TACH

FUNC_TEST

CLOCK NO_TESTS
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

LPC+ Debug Connector


63

I20

I111

Battery Digital Connector

FUNC_TEST
58

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


45 46

II NOT TO REPRODUCE OR COPY IT


45 46

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

108

(EMI PAD FOR INVERTER GONNECTOR)


SPKR-MIC-CLIP-M42

67

ZS0620

INVT_CHGND

NC

1 EMI-SPRING

ZS0621

LVDS ALIASES

SM

NB CFG ALIASES

CLIP-SM-M42

FIREWIRE ALIASES

NO-CONNECT UNUSED LVDS INTERFACE PORTS


NO-CONNECT UNUSED CFG INTERFACE PORTS

LVDS_B_CLK_N
LVDS_B_CLK_P
LVDS_B_DATA_N<0>
LVDS_B_DATA_N<1>
LVDS_B_DATA_N<2>
LVDS_B_DATA_P<0>
LVDS_B_DATA_P<1>
LVDS_B_DATA_P<2>

13

CHASSIS GND

13

BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GND


GND_CHASSIS_IO

13
13

OMIT

Z0606

13

5R2P3-7SQB

=GND_BATT_CHGND
=GND_CHASSIS_AUDIO_JACK
56
=GND_CHASSIS_AUDIO_SPKRCONN
57 =GND_CHASSIS_AUDIO_MIC
=GND_CHASSIS_AUDIO_SHIELD1
=GND_CHASSIS_AUDIO_SHIELD2
=GND_CHASSIS_AUDIO_SHIELD3
28 =GND_CHASSIS_DIPDIMM_LEFT

13

65

13
13

LVDS_B_CLK_N_SPN
LVDS_B_CLK_P_SPN
LVDS_B_DATA_N0_SPN
LVDS_B_DATA_N1_SPN
LVDS_B_DATA_N2_SPN
LVDS_B_DATA_P0_SPN
LVDS_B_DATA_P1_SPN
LVDS_B_DATA_P2_SPN

5
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE

14

NB_CFG<3>

TP_NB_CFG3

14

NB_CFG<4>

TP_NB_CFG4

14

NB_CFG<6>

TP_NB_CFG6

14

NB_CFG<8>

TP_NB_CFG8

14

NB_CFG<10>

TP_NB_CFG10

14

NB_CFG<11>

TP_NB_CFG11

14

NB_CFG<12>

TP_NB_CFG12

14

NB_CFG<13>

TP_NB_CFG13

14

NB_CFG<14>

TP_NB_CFG14

14

NB_CFG<15>

TP_NB_CFG15

14

NB_CFG<17>

TP_NB_CFG17

NO-CONNECT UNUSED FIREWIRE INTERFACE PORTS

13

GND_CHASSIS_SATA

OMIT

35

Z0607

VOLTAGE=0V
MAKE_BASE=TRUE

6P5R2P6-5P5B
1

13
13

38

MAKE_BASE=TRUE

38

MAKE_BASE=TRUE

38

MAKE_BASE=TRUE

38

y
r
38

MAKE_BASE=TRUE

38

MAKE_BASE=TRUE
MAKE_BASE=TRUE

13
13

1
67

C0607

0.1UF

=GND_CHASSIS_LVDS

C0608

13

0.01uF

13

10%
16V
2 CERM
402

10%
16V
2 X5R
402

13
13
13

DCIN CONNECTOR CHASSIS GND

13

OMIT

GND_CHASSIS_DCIN

Z0602

VOLTAGE=0V
MAKE_BASE=TRUE

5R2P3-7SQB

=GND_DCIN_CHGND

65

13
13
13

13

37

=GND_CHASSIS_RJ45

69

=GND_CHASSIS_TMDS_UPPER

C0630

13

0.1UF

13

10%
16V
2 X5R
402

13
13
13
13

I/O CONNECTOR CHASSIS GND

OMIT

GND_CHASSIS_IO

Z0608

13

5P0R2P3-7BLB

13

VOLTAGE=0V
MAKE_BASE=TRUE

=GND_CHASSIS_FW_DOWN
=GND_CHASSIS_USB

39
42

C0610

13
13

C0611

0.1UF

0.01uF

13

10%
16V
402

10%
16V
2 X5R
402

13

13

2 CERM

13
13

DIP DIMM CONNECTOR CHASSIS GND

OMIT

GND_CHASSIS_CENTER
29 28

VOLTAGE=0V
MAKE_BASE=TRUE

=GND_CHASSIS_DIPDIMM_CENTER

C0616

13

5R2P3-7SQB

13

1
1

0.1UF

13

C0617

13

0.01uF

13

10%
16V
2 CERM
402

10%
16V
2 X5R
402

13

Z0610

13
13

13

OMIT

29

13

5R2P3-7SQB

VOLTAGE=0V
MAKE_BASE=TRUE

=GND_CHASSIS_DIPDIMM_RIGHT

13

Z0609

GND_CHASSIS_RIGHT

13

13

C0614

0.1UF

C0615

13

0.01uF

13

10%
16V
402

10%
16V
2 X5R
402

2 CERM

OMIT

Z0601

5R2P3-7SQB
GND_CHASSIS_CPU 1

13
13
13

OMIT

Z0611

5R2P3-7B
GND_CHASSIS_FANSCREW 1

13

P
13
13

13

C0612
0.1UF

10%
16V
2 X5R
402

C0613

10%
16V
402

10%
16V
2 X5R
402

0.01uF

C0618
0.1UF

2 CERM

C0619
0.01uF
10%

16V
2 CERM
402

69

OMIT

DIGITAL GND SCREW HOLE

Z0603

Z0604

STDOFF-4.5OD3.95H-1.1-3.7-TH1
NB_RIGHT_DOWN_SCREW
1

R0612

R0610

STDOFF-4.5OD3.95H-1.1-3.7-TH1
CPU_THERMAL_SCREW_UP

5%
1/16W
MF-LF
2 402

OMIT

5%
1/16W
MF-LF
2 402

OMIT

Z0621
STDOFF-4.5OD3.95H-1.1-3.7-TH1

SATA_A_D2R_N

21

SATA_A_D2R_P

SATA_A_D2R_P_SPN

21

SATA_A_R2D_C_N

SATA_A_R2D_C_N_SPN

MAKE_BASE=TRUE
MAKE_BASE=TRUE
21

a
n
i

SATA_A_R2D_C_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

SATA_A_R2D_C_P_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

PCI_EXP ALIASES

MAKE_BASE=TRUE
MAKE_BASE=TRUE

NO-CONNECT UNUSED PCI_EXP INTERFACE PORTS

MAKE_BASE=TRUE
MAKE_BASE=TRUE
22

PCIE_C_D2R_N

PCIE_C_D2R_N_SPN

22

PCIE_C_D2R_P

PCIE_C_D2R_P_SPN

22

PCIE_C_R2D_C_N

PCIE_C_R2D_C_N_SPN

22

PCIE_C_R2D_C_P

PCIE_C_R2D_C_P_SPN

22

PCIE_D_D2R_N

PCIE_D_D2R_N_SPN

22

PCIE_D_D2R_P

PCIE_D_D2R_P_SPN

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
22

PCIE_D_R2D_C_N

PCIE_D_R2D_C_N_SPN

22

PCIE_D_R2D_C_P

PCIE_D_R2D_C_P_SPN

22

PCIE_E_D2R_N

PCIE_E_D2R_N_SPN

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
22

PCIE_E_D2R_P

PCIE_E_D2R_P_SPN

22

PCIE_E_R2D_C_N

PCIE_E_R2D_C_N_SPN

22

PCIE_E_R2D_C_P

PCIE_E_R2D_C_P_SPN

22

PCIE_F_D2R_N

PCIE_F_D2R_N_SPN

22

PCIE_F_D2R_P

PCIE_F_D2R_P_SPN

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

m
il
MAKE_BASE=TRUE
MAKE_BASE=TRUE

22

PCIE_F_R2D_C_N

PCIE_F_R2D_C_N_SPN

22

PCIE_F_R2D_C_P

PCIE_F_R2D_C_P_SPN

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

EXTAUSB_OC_L

32

CK410_SRC1_N

CK410_SRC1_N_SPN

MAKE_BASE=TRUE

32

CK410_SRC1_P

CK410_SRC1_P_SPN

=USB2_GEYSER_P

USB2_GEYSER_P

40

=USB2_GEYSER_N

USB2_GEYSER_N

MAKE_BASE=TRUE

32

CK410_SRC3_N

MAKE_BASE=TRUE

32

CK410_SRC3_P

MAKE_BASE=TRUE

32

CK410_SRC7_N

32

CK410_SRC7_P

MAKE_BASE=TRUE

32

CK410_SRC_CLKREQ1_L

MAKE_BASE=TRUE

32

CK410_SRC_CLKREQ3_L

MAKE_BASE=TRUE

USB_B_P

22

USB_B_N

22

MAKE_BASE=TRUE

=USB2_EXTB_P

USB2_EXTB_P

42

=USB2_EXTB_N

USB2_EXTB_N

42

=EXTBUSB_OC_L

USB_C_P

22

USB_C_N

22

USB_C_OC_L

22

USB_D_P

22

USB_D_N

22

USB_E_P

22

MAKE_BASE=TRUE
MAKE_BASE=TRUE

EXTBUSB_OC_L
MAKE_BASE=TRUE

USB PORT D = CAMERA

67 =USB2_CAMERA_P

USB2_CAMERA_P

67 =USB2_CAMERA_N

USB2_CAMERA_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB PORT "E" = Unused


5

TP_USBP_E
MAKE_BASE=TRUE

USB_E_N

TP_USBN_E
MAKE_BASE=TRUE

41

22

USB PORT "F" = IR CONTROLLER

=USB2_IR_P

USB_IR_P

USB_F_P
22

=USB2_IR_N

USB_IR_N

MAKE_BASE=TRUE

USB_F_N
22

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB PORT "G" = BLUETOOTH

MAKE_BASE=TRUE

44

=USB2_BT_P

USB_BT_P

44

=USB2_BT_N

USB_BT_N

MAKE_BASE=TRUE

USB_G_P

22

USB_G_N

22

MAKE_BASE=TRUE

USB PORT "H" = PCI-E Mini Card


43

=USB2_AIRPORT_P

USB2_AIRPORT_P

43

=USB2_AIRPORT_N

USB2_AIRPORT_N

MAKE_BASE=TRUE

USB_H_P

22

USB_H_N

22

MAKE_BASE=TRUE

ANALOG SWITCH GPIO


69

=SB_GPIO22

SB_GPIO22

TP_SB_GPIO22

22

MAKE_BASE=TRUE

45 14

PM_EXTTS_L<0>

DIMM_OVERTEMP_L

28 29

MAKE_BASE=TRUE

47 21 5

FWH_INIT_L

SMC_CPU_INIT_3_3_L

45

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

SB ALIASES

NO-CONNECT UNUSED CLOCK INTERFACE PORTS

MAKE_BASE=TRUE
MAKE_BASE=TRUE

23

SUS_CLK_SB

SUS_CLK_SB_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

SO-DIMM ALIASES

VOLTAGE=0V
MAKE_BASE=TRUE

NO-CONNECT UNUSED ADDRESS INTERFACE PORTS


28
28
29
29

MEM_A_A<15>
MEM_A_A<14>
MEM_B_A<15>
MEM_B_A<14>

MEM_A_A15_SPN
MEM_A_A14_SPN
MEM_B_A15_SPN
MEM_B_A14_SPN

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

Ethernet ALIASES
36
36

ENET_CTRL12
ENET_CTRL25

ENET_CTRL12_SPN
ENET_CTRL25_SPN

SIGNAL ALIAS /RESET

MAKE_BASE=TRUE
MAKE_BASE=TRUE

SYNC_MASTER=ENET

SYNC_DATE=08/19/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

TABLE_5_HEAD

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

Z0603,Z0604,Z0605,Z0621

STANDOFF

Z0612

STANDOFF

TABLE_5_ITEM

860-0722

THERMAL STANDOFF

860-0723

STANDOFF WIRELESS

CPU_THERMAL_SCREW_RIGHT 1

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

TABLE_5_ITEM

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


TABLE_5_ITEM

OMIT

OMIT

Z0612

Z0613

STDOFF-4.2OD2.15H-1.2-TH

STDOFF-4.2OD2.15H-1.2-TH

NC

NC

860-0749

STANDOFF W/THRU HOLES,WIRELESS

Z0613

STANDOFF
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

REV.

051-7173
SHT
NONE

22

MAKE_BASE=TRUE

42

MAKE_BASE=TRUE

PART#

5%
1/16W
MF-LF
2 402

22

USB_A_OC_L

USB PORT C = External USB2.0 Port B

MAKE_BASE=TRUE

5
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE
CK410_SRC3_N_SPN
5
MAKE_BASE=TRUE
CK410_SRC3_P_SPN
5
MAKE_BASE=TRUE
CK410_SRC7_N_SPN
5
MAKE_BASE=TRUE
CK410_SRC7_P_SPN
5
MAKE_BASE=TRUE
CK410_SRC_CLKREQ1_L_SPN
5
MAKE_BASE=TRUE
CK410_SRC_CLKREQ3_L_SPN
5
MAKE_BASE=TRUE

22

USB_A_N

MAKE_BASE=TRUE

40

41

MAKE_BASE=TRUE

USB_A_P

MAKE_BASE=TRUE
MAKE_BASE=TRUE

USB PORT B = Trackpad(Geyser)

MAKE_BASE=TRUE

CLOCK ALIASES

MAKE_BASE=TRUE

I393

5%
1/16W
MF-LF
2 402

USB2_EXTA_N

42 =EXTAUSB_OC_L

NO-CONNECT UNUSED CLOCK INTERFACE PORTS

=GND_CHASSIS_FW_UPPER

R0621

USB2_EXTA_P

42 =USB2_EXTA_N

MAKE_BASE=TRUE

R0611

USB PORT A = External USB2.0 Port

42 =USB2_EXTA_P

MAKE_BASE=TRUE
MAKE_BASE=TRUE

NO_TEST=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

GND_CHASSIS_IO1

=GND_CHASSIS_TMDS_DOWN

SATA_A_D2R_N_SPN

OMIT

Z0605
1

21
MAKE_BASE=TRUE

5
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE
5
MAKE_BASE=TRUE

STDOFF-4.5OD3.95H-1.1-3.7-TH1
CPU_THERMAL_SCREW_DOWN

39

NO-CONNECT UNUSED SATA INTERFACE PORTS

MAKE_BASE=TRUE

e
r

13

DIP DIMM CONNECTOR CHASSIS GND

MAKE_BASE=TRUE
MAKE_BASE=TRUE

NC_FWPWR_PWRON

38

MAKE_BASE=TRUE

SATA ALIASES

PEG_D2R_N0_SPN
PEG_D2R_N2_SPN
PEG_D2R_N3_SPN
PEG_D2R_N4_SPN
PEG_D2R_N5_SPN
PEG_D2R_N6_SPN
PEG_D2R_N7_SPN
PEG_D2R_N8_SPN
PEG_D2R_N9_SPN
PEG_D2R_N10_SPN
PEG_D2R_N11_SPN
PEG_D2R_N12_SPN
PEG_D2R_N13_SPN
PEG_D2R_N14_SPN
PEG_D2R_N15_SPN
PEG_D2R_P0_SPN
PEG_D2R_P2_SPN
PEG_D2R_P3_SPN
PEG_D2R_P4_SPN
PEG_D2R_P5_SPN
PEG_D2R_P6_SPN
PEG_D2R_P7_SPN
PEG_D2R_P8_SPN
PEG_D2R_P9_SPN
PEG_D2R_P10_SPN
PEG_D2R_P11_SPN
PEG_D2R_P12_SPN
PEG_D2R_P13_SPN
PEG_D2R_P14_SPN
PEG_D2R_P15_SPN
PEG_R2D_C_N4_SPN
PEG_R2D_C_N5_SPN
PEG_R2D_C_N6_SPN
PEG_R2D_C_N7_SPN
PEG_R2D_C_N8_SPN
PEG_R2D_C_N9_SPN
PEG_R2D_C_N10_SPN
PEG_R2D_C_N11_SPN
PEG_R2D_C_N12_SPN
PEG_R2D_C_N13_SPN
PEG_R2D_C_N14_SPN
PEG_R2D_C_N15_SPN
PEG_R2D_C_P4_SPN
PEG_R2D_C_P5_SPN
PEG_R2D_C_P6_SPN
PEG_R2D_C_P7_SPN
PEG_R2D_C_P8_SPN
PEG_R2D_C_P9_SPN
PEG_R2D_C_P10_SPN
PEG_R2D_C_P11_SPN
PEG_R2D_C_P12_SPN
PEG_R2D_C_P13_SPN
PEG_R2D_C_P14_SPN
PEG_R2D_C_P15_SPN

=FWPWR_PWRON

MAKE_BASE=TRUE

NO-CONNECT UNUSED SDVO INTERFACE PORTS

PEG_D2R_N<0>
PEG_D2R_N<2>
PEG_D2R_N<3>
PEG_D2R_N<4>
PEG_D2R_N<5>
PEG_D2R_N<6>
PEG_D2R_N<7>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_N<10>
PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>
PEG_D2R_N<14>
PEG_D2R_N<15>
PEG_D2R_P<0>
PEG_D2R_P<2>
PEG_D2R_P<3>
PEG_D2R_P<4>
PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_P<7>
PEG_D2R_P<8>
PEG_D2R_P<9>
PEG_D2R_P<10>
PEG_D2R_P<11>
PEG_D2R_P<12>
PEG_D2R_P<13>
PEG_D2R_P<14>
PEG_D2R_P<15>
PEG_R2D_C_N<4>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>
PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>
PEG_R2D_C_P<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>

39

38

PCI_EXPRESS GRAPHICS ALIASES


13

FW_B_TPBIAS_SPN
FW_B_TPA_P_SPN
FW_B_TPA_N_SPN
FW_B_TPB_P_SPN
FW_B_TPB_N_SPN
FW_C_TPBIAS_SPN
FW_C_TPA_P_SPN
FW_C_TPA_N_SPN
FW_C_TPB_P_SPN
FW_C_TPB_N_SPN

38

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SATA,LVDS CONNECTOR CHASSIS GND

38

FW_B_TPBIAS
FW_B_TPA_P
FW_B_TPA_N
FW_B_TPB_P
FW_B_TPB_N
FW_C_TPBIAS
FW_C_TPA_P
FW_C_TPA_N
FW_C_TPB_P
FW_C_TPB_N

MAKE_BASE=TRUE

C
OF

108

OMIT

U0700

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12
12

IO

12

IO

12

IO

12

IO

12
12

IO
IO

12

IO

12

IO

12

IO

12
12
12
12
12
12
12
12
12

IO

12
12

IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

21

IN

21

OUT

21

IN

21
21

IN
IN

21

IN

21

IN

J1 A9*
N3 A10*
P5 A11*
P2 A12*
L1 A13*
P4 A14*
P1 A15*
R1 A16*
L2 ADSTB0*

FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>

BPRI*
DEFER*

H5

12

F21

12

E1

12

FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L

F1

12

FSB_BREQ0_L

IO

INIT*

D20
B3

21

FSB_IERR_L
CPU_INIT_L

IN

LOCK*

H4

12

FSB_LOCK_L

IO

RESET*
RS0*

B1

12 11

F3
F4

12

G3

12

G2

12

G6
E4

12

AD4
AD3

11

AD1
AC4

11

AC2

11

AC1
AC5

11
11 7

AA6

11 7

AB3
AB5

11
11 7

AB6

11

C20

26 11

DRDY*
DBSY*
BR0*
IERR*

RS1*
RS2*
TRDY*

K3 REQ0*
H2 REQ1*
K2 REQ2*
J3 REQ3*

HIT*
HITM*

12

12

12

FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L
FSB_HIT_L
FSB_HITM_L

U2 A23*
R4 A24*
T5 A25*
T3 A26*
W3 A27*
W5 A28*
Y4 A29*
W2 A30*
Y1 A31*
V4 ADSTB1*

CPU_A20M_L
CPU_FERR_L
CPU_IGNNE_L

A6 A20M*
A5 FERR*
C4 IGNNE*

CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L

D5 STPCLK*
C6 LINT0
B4 LINT1
A3 SMI*

TP_CPU_A32_L
TP_CPU_A33_L
TP_CPU_A34_L
TP_CPU_A35_L
TP_CPU_A36_L
TP_CPU_A37_L
TP_CPU_A38_L
TP_CPU_A39_L
TP_CPU_APM0_L
TP_CPU_APM1_L

AA1 RSVD1
AA4 RSVD2
AB2 RSVD3
AA3 RSVD4
M4 RSVD5
N5 RSVD6
T2 RSVD7
V3 RSVD8
B2 RSVD9
C3 RSVD10

TP_CPU_HFPLL

B25 RSVD11

BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*
TCK
TDI
TDO
TMS
TRST*
DBR*

11

11

58 46

THERMDA

D21
A24

THERMDC

A25

10

PROCHOT*

THERMTRIP*

BCLK0
BCLK1

RSVD12

RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

C7

10

46 21 14

A22

33

A21

33

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
CPU_PROCHOT_L
CPU_THERMD_P
CPU_THERMD_N
PM_THRMTRIP_L

FSB_CLK_CPU_P
FSB_CLK_CPU_N

TP_CPU_SPARE0
TP_CPU_SPARE1
TP_CPU_SPARE2
TP_CPU_SPARE3
TP_CPU_SPARE4
TP_CPU_SPARE5
TP_CPU_SPARE6
TP_CPU_SPARE7

D2
F6
D3
C1
AF1
D22
C23
C24

54.9 2
1%
402

R0721
11 7

XDP_TDI

54.9 2
1%
402

R0722
11 7

XDP_TCK

54.9 2
1%
402

1%
1/16W
MF-LF
2 402

IO
IO

PLACE TESTPOINT ON
FSB_IERR_L WITH A GND
0.1" AWAY

y
r

IN
IN
IN
IN

=PP1V05_S0_CPU

IN

7 8 9 11 64

IO
IO

R0703

IO
IO
IO

54.9

OMIT

1%
1/16W
MF-LF
2 402

a
n
i
U0700

IO
IO
IO
IN
IN

R0704

OUT

5%
1/16W
MF-LF
2 402

IN
IN

12

IO

12

IO

12

IO

12

IO

12

68

OUT

OUT
OUT

CPU_PROCHOT_L TO SMC
AND CPU VR TO INFORM
CPU IS HOT

OUT
OUT

PM_THRMTRIP#
SHOULD CONNECT TO
ICH7-M AND GMCH
WITHOUT T-ING (NO
STUB)

IN
IN

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTBN_L<0>
FSB_DSTBP_L<0>
FSB_DINV_L<0>

m
il
12

IO

12

IO

12

SPARE[7-0],HFPLL:
ROUTE TO TP VIA AND
PLACE GND VIA W/IN 1000 MILS

e
r

7 8 9 11 64

R0720
XDP_TMS

54.9

IO

TP_CPU_EXTBREF

T22

=PP1V05_S0_CPU

11 7

R0702

IO

Y2 A17*
U5 A18*
R3 A19*
W6 A20*
U4 A21*
Y5 A22*

IO

L5 REQ4*

FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_ADSTB_L<1>

7 8 9 11 64

IO

64 11 9 8 7

=PP1V05_S0_CPU

R0705
1K

1%
1/16W
MF-LF
2 402

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

R0706
2.0K

1%
1/16W
MF-LF
2 402

OUT 33
OUT 33
33

E25 D6*
E23 D7*
K24 D8*

G24 D9*
J24 D10*
J23 D11*

H26 D12*
F26 D13*
K22 D14*
H25 D15*
H23 DSTBN0*

D32*
D33*

BGA

(2 OF 4)

D34*
D35*
D36*
D37*
D38*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*

DINV2*

N22 D16*
K25 D17*
P26 D18*
R23 D19*

D48*

L25 D20*
L22 D21*
L23 D22*

D52*
D53*

M23 D23*
P25 D24*
P22 D25*
P23 D26*
T24 D27*
R24 D28*

D49*
D50*
D51*

L26 D29*
T25 D30*
N24 D31*

CPU_TEST1

C26 TEST1

CPU_TEST2

D25 TEST2
B22 BSEL0
B23 BSEL1
C21 BSEL2

D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*

D63*
DSTBN3*

M24 DSTBN1*
N25 DSTBP1*
M26 DINV1*

CPU_BSEL<0>
CPU_BSEL<1>
CPU_BSEL<2>

D39*

DSTBN2*
DSTBP2*

G22 DSTBP0*
J26 DINV0*

AD26 GTLREF
A2 NC

LAYOUT NOTE: 0.5" MAX LENGTH

YONAH
CPU

H22 D3*
F23 D4*
G25 D5*

FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTBN_L<1>
FSB_DSTBP_L<1>
FSB_DINV_L<1>

CPU_GTLREF

OUT

IO

12

E22 D0*
F24 D1*
E26 D2*

DATA GRP2

IO

12

DATA GRP3

IO

12

=PP1V05_S0_CPU

12

DATA GRP0

IO

12

BGA

FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L

H1
E2
G5

ADS*
BNR*

DATA GRP1

12

(1 OF 4)

CONTROL

IO

K5 A6*
M1 A7*
N2 A8*

XDP/ITP SIGNALS

IO

THERM

IO

12

YONAH
CPU

HCLK

12

12

J4 A3*
L4 A4*
M3 A5*

ADDR GROUP0

IO

FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_ADSTB_L<0>

ADDR GROUP1

IO

12

RESERVED

12

DSTBP3*
DINV3*

MISC

402
1

R0712
51

5%
1/16W
MF-LF
2 402

12

V26

12

W25
U23

12

U25

12

U22
AB25

12

W22
Y23

12

AA26

12

Y26
Y22

12

AC26

12

AA24
W24

12

Y25

12

V23

12

AC22
AC23

12

AB22
AA21

12

AB21

12

AC25
AD20

12

AE22

12

AF23
AD24

12

AE21

12

AD21
AE25

12

AF25
AF22

12

AF26

12

AD23
AE24

12

AC20

12

R26

COMP1

U26
U1

DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*

R0730

12

AB24
V24

COMP0
COMP2
COMP3

NOSTUFF

AA23

12

12

12

12

12

12

12

12

12

12

12

12

12

FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTBN_L<3>
FSB_DSTBP_L<3>
FSB_DINV_L<3>

IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

58 21
21

D24

12

D6
D7

21

AE6

58

12

CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_SLPCPU_L
CPU_PSI_L

IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

LAYOUT NOTE:
COMP0,2 CONNECT WITH
TRACE LENGTH SHORTER
COMP1,3 CONNECT WITH
TRACE LENGTH SHORTER

IO
IO
IO
IO

ZO=27.4OHM, MAKE
THAN 0.5".
ZO=55OHM, MAKE
THAN 0.5".

IO
IO

R0716

IO

IO
IO

27.4 2
402

R0717

IO

IO

54.9 2
1%

IO

402

R0718

IO

CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<2>
CPU_COMP<3>

V1
E5
B5

FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTBN_L<2>
FSB_DSTBP_L<2>
FSB_DINV_L<2>

27.4 2

R0719
1

54.9 2
1%
402

IN
IN
IN
IN
IN
IN

NOSTUFF
1

R0707
1K

5%
1/16W
MF-LF
2 402

CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9

CPU 1 OF 2-FSB

WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50


SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM
TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)

SYNC_MASTER=MASTER

SYNC_DATE=05/03/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

108

OMIT
A4 VSS_1
A8 VSS_2
A11 VSS_3

=PPVCORE_S0_CPU
OMIT
A7 VCC_1
A9 VCC_2
A10 VCC_3

A12 VCC_4
A13 VCC_5
A15 VCC_6

BGA
(3 OF 4)

B7 VCC_10
B9 VCC_11
B10 VCC_12

VCC_77 AD7
VCC_78 AD9
VCC_79 AD10

B12 VCC_13
B14 VCC_14
B15 VCC_15

VCC_80 AD12
VCC_81 AD14

C15 VCC_23
C17 VCC_24
C18 VCC_25
D9 VCC_26
D10 VCC_27
D12 VCC_28
D14 VCC_29

VCC_85 AE9
VCC_86 AE10
VCC_87 AE12

VCC_91 AE18
VCC_92 AE20
VCC_93 AF9
VCC_94 AF10
VCC_95 AF12
VCC_96 AF14
VCC_97 AF15
VCC_98 AF17

E9 VCC_34
E10 VCC_35
E12 VCC_36

VCCP_1 V6
VCCP_2 G21

E13 VCC_37
E15 VCC_38
E17 VCC_39

VCCP_3 J6
VCCP_4 K6
VCCP_5 M6

E18 VCC_40
E20 VCC_41
F7 VCC_42

VCCP_6 J21
VCCP_7 K21
VCCP_8 M21

F9 VCC_43
F10 VCC_44
F12 VCC_45

VCCP_9 N21
VCCP_10 N6
VCCP_11 R21

F14 VCC_46
F15 VCC_47
F17 VCC_48

VCCP_12 R6
VCCP_13 T21

AA9 VCC_52
AA10 VCC_53
AA12 VCC_54
AA13 VCC_55
AA15 VCC_56
AA17 VCC_57
AA18 VCC_58
AA20 VCC_59
AB9 VCC_60
AC10 VCC_61

=PP1V05_S0_CPU

9 64

(CPU INTERNAL PLL POWER 1.5V)


VID0 AD6
VID1 AF5
VID2 AE5
VID3 AF4
VID4 AE3
VID5 AF2
VID6 AE2

CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>

OUT

OUT

OUT

OUT

OUT

OUT

OUT

e
r

VID FOR CPU POWER SUPPLY


IF NO USE, NEED PULL-UP OR
PULL-DOWN

=PPVCORE_S0_CPU
1

R0802
100

1%
1/16W
MF-LF

AB10 VCC_62
AB12 VCC_63
AB14 VCC_64
AB15 VCC_65
AB17 VCC_66
AB18 VCC_67

m
il

VCCA=1.5 ONLY

=PP1V5_S0_CPU

2 402

VCCSENSE AF7

CPU_VCCSENSE_P

VSSSENSE AE7

CPU_VCCSENSE_N

R0803

LAYOUT NOTE: CONNECT R0803


TO TP_VSSSENSE WITH NO
STUB.

100

1%
1/16W
MF-LF
2 402

LAYOUT NOTE:
VCCSENSE AND VSSSENSE LINES
SHOULD BE OF EQUAL LENGTH

VSS_87 R22
VSS_88 R25
VSS_89 T1
VSS_90 T4
VSS_91 T23
VSS_92 T26
VSS_93 U3
VSS_94 U6
VSS_95 U21

B21 VSS_15
B24 VSS_16
C5 VSS_17

VSS_96 U24
VSS_97 V2

y
r

VSS_98 V5
VSS_99 V22
VSS_100 V25
VSS_101 W1
VSS_102 W4
VSS_103 W23

C2 VSS_23
C22 VSS_24
C25 VSS_25
D1 VSS_26
D4 VSS_27

VSS_104 W26
VSS_105 Y3
VSS_106 Y6

D8 VSS_28
D11 VSS_29
D13 VSS_30

VSS_109 AA2
VSS_110 AA5
VSS_111 AA8

D16 VSS_31
D19 VSS_32
D23 VSS_33

VSS_112 AA11
VSS_113 AA14
VSS_114 AA16

D26 VSS_34
E3 VSS_35
E6 VSS_36

VSS_115 AA19
VSS_116 AA22
VSS_117 AA25

E8 VSS_37
E11 VSS_38
E14 VSS_39

VSS_118 AB1
VSS_119 AB4

E16 VSS_40
E19 VSS_41
E21 VSS_42
E24 VSS_43
F5 VSS_44

7 9 11 64

(CPU IO POWER 1.05V)

VCCP_14 T6
VCCP_15 V21
VCCP_16 W21

VCCA B26

BGA
(4 OF 4)

P6

P21
VSS_84 P24
VSS_85 R2
VSS_86 R5

a
n
i

VCC_88 AE13
VCC_89 AE15
VCC_90 AE17

VCC_99 AF18
VCC_100 AF20

YONAH
CPU

B13 VSS_12
B16 VSS_13
B19 VSS_14

C8 VSS_18
C11 VSS_19
C14 VSS_20
C16 VSS_21
C19 VSS_22

VCC_82 AD15
VCC_83 AD17
VCC_84 AD18

D15 VCC_30
D17 VCC_31
D18 VCC_32
E7 VCC_33

F18 VCC_49
F20 VCC_50
AA7 VCC_51

A23 VSS_7
A26 VSS_8
B6 VSS_9
B8 VSS_10
B11 VSS_11

VCC_71 AC9
VCC_72 AC12
VCC_73 AC13
VCC_74 AC15
VCC_75 AC17
VCC_76 AC18

C9 VCC_19
C10 VCC_20
C12 VCC_21
C13 VCC_22

YONAH
CPU

VCC_68 AB20
VCC_69 AB7
VCC_70 AC7

A17 VCC_7
A18 VCC_8
A20 VCC_9

B17 VCC_16
B18 VCC_17
B20 VCC_18

U0700

A14 VSS_4
A16 VSS_5
A19 VSS_6

8 9 48 64

(CPU CORE POWER)

U0700 VSS_82
VSS_83

LAYOUT NOTE:
CPU_VCCSENSE_P/CPU_VCCSENSE_N USE
ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.

OUT

58

OUT

58

8 9 48 64

VSS_123 AB16
VSS_124 AB19
VSS_125 AB23
VSS_126 AB26
VSS_127 AC3
VSS_128 AC6

F2 VSS_50
F22 VSS_51
F25 VSS_52

VSS_131 AC14
VSS_132 AC16
VSS_133 AC19

G4 VSS_53
G1 VSS_54
G23 VSS_55

VSS_134 AC21
VSS_135 AC24
VSS_136 AD2

G26 VSS_56
H3 VSS_57
H6 VSS_58

VSS_137 AD5
VSS_138 AD8
VSS_139 AD11

H21 VSS_59
H24 VSS_60
J2 VSS_61

VSS_140 AD13
VSS_141 AD16

J5 VSS_62
J22 VSS_63
J25 VSS_64
K1 VSS_65
K4 VSS_66

VSS_129 AC8
VSS_130 AC11

VSS_142 AD19
VSS_143 AD22
VSS_144 AD25

VSS_145 AE1
VSS_146 AE4
VSS_147 AE8

K23 VSS_67
K26 VSS_68
L3 VSS_69

VSS_148 AE11
VSS_149 AE14
VSS_150 AE16

L6 VSS_70
L21 VSS_71
L24 VSS_72

VSS_151 AE19
VSS_152 AE23

N4 VSS_78
N23 VSS_79
N26 VSS_80
P3 VSS_81

VSS_120 AB8
VSS_121 AB11
VSS_122 AB13

F8 VSS_45
F11 VSS_46
F13 VSS_47
F16 VSS_48
F19 VSS_49

M2 VSS_73
M5 VSS_74
M22 VSS_75
M25 VSS_76
N1 VSS_77

LAYOUT NOTE:
PROVIDE A TEST POINT (WITH NO STUB)
TO CONNECT A DIFFERENCTIAL PROBE
BETWEEN VCCSENSE AND VSSSENSE AT THE
LOCATION WHERE THE TWO 54.9 OHM
RESISTORS TERMINATE THE 55 OHM
TRANSMISSION LINE

VSS_107 Y21
VSS_108 Y24

VSS_153 AE26
VSS_154 AF3
VSS_155 AF6
VSS_156 AF8
VSS_157 AF11
VSS_158 AF13
VSS_159 AF16
VSS_160 AF19
VSS_161 AF21
VSS_162 AF24

CPU 2 OF 2-PWR/GND
SYNC_MASTER=MASTER

SYNC_DATE=05/03/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

108

CPU CORE VID<> SETTINGS


VCCA DECOUPLING

(CPU INTERNAL PLL POWER 1.5V)


64 8

y
r

=PP1V5_S0_CPU

C0950 1

0.01uF

C0951
10UF

10%
16V
CERM 2
402

20%
2 6.3V
X5R
603

ALTERNATE FOR
PART NUMBER

BOM OPTION

138S0603

138S0602

REF DES

COMMENTS:

USE SAMSUNG AND MURATA ONLY


TABLE_ALT_ITEM

138S0606

138S0602

ALL

USE TAIYO

VCCP CORE DECOUPLING

m
il

64 11 8 7

C0926

C0934
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

CRITICAL

=PPVCORE_S0_CPU
1

PLACE NEAR THE CPU


ON BOTTOM SIDE

e
r

CRITICAL

C0923
C0911
C0910
C0908
22UF
22UF
22UF
22UF
20%
6.3V
2 CERM-X5R
805

CRITICAL

CRITICAL

CRITICAL

20%
6.3V
2 CERM-X5R
805

(10 PCS ON NORTH SIDE


10 PCS ON SOUTH SIDE)

CRITICAL

20%
6.3V
2 CERM-X5R
805

20%
6.3V
2 CERM-X5R
805

CRITICAL

CRITICAL

1 C0918 1 C0913 1 C0912


C0924
22UF
22UF
22UF
22UF

20%
2 6.3V
CERM-X5R
805

20%
2 6.3V
CERM-X5R
805

20%
2 6.3V
CERM-X5R
805

20%
2 6.3V
CERM-X5R
805

CRITICAL

C0901
22UF

20%
6.3V
2 CERM-X5R
805

CRITICAL

C0904
22UF

20%
2 6.3V
CERM-X5R
805

C0928
22UF

20%
6.3V
2 CERM-X5R
805

CRITICAL

C0930
22UF

20%
2 6.3V
CERM-X5R
805

20%
2 2.5V
TANT
D2T

CRITICAL

CRITICAL

CRITICAL

20%
6.3V
2 CERM-X5R
805

20%
6.3V
2 CERM-X5R
805

20%
6.3V
2 CERM-X5R
805

CRITICAL

CRITICAL

CRITICAL

CRITICAL

1 C0931 1 C0939 1 C0920


C0902
22UF
22UF
22UF
22UF

20%
2 6.3V
CERM-X5R
805

20%
2 6.3V
CERM-X5R
805

20%
2 6.3V
CERM-X5R
805

(2 PCS ON NORTH SIDE


2 PCS ON SOUTH SIDE)

NOSTUFF
CRITICAL
1

CRITICAL
1

C0941

470UF-8MOHM

20%
3 2 2.5V
POLY
D2T

C0942

470UF-8MOHM

20%
2 2.5V
POLY
D2T

CRITICAL
1

470UF-8MOHM

20%
3 2 2.5V
POLY
D2T

20%
2 2.5V
POLY
D2T

IN

CPU_VID<3>

IN

CPU_VID<2>

IN

CPU_VID<1>

IN

CPU_VID<0>

DUAL CORE
SV CPU

MIN
VCCHFM 1.1625
VCCLFM TBD

SINGLE CORE
SV CPU

VCCHFM 1.1625
VCCLFM

DUAL CORE
LV CPU

VCCHFM
VCCLFM

1.0

ULV CPU

VCCHFM
VCCLFM

TBD

TYP

CPU_VID_R<6>

OUT

58

CPU_VID_R<5>

OUT

58

CPU_VID_R<4>

OUT

58

CPU_VID_R<3>

OUT

58

CPU_VID_R<2>

OUT

58

CPU_VID_R<1>

OUT

58

CPU_VID_R<0>

OUT

MAX
1.30
TBD

1.30
TBD
1.1625
TBD
TBD
TBD

UNIT: V

# ALL PROCESSOR DEFAULT VCORE FOR INITIAL POWER UP IS 1.2V


# TWO PROCESSORS AT THE SAME FREQUENCY MAY HAVE DIFFERENT SETTING
WITH THE VID RANGE(VCORE VOLTAGE)!
# REFER TO YONAH PROCESSOR EMTS REV 1.0
CPU DECAPS & VID<>
# VCCHFM: VCORE AT HIGHEST FREQUENCY MODE
# VCCLFM: VCORE AT LOWEST FREQUENCY MODE

C0946

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

470UF-8MOHM

II NOT TO REPRODUCE OR COPY IT

20%
2 2.5V
POLY
D2T

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7173

SCALE

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

CRITICAL
1

C0944

470UF-8MOHM

CPU_VID<4>

58

NOTICE OF PROPRIETARY PROPERTY

CRITICAL
1

C0943

IN

2
0
MF-LF402
2
0
MF-LF402
2
0
MF-LF402
2
0
MF-LF402
2
0
MF-LF402
2
0
MF-LF402
2
0
MF-LF402

20%
2 6.3V
CERM-X5R
805

IF WE USE LOW ESL CAP,THEN WE CAN USE 20 PCS 22UF CAP

R0921
1
5% 1/16W
R0922
1
5% 1/16W
R0923
1
5% 1/16W
R0924
1
5% 1/16W
R0925
1
5% 1/16W
R0926
1
5% 1/16W
R0927
1
5% 1/16W

CRITICAL

C0900
C0909
C0907
C0929
22UF
22UF
22UF
22UF
1

20%
6.3V
2 CERM-X5R
805

CRITICAL

C0940
470UF

VCC (CPU
CORE
DECOUPLING
CORE POWER)
64 48 8

CRITICAL

1 C0936 1 C0937 1 C0938


C0935
0.1UF
0.1UF
0.1UF
0.1UF

20%
2 10V
CERM
402

CPU_VID<5>

THIS 470UF FOR CPU,GMCH FSB BUS 1.05V

(CPU IO POWER 1.05V)


=PP1V05_S0_CPU
1
PLACE NEAR THE NORTH BRIDGE
0.1UF
ON BOTTOM SIDE
20%
2 10V
CERM
402

CPU_VID<6>

IN

R0921~R0927 FOR CPU VOLTAGE MANUAL SETTING

TABLE_ALT_ITEM

ALL

IN

a
n
i

TABLE_ALT_HEAD

PART NUMBER

C
OF

108

y
r

a
n
i

CPU ZONE THERMAL SENSOR

64 49 =PP3V3_S0_THRM_SNR

C
LAYOUT NOTE:

LAYOUT NOTE:

ADD GND GUARD TRACE

ROUTE CPU_THERMD_P AND

FOR CPU_THERMD_P AND

CPU_THERMD_N ON SAME

CPU_THERMD_N

LAYER.

C1002
0.1UF

PLACEHOLDER ADT7461A

10 MIL TRACE
10 MIL SPACING

CRITICAL

10%
16V
X5R
402

ALERT*/
THM2*

R1001
OUT

CPU_THERMD_P

499
1

THRM_CPU_DX_P
THRM_CPU_DX_N

2
1%
1/16W
MF-LF
402

C1001
0.001uF

R1002
7

CPU_THERMD_N

499

10%
50V
CERM
402

1%
1/16W
MF-LF
402

U1001

THM*

THRM_ALERT_L

THRM_ALERT

ADT7461

SCLK
SDATA

8
7

GND
5

e
r

D+
D-

MSOP

(TO CPU INTERNAL THERMAL DIODE)

IN

R1006

10K

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

m
il
VDD

R1005

27
27

SMB_THRM_CLK
SMB_THRM_DATA

IO
IO

PLACE U1001 NEAR THE U1200

CPU MISC1-TEMP SENSOR


SYNC_MASTER=ENET

SYNC_DATE=08/19/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

10

108

y
r

a
n
i

CPU ITP700FLEX DEBUG SUPPORT

64 11 9 8 7

=PP1V05_S0_CPU
1

R1101 1R1103

m
il
54.9

1%
1/16W
MF-LF
2 402

54.9

1%
1/16W
MF-LF
2 402
ITP

R1102

IN

XDP_TDO

ITP

R1100

12 7

IN

FSB_CPURST_L

22.6 2
1%
1/16W
MF-LF
402

(FROM CK410M HOST 133/167MHZ)

22.6 2
1%
1/16W
MF-LF
402

e
r
64 26 23

(AND WITH RESET BUTTON)

=PP3V3_S5_SB_PM

R1104
240

5%
1/16W
MF-LF
2 402

OUT

26 7

OUT
OUT

J1102
F-ST-5047
SM1

XDP_TDI

XDP_TRST_L

10

11 7

11

12

XDP_BPM_L<5>

13

14

ITPRESET_L

15

16

XDP_BPM_L<4>

XDP_BPM_L<3>

17

18

19

20

21

22

23

24

25

26

27

28

29

30

XDP_TCK
ITP_TDO

(TCK)

CPU_XDP_CLK_N
CPU_XDP_CLK_P

IN

33 IN

IO

ITP

CRITICAL

OUT

33

64 11 9 8 7

=PP1V05_S0_CPU

XDP_TMS

OUT

NC
NC

XDP_TCK

(FBO)
OUT
IO

IO

XDP_BPM_L<2>

IO

XDP_BPM_L<1>

IO

XDP_BPM_L<0>

IO

ITP
1

C1100

0.1UF

10%
2 16V
X5R
402

516S0416

XDP_DBRESET_L

(DBA#)

INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.

(DEBUG PORT ACTIVE)


(DBR#) TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC
(DEBUG PORT RESET)

R1106

ITP TCK SIGNAL LAYOUT NOTE:


ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTORS TCK PIN TO CPUS
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX
CONNECTORS FBO PIN.

680
5%
1/16W
MF-LF
2 402

CPU ITP700FLEX DEBUG


SYNC_MASTER=MASTER

SYNC_DATE=5/23/05

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

11

108

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO

IO
IO

IO

IO

IO

IO

1%
1/16W
MF-LF
402

R1221

24.9

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

64 33 19 12

54.9
1%
1/16W
MF-LF
402

100

=PP1V05_S0_FSB_NB

R1230

R1226

C1226
0.1uF

1%
1/16W
MF-LF
402

10%
16V
X5R
402

R1235
221

A
R1231

24.9
1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

R1236

100

1%
1/16W
MF-LF
402

IO
IO

IO

IO

IO

IO

IO

IO

IO

IO

F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3

IO

IO

IO

IO

IO

IO

IO

IO

Y3
Y7
W5

Y10
AB8
W2

AA4
AA7
AA2
AA6

AA10
Y8

AA1
AB4
AC9

AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5

AD10
AD4
AC8

NB_FSB_XRCOMP
NB_FSB_XSCOMP
NB_FSB_XSWING

E1
E2
E4

NB_FSB_YRCOMP
NB_FSB_YSCOMP
NB_FSB_YSWING

33

IN

33

IN

HD0*
HD1*
HD2*
HD3*
HD4*
HD5*
HD6*
HD7*
HD8*
HD9*
HD10*
HD11*
HD12*
HD13*
HD14*
HD15*
HD16*
HD17*
HD18*
HD19*
HD20*
HD21*
HD22*
HD23*
HD24*
HD25*
HD26*
HD27*
HD28*
HD29*
HD30*
HD31*
HD32*
HD33*
HD34*
HD35*
HD36*
HD37*
HD38*
HD39*
HD40*
HD41*
HD42*
HD43*
HD44*
HD45*
HD46*
HD47*
HD48*
HD49*
HD50*
HD51*
HD52*
HD53*
HD54*
HD55*
HD56*
HD57*
HD58*
HD59*
HD60*
HD61*
HD62*
HD63*

LEMENU

U1200
945GM
NB
BGA

(1 OF 10)

HA3*
HA4*
HA5*
HA6*
HA7*
HA8*
HA9*
HA10*
HA11*
HA12*
HA13*
HA14*
HA15*
HA16*
HA17*
HA18*
HA19*
HA20*
HA21*
HA22*
HA23*
HA24*
HA25*
HA26*
HA27*
HA28*
HA29*
HA30*
HA31*

H9

C9

E11

G11

F11

G12

F9

H11

J12

G14

D9

J14

H13

J15

F14

D12

A11

C11

A12

A13

E13

G13

F12

B12

B14

C12

A14

C14

D14

FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>

HADS*
HADSTB0*
HADSTB1*
HAVREF
HBNR*
HBPRI*
HBREQ0*
HCPURST*
HDBSY*
HDEFER*
HDPWR*
HDRDY*
HDVREF

E8

B9

C13

Y1
U1
W1

FSB_CLK_NB_P
FSB_CLK_NB_N

AG2
AG1

HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
HCLKIN
HCLKIN*

IO
IO

y
r

IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

a
n
i

HDINV0*
HDINV1*
HDINV2*
HDINV3*

J7

W8

U3

AB10

HDSTBN0*
HDSTBN1*
HDSTBN2*
HDSTBN3*

K4

T7

Y5

AC4

HDSTBP0*
HDSTBP1*
HDSTBP2*
HDTSBP3*

K3

T6

AA5

AC5

HHIT*
HHITM*
HLOCK*

D3

D4

B3

HREQ0*
HREQ1*
HREQ2*
HREQ3*
HREQ4*

D8

G8

B8

F8

A8

HRS0*
HRS1*
HRS2*

B4

E6

D6

HSLPCPU*
HTRDY*

E3

E7

J13
C6

F6

C7

FSB_ADS_L
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
NB_FSB_VREF
FSB_BNR_L
FSB_BPRI_L
FSB_BREQ0_L
FSB_CPURST_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DPWR_L
FSB_DRDY_L

B7

A7

C3

J9

H8

K13

FSB_DINV_L<0>
FSB_DINV_L<1>
FSB_DINV_L<2>
FSB_DINV_L<3>

FSB_DSTBN_L<0>
FSB_DSTBN_L<1>
FSB_DSTBN_L<2>
FSB_DSTBN_L<3>
FSB_DSTBP_L<0>
FSB_DSTBP_L<1>
FSB_DSTBP_L<2>
FSB_DSTBP_L<3>
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_SLPCPU_L
FSB_TRDY_L

IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

=PP1V05_S0_FSB_NB

IO
IO

12 19 33 64

R1210
100

IO
IO

1%
1/16W
MF-LF
402

IO

IO

OUT
IO

OUT
IO

C1211

10%
16V
X5R
402

R1211
200

0.1uF

1%
1/16W
MF-LF
402

OUT
IO
IO

IO
IO
IO
IO
IO
IO
IO
IO

IO
IO
IO
IO

IO
IO
IO

IO
IO
IO
IO
IO

OUT
OUT
OUT

OUT
OUT

NB CPU Interface
SYNC_MASTER=NB

SYNC_DATE=07/25/2005

NOTICE OF PROPRIETARY PROPERTY

C1236

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

0.1uF

IO

m
il

e
r

R1225
221

IO

54.9

IO

IO

R1220 1

IO

64 33 19 12

IO

=PP1V05_S0_FSB_NB

IO

FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>

HOST

10%
16V
X5R
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

12

108

=PP1V5_S0_NB_PCIE
1

U1200

OUT
OUT

67

IO

67

IO

67

67
67

IO

OUT
IN

67 IN
67
67

OUT
OUT
OUT
OUT

67
67

OUT
OUT

67

OUT

67

OUT

67

67

OUT
OUT
OUT 6
OUT
OUT

6
6

OUT 6

OUT
OUT

TV-Out Signal Usage:


69

Composite: DACA only


S-Video:
DACB & DACC only
Component: DACA, DACB & DACC

69
69

69

Unused DAC outputs must remain powered, but can omit


filtering components. Unused DAC outputs should
connect to GND through 75-ohm resistors.

69
69
69

OUT
OUT
OUT
OUT
OUT
OUT
OUT

6
6

LVDS_A_CLK_N
LVDS_A_CLK_P
LVDS_B_CLK_N
LVDS_B_CLK_P

69
69
69
69
69

CRT Disable
69

Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie


HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core
rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

OUT
OUT
OUT
OUT
OUT
OUT

69

IO

69

IO

69

OUT

69

OUT
OUT

D38

EXP_A_RXN0
EXP_A_RXN1

F34

L_CLKCTLB

G38

68

L_DDC_CLK
L_DDC_DATA

EXP_A_RXN2

H34

J38

L_IBG

EXP_A_RXN3
EXP_A_RXN4

L34

EXP_A_RXN5
EXP_A_RXN6

M38

N34

EXP_A_RXN7

P38

EXP_A_RXN8
EXP_A_RXN9

R34

T38

H30
H29
G26

B38
C35
F32
C33
C32

L_VREFH
L_VREFL

A32

LA_CLK

EXP_A_RXN10

V34

E27

LB_CLK*
LB_CLK

EXP_A_RXN11
EXP_A_RXN12

W38

Y34

EXP_A_RXN13

AA38

EXP_A_RXN14
EXP_A_RXN15

AB34

AC38

EXP_A_RXP0

D34

EXP_A_RXP1
EXP_A_RXP2

F38

68

G34

EXP_A_RXP3

H38

EXP_A_RXP4
EXP_A_RXP5

J34

L38

EXP_A_RXP6

M34

EXP_A_RXP7
EXP_A_RXP8

N38

P34

EXP_A_RXP9

R38

EXP_A_RXP10
EXP_A_RXP11

T34

V38

EXP_A_RXP12
EXP_A_RXP13

W34

Y38

EXP_A_RXP14

AA34

EXP_A_RXP15

AB38

B35

LA_DATA1*

A37

LA_DATA2*

LVDS_A_DATA_P<0>
LVDS_A_DATA_P<1>
LVDS_A_DATA_P<2>

B37

LA_DATA0

LVDS_B_DATA_P<0>
LVDS_B_DATA_P<1>
LVDS_B_DATA_P<2>

TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC

B34

LA_DATA1

A36

LA_DATA2

D30

LB_DATA0*
LB_DATA1*

F29

LB_DATA2*

G30

F30
D29
F28

LB_DATA0
LB_DATA1
LB_DATA2

C18

TV_DACA_OUT
TV_DACB_OUT

A19

TV_DACC_OUT

A16

J20

TV_IREF

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC_R
CRT_IREF
CRT_VSYNC_R

B19

TV_IRTNC

EXP_A_TXN0
EXP_A_TXN1

F36

68

G40

68

EXP_A_TXN2

H36

68

EXP_A_TXN3
EXP_A_TXN4

J40

68

L36

EXP_A_TXN5
EXP_A_TXN6

M40

N36

EXP_A_TXN7

P40

EXP_A_TXN8
EXP_A_TXN9

R36

T40

EXP_A_TXN10

V36

EXP_A_TXN11
EXP_A_TXN12

W40

C25

CRT_DDC_CLK
CRT_DDC_DATA

Y36

G23

HSYNC

EXP_A_TXN13

AA40

J22

CRT_IREF
CRT_VSYNC

EXP_A_TXN14
EXP_A_TXN15

AB36

AC40

E23
D23
C22
B22
A21
B21
C26

H23

CRT_BLUE
CRT_BLUE*

CRT_GREEN
CRT_GREEN*
CRT_RED

CRT_RED*

PEG_D2R_N<0>
PEG_D2R_N<1>
PEG_D2R_N<2>
PEG_D2R_N<3>
PEG_D2R_N<4>
PEG_D2R_N<5>
PEG_D2R_N<6>
PEG_D2R_N<7>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_N<10>
PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>
PEG_D2R_N<14>
PEG_D2R_N<15>

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

EXP_A_TXP0

D36

68

EXP_A_TXP1
EXP_A_TXP2

F40

68

G36

68

EXP_A_TXP3

H40

68

EXP_A_TXP4
EXP_A_TXP5

J36

L40

EXP_A_TXP6

M36

EXP_A_TXP7
EXP_A_TXP8

N40

P36

EXP_A_TXP9

R40

EXP_A_TXP10
EXP_A_TXP11

T36

V40

EXP_A_TXP12
EXP_A_TXP13

W36

Y40

EXP_A_TXP14

AA36

EXP_A_TXP15

AB40

IN
IN
IN
IN

PEG_D2R_P<0>
PEG_D2R_P<1>
PEG_D2R_P<2>
PEG_D2R_P<3>
PEG_D2R_P<4>
PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_P<7>
PEG_D2R_P<8>
PEG_D2R_P<9>
PEG_D2R_P<10>
PEG_D2R_P<11>
PEG_D2R_P<12>
PEG_D2R_P<13>
PEG_D2R_P<14>
PEG_D2R_P<15>

IN
IN
IN
IN
IN
IN
IN
IN
IN

SDVO_TVCLKIN#
SDVO_INT#
SDVO_FLDSTALL#

y
r

IN

a
n
i

m
il

CRT_BLUE
CRT_BLUE_L
CRT_GREEN
CRT_GREEN_L
CRT_RED
CRT_RED_L

B18

TV_IRTNA
TV_IRTNB

B16

1%
1/16W
MF-LF
402

SDVO Alternate Function

LA_CLK*

E26

R1310

PEG_COMP

A33

LA_DATA0*

LVDS_B_DATA_N<0>
LVDS_B_DATA_N<1>
LVDS_B_DATA_N<2>

(3 OF 10)

L_VBG
L_VDDEN

C37

e
r
69

D40

EXP_A_COMPO

L_BKLTEN
L_CLKCTLA

LVDS_A_DATA_N<0>
LVDS_A_DATA_N<1>
LVDS_A_DATA_N<2>

TV-Out Disable
Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.
Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and
VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.

EXP_A_COMPI

BGA

L_BKLTCTL

J30

G25

945GM
NB

D32

PCI-EXPRESS GRAPHICS

67

OUT

LVDS

67

LVDS_BKLTCTL
LVDS_BKLTEN
LVDS_CLKCTLA
LVDS_CLKCTLB
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_IBG
TP_LVDS_VBG
LVDS_VDDEN
LVDS_VREFH
LVDS_VREFL

OUT

TV

67

VGA

67

Can leave all signals NC if LVDS is not implemented


Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used
VCCD_LVDS must remain powered with proper decoupling.
Otherwise, tie VCCD_LVDS to GND also.

19 64

24.9

LEMENU

LVDS Disable

SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL

IN
IN
IN
IN
IN
IN
IN

PEG_R2D_C_N<0>
PEG_R2D_C_N<1>
PEG_R2D_C_N<2>
PEG_R2D_C_N<3>
PEG_R2D_C_N<4>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>
PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>
PEG_R2D_C_P<0>
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
PEG_R2D_C_P<3>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>
PEG_R2D_C_P<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

SDVOB_RED#
SDVOB_GREEN#
SDVOB_BLUE#
SDVOB_CLKN
SDVOC_RED#
SDVOC_GREEN#
SDVOC_BLUE#
SDVOC_CLKN

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

SDVOB_RED
SDVOB_GREEN
SDVOB_BLUE
SDVOB_CLKP
SDVOC_RED
SDVOC_GREEN
SDVOC_BLUE
SDVOC_CLKP

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

NB PEG / Video Interfaces


SYNC_MASTER=NB

SYNC_DATE=07/25/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

13

108

R1440 1

10K

LEMENU

5%
1/16W
MF-LF
402

(D_PLLMON1#)
(D_PLLMON1)
(H_EDRDY#)
(H_PCREQ#)
(H_PLLMON1#)
(H_PLLMON1)
(H_PROCHOT#)
(TESTIN#)
(TV_DCONSEL0)
(TV_DCONSEL1)
(VSS_MCHDETECT)
(LA_DATAN3)
(LA_DATAP3)
(LB_DATAN3)
(LB_DATAP3)

NC
NC
NC
NC
NC
NC

33

IN

33

IN

33

IN

IN

20

IN

IN

20

IN

IN

20

IN

IN

IN

6 IN

=PP3V3_S0_NB

IN

IN

6 IN

R1420 1

R1421

45 6

58 23

IN

IN

10K

10K

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
402 2

PM_EXTTS_L<0>

IN

IN

IN

20

IN

20

IN

20

IN

R1422
1

R1430
26

20

23

PM_DPRSLPVR

NB_RST_IN_L

100

945GM
NB

SM_CK0

AY35

28

R32

RSVD2
RSVD3

BGA

28

(2 OF 10)

SM_CK1
SM_CK2

AR1

F3

AW7

29

F7

RSVD4

SM_CK3

AW40

29

AG11

RSVD5
RSVD6

SM_CK0*
SM_CK1*

AW35

28

AT1

28

SM_CK2*

AY7

29

SM_CK3*

AY40

29

SM_CKE0
SM_CKE1

AU20

30 28

AT20

30 28

SM_CKE2

BA29

30 29

SM_CKE3

AY29

30 29

SM_CS0*
SM_CS1*

AW13

30 28

AW12

30 28

SM_CS2*
SM_CS3*

AY21

30 29

AW21

30 29

SMOCDCOMP0

AL20

SMOCDCOMP1

AF10

AF11
H7
J19

OUT

5%
1/16W
MF-LF
402

OUT
58 26

IN

68
68

IO
IO

22

OUT

32

OUT

RSVD9

J29
A41

RSVD10
RSVD11

TP_NB_XOR_LVDS_A35
TP_NB_XOR_LVDS_A34
TP_NB_XOR_LVDS_D28
TP_NB_XOR_LVDS_D27

A35

RSVD12

A34

RSVD13
RSVD14

D27

RSVD15

NB_BSEL<0>
NB_BSEL<1>
NB_BSEL<2>
NB_CFG<3>
NB_CFG<4>
NB_CFG<5>
NB_CFG<6>
NB_CFG<7>
NB_CFG<8>
NB_CFG<9>
NB_CFG<10>
NB_CFG<11>
NB_CFG<12>
NB_CFG<13>
NB_CFG<14>
NB_CFG<15>
NB_CFG<16>
NB_CFG<17>
NB_CFG<18>
NB_CFG<19>
NB_CFG<20>

K16
K18

CFG0
CFG1

J18

CFG2

F18
E15

CFG3
CFG4

F15

CFG5

E18
D19

CFG6
CFG7

D16

CFG8

G16

CFG9
CFG10

D28

E16

G15

CFG11
CFG12

K15

CFG13

C15
H16

CFG14
CFG15

G18

CFG16

D15

PM_DPRSLPVR_R
PM_THRMTRIP_L
VR_PWRGOOD_DELAY
NB_RST_IN_L_R
SDVO_CTRLCLK
SDVO_CTRLDATA
NB_SB_SYNC_L
CLK_NB_OE_L

IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPD

SM_ODT0

BA13

30 28

SM_ODT1
SM_ODT2

BA12

30 28

AY20

30 29

SM_ODT3

AU21

30 29

SMRCOMP*

AV9

SMRCOMP

AT9

SMVREF0

AK1

SMVREF1

AK41

G_CLKIN*

AF33

J25

CFG17
CFG18

K27

CFG19

J26

CFG20

G28

PM_BM_BUSY*
PM_EXTTS0*

H15

H26
G6

33

G_CLKIN
D_REFCLKIN*

AG33

33

A27

33

D_REFCLKIN

A26

33

D_REFSSCLKIN*
D_REFSSCLKIN

C40

33

D41

33

DMI_RXN0

AE35

22

DMI_RXN1
DMI_RXN2

AF39

22

AG35

22

DMI_RXN3

AH39

22

PWROK

DMI_RXP0

AC35

22

AH34

RSTIN*

DMI_RXP1
DMI_RXP2

AE39

22

AF35

22

DMI_RXP3

AG39

22

DMI_TXN0

AE37

22

H27

SDVO_CTRLCLK
SDVO_CTRLDATA

K28

ICH_SYNC*

H32

CLK_REQ*

DMI_TXN1
DMI_TXN2

AF41

22

AG37

22

NC0
NC1

DMI_TXN3

AH41

22

DMI_TXP0
DMI_TXP1

AC37

22

BA41

NC2
NC3

AE41

22

BA40

NC4

DMI_TXP2

AF37

22

BA39

DMI_TXP3

22

BA3

NC5
NC6

AG41

BA2

NC7

BA1

NC8
NC9

D1

C41
C1

B41
B2

NC10

AY41

NC11
NC12

AY1

AW1

NC13
NC14

A40

NC15

A4
A39

NC16
NC17

A3

NC18

AW41

MEM_CLK_N<0>
MEM_CLK_N<1>
MEM_CLK_N<2>
MEM_CLK_N<3>
MEM_CKE<0>
MEM_CKE<1>
MEM_CKE<2>
MEM_CKE<3>

y
r

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

MEM_CS_L<0>
MEM_CS_L<1>
MEM_CS_L<2>
MEM_CS_L<3>

MEM_ODT<0>
MEM_ODT<1>
MEM_ODT<2>
MEM_ODT<3>

OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

MEM_RCOMP_L
MEM_RCOMP

AH33

H28

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

PM_EXTTS1*
PW_THRMTRIP*

MEM_CLK_P<0>
MEM_CLK_P<1>
MEM_CLK_P<2>
MEM_CLK_P<3>

a
n
i

NC
NC

m
il

PM_BMBUSY_L

e
r

RSVD7
RSVD8

K30

F25

5%
1/16W
MF-LF
402

RSVD1

NC

6 IN

NOSTUFF1

T32

TP_NB_XOR_FSB2_H7
TP_NB_TESTIN_L
NB_TV_DCONSEL0
NB_TV_DCONSEL1

U1200

RSVD

DDR MUXING

CFG

R1441

CLK

5%
1/16W
MF-LF
402

PM

10K

64 20 19 14

=PP3V3_S0_NB

MISC
DMI

64 20 19 14

NB_CLK100M_GCLKIN_N
NB_CLK100M_GCLKIN_P
NB_CLK_DREFCLKIN_N
NB_CLK_DREFCLKIN_P
NB_CLK_DREFSSCLKIN_N
NB_CLK_DREFSSCLKIN_P
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>

IN

C1415

IN

0.1uF
20%
10V
CERM
402

IN
IN

=PP1V8_S3_MEM_NB

16 19 28 29 61 64

R1410
80.6

1%
1/16W
MF-LF
402

19
19

C1416
0.1uF
20%
10V
CERM
402

MEM_VREF_NB_0
MEM_VREF_NB_1

C
IN
IN

R1411
80.6

1%
1/16W
MF-LF
2 402

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

NC

NB Misc Interfaces
SYNC_MASTER=NB

SYNC_DATE=08/15/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

14

108

LEMENU

IO

28

IO

28

IO

28

IO

28

IO

28
28
28
28
28
28

IO
IO
IO
IO
IO

28

IO

28

IO

28

IO

28
28
28
28
28
28
28
28

IO
IO
IO
IO
IO
IO
IO
IO
IO

28

IO

28

IO

28

IO

28
28
28

IO
IO
IO

28

IO

28

IO

28
28
28
28
28
28
28
28
28
28
28

IO

28

28

IO

IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

28

IO

28

IO

28

IO

28

IO

28

IO

28

IO

28

IO

28

IO

28

IO

28

IO

28

IO

28

IO

28

IO

28

IO

28

IO

28

IO

28

IO

28

IO

28
28

IO
IO

AJ35

SA_DQ0

AJ34

SA_DQ1
SA_DQ2

AM31

AJ36

SA_DQ3
SA_DQ4

AK35

SA_DQ5

AM33

AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23

AT12
AL14
AL12
AK9
AN7
AK8
AK7

28

SA_DQ8

AM14

28

SA_DQ9
SA_DQ10

SA_DM5

AL9

28

AR3

28

SA_DQ11

SA_DM6
SA_DM7

AH4

28

SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16

SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24

SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35

28

SA_DQS4

AN12

28

SA_DQS5
SA_DQS6

AN8

28

AP3

28

SA_DQS7

AG5

28

AK32

28

AU33

28

AN27

28

SA_DQS3*
SA_DQS4*

AM21

28

AM12

28

SA_DQS5*
SA_DQS6*

AL8

28

AN3

28

SA_DQS7*

AH5

28

SA_MA0

AY16

30 28

SA_MA1

AU14

30 28

SA_MA2
SA_MA3

AW16

30 28

BA16

30 28

SA_MA4

BA17

30 28

SA_MA5
SA_MA6

AU16

30 28

AV17

30 28

SA_DQ39
SA_DQ40

SA_MA9

AT16

30 28

AU13

SA_DQ41

SA_MA10
SA_MA11

30 28

AT17

30 28

SA_MA12

AV20

30 28

SA_MA13

AV12

30 28

SA_DQ42
SA_DQ43

AP1
AN2

SA_DQ50
SA_DQ51

AV2

SA_DQ52

AT3
AN1

SA_DQ53
SA_DQ54

AL2

SA_DQ55

AG7

SA_DQ56
SA_DQ57

AF8

AM22

30 28

SA_DQ49

AF4

28

AW17

AW2

AH6

28

AN28

SA_DQS2*

SA_DQ38

AY2

AG9

AT33

SA_DQS2
SA_DQS3

30 28

SA_DQ47
SA_DQ48

AF6

28

AU17

SA_DQ45
SA_DQ46

AG4

AK33

SA_MA7
SA_MA8

AN9

AF9

SA_DQS0
SA_DQS1

SA_DQS0*
SA_DQS1*

SA_DQ36
SA_DQ37

SA_DQ44

AL5

AN22

AP9

AT5

30 28

AY13

SA_DM3
SA_DM4

SA_DQ30

AT13

SA_CAS*

28

SA_DQ19

AW14

SA_RCVENIN*
SA_RCVENOUT*

AK23

SA_WE*

AY14

SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AK24

30 28

MEM_A_CAS_L
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>

30 28

MEM_A_WE_L

IO

OUT

29

IO

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>

NC
NC

29

OUT

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

MEM_A_RAS_L

OUT

OUT

OUT

29

IO

29

IO

29

IO

29

IO

29
29
29
29
29
29

IO
IO
IO
IO
IO
IO

29

IO

29

IO

29

IO

29

IO

29
29
29
29
29
29
29
29
29

IO
IO
IO
IO
IO
IO
IO
IO
IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT

29

IO

29

IO

29
29
29
29
29
29
29
29
29
29
29

IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29
29

IO
IO

AK39

SB_DQ0

AJ37

SB_DQ1
SB_DQ2

AP39

y
r

SB_BS0

AT24

30 29

SB_BS1
SB_BS2

AV23

30 29

AY28

30 29

SB_CAS*

AR24

30 29

SB_DM0
SB_DM1

AK36

29

AR38

29

SB_DQ6
SB_DQ7

SB_DM2

AT36

29

BA31

29

SB_DQ8

SB_DM3
SB_DM4

AL17

29

SB_DQ9
SB_DQ10

SB_DM5

AH8

29

BA5

29

SB_DQ11

SB_DM6
SB_DM7

AN4

29

SB_DQS0
SB_DQS1

AM39

29

AT39

29

SB_DQS2
SB_DQS3

AU35

29

AR29

29

SB_DQS4

AR16

29

SB_DQS5
SB_DQS6

AR10

29

AR7

29

SB_DQS7

AN5

29

SB_DQS0*
SB_DQS1*

AM40

29

AU39

29

SB_DQS2*

AT35

29

SB_DQS3*
SB_DQS4*

AP29

29

AP16

29

SB_DQS5*
SB_DQS6*

AT10

29

AT7

29

SB_DQS7*

AP5

29

AJ38

SB_DQ3
SB_DQ4

AK38

SB_DQ5

AR41

AN41
AP41
AT40
AV41

945GM
NB
BGA

(5 OF 10)

a
n
i

m
il
OUT

e
r
SA_RAS*

P
SA_DQ58
SA_DQ59

MEM_A_BS<0>
MEM_A_BS<1>
MEM_A_BS<2>

(4 OF 10)

AL26

AP20

AP12

30 28

SA_DM2

AP24

AP13

30 28

BA20

SA_DQ6
SA_DQ7

SA_DQ28
SA_DQ29

AR14

AV14

28

SA_DQ27

AR12

SA_BS1
SA_BS2

28

AN20

AT21

30 28

AM35

AP21

AL23

AU12

AJ33

SA_DQ25
SA_DQ26

AL22

BGA

SA_BS0

SA_DM0
SA_DM1

SA_DQ17
SA_DQ18

U1200

945GM
NB

AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33

SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24

AT31

SB_DQ25
SB_DQ26

AU29

SB_DQ27

BA33

AW31

SB_DQ28
SB_DQ29

AV29

SB_DQ30

AU31

AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10

AW24

30 29

SB_MA2
SB_MA3

AY24

30 29

AR28

30 29

SB_MA4

AT27

30 29

SB_MA5
SB_MA6

AT28

30 29

AU27

30 29

SB_MA7
SB_MA8

AV28

30 29

AV27

30 29

SB_DQ39
SB_DQ40

SB_MA9

AW27

30 29

AV24

SB_DQ41

SB_MA10
SB_MA11

30 29

BA27

30 29

SB_MA12

AY27

30 29

SB_MA13

AR23

30 29

SB_RAS*

AU23

30 29

SB_RCVENIN*
SB_RCVENOUT*

AK16

MEM_B_RAS_L
TP_SB_RCVENIN_L

SB_WE*

AR27

30 29

MEM_B_WE_L

SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38

SB_DQ42
SB_DQ43

AH11

SB_DQ45
SB_DQ46

BA10

SB_DQ47
SB_DQ48

AW10

SB_DQ49

BA4
AW4

SB_DQ50
SB_DQ51

AY10

SB_DQ52

AY9
AW5

SB_DQ53
SB_DQ54

AY5

SB_DQ55

AV4

SB_DQ56
SB_DQ57

AR5

AK3

SB_DQ58
SB_DQ59

AT4

SB_DQ60

AK5
AJ5

SB_DQ61
SB_DQ62

AJ3

SB_DQ63

AK4

AK18

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

IO
IO
IO
IO
IO
IO
IO
IO
IO

IO
IO
IO
IO
IO
IO
IO

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>

SB_MA1

SB_DQ33

OUT

MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

30 29

SB_DQ31
SB_DQ32

OUT

MEM_B_CAS_L
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>

AY23

SB_DQ44

AJ8

MEM_B_BS<0>
MEM_B_BS<1>
MEM_B_BS<2>

SB_MA0

AK13

AK10

DDR SYSTEM MEMORY B

28

MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

DDR SYSTEM MEMORY A

IO

LEMENU

U1200
28

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

NC

OUT

NB DDR2 Interfaces
SYNC_MASTER=NB

SYNC_DATE=07/25/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

15

108

NCTF balls are Not Critical To Function

=PPVCORE_S0_NB
AD27
AC27
AB27
AA27

VCC_NCTF4

W27
V27

VCC_NCTF5
VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8
VCC_NCTF9

VCC_NCTF10

AC26

VCC_NCTF11
VCC_NCTF12

AA26

VCC_SM78
VCC_SM79

VCC_SM80

VCC_SM81
VCC_SM82

VCC_SM83

VCC_SM84
VCC_SM85

VCC_SM86

VCC_SM87
VCC_SM88

VCC_SM89
VCC_SM90

VCC_SM91

VCC_SM92
VCC_SM93

VCC_SM94

VCC_SM95
VCC_SM96

VCC_SM97

VCC_SM98
VCC_SM99

VCC_SM100
VCC_SM101

VCC_SM102

VCC_SM103
VCC_SM104

VCC_SM105

VCC_SM106
VCC_SM107

AR15

AJ14

AJ13

AK12

AJ12

AG12

AK11

AY8

AV8

AT8

AP8

BA6

AW6

AV6

AR6

AN6

AL6

AJ6

AV1

L16

N16

M16

VCC_109
VCC_110

M17

VCC_SM76
VCC_SM77
AU15

VCC_108

N17

P17

VCC_SM75
AV15

AJ1

VCC_SM73
VCC_SM74
AY15

VCC_106
VCC_107

L18

VCC_SM72
BA15

C1612

10uF

0.47UF

0.47UF

0.47UF

20%
6.3V
X5R
603

10%
6.3V
CERM-X5R
402

10%
6.3V
CERM-X5R
402

10%
6.3V
CERM-X5R
402

AK6

VCC_SM70
VCC_SM71
AJ16

VCC_105

M18

N18

L19

VCC_SM69
AH17

VCC_103
VCC_104

VCC_SM67
VCC_SM68
AJ18

NB_VCCSM_LF2
NB_VCCSM_LF1

C1610

AP6

VCC_SM65
VCC_SM66
AK19

VCC_102

M19

N19

Y19

VCC_SM64
AP19

VCC_100
VCC_101

AA19

VCC_SM62
VCC_SM63
AT19

AT6

VCC_SM61
AU19

VCC_98
VCC_99

AB19

VCC_SM59
VCC_SM60
AW19

VCC_97

L20

VCC_SM58
AY19

C1621

AY6

VCC_SM56
VCC_SM57
AK20

VCC_95
VCC_96

N20

VCC_SM54
VCC_SM55
AJ22

AR8

VCC_SM53
AK22

AW8

VCC_SM51
VCC_SM52
AR22

BA8

VCC_SM50
AT22

AH12

VCC_SM48
VCC_SM49
AV22

AH13

VCC_SM47
AW22

AJ15

VCC_SM45
VCC_SM46
BA22

m
il

10uF
20%
6.3V
X5R
603

AT15

VCC_SM43
VCC_SM44
BA23

AW15

VCC_SM42
AH24

Layout Note:
Place near pin BA23

C1620

AH16

VCC_SM40
VCC_SM41
AH25

=PP1V8_S3_MEM_NB

10%
6.3V
CERM-X5R
402

AJ17

VCC_SM39
AJ25

AJ19

VCC_SM37
VCC_SM38
AJ26

10%
6.3V
CERM-X5R
402

AR19

VCC_SM36
AR26

0.47UF

10%
6.3V
CERM-X5R
402

AV19

VCC_SM34
VCC_SM35
AU26

0.47UF

BA19

VCC_SM32
VCC_SM33
AW26

C1613

AK21

VCC_SM31
AY26

61 29 28 19 14
64

AP22

VCC_SM29
VCC_SM30
AH27

AU22

VCC_SM28
AJ27

C1615
0.47UF

C1614

AY22

VCC_SM26
VCC_SM27
AJ28

AJ23

VCC_SM25
AH29

AJ24

VCC_SM23
VCC_SM24
AK29

AH26

VCC_SM21
VCC_SM22
AM29

AT26

VCC_SM20
AM30

AV26

VCC_SM18
VCC_SM19
AP30

NB_VCCSM_LF4
NB_VCCSM_LF5

BA26

VCC_SM17
AR30

AH28

VCC_SM15
VCC_SM16
AU30

AJ29

VCC_SM14
AV30

AL29

VCC_SM12
VCC_SM13
AY30

AN30

VCC_SM10
VCC_SM11
AR34

AT30

VCC_SM9
AT34

AW30

VCC_SM7
VCC_SM8
AV34

BA30

VCC_SM6
AW34

AU34

VCC_SM4
VCC_SM5
AY34

VCC_SM3

VCC_94

W20

Y20

P20

VCC_92
VCC_93

VCC_91

AC20

L21

M21

N21

AB20

VCC_89
VCC_90

VCC_87
VCC_88

VCC_86

AA21

AC21

W21

VCC_84
VCC_85

VCC_83

M22

N22

L22

VCC_81
VCC_82

VCC_80

W22

P22

VCC_78
VCC_79

AB22

AC22

L23

M23

N23

Y22

VCC_76
VCC_77

VCC_75

VCC_73
VCC_74

VCC_72

Y23

AA23

P23

VCC_70
VCC_71

VCC_69

M24

AB23

VCC_67
VCC_68

P24

L25

M25

N25

L26

N26

P26

L27

N24

VCC_65
VCC_66

VCC_64

VCC_62
VCC_63

VCC_61

VCC_59
VCC_60

VCC_58

N27

M27

VCC_56
VCC_57

L28

M28

P27

VCC_54
VCC_55

VCC_53

P28

R28

T28

U28

V28

N28

VCC_51
VCC_52

VCC_50

VCC_48
VCC_49

VCC_47

AA28

Y28

VCC_45
VCC_46

L29

M29

AB28

VCC_43
VCC_44

VCC_42

R29

U29

P29

VCC_40
VCC_41

VCC_39

W29

Y29

AA29

L30

V29

VCC_37
VCC_38

VCC_36

VCC_34
VCC_35

N30

P30

M30

VCC_32
VCC_33

VCC_31

T30

U30

R30

VCC_29
VCC_30

VCC_28

W30

Y30

AA30

M31

V30

VCC_26
VCC_27

VCC_25

VCC_23
VCC_24

P31

R31

N31

VCC_21
VCC_22

VCC_20

V31

W31

T31

VCC_18
VCC_19

VCC_17

J32

L32

AA31

VCC_15
VCC_16

VCC_14

M32

P32

V32

N32

VCC_12
VCC_13

VCC_11

VCC_10

Y32

W32

VCC_8
VCC_9

AA32

L33

J33

VCC_6
VCC_7

VCC_5

(6 OF 10)

P33

N33

VCC_3
VCC_4

W33

BA34

BGA

VCC_2

AU40

AM41

VCC_SM1
VCC_SM2

945GM
NB

AA33

VCC_0
VCC_1
VCC_SM0

AT41

LEMENU

AU41

U1200

VCC

M20

a
n
i

1.05V or 1.5V

C1611

Layout Note:
Place near pin BA15

Layout Note:
Place in cavity
(Need to better define cavity)

e
r

945GM
NB
BGA

(7 OF 10)

y
r
AD26

AB26

16 19 64

U1200

VCC_NCTF2
VCC_NCTF3

Y27

R27

=PPVCORE_S0_NB

VCC_NCTF0
VCC_NCTF1

NCTF

64 19 16

These connections can break without


impacting part performance.
LEMENU
VSS_NCTF0
VSS_NCTF1

AE27

VSS_NCTF2
VSS_NCTF3

AE25

VSS_NCTF4

AE23

VSS_NCTF5
VSS_NCTF6

AE22

VSS_NCTF7

AE20

VSS_NCTF8
VSS_NCTF9

AE19

VSS_NCTF10

AC17

VSS_NCTF11
VSS_NCTF12

Y17

AE26

AE24

AE18

U17

Y26

VCC_NCTF13
VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16
VCC_NCTF17

VCCAUX_NCTF0

AG27

U26

VCC_NCTF18

R26

VCCAUX_NCTF1
VCCAUX_NCTF2

AF27

T26

VCCAUX_NCTF3

AF26

AD25

VCC_NCTF19
VCC_NCTF20
VCC_NCTF21

AB25

VCCAUX_NCTF4
VCCAUX_NCTF5

AG25

AC25

VCC_NCTF22
VCC_NCTF23

VCCAUX_NCTF6

AG24

VCCAUX_NCTF7
VCCAUX_NCTF8

AF24

AA25
Y25

=PP1V5_S0_NB_VCCAUX

AF25

W25

VCC_NCTF26

U25

VCCAUX_NCTF9
VCCAUX_NCTF10

AF23

V25

VCCAUX_NCTF11

AF22

T25

VCC_NCTF27
VCC_NCTF28
VCC_NCTF29

AD24

VCCAUX_NCTF12
VCCAUX_NCTF13

AG21

R25

VCCAUX_NCTF14

AG20

AC24

VCC_NCTF30
VCC_NCTF31
VCC_NCTF32

AA24

VCCAUX_NCTF15
VCCAUX_NCTF16

AF20

AB24

VCC_NCTF33
VCC_NCTF34

VCCAUX_NCTF17

AF19

VCCAUX_NCTF18
VCCAUX_NCTF19

R19

W24

AG23

AG22

AF21

V24

VCC_NCTF37

T24

VCCAUX_NCTF20
VCCAUX_NCTF21

AF18

U24

VCCAUX_NCTF22

AG17

R24

VCC_NCTF38
VCC_NCTF39
VCC_NCTF40

V23

VCCAUX_NCTF23
VCCAUX_NCTF24

AF17

AD23

VCCAUX_NCTF25

AD17

U23

VCC_NCTF41
VCC_NCTF42
VCC_NCTF43

R23

VCCAUX_NCTF26
VCCAUX_NCTF27

AB17

T23

VCC_NCTF44
VCC_NCTF45

VCCAUX_NCTF28

W17

VCCAUX_NCTF29
VCCAUX_NCTF30

V17

R17

V22
U22

VCC_NCTF46
VCC_NCTF47

AG18

R18

AE17

AA17

T17

T22

VCC_NCTF48

R22

VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33

AF16

AD21

VCC_NCTF49
VCC_NCTF50
VCC_NCTF51

U21

VCCAUX_NCTF34
VCCAUX_NCTF35

AE16

V21

VCCAUX_NCTF36

AC16

T21

VCC_NCTF52
VCC_NCTF53
VCC_NCTF54

AD20

VCCAUX_NCTF37
VCCAUX_NCTF38

AB16

R21

VCC_NCTF55
VCC_NCTF56

VCCAUX_NCTF39

Y16

VCCAUX_NCTF40
VCCAUX_NCTF41

W16

U16

V20
U20
T20

VCC_NCTF57
VCC_NCTF58

AG16

AD16

AA16

V16

R20

VCC_NCTF59

AD19

VCCAUX_NCTF42
VCCAUX_NCTF43

VCC_NCTF60
VCC_NCTF61

VCCAUX_NCTF44

R16

V19
U19

VCC_NCTF62

T19

VCCAUX_NCTF45
VCCAUX_NCTF46

VCC_NCTF63
VCC_NCTF64

VCCAUX_NCTF47

AE15

AD18

VCC_NCTF65

AB18

VCCAUX_NCTF48
VCCAUX_NCTF49

AD15

AC18

VCC_NCTF66
VCC_NCTF67

VCCAUX_NCTF50

AB15

VCCAUX_NCTF51
VCCAUX_NCTF52

AA15

W15

Y18
W18

VCC_NCTF68
VCC_NCTF69

AF15

AC15

Y15

V18

VCC_NCTF70

U18

VCCAUX_NCTF53
VCCAUX_NCTF54

VCC_NCTF71
VCC_NCTF72

VCCAUX_NCTF55

U15

VCCAUX_NCTF56
VCCAUX_NCTF57

T15

T18

T16

AG15

AA18

AG19

VCC_NCTF35
VCC_NCTF36

AD22

17 19 64

AG26

VCC_NCTF24
VCC_NCTF25

Y24

AE21

V15

R15

NB Power 1
SYNC_MASTER=NB

SYNC_DATE=07/25/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

16

108

LEMENU
64 19

=PP2V5_S0_NB_VCCSYNC

H22

VCCSYNC

64 19

=PP2V5_S0_NB_VCC_TXLVDS

C30

VCC_TXLVDS0

B30

VCC_TXLVDS1
VCC_TXLVDS2

A30

VTT0

AC14

945GM
NB

VTT1
VTT2

AB14

BGA

VTT3
VTT4

V14

(8 OF 10)
PP1V5_S0_NB_VCC3G

VTT5

R14

VCC3G1
VCC3G2

VTT6
VTT7

P14

V41

VCC3G3

VTT8

M14

R41

VCC3G4
VCC3G5

VTT9
VTT10

L14

VTT11

AC13

VTT12
VTT13

AB13

VTT14
VTT15

Y13

N41
L41

19

PP1V5_S0_NB_VCCA_3GPLL
=PP2V5_S0_NB_VCCA_3GBG
GND_NB_VSSA_3GBG

19

PP2V5_S0_NB_VCCA_CRTDAC

19
64 19

AC33
G41

F21

VCCA_CRTDAC0
VCCA_CRTDAC1

VTT16

V13
U13

VSSA_CRTDAC

PP1V5_S0_NB_VCCA_DPLLA
PP1V5_S0_NB_VCCA_DPLLB
PP1V5_S0_NB_VCCA_HPLL

B26

VCCA_DPLLA

VTT19

R13

C39

VCCA_DPLLB
VCCA_HPLL

VTT20
VTT21

N13

VCCA_LVDS

VTT22

L13

A38
B39

VSSA_LVDS

VTT23
VTT24

AB12

19

=PP2V5_S0_NB_VCCA_LVDS
GND_NB_VSSA_LVDS

19

PP1V5_S0_NB_VCCA_MPLL

AF2

VCCA_MPLL

Y12

H20

VCCA_TVBG
VSSA_TVBG

VTT27

V12

19

PP3V3_S0_NB_VCCA_TVBG
GND_NB_VSSA_TVBG

VTT25
VTT26

PP3V3_S0_NB_VCCA_TVDACC

E20

VCCA_TVDACC0

VTT28
VTT29

U12

19

F20

VCCA_TVDACC1

VTT30

R12

C20

VCCA_TVDACB0
VCCA_TVDACB1

VTT31
VTT32

P12

E19

VCCA_TVDACA0

VTT33

M12

F19

VCCA_TVDACA1

L12

AH1

VTT34
VTT35

VCCD_HMPLL0
VCCD_HMPLL1

VTT36
VTT37

P11

19

64 19

19

19

AF1

G20

PP3V3_S0_NB_VCCA_TVDACB

D20
19

64 19

PP3V3_S0_NB_VCCA_TVDACA

=PP1V5_S0_NB_VCCD_HMPLL

AH2

64 19

=PP1V5_S0_NB_VCCD_LVDS

19

64 19

19

64 19 16

AA12

W12

T12

N12

R11

N11

VTT38

M11

B28

VCCD_LVDS1
VCCD_LVDS2

VTT39
VTT40

R10

VTT41

N10

VCCD_TVDAC

a
n
i

M13

VCCD_LVDS0

D21

PP1V5_S0_NB_VCCD_TVDAC

T13

A28

C28

P10

M10

m
il

=PP3V3_S0_NB_VCC_HV

PP1V5_S0_NB_VCCD_QTVDAC
=PP1V5_S0_NB_VCCAUX

e
r

W13

G21

19

AA13

VSSA_3GBG

GND_NB_VSSA_CRTDAC

19

y
r

AD13

VTT17
VTT18

19

VCCA_3GPLL
VCCA_3GBG

N14

H41

E21

VCC3G6

A23

VCC_HV0

VTT42
VTT43

B23

VCC_HV1

VTT44

N9

B25

VCC_HV2

M9

H19

VTT45
VTT46

VCCD_QTVDAC

P8

P9

R8

AK31

VCCAUX0

VTT47
VTT48

AF31

VCCAUX1

VTT49

M8

AE31

VCCAUX2
VCCAUX3

VTT50
VTT51

P7

AC31
AL30

VCCAUX4

VTT52

M7

AK30

VTT53
VTT54

R6

AJ30

VCCAUX5
VCCAUX6

AH30

VCCAUX7

VTT55

M6

AG30

VCCAUX8
VCCAUX9

VTT56
VTT57

A6

VCCAUX10
VCCAUX11

VTT58
VTT59

P5

C1713

N5

0.47UF

AC30

VCCAUX12

VTT60

M5

AG29

VTT61
VTT62

P4

AF29

VCCAUX13
VCCAUX14

10%
6.3V
CERM-X5R
402

AE29

VCCAUX15

VTT63

M4

AD29

VCCAUX16
VCCAUX17

VTT64
VTT65

R3

AC29
AG28

VCCAUX18

VTT66

N3

AF28

VCCAUX19
VCCAUX20

VTT67
VTT68

M3

VCCAUX21
VCCAUX22

VTT69
VTT70

P2

AJ21
AH21

VCCAUX23

VTT71

D2

AJ20

VCCAUX24
VCCAUX25

VTT72
VTT73

AB1

AH20
AH19

VCCAUX26

VTT74

P1

C1711

P19

VCCAUX27
VCCAUX28

VTT75
VTT76

N1

0.47UF

P16

M1

AH15

VCCAUX29

10%
6.3V
CERM-X5R
402

P15

VCCAUX30
VCCAUX31

AF30
AE30
AD30

AE28
AH22

AH14
AG14
AF14

VCCAUX32
VCCAUX33

AE14

VCCAUX34

Y14
AF13

VCCAUX35
VCCAUX36

AE13

VCCAUX37

AF12
AE12

VCCAUX38
VCCAUX39

AD12

VCCAUX40

19 64

T14

VCC3G0

AB41
Y41

W14

AJ41

POWER

19

=PP1V05_S0_NB_VTT

U1200

N8

N7

P6

NB_VTTLF_CAP3

R5

N4

P3

R2

M2

NB_VTTLF_CAP2
NB_VTTLF_CAP1

R1
1

C1712
0.22UF
20%
6.3V
X5R
402

NB Power 2
SYNC_MASTER=NB

SYNC_DATE=07/25/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

17

108

AC41
AA41
W41

VSS_3

P41

VSS_4
VSS_5

NB
BGA

(9 OF 10)

AK34

VSS_98
VSS_99

AG34

VSS_100

AE34

VSS_101
VSS_102

AC34

VSS_8

VSS_105

AR33

VSS_106
VSS_107

AE33

AN40

VSS_9
VSS_10

AK40

VSS_11

VSS_108

Y33

VSS_109
VSS_110

V33

AH40

VSS_12
VSS_13

AG40

VSS_14

VSS_111

R33

AF40

VSS_15
VSS_16

VSS_112
VSS_113

M33

B40

VSS_117
VSS_118

B33

AR39

VSS_20
VSS_21

AN39

VSS_22

VSS_119

AG32

VSS_120
VSS_121

AF32

AC39

VSS_23
VSS_24

AB39

VSS_25

VSS_122

AC32

VSS_26
VSS_27

VSS_123
VSS_124

AB32

VSS_28
VSS_29

VSS_125
VSS_126

B32

Y39
W39
V39

AB31

L39
J39

VSS_36

VSS_133

AB30

VSS_37
VSS_38

VSS_134
VSS_135

E30

VSS_136
VSS_137

AN29

D39

VSS_39
VSS_40

AT38

VSS_41

VSS_138

T29

AM38

VSS_42
VSS_43

VSS_139
VSS_140

N29

VSS_44

VSS_141

G29

VSS_142
VSS_143

E29

AE38

VSS_45
VSS_46

C38

VSS_47

VSS_144

B29

VSS_48
VSS_49

VSS_145
VSS_146

A29

VSS_50
VSS_51

VSS_147
VSS_148

AW28
AU28

J28

J27

VSS_66

VSS_163

B27

AW36

VSS_67
VSS_68

VSS_164
VSS_165

AN26

VSS_69

VSS_166

K26

VSS_70
VSS_71

VSS_167
VSS_168

F26

VSS_169
VSS_170

AK25

W35
V35

VSS_83
VSS_84

T35

VSS_85

R35

VSS_86
VSS_87

P35
N35
M35
L35
J35
H35
G35
F35
D35
AN34

VSS_88
VSS_89
VSS_90
VSS_91

e
r

AM27

AY36

Y35

AP7

VSS_211

VSS_304

AJ7

VSS_212
VSS_213

VSS_305
VSS_306

AH7

VSS_214

VSS_307

AC7

VSS_215
VSS_216

VSS_308
VSS_309

R7

VSS_217

VSS_310

D7

VSS_218
VSS_219

VSS_311
VSS_312

AG6

VSS_220
VSS_221

VSS_313
VSS_314

AB6

VSS_222

VSS_315

U6

VSS_223
VSS_224

VSS_316
VSS_317

N6

VSS_225

VSS_318

H6

VSS_226
VSS_227

VSS_319
VSS_320

B6

VSS_228

VSS_321

AF5

VSS_229
VSS_230

VSS_322
VSS_323

AD5

VSS_231
VSS_232

VSS_324
VSS_325

AR4

VSS_233

VSS_326

AL4

VSS_234
VSS_235

VSS_327
VSS_328

AJ4

J16
F16

VSS_236

VSS_329

U4

C16

VSS_237
VSS_238

VSS_330
VSS_331

R4

AN15
AM15

VSS_239

VSS_332

F4

AK15

VSS_240
VSS_241

VSS_333
VSS_334

C4

VSS_335
VSS_336

AW3

L15

VSS_242
VSS_243

B15

VSS_244

VSS_337

AL3

AL16

F27

VSS_81
VSS_82

VSS_302
VSS_303

AN16

AD28

VSS_161
VSS_162

AA35

VSS_209
VSS_210

AV16

VSS_64
VSS_65

VSS_80

BA7

AK17

F37

AB35

VSS_300
VSS_301

AM17

G27

AH35

C8

VSS_207
VSS_208

AP17

VSS_160

VSS_78
VSS_79

VSS_299

C27

M26

D26

P
P25

VSS_171

K25

VSS_172
VSS_173

H25
E25

VSS_174

D25

VSS_175
VSS_176

A25

VSS_177

AU24

VSS_178
VSS_179

AL24

BA24

AW23

N15
M15

A15

VSS

AJ10

AC10

R9

E9

AD8

K8

AV7

AL7

AF7

G7

Y6

K6

AV5

AY4

AP4

Y4

J4

AY3

VSS_338
VSS_339

VSS_247

VSS_340

AF3

AK14

VSS_248
VSS_249

VSS_341
VSS_342

AD3

AD14
AA14

VSS_250

VSS_343

AA3

U14

VSS_251
VSS_252

VSS_344
VSS_345

G3

VSS_346
VSS_347

AR2

E14

VSS_253
VSS_254

AV13

VSS_255

VSS_348

AK2

AR13

VSS_349
VSS_350

AJ2

AN13

VSS_256
VSS_257

AM13

VSS_258

VSS_351

AB2

AL13

VSS_259
VSS_260

VSS_352
VSS_353

Y2

AG13
P13

VSS_261

VSS_354

T2

F13

VSS_262
VSS_263

VSS_355
VSS_356

N2

VSS_357
VSS_358

H2

AY12

VSS_264
VSS_265

AC12

VSS_266

VSS_359

C2

K12

VSS_360

AL1

H12

VSS_267
VSS_268

E12

VSS_269

AD11
AA11

VSS_270
VSS_271

Y11

VSS_272

AV3

VSS_245
VSS_246

B13

AD6

AT14

D13

y
r

AH9

BA14

H14

BA9

AH3

K14

VSS_92
VSS_93

(10 OF 10)

a
n
i

m
il

BA28

VSS_63

AR35

VSS_206

AR17

G37

VSS_77

U8

A18

AK27

AV35

VSS_297
VSS_298

AY17

VSS_158
VSS_159

BA35

AA8

VSS_204
VSS_205

D18

C29

VSS_61
VSS_62

VSS_75
VSS_76

VSS_296

H18

AP27

B36

VSS_203

P18

VSS_156
VSS_157

VSS_74

Y21

AH18

VSS_59
VSS_60

C36

VSS_294
VSS_295

K29

E28

AC36

VSS_201
VSS_202

AG8

AB21

C19

VSS_155

VSS_72
VSS_73

A9

AL21

G19

VSS_58

AE36

VSS_293

AB29

W28

AF36

VSS_200

K19

VSS_153
VSS_154

AG36

AN21

W19

VSS_56
VSS_57

AH36

VSS_291
VSS_292

AT29

AC28

AN36

VSS_198
VSS_199

G9

AR21

AC19

VSS_152

D37

Y9

A20

VSS_55

H37

AB9

VSS_289
VSS_290

AN19

AM28

J37

VSS_288

VSS_196
VSS_197

B20

VSS_150
VSS_151

L37

VSS_195

A22

Y31

VSS_53
VSS_54

M37

VSS_286
VSS_287

D22

K20

W37

N37

VSS_193
VSS_194

AR9

E22

AA20

AP28

P37

F22

AM20

VSS_149

R37

AW9

AR20

VSS_52

T37

VSS_285

AJ31

Y37

V37

VSS_192

C21

VSS_131
VSS_132

AA37

G22

AW20

VSS_34
VSS_35

AB37

VSS_283
VSS_284

AY31

AG31

AH37

VSS_190
VSS_191

U10

K22

H21

VSS_130

AK37

W10

AA22

G32

VSS_33

AF38

VSS_282

J21

AN31

AG38

VSS_189

K21

VSS_128
VSS_129

AH38

C23

P21

VSS_127

F39

VSS_280
VSS_281

AE32

VSS_31
VSS_32

G39

VSS_187
VSS_188

AG10

F23

AH32

VSS_30

H39

AL10

AV21

R39

M39

VSS_278
VSS_279

BA21

AV31

N39

VSS_277

VSS_185
VSS_186

F33

T39

P39

VSS_184

W23

H33

D33

B11

AP10

T33

VSS_116

AA39

AV10

BGA

AC23

AB33

VSS_19

AJ39

D11

VSS_275
VSS_276

J23

G33

AV39

945GM
NB

VSS_274

VSS_182
VSS_183

AV33

VSS_114
VSS_115

AW39

J11

VSS_181

AM23

K23

VSS_17
VSS_18

AY39

VSS_273

AN23

U1200

C34

AV40

AE40

VSS_180

AH23

F41

VSS

AT23
AF34

AW33

AJ40

945GM

LEMENU
VSS_97

VSS_103
VSS_104

AP40

U1200

VSS_6
VSS_7

J41

VSS_1
VSS_2

T41

M41

VSS_0

LEMENU

AG3

AC3

AT2

AP2

AD2

U2

J2

F2

NB Grounds
SYNC_MASTER=NB

SYNC_DATE=07/25/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

VSS_94
VSS_95

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

VSS_96

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

18

108

1
MCH VCCA_LVDS FILTER

Power Interface

(MCH LVDS ANALOG 2.5V PWR)


=PP2V5_S0_NB_VCCA_LVDS

These are the power signals that leave the NB "block"

IN
IN
IN
IN

16 19 64
19 64

IN

=PP2V5_S0_NB_CRTDAC

IN
IN
IN
IN
IN

IN
IN
IN
IN

IN

=PP5V_S0_NB_TVDAC

CRITICAL

19 64

U1900

=PP2V5_S0_NB_DISP_PLL

64

TPS73115

19 64

SOT23-5

17 64

1
3

17 19 64

IN
EN

OUT
NR/FB

PP1V5_S0_DPLL
TPS73115_NR

14 16 28 29 61 64

C1950

GND
2

17 19 64

0.01uF

10%
2 6.3V
CERM
402

19 64

C1951

10uF

10%
16V
CERM
402

C1952

17 19 64
17 19 64

=PP1V8_S3_MEM

64 29 28 19

=PP1V5_S0_NB_PLL

=PP1V8_S3_MEM

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

1
0603

R1987

1%
1/16W
MF-LF
2 402

20%
3 2 2.5V
TANT
D2T

10uF

20%
6.3V
X5R
603

20%
6.3V
X5R
603

C1904

C1903

10uF

1UF

10%
2 6.3V
CERM
402

C1905

=PP1V5_S0_NB_VCCD_LVDS

64 19 17

C1914

0.22uF
20%
6.3V
X5R
402

MCH VCCSYNC BYPASS


(MCH H/V SYNC 2.5V PWR)
=PP2V5_S0_NB_VCCSYNC
17

0.1uF

0.1uF

20%
6.3V
X5R
603

20%
10V
CERM
402

20%
10V
CERM
402

C1912

C1913

64 19 17 16

C1916

4.7uF

0.1uF

0.1uF

20%
6.3V
CERM
603

20%
10V
CERM
402

20%
10V
CERM
402

16V
NFM18

0.1uF
20%
10V
CERM
402

22000pF-1000mA
16V
NFM18

PP1V5_S0_NB_QTVDAC

MM1573DN_NR

NOISE 4

10

1%
1/16W
MF-LF
402

C1941

1UF

C1942
1UF

0.01uF

10%
6.3V
2 CERM
402

10%
16V
CERM
402

0.1uF
20%
10V
CERM
402

20%
10V
CERM
402

C1965

C1966

4.7uF

2.2uF

20%
6.3V
CERM
603

20%
6.3V
CERM1
603

Layout Note:
Place in cavity

64

Layout Note:
These 2 caps should be
within 6.35 mm of NB edge
GND_NB_VSSA_CRTDAC

SOT-363
3

PP3V3_S0_NB_TVDAC_FOLLOW
VOLTAGE=3.3V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm

=PP1V5_S0_NB

NC

C1992

L1990

22000pF-1000mA

180-OHM-1.5A

16V
NFM18

PP3V3_S0_NB_TVDAC_F

MCH VCCA_TVDACC FILTER


(MCH TV OUT CHANNEL A 3.3V PWR)
PP3V3_S0_NB_VCCA_TVDACA

C1990
10uF

20%
6.3V
X5R
603

C1991
20%
10V
CERM
402

C1994
22000pF-1000mA
16V
NFM18

C1993

MCH VCCA_TVDACC FILTER


(MCH TV OUT CHANNEL B 3.3V PWR)
PP3V3_S0_NB_VCCA_TVDACB

17

VOLTAGE=3.3V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm

0.1uF
20%
10V
CERM
402

Layout Note:
These 8 caps should be
within 6.35 mm of NB edge

Layout Note:
Place on the edge

C1995

MCH VCCA_TVDACC FILTER


(MCH TV OUT CHANNEL C 3.3V PWR)
PP3V3_S0_NB_VCCA_TVDACC

17

VOLTAGE=3.3V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm

0.1uF
20%
10V
CERM
402

GMCH VCC3G FILTER


(PCI-E/DMI ANALOG 1.5V PWR)

C1998
PP1V5_S0_NB_VCC3G

22000pF-1000mA

17

VOLTAGE=1.5V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm

CRITICAL

C1970

C1971

10uF

220UF
20%
2.5V
POLY
SMB2

C1972
10uF

20%
6.3V
X5R
603

20%
6.3V
X5R
603

16V
NFM18
1

Layout Note:
10uF caps should
be close to MCH
on opposite side.

C1997

MCH VCCA_TVBG FILTER


(MCH TV DAC BAND GAP 3.3V PWR)
PP3V3_S0_NB_VCCA_TVBG

17

VOLTAGE=3.3V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm

0.1uF
20%
10V
CERM
402

GND_NB_VSSA_TVBG

17

Layout Note: Route to caps, then GND

GMCH VCCA_3GPLL FILTER


(3GIO PLL 1.5V PWR)

1uH, 20%

L1975
=PP1V5_S0_NB_3GPLL

2
0805

GMCH VCCD_QTVDAC FILTER


(MCH TVDAC DIGITAL QUIET 1.5V PWR)

R1975

1.0UH-220MA-0.12-OHM

PP1V5_S0_NB_3GPLL_F
VOLTAGE=1.5V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm

17

VOLTAGE=1.5V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm

Layout Note:
3GPLL 10uF cap should
be placed in cavity

PP1V5_S0_NB_VCCA_3GPLL

0.51
1

17

VOLTAGE=1.5V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm

2
1%
1/16W
MF-LF
402

C1975

SYNC_MASTER=NB

SYNC_DATE=06/22/2005

0.1uF

10uF
20%
6.3V
X5R
603

NB (GM) Decoupling

C1976

NOTICE OF PROPRIETARY PROPERTY

20%
10V
CERM
402

GND_NB_VSSA_3GBG

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

17

Layout Note: Route to caps, then GND

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7173

SCALE

17

0.1uF

SIZE

VOLTAGE=3.3V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm

0603
1

19 64

17

64

17

D1986

16V
NFM18

1210

17

VOLTAGE=2.5V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm

C1996

Layout Note:
Place L and C
close to MCH

PP2V5_S0_NB_VCCA_CRTDAC
3

22000pF-1000mA

91nH

MCH VCCA_CRTDAC BYPASS


(MCH CRTDAC ANALOG 2.5V PWR)

BAT54DW

20%
6.3V
X5R
402

L1970

16V
NFM18

0.22uF
2

19 64

C1967

91NH, 20%, 20MOHM, 1.5A (1210 TYP)


CRITICAL

=PP1V5_S0_NB_3G

=PP1V05_S0_NB

Layout Note: Route to caps, then GND

MCH VTT BYPASS


(MCH FSB 1.05V PWR) (SHARE C0940 470UF)

=PP1V05_S0_NB_VTT

NC

0.1uF

0.1uF
20%
10V
CERM
402

3 CONT

R1990

C1985

VOLTAGE=1.5V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm

PP1V5_S0_NB_VCCD_QTVDAC

0603

C1922

20%
10V
CERM
402

Layout Note:
These 4 caps should be
within 6.35 mm of NB edge

C1923

PP3V3_S0_NB_TVDAC

C1940

C1937

GMCH VCCD_TVDAC FILTER


(MCH TVDAC DEDICATED PWR 1.5V)

PP1V5_S0_NB_VCCD_TVDAC

C1920

C1918
0.1uF

C1921

L1922

=PP1V5_S0_NB_VCCAUX

22000pF-1000mA

180-OHM-1.5A

P
2

=PP1V5_S0_NB_TVDAC

PP2V5_S0_NB_CRTDAC_F

GMCH VCCAUX FILTER


(MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V)

MCH VCCA_3GBG BYPASS


(MCH PCIE/DMI BAND GAP 2.5V PWR)
=PP2V5_S0_NB_VCCA_3GBG
64 19 17

945 EDS: 1210?

C1917

10uF

20%
10V
CERM
402

(MCH LVDS DATA/CLK TX 2.5V PWR)


=PP2V5_S0_NB_VCC_TXLVDS
64 19 17

64 19

0.1uF
2

64 19 17

20%
6.3V
X5R
603

SOT23-5-LF
1 VIN
VOUT 5

10%
6.3V
2 CERM
402

17

VOLTAGE=1.5V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm

e
r

C1915

945 EDS: 5 mOhm, 1nH (1210?)

m
il

C1907

20%
6.3V
X5R
402

10uF

GMCH VCCTX_LVDS BYPASS

0.22uF

=PP3V3_S0_NB_VCC_HV

C1911

C1906

20%
6.3V
X5R
402

64 19

C1910

0.22uF

MCH VCC_HV BYPASS


(MCH HV BUFFER 3.3V PWR)

GMCH VCCD_LVDS BYPASS


(MCH LVDS DIGITAL 1.5V PWR)

PP1V5_S0_NB_VCCA_MPLL

22UF
20%
6.3V
CERM-X5R
805

CRITICAL

C1902

20%
10V
CERM
402

CRITICAL

C1936

=PPVCORE_S0_NB
1

GMCH CORE PWR 1.05V BYPASS

470UF

FERR-120-OHM-0.2A

1K

1%
1/16W
MF-LF
402

MM157

=PP5V_S0_NB_TVDAC

64 19

0.1uF

L1936

14

VOLTAGE=0.9V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

R1989

a
n
i
U1901

C1935

GMCH VCCA_MPLL FILTER


(MCH MEMORY PLL 1.5V PWR)

THIS 470UF FOR GMCH CORE 1.05V

C1900

GND

MEM_VREF_NB_1

14

1K

20%
6.3V
CERM-X5R
805

R1986
1K

MEM_VREF_NB_0

22UF

VOLTAGE=0.9V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

CRITICAL

17

22000pF-1000mA

Layout Note:
THESE 4 0.1UF CAPS SHOULD
be within 5 mm of NB edge

VOLTAGE=1.5V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm

CRITICAL

C1934

1K

PP1V5_S0_NB_VCCA_HPLL

2
0603

PLACE THOSE COMPONENT


CLOSE TO GMCH
1
R1988

y
r

L1985

0603

20%
10V
CERM
402

SOT-363

C1986

180-OHM-1.5A

GMCH VCCA_HPLL FILTER


(HOST PLL 1.5V PWR)

FERR-120-OHM-0.2A

VOLTAGE=2.5V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm

1%
1/16W
MF-LF
402

0.1uF
2

19 64

PP2V5_S0_NB_CRTDAC_FOLLOW

17 19 64

10

C1954

17 19 64

14 20 64

64 29 28 19

VOLTAGE=1.5V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm
1

17

BAT54DW

R1985

=PP2V5_S0_NB_CRTDAC

(MCH DISPLAY B PLL 1.5V PWR)


PP1V5_S0_NB_VCCA_DPLLB
17

5%
1/16W
MF-LF
402

64 19

64 19 17

64 19

GMCH VCCA_DPLL_B FILTER

R1951

20%
6.3V
X5R
603

10%
16V
CERM
402

D1986

20%
10V
CERM
402

16 17 19 64

C1981
0.01uF

Layout Note: Route to caps, then GND

C1953

20%
10V
CERM
402

GND_NB_VSSA_LVDS

VOLTAGE=1.5V
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=1.0 mm
1

C1980
0.1uF

0.1uF

(MCH DISPLAY A PLL 1.5V PWR)


PP1V5_S0_NB_VCCA_DPLLA
17

5%
1/16W
MF-LF
402

13 64

L1934

64 19 16

19 64

=PP2V5_S0_NB_VCCSYNC
=PP2V5_S0_NB_VCC_TXLVDS
=PP2V5_S0_NB_VCCA_3GBG
=PP2V5_S0_NB_VCCA_LVDS

IN

R1950

MCH DISPLAY PLL POWER LDO

1UF

=PP3V3_S0_NB
=PP3V3_S0_NB_VCC_HV

IN

MCH VCCA_DPLLA FILTER

17 19 64

IN

IN

Layout Note:
This 0.1uF cap should
be within 5 mm of NB edge

12 33 64

=PP1V5_S0_NB
=PP1V5_S0_NB_PCIE
=PP1V5_S0_NB_PLL
=PP1V5_S0_NB_TVDAC
=PP1V5_S0_NB_VCCD_HMPLL
=PP1V5_S0_NB_VCCD_LVDS
=PP1V5_S0_NB_VCCAUX
=PP1V8_S3_MEM_NB

IN

=PP1V05_S0_FSB_NB
=PPVCORE_S0_NB
=PP1V05_S0_NB
=PP1V05_S0_NB_VTT

17 19 64

C
OF

19

108

Internal pull-ups
00
01
10
11

NB_CFG<13:12>
NB_CFG<3>

RESERVED

NB_CFG<4>

RESERVED

Internal pull-up

NB_CFG<14>

RESERVED

NB_CFG<15>

RESERVED

R2075

High = DMIx4

2.2K

Low

5%
1/16W
MF-LF
402

= DMIx2
2

PROBABLY NOT NEEDED


NB_CFG<16>

14

Internal pull-up

NB_CFG<6>

RESERVED

FSB Dynamic
ODT

Internal pull-up

NO STUFF
1

NB_CFG<7>

High = Mobile CPU

CPU Strap

Low

R2077
2.2K

= RESERVED
2

R2085

High = Enabled

2.2K

Low

5%
1/16W
MF-LF
402

= Disabled
2

m
il

NB_CFG<7>

14

5%
1/16W
MF-LF
402

NB_CFG<17>

y
r

NBCFG_DYN_ODT_DISABLE
1

NB_CFG<16>

a
n
i

NBCFG_DMI_X2
1

DMI x2 Select

Partial Clock Gating Disable


XOR Mode Enabled
All-Z Mode Enabled
Normal Operation

NB_CFG<5>

14

NB_CFG<5>

=
=
=
=

RESERVED

=PP3V3_S0_NB

14 19 20 64

NBCFG_VCC_1V5

NB_CFG<8>

e
r

RESERVED

B
NB_CFG<9>

14

Internal pull-up

NBCFG_PEG_REVERSE
1

NB_CFG<9>

High = Normal

2.2K

PCIE Graphics
Lane Reversal

Low

5%
1/16W
MF-LF
402

NB_CFG<10>

R2079

NB_CFG<11>

= Reversed
2

RESERVED

RESERVED

NB_CFG<18>
VCC Select

Low

R2058
2.2K

High = 1.5V

= 1.05V

5%
1/16W
MF-LF
402

NB_CFG<18>

14

Internal pull-down

=PP3V3_S0_NB

14 19 20 64

NBCFG_DMI_REVERSE

NB_CFG<19>

High = Reversed

DMI Lane
Reversal

Low

R2059
2.2K

= Normal

5%
1/16W
MF-LF
402

NB_CFG<19>

14

Internal pull-down

=PP3V3_S0_NB

945 External Design Spec says reserved

NB_CFG<20>

High = Both active

PCIe Backward
Interop. Mode

Low

14

= Only SDVO
or PCIe x1

14 19 20 64

NBCFG_SDVO_AND_PCIE
1

R2060
2.2K

5%
1/16W
MF-LF
402

NB_CFG<20>
Internal pull-down

PROBABLY NOT NEEDED


NB Config Straps
SYNC_MASTER=NB

SYNC_DATE=06/28/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

20

108

PP3V3_S5_SB_RTC

=PP3V3_S0_SB_GPIO

R2105
402 MF-LF
1/16W 1%

R2194

10K

U2100

SB_SM_INTRUDER_L

TP_SB_XOR_W1
TP_SB_XOR-Y1
TP_SB_XOR-Y2

Y5
INTRUDER*
SB_INTVRMEN W4 INTVRMEN

(INT PU)
(INT PU)
(WEAK INT PD)

54 5

OUT

54 5

OUT

57 54 5

OUT

54 5

IN

ACZ_BITCLK
ACZ_SYNC

R2197

ACZ_RST_L
ACZ_SDATAIN<0>

39

A20GATE
A20M*

LAN_CLK

CPUSPL*

LAN_RSTSYNC

TP1/DPRSTP*
TP2/DPSLP*
FERR*
GPIO49/CPUPWRGD

U7
LAN_TXD0
V6
LAN_TXD1
V7
LAN_TXD2

TP_SB_XOR-U7
TP_SB_XOR-V6
TP_SB_XOR-V7

R2195 1
R2198

V3

LFRAME*

U5
LAN_RXD0
V4
LAN_RXD1
T5
LAN_RXD2

(WEAK INT PU)

5%
1/16W
MF-LF
402

W1
EE_CS
Y1
EE_SHCLK
Y2
EE_DOUT
W3
EE_DIN

U3

TP_SB_XOR-U3
NOTE:
POR IS SMC WILL PUT LAN INTF
INTO RESET STATE TO SAVE PWR.
INTEL CONFIRMS OK TO LEAVE PINS AS NC

SB_ACZ_BITCLK
39 SB_ACZ_SYNC

U1
ACZ_BIT_CLK
R6
ACZ_SYNC

39

R5
ACZ_RST*
T2
ACZ_SDIN0
T3 20K PD
ACZ_SDIN1
T1 20K PD
ACZ_SDIN2

SB_ACZ_RST_L

TP_SB_ACZ_SDIN1
TP_SB_ACZ_SDIN2

LDRQ0*
LDRQ1*/GPIO23

CPU

IN

NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L

RTCRST*

LPC

SB_RTC_RST_L

LAD0
LAD1
LAD2
LAD3

BGA
(1 OF 6)

RTC

26

IN

AA3

ICH7-M
SB

LAN

26

OUT

AB1
RTCX1
AB2
RTCX2

IGNNE*
INIT3_3V*
INIT*
INTR
RCIN*

AC-97/
AZALIA

26

SB_RTC_X1
SB_RTC_X2

NMI
SMI*
STPCLK*

20K PD
54 5

OUT

ACZ_SDATAOUT

R2196

39

SB_ACZ_SDATAOUT

T4

THRMTRIP*

ACZ_SDOUT

OUT

OUT

35

IN

35

IN

35

33

IN
IN

AC 07

ACZ_BIT_CLK

INTERNAL 20K PD ENABLED WHEN

SB_CLK100M_SATA_N
SB_CLK100M_SATA_P
IN

35

IN

34

OUT

34

OUT
OUT

34

IN

34

IN

34

IN

AF7
SATA_2RXN
AE7
SATA_2RXP
AG6
SATA_2TXN
AH6
SATA_2TXP
AF1
SATA_CLKN
AE1
SATA_CLKP

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15

e
r

SATA_RBIAS_N
SATA_RBIAS_P
IDE_PDIOR_L
IDE_PDIOW_L
IDE_PDDACK_L
IDE_IRQ14
IDE_PDIORDY
IDE_PDDREQ

AH10
SATARBIASN
AG10
SATARBIASP

AF15
AH15
AF16
AH16
AG16
AE15

DIOR* (HSTROBE)
DIOW* (STOP)
DDACK*
IDEIRQ
IORDY (DSTROBE)
DDREQ

53 47 45 5
53 47 45 5
53 47 45 5

AC3
AA5
AB3

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>

TP_SB_DRQ0_L
TP_SB_GPIO23
53
47 45 5

LPC_FRAME_L

AE22
AH28
AG27
AF24
AH25

IO

NOTE: LAD<0-3> HAVE INTERNAL 20K PU

IO
IO

NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU


IO

NOSTUFF
OUT

SB_A20GATE
CPU_A20M_L

CPU_DPRSTP_L
CPU_DPSLP_L

AG22
AG21
AF22
AF25

CPU_PWRGD

CPU_IGNNE_L
FWH_INIT_L
7 CPU_INIT_L
7 CPU_INTR

47 6 5

AG23

a
n
i

NOTE: PULLED UP PER INTEL


OUT

OUT
OUT

OUT
OUT
OUT

AH22

7 CPU_NMI
CPU_SMI_L

CPU_STPCLK_L

5%
1/16W
MF-LF
402

R2199
10K

5%
1/16W
MF-LF
2 402

R2100

OUT

NOTE: KEYBOARD CONTROLLER RESET CPU

OUT

NOSTUFF

OUT

CPU_RCIN_L

AH24
AF23

NOTE: RISING-EDGE TRIGGERED AT CPU

OUT
OUT

AF26

DA0
DA1
DA2

DCS1*
DCS3*

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
AH17
AE17
AF17
AE16
AD16

34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34

IDE_PDD<0>
IDE_PDD<1>
IDE_PDD<2>
IDE_PDD<3>
IDE_PDD<4>
IDE_PDD<5>
IDE_PDD<6>
IDE_PDD<7>
IDE_PDD<8>
IDE_PDD<9>
IDE_PDD<10>
IDE_PDD<11>
IDE_PDD<12>
IDE_PDD<13>
IDE_PDD<14>
IDE_PDD<15>

34
34
34

34
34

IDE_PDA<0>
IDE_PDA<1>
IDE_PDA<2>

IDE_PDCS1_L
IDE_PDCS3_L

IO
IO
IO
IO
IO
IO
IO
IO

21 23 64

2.2K 2
1

AG26
AG24

=PP3V3_S0_SB_GPIO

R2101

TP_CPU_CPUSLP_L
58 7

y
r

IO

MF-LF 402
1/16W 5%

45

SMC_RCIN_L

=PP1V05_S0_SB_CPU_IO

NOTE:

R2110

SPEC SAYS WEAK PU IS REQUIRED

54.9

BUT CAPELL VALLEY USES 56-OHM PU

21 24 25 64

MF-LF 402
1/16W 1%

NOTE: R2110=56 IN CV.


CHANGED TO 54.9 FOR
BOM CONSOLIDATION

CHECK WITH INTEL

IN

NOTE: R2108=56 IN CV.


CHANGED TO 54.9 FOR
2
BOM CONSOLIDATION

CPU_FERR_L

R2107
CPU_THERMTRIP_R

24.9 2

IN

=PP1V05_S0_SB_CPU_IO

R2108
54.9
MF-LF 402
1/16W 1%

46 14 7

21 24 25 64

LAYOUT NOTE: R2108 TO BE


< 2 IN OF R2107 W/O STUB

PM_THRMTRIP_L

IN

MF-LF 402
1/16W 1%

LAYOUT NOTE: R2107 TO BE


< 2 IN OF SB

NOTE: DD<7> HAS INTERNAL 11.5K PD

IO
IO
IO
IO
IO
IO
IO
IO

OUT
OUT
OUT
OUT
OUT

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES RS

SB: 1 OF 4

INTEL HIGH DEFINITION AUDIO

INTERNAL 20K PD ONLY ENABLED IN S3COLD

- LSO BIT IN AC97 GLOBAL CONTROL REG = 1; OR

ACZ_RST#

OUT

35

34

NOTE: DDREQ HAS INTERNAL 11.5K PD

OUT

SATA_C_D2R_N
SATA_C_D2R_P
SATA_C_R2D_C_N
SATA_C_R2D_C_P

AF3
SATA_0RXN
AE3
SATA_0RXP
AG2
SATA_0TXN
AH2
SATA_0TXP

IDE

35

33

IN

SATA_A_D2R_N
SATA_A_D2R_P
SATA_A_R2D_C_N
SATA_A_R2D_C_P

SATA

IN

53 47 45 5

m
il

TP_SB_SATALED_L AF18 SATALED*


6

AA6
AB5
AC4
Y6

LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE

5%
1/16W
MF-LF
2 402

LEMENU

IN

21 23 64

NOTE: ENABLE INTERNAL 1.05V SUSPEND REG

332K

26

26 25 24

NONE
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

ACZ_SDIN[0-2]

INTERNAL 20K PD

INTERNAL 20K PD

ACZ_SDOUT

INTERNAL 20K PD ENABLED DURING RESET AND WHEN

INTERNAL 20K PD ENABLED WHEN

- LSO BIT IN AC97 GLOBAL CONTROL REG = 1; OR

- LSO BIT IN AC97 GLOBAL CONTROL REG = 1; OR

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

SIZE

ACZ_SYNC

INTERNAL 20K PD

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

21

108

7
64

=PP3V3_S5_SB_USB
LEMENU

R2200

R2250

10K

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

R2255
10K

5%
1/16W
MF-LF
2 402

USB_E_OC_PU

R2223

R2251
10K

5%
1/16W
MF-LF
2 402

R2226

R2208

10K

10K

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

U2100
36

IN

36

IN

36

OUT

36
22 6
22

22 6
22
22

USB_A_OC_L
USB_B_OC_L
USB_C_OC_L
USB_D_OC_L
USB_E_OC_L

OUT

43

43

OUT

43

OUT
6

IN

IN

22

SB_GPIO29

22

SB_GPIO31

OUT

OUT
6

36 22

IN

43 IN

SB_GPIO30
64

OUT

OUT
6

NOSTUFF

R2205
10K
MF-LF
1/16W
402 5%

50 45

IO

50 45

IO

45

IO

50 45

IO

50 45

IO

R2207

10K
MF-LF
1/16W
402 5%

OUT

10K
1

MF-LF
1/16W
402 5%

IN

OUT

R2206

IN

IN
IN

OUT

OUT

IN

22

22
22

m
il
=PP3V3_S0_SB

E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6

38

IO

38

IO

PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>

38 26

IO

PCI_FRAME_L F16 FRAME*

26

IO

26

IO

26

IO

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38

IO

38 26

IO

INT_PIRQA_L
INT_PIRQB_L
INT_PIRQC_L
INT_PIRQD_L
TP_SB_XOR-AE5
TP_SB_XOR-AD5
TP_SB_XOR-AG4
TP_SB_XOR-AH4
TP_SB_XOR-AD9

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

A3
PIRQA*
B4
PIRQB*
C5
PIRQC*
B5
PIRQD*
AE5
AD5
AG4
AH4
AD9

RSVD0
RSVD1
RSVD2
RSVD3
RSVD4

U2100

NOTE:
GNT[0-3]# HAVE INT 20K PU
ENABLED ONLY WHEN PCIRST#=0
AND PWROK=H

ICH7-M
SB
BGA
(2 OF 6)

PCI

REQ0*
GNT0*
REQ1*
GNT1*
REQ2*
GNT2*
REQ3*
GNT3*
REQ4*/GPIO22
GNT4*/GPIO48
GPIO1/REQ5*
GPIO17/GNT5*

C/BE0*
C/BE1*
C/BE2*
C/BE3*

D7
26 PCI_REQ0_L
IN
E7
TP_PCI_GNT0_L OUT
C16
26 PCI_REQ1_L
IN
D16
TP_PCI_GNT1_L OUT
C17
26 PCI_REQ2_L
IN
D17
TP_PCI_GNT2_L OUT
E13 38 26 PCI_REQ3_L
IN
F13
38 PCI_GNT3_L
IN
A13 6 TP_SB_GPIO22
IO NOTE:
A14 NOTE: TBL_L NET REMOVED
C8
D8

B15
C12
D12
C15

38
38

PLTRST*
PCIRST*
(INT 20K PU) PME*

INT I/F GPIO2/PIRQE*


GPIO3/PIRQF*
GPIO4/PIRQG*
GPIO5/PIRQH*

MISC

RSVD5
RSVD6
NOTE: CHANGE SYMBOL
RSVD7
TO RSVD[1-9]
RSVD8
MCH_SYNC*

38

A7
E10
A9
A12
C9
E11
B10
F15
F14

33

38
26

38

38
38
38

C26
B18
B19

G8
F7
F8
G7

PCI_IRDY_L
38 PCI_PAR
PCI_CLK_SB
PCI_DEVSEL_L
26 PCI_PERR_L
26 PCI_LOCK_L
26 PCI_SERR_L
26 PCI_STOP_L
26 PCI_TRDY_L

38 26

PLT_RST_L
PCI_RST_L
TP_PCI_PME_L

26

26 23
26

34 26

AE9
AG8
AH8
F21
AH20

26
38

25 34 64

R2299
10K

PCIE_C_D2R_N
PCIE_C_D2R_P
PCIE_C_R2D_C_N
PCIE_C_R2D_C_P

K26
PERN3
K25
PERP3
J28
PETN3
J27
PETP3

PCIE_D_D2R_N
PCIE_D_D2R_P
PCIE_D_R2D_C_N
PCIE_D_R2D_C_P

M26
PERN4
M25
PERP4
L28
PETN4
L27
PETP4

PCIE_E_D2R_N
PCIE_E_D2R_P
PCIE_E_R2D_C_N
PCIE_E_R2D_C_P

P26
PERN5
P25
PERP5
N28
PETN5
N27
PETP5

PCIE_F_D2R_N
PCIE_F_D2R_P
PCIE_F_R2D_C_N
PCIE_F_R2D_C_P

T25
PERN6
T24
PERP6
R28
PETN6
R27
PETP6

(3 OF 6)

D3
C4
D5
D4
E5
C3
A2
B3

USB_A_OC_L
USB_B_OC_L
USB_C_OC_L
USB_D_OC_L
USB_E_OC_L
22 SB_GPIO29
36 22 SB_GPIO30
22 SB_GPIO31

14
14
14
14

Y26
DMI1RXN
Y25
DMI1RXP
W28
DMI1TXN
W27
DMI1TXP

14
14
14
14

DMI_N2S_N<0>
DMI_N2S_P<0>
DMI_S2N_N<0>
DMI_S2N_P<0>
DMI_N2S_N<1>
DMI_N2S_P<1>
DMI_S2N_N<1>
DMI_S2N_P<1>

PD)

OC0*
OC1*
OC2*
OC3*
OC4*
OC5*/GPIO29
OC6*/GPIO30
OC7*/GPIO31

IN

OUT
IN

IN
OUT

y
r
AB26
DMI2RXN
AB25
DMI2RXP
AA28
DMI2TXN
AA27
DMI2TXP

14
14

14
14

AD25
DMI3RXN
AD24
DMI3RXP
AC28
DMI3TXN
AC27
DMI3TXP

14
14

14
14

AE28
DMI_CLKN
AE27
DMI_CLKP

DMI_N2S_N<2>
DMI_N2S_P<2>
DMI_S2N_N<2>
DMI_S2N_P<2>
DMI_N2S_N<3>
DMI_N2S_P<3>
DMI_S2N_N<3>
DMI_S2N_P<3>

33

33

OUT
IN
IN

OUT
OUT
IN
IN

OUT
OUT

SB_CLK100M_DMI_N
SB_CLK100M_DMI_P

C25
DMI_ZCOMP
D25
DMI_IRCOMP

PD)

IN

OUT

IN

PP1V5_S0_SB_VCC1_5_B

R2203

DMI_IRCOMP_R

LAYOUT NOTE:
PLACE R2203 < 1/2 IN FROM SB

24.9 2

1/16W MF-LF 1% 402

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

D2
USBRBIAS*
D1
USBRBIAS

6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6

USB_A_N
USB_A_P
USB_B_N
USB_B_P
USB_C_N
USB_C_P
USB_D_N
USB_D_P
USB_E_N
USB_E_P
USB_F_N
USB_F_P
USB_G_N
USB_G_P
USB_H_N
USB_H_P

IO

EXTERNAL 0

IO
IO

TRACKPAD (Geyser)

IO
IO

EXTERNAL 1

IO
IO

CAMERA

NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD

IO
IO

EXTERNAL 2

IO
IO

IR

IO
IO

BT

IO
IO

AIRPORT

IO

R2204
USB_RBIAS_PN

22.6 2
1%
1/16W
MF-LF
402

VOLTAGE=0

LAYOUT NOTE:
PLACE R2204 < 1/2 IN FROM SB

FWH_WP_L NOT USED

IO
IO
IO
IO

38

PCI_PME_FW_L

NOTE:
NOT PLANNED TO GO TO LPC+ CONN

IN

BOOT_LPC_SPI_L

47 45 5

BOM NOTE:
NO STUFF - DEFAULT
STUFF - A16 SWAP OVERRIDE

OUT

R2211

1K

5%
1/16W
MF-LF
2 402

(STRAPPED TO TOP-BLOCK SWAP MODE


IE SB INVERTS A16 FOR ALL CYCLES
TARGETING FWH BIOS SPACE)

IO
IO

IN

SB BOOT BIOS SELECT

IO
IO
IO

STRAP

GNT5#
R2211

GNT4#
R2210

IO

LPC (DEFAULT)

11

UNSTUFF

IO

PCI

10

UNSTUFF

STUFF

OUT

SPI

01

STUFF

UNSTUFF

IO

UNSTUFF

OUT

NOTE: GNT4#

HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

SB: 2 OF 4
SB_GPIO2
SB_GPIO3
SB_GPIO4
SB_GPIO5

14

NOTICE OF PROPRIETARY PROPERTY

IO
IO

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

IO

TP_SB_XOR_AE9
TP_SB_XOR_AG8
TP_SB_XOR_AH8
TP_SB_RSVD9 (AKA
NB_SB_SYNC_L IN

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

TP3, INTERNAL 20K PU)

DRAWING NUMBER

SHT
NONE

REV.

051-7173

SCALE

IO

APPLE COMPUTER INC.

24 25

IN

5%
1/16W
MF-LF
2 402

e
r

PCI_C_BE_L<0>
PCI_C_BE_L<1>
PCI_C_BE_L<2>
PCI_C_BE_L<3>

P
IRDY*
PAR
PCICLK
DEVSEL*
PERR*
PLOCK*
SERR*
STOP*
TRDY*

38

H26
PERN2
H25
PERP2
G28
PETN2
G27
PETP2

V26
DMI0RXN
V25
DMI0RXP
U28
DMI0TXN
U27
DMI0TXP

BGA

P5
SPI_MOSI
P2
SPI_MISO

SPI_SI
SPI_SO

22 6

38

PCIE_B_D2R_N
PCIE_B_D2R_P
PCIE_B_R2D_C_N
PCIE_B_R2D_C_P

ICH7-M
SB

R2
SPI_CLK (INT
P6
SPI_CS*
P1
SPI_ARB (INT

SPI_SCLK
SPI_CE_L
SPI_ARB

22 6

LEMENU

F26
PERN1
F25
PERP1
E28
PETN1
E27
PETP1

a
n
i
6

IN

=PP3V3_S5_SB_IO

IN

PCIE_A_D2R_N
PCIE_A_D2R_P
PCIE_A_R2D_C_N
PCIE_A_R2D_C_P

DMI

5%
1/16W
MF-LF
2 402

USB_D_OC_PU
1

USB

10K

PCI-EXP

R2225

SPI

USB_C_OC_PU
1

C
OF

22

108

NOTE FOR R2323 (DEF=NOSTUFF)


STRAPPING @ PWROK RISING:
SB WILL DISABLE TCO TIMER
SYSTEM REBOOT FEATURE

=PP3V3_S0_SB_GPIO

21 23 64

=PP3V3_S5_SB

8
1

D
64 25 23

=PP3V3_S5_SB

7 6

1 NOSTUFF 1 NOSTUFF 1 NO_REBOOT_MODE

R2318

R2395

R2396

R2397

R2327

R2326

R2323

10K

8.2K

10K

8.2K

10K

10K

1K

1/16W
2 402
MF-LF
5%

1/16W
2 402
MF-LF
5%

1/16W
2 402
MF-LF
5%

1/16W
2 402
MF-LF
5%

1/16W
2 402
MF-LF
5%

1/16W
2 MF-LF
402
5%

23 25 64

RP2300

=PP3V3_S5_SB_PM

5%
1/16W
SM-LF

1/16W
2 402
MF-LF
5%

2 3

U2100

ICH7-M
SB

BGA

R2398

R2320

R2317

R2316

1K

10K

10K

10K

1/16W
2 402
MF-LF
5%

1/16W
2 402
MF-LF
5%

1/16W
2 402
MF-LF
5%

1/16W
2 402
MF-LF
5%

27

IO

27

IO

C22
B22
SMB_LINK_ALERT_L A26
B25
SMLINK<0>
A25
SMLINK<1>

SMB_CLK
SMB_DATA

NOT USED

PM_RI_L
SB_SPKR
45 26

IN

PM_SUS_STAT_L
PM_SYSRST_L

14

IN

PM_BMBUSY_L

53 47 46 45 5

OUT

SMB_ALERT_L

A28

B23

NOTE: RESERVED FOR FUTURE


32

OUT

32

OUT
IN

A21

SB_GPIO26
23
23

53 47 45 38 5

IO

IN
IO

45 IN

PCIE_WAKE_L
INT_SERIRQ
PM_THRM_L

IN
IN

SMC_RUNTIME_SCI_L
SMC_EXTSMI_L

IN

VR_PWRGD_CK410

IO

SB_RUNTIME_SCI_L

TP_SB_GPIO6

PWROK

GPIO16/DPRSLPVR
TP0/BATLOW*

RSMRST*

DEF=GPI
DEF=GPI

VRMPWRGD

AC21
GPIO6
AC18
GPIO7
E21
GPIO8

33
33

C20

B24
SLP_S3*
D23
SLP_S4*
F22
SLP_S5*

LAN_RST*

GPIO32/CLKRUN*

AC19
GPIO33/AZ_DOCK_EN*
U2
GPIO34/AZ_DOCK_RST*

AD22

SUSCLK

(INT 20K PU) PWRBTN*

m
il

R2300
45

TP_AZ_DOCK_EN_L
TP_AZ_DOCK_RST_L

GPIO26

F20
WAKE*
AH21
SERIRQ
AF20
THRM*
26

45

GPIO11/SMBALERT*

AC1
CLK14
B2
CLK48
6

100 1
100 1

2
2

R2302
R2303

100 1

R2305

y
r
35

SB_CLK14P3M_TIMER
SB_CLK48M_USBCTLR

SUS_CLK_SB

IN
IN

OUT

SATA_C_DET_L

OD

GPIO

DEF=GPI

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35
GPIO38
GPIO39

46 45

PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L

26

PM_SB_PWROK

IN

58 14

PM_DPRSLPVR

OUT

63 45

63 61 60 45

AA4

AC22
C21

OUT
OUT
OUT

R2319 R2343
8.2K

10K
1/16W
2 402
MF-LF
5%

5%
2 1/16W
MF-LF
402

IN

NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN

C23

PM_PWRBTN_L

IN

PM_LAN_ENABLE

IN

45

C19

45

Y4

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

a
n
i

GPIO0/BM_BUSY*

B21
GPIO27
E23
GPIO28
AG18

RESERVED FOR MOBILE


AZALIA DOCKING INTF

43 36

BIOS_REC
FWH_MFG_MODE

PM_CLKRUN_L

C
53 47 45 5

PD)

AC20
GPIO18/STPPCI*
AF21
GPIO20/STPCPU*

PM_STPPCI_L
PM_STPCPU_L

AF19 SB_GPIO21
GPIO21/SATA0GP
AH18 SB_GPIO19
GPIO19/SATA1GP
AH19
GPIO36/SATA2GP
AE19 SB_GPIO37
GPIO37/SATA3GP

RI*

A19
SPKR (INT WEAK
A27
SUS_STAT*
A22
SYS_RST*
AB18

SATA GPIO

(4 OF 6)
SMBCLK
SMBDATA
LINKALERT*
SMLINK0
SMLINK1

CLKS

SMB

SYS GPIO
PWR MNGT

11 26 64

LEMENU

10K

23

45

NOTE:
SMC WILL DRIVE 0-1-0 TO KEEP LAN INTF
IN RESET STATE TO SAVE PWR

SMS_INT_L
SMC_SB_NMI
PATA_PWR_EN_L

46 45

IN

45

IN

45

PM_BATLOW_L

IN

PM_RSMRST_L

IN

R2399
1

NOTE: PATA_DET IS ACTUALLY CABLE TYPE DETECT

100K

5% 1/16W
402 MF-LF

OUT

45

SMC_WAKE_SCI_L

IN

SB_GPIO14
OUT
SV_SET_UP 5 23 47
CRB_SV_DET 23
TP_SB_GPIO25_DO_NOT_USE
32 SB_CLK100M_SATA_OE_L
OUT
TP_SB_GPIO38 IO
23 SATA_C_PWR_EN_L
OUT
23

NOTE FOR GPIO25:


- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS
- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)

64 25 23

e
r

=PP3V3_S5_SB

B
1 NOSTUFF

NOTE:
SV_SET_UP IS LINDACARD DETECT
HI = PRESENT
LO = NOT PRESENT

R2306 R2308
10K

10K

1/16W
2 402
MF-LF
5%

1/16W
2 402
MF-LF
5%

SV_SET_UP
CRB_SV_DET

LAYOUT NOTE:

P
1 NOSTUFF

R2307 R2309

PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE

64 25 23

10K
1/16W
402
2 MF-LF
5%

=PP3V3_S5_SB
1

23

10K
1/16W
2 402
MF-LF
5%

B
1

R2390

23

PATA_PWR_EN_L

23

SATA_C_PWR_EN_L

R2388

10K

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

R2312
26 22

SB_GPIO3

5%
1/16W
MF-LF
402

IDE_RESET_L

34

R2315
23

SB_GPIO14

R2310

R2389

10K

1/16W
402
2 MF-LF
5%

21 23 64

NOSTUFF

R2313

1/16W
402
2 MF-LF
5%

5 23 47

=PP3V3_S0_SB_GPIO

15K

SB: 3 OF 4

5%
1/16W
MF-LF
402

FWH_MFG_MODE 23
BIOS_REC 23

NOTICE OF PROPRIETARY PROPERTY

5%
1/16W
MF-LF
402 2

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

1 NOSTUFF

R2314
0
1/16W
2 402
MF-LF
5%

II NOT TO REPRODUCE OR COPY IT

1 NOSTUFF

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

R2311

R2312,R2315 and R2389 close to SB

10K
1/16W
2 402
MF-LF
5%

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

23

108

LEMENU

LEMENU
A4
A23
N24
P24
R18
U14
V27
AA24
AB27
AD11
B1
D10
F4
G18
J1
L24
M17
N14
N17
N18
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P27
P28
R1
R11
R12
R13
R14
R15
R16
R17
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB28
AC2
AC5
AC9
AC11
AD1
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7

5
25

AD3
AD4
AD7
AD8
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N15
N16
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

U2100
ICH7-M
SB
BGA
(6 OF 6)

VSS

25

25 22

PP5V_S5_SB_V5REF_SUS

PP1V5_S0_SB_VCC1_5_B

G10
AD17
F6
AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23

V5REF
V5REF_SUS

U2100
ICH7-M
SB
BGA
(5 OF 6)

CORE
VCC1_05

VCC PAUX
VCCLAN_3_3

e
r

=PP3V3_S0_SB_VCC3_3

B27

PP1V5_S0_SB_VCCDMIPLL

AG28

=PP1V5_S0_SB_VCC1_5_A_ARX

AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5

64 25

64 25 24

64 25

=PP1V5_S0_SB_VCCSATAPLL
=PP3V3_S0_SB_VCC3_3

=PP1V5_S0_SB_VCC1_5_A_ATX

AD2

AH11
AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9

VCC3_3/VCCHDA
VCCSUS3_3/VCCSUSHDA

VCC1_5_B

V_CPU_IO

IDE

VCC3_3

VCC3_3

PCI

VCC3_3

VCCRTC

25 64

y
r

NOTE FOR VCCLAN_3_3:


S3 IF INTERNAL LAN IS USED
S0 OR S3 IF NOT

=PP3V3_S0_SB_VCCLAN3_3 25

64

U6
R7

=PP3V3_S0_SB_3V3_1V5_VCCHDA
=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA

AE23
AE26
AH26

=PP1V05_S0_SB_CPU_IO

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

=PP3V3_S0_SB_VCC3_3_IDE

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
W5

P7

64

21 25 64

25 64

=PP3V3_S0_SB_VCC3_3_PCI 25
PP3V3_S5_SB_RTC

25 64

NOTE:
VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V
DEPENDING ON VIO OF AZALIA INTERFACE
CODEC ICS CONSIDERED SO FAR ARE 3.3V

64

21 25 26

=PP3V3_S5_SB_VCCSUS3_3 24

25 64

A24
C24
D19
VCCSUS3_3
D22
G19

ARX

VCC1_5_A

USB
VCCSUS3_3

VCCSATAPLL

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

=PP3V3_S5_SB_VCCSUS3_3_USB

25 64

VCC3_3

AB17
VCC1_5_A AC17

VCC1_5_A

ATX
VCC1_5_A

T7
F17
G17
=PP1V5_S0_SB_VCC1_5_A

25 64

AB8
VCC1_5_A AC8
K7

64 25 24

E3 VCCSUS3_3

64 25

=PP1V5_S0_SB_VCCUSBPLL

C1

VCCSAUS1_5
CHANGE SYMBOL TO 1.05

AA2
Y7

V5
V1
W2
W7

=PPVCORE_S0_SB

VCCDMIPLL

=PP3V3_S5_SB_VCCSUS3_3

VOLTAGE GENERATED INTERNALLY


SO NO CONNECT HERE

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

a
n
i

VCCA3GP

m
il
64 25 24

25

64 25

PP5V_S0_SB_V5REF

C28
G20

VOLTAGE GENERATED INTERNALLY


SO NO CONNECT HERE

VCCUSBPLL
VCCLAN1_5
CHANGE SYMBOL TO 1.05

USB CORE
VCC1_5_A

A1
H6
H7
J6
J7

SB: 4 OF 4
=PP1V5_S0_SB_VCC1_5_A_USB_CORE

25 64

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.


0

DRAWING NUMBER

SCALE

REV.

051-7173
SHT
NONE

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

C
OF

24

108

8
64 34 22

64

=PP3V3_S0_SB
64

=PP5V_S0_SB
2

ICH VCC1_5_A/ARX BYPASS


(ICH LOGIC&IO[ARX] 1.5V PWR)
24 =PP1V5_S0_SB_VCC1_5_A_ARX
1

R2502
100
1/16W
MF-LF
402
5%

10%
2 16V
X5R
402

BAT54DW
SOT-363

ICH V5REF BYPASS


(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)
PP5V_S0_SB_V5REF 24

D
1

C2511
0.1UF

D2502

C2503

10%
16V
2 X5R
402

64 24

C2517
0.1UF

10%
2 16V
X5R
402

D2502

1/16W
MF-LF
402
5%

64 25

ICH V5REF_SUS BYPASS


(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)
PP5V_S5_SB_V5REF_SUS 24
VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM

C2504

C2513

10%
2 16V
X5R
402

64 24

C2514
1UF

10%
6.3V
2 CERM
402

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PIN AG9
64

m
il

ICH VCCA3GP(VCC1_5_B BYPASS


(ICH IO,LOGIC 1.5V PWR)

PP1V5_S0_SB_VCC1_5_B

22 24

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

CRITICAL
1

C2500 1 C2505 1 C2506 1 C2507


0.1UF

220UF

10%
2 16V
X5R
402

20%
2 2.5V
POLY
SMB2

0.1UF

10%
2 16V
X5R
402

0.1UF

ICH VCCSUS3_3 BYPASS


(ICH SUSPEND 3.3V PWR)
64 25 24

=PP3V3_S5_SB_VCCSUS3_3

10%
2 16V
X5R
402

C2520
0.1UF

10%
16V
2 X5R
402

PLACEMENT NOTE:
PLACE C2500 & C2505-07 < 2.54MM OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
NEAR PINS D28, T28, AD28

e
r

ICH VCCUSBPLL BYPASS


(ICH USB PLL 1.5V PWR)
ICH VCC3_3 BYPASS
(ICH IO BUFFER 3.3V PWR)
=PP3V3_S0_SB_VCC3_3

64 24

=PP1V5_S0_SB_VCCUSBPLL

C2515
0.1UF

C2509
0.1UF

10%
2 16V
X5R
402

PLACEMENT NOTE:
PLACE C2509 NEAR PIN B27 OF SB

64 25

=PP1V5_S0_SB

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

1206

C2501

C2523
0.1UF

10%
2 16V
X5R
402

0.1UF

10%
2 16V
X5R
402

10%
2 16V
X5R
402

0.1UF

C2522

0.1UF

=PP3V3_S5_SB_VCCSUS3_3_USB

C2533

10%
16V
2 X5R
402

64 24

=PP1V5_S0_SB_VCC1_5_A

C2510

PLACEMENT NOTE:
PLACE CAPS NEAR PINS
AB8 AND AC8 OF SB

0.1UF

10%
16V
2 X5R
402

C2524

20%
2 6.3V
CERM
603

64 24

64 24

ICH IDE/VCC3_3 BYPASS


(ICH IDE I/O 3.3V PWR)
=PP3V3_S0_SB_VCC3_3_IDE

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PINS AA7 ... AG19

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PINS A1 ... J7

C2512
0.1UF

10%
16V
2 X5R
402

C2525
0.1UF

10%
16V
2 X5R
402

ICH PCI/VCC3_3 BYPASS


(ICH PCI I/O 3.3V PWR)
64 24

PLACEMENT NOTE:
DISTRIBUTE IN PCI SECTION OF SB
NEAR PINS A5 ... G16

=PP3V3_S0_SB_VCC3_3_PCI

C2526
0.1UF

10%
16V
2 X5R
402

C2527
0.1UF

C2528
0.1UF

10%
16V
2 X5R
402

10%
16V
2 X5R
402

SB: 4 OF 4
24

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

26 24 21

ICH VCCRTC BYPASS


(ICH RTC 3.3V PWR)
PP3V3_S5_SB_RTC

PLACEMENT NOTE:
PLACE CAPS NEAR PIN W5 OF SB

C2530
0.1UF

10%
2 16V
X5R
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

C2529

II NOT TO REPRODUCE OR COPY IT

0.1UF

10%
2 16V
X5R
402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7173

SCALE

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

C2508

20%
2 6.3V
X5R
603

0.1UF

10%
16V
2 X5R
402

4.7UF

10%
2 16V
X5R
402

C2532

0.1UF

ICH VCC1_5A BYPASS


(ICH LOGIC&IO 1.5V PWR)

10UF

10%
2 16V
CERM
402

ICH USB/VCCSUS3_3 BYPASS


(ICH SUSPEND USB 3.3V PWR)

C2534

0.1UF

ICH USB CORE/VCC1_5_A BYPASS


(ICH USB CORE 1.5V PWR)

0.01UF

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON
SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACEMENT NOTE:
PLACE C2520 NEAR PIN C1 OF SB

ICH VCCDMIPLL BYPASS


(ICH DMI PLL 1.5V PWR)
PP1V5_S0_SB_VCCDMIPLL

0.28-OHM
PP1V5_S0_SB_VCCDMIPLL_F

10%
16V
2 X5R
402

L2507

R2500
1/10W 5%
MF-LF 603

C2521

10%
16V
2 X5R
402

ICH V_CPU_IO BYPASS


(ICH CPU I/O 1.05V PWR)
=PP1V05_S0_SB_CPU_IO
24 21

PLACEMENT NOTE:
PLACE C2520 NEAR PIN E3 OF SB

B
64 25 24

C2531

PLACEMENT NOTE:
PLACE CAPS NEAR PINS
K3 ... N7 OF SB

PLACEMENT NOTE:
PLACE NEAR PINS AE23, AE26 & AH26 OF SB

SM-3
1

L2500

64 24

a
n
i

ICH VCC1_5_A/ATX BYPASS


(ICH LOGIC&IO[ATX] 1.5V PWR)
=PP1V5_S0_SB_VCC1_5_A_ATX

=PP1V5_S0_SB

0.1UF

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PIN U6

100-OHM-EMI

y
r

C2519

10%
16V
2 X5R
402

ICH VCC3_3/VCCHDA BYPASS


(ICH INTEL HDA CORE 3.3V PWR)
64 24 =PP3V3_S0_SB_3V3_1V5_VCCHDA

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PIN AH11

0
PLACEMENT NOTE:
PLACE C2504 < 2.54MM OF PIN F6 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY

64 25

=PP3V3_S5_SB_VCCSUS3_3

PLACEMENT NOTE:
PLACE CAPS NEAR PINS
A24 ... G19 AND P7 OF SB

PLACEHOLDER
FOR 270UF

20%
2 2.5V
POLY
CASE-C2

0.1UF

0.1UF

10%
6.3V
2 CERM
402

ICH VCC_PAUX/VCCLAN3_3 BYPASS


(ICH LAN I/F BUFFER 3.3V PWR)
=PP3V3_S0_SB_VCCLAN3_3
24 64

ICH VCC3_3 BYPASS


(ICH IO BUFFER 3.3V PWR)
24 =PP3V3_S0_SB_VCC3_3

SOT-363

10%
16V
2 X5R
402

C2516
330UF

PLACEMENT NOTE:
PLACE CAP UNDER SB NEAR PINS V1,
V5, W2, OR W7

BAT54DW

NC

10

1UF

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PIN AD2

=PP3V3_S5_SB

R2501

C2502

=PP5V_S5_SB
2

64

ICH VCCSATAPLL BYPASS


(ICH SATA PLL 1.5V PWR)
=PP1V5_S0_SB_VCCSATAPLL

0
64 23

64 25 24

24 64

VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM

PLACEMENT NOTE:
PLACE C2503 < 2.54MM OF PIN AD17 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY

0.1UF

0.1UF

10%
16V
2 X5R
402

ICH VCCSUS3_3 BYPASS


(ICH SUSPEND 3.3V PWR)

CRITICAL

C2518

ICH CORE/VCC1_05 BYPASS


(ICH CORE 1.05V PWR)
=PPVCORE_S0_SB

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PIN AG5

PLACEMENT NOTE:
PLACE CAPS AT EDGE OF SB

5
NC

C
OF

25

108

1
=PP3V3_S0_SB_PCI

64

D2600
BAT54DW
SOT-363
1
6

=PP3V42_G3H_SB_RTC

PP3V3_G3C_SB_RTC_D

PP3V3_S5_SB_RTC

5%

21 24 25

MAKE_BASE=TRUE

NC

C2610
1UF

RTC Battery Connector

CRITICAL

J2600

R2607

21

5%
1/16W
MF-LF
402

38 22

IO

38 22

IO

38 22

IO

1M
5%
1/16W
MF-LF
2 402

21

C2605

38 22

IO

38 22

IO

38 22

IO

22

IO

SB_SM_INTRUDER_L

y
r

RP2602
8.2K

OUT

5%

NC
22

IN

22

IN

a
n
i
22

IN

38 22

IN

22

38 22
22

23 22

22

SB RTC Crystal Circuit


0

10M

32.768K

5%
1/16W
MF-LF
402 2
21

SM-LF

197S0098

64 26

R2696

5%
50V
CERM
402

11 7 IN

XDP_DBRESET_L

15pF
5%
50V
CERM
402

C2611
0.1UF

SC70-5
4

U2603

58

32

OUT

CK410_PD_VTT_PWRGD_L

VR_PWRGD_CK410_L

MAKE_BASE=TRUE
3

IN

MC74VHC1G08

OUT

23

PM_SYSRST_L

MAKE_BASE=TRUE

PM_SB_PWROK

R26121

IO
IO
IO
IO
IO

R2637
R2636
R2638
R2639
R2640
R2642
R2641
R2643

INT_PIRQA_L
INT_PIRQB_L
INT_PIRQC_L
INT_PIRQD_L
SB_GPIO2
SB_GPIO3
SB_GPIO4
SB_GPIO5

8
7
6
5

1/16W
SM-LF

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K

Unbuffered

OUT

R2698

20%
10V
CERM 2
402

45 23

=PP3V3_S0_SB_PM

IO

1
2
3
4

PCI_REQ0_L
PCI_REQ1_L
PCI_REQ2_L
PCI_REQ3_L

Platform Reset Connections

OMIT

0.1UF

MC74VHC1G00

VR_PWRGD_CK410

XDP_DBRESET_L_R

C2607 1

20%
2 10V
CERM
402

23

22

100K

5%
1/16W
MF-LF
402 2

Silk: "SYS RST"

m
il

e
r
64 26

1K

This part is never stuffed,


it provides a set of pads
on the board to short or
to solder a reset button.

=PP3V3_S0_SB_PM

OUT

5%
1/16W
MF-LF
402

C2609
1

SB_RTC_X2
Is this the best part to use?

10K

5%
1/16W
MF-LF
402 2

IO

IO

R26971

CRITICAL

Y2600

34 22

=PP3V3_S5_SB_PM

15pF

SB_RTC_X1_R

5%
1/16W
MF-LF
402

R26091

64 23 11

C2608

R2610

8
7
6
5

1/16W
SM-LF

22

SB_RTC_X1

1
2
3
4

PCI_SERR_L
PCI_DEVSEL_L
PCI_PERR_L
PCI_LOCK_L

22

21

5%

OUT

518S0188

8
7
6
5

1
2
3
4

PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L

RP2601
8.2K

SB_RTC_RST_L

10%
2 6.3V
CERM
402

IO

1/16W
SM-LF

1UF

R2606

PPVBATT_G3C_RTC

20K

5%
1/16W
MF-LF
2 402

NC

NC

1K

SYM_1

F-RT-SM

38 22

R2600

SOT-363
4
3

PPVBATT_G3C_RTC_R

88460-0201

10%
2 6.3V
CERM
402

D2600
BAT54DW

64

RP2600
8.2K

64

IN

PLT_RST_L

NB_RST_IN_L

14

MAKE_BASE=TRUE

100-ohm on NB page

R2687
1

R2685
1

Buffered

MC74VHC1G08

C2680

PLT_RST_BUF_L

100K

R2683

TPM

5%
1/16W
MF-LF
2 402

20%
10V
2 CERM
402

AIRPORT_RST_L

5%
1/16W
MF-LF
402

R2680

0.1UF

68

43

R2681

SC70

U2680 4
2

TMDS_RST_L

5%
1/16W
MF-LF
402

=PP3V3_S0_RSTBUF

5%
1/16W
MF-LF
402

SMC_LRESET_L

45

TPM_LRESET_L

53

ENET_RST_L

36

5%
1/16W
MF-LF
402

R2684
1

100

DEBUG_RST_L
5 47
Linda Card represents 3 loads

5%
1/16W
MF-LF
402

R2611
1.8K

5%
1/16W
MF-LF
2 402

SC70
4

U2601 2
3

58
14

VR_PWRGOOD_DELAY
ALL_SYS_PWRGD

63 45 5

64

R2688

Q2680

100K

BSS138

R2622

5%
1/16W
MF-LF
402 2

NOSTUFF

NOSTUFF
IN

10K

Gated

=PP3V3_S3_RSTGATE

IN

5%
1/16W
MF-LF
2 402

SOT23

10K

5%
1/16W
MF-LF
2 402

R2689
0

5%
1/16W
MF-LF
2 402

R2682

PLT_RST_GATED_L

5%
1/16W
MF-LF
402

G
1
45

IN

Initial resistor values are based on CRB,


but may change after characterization.

SMC_RSTGATE_L

SB Misc
SYNC_MASTER=NB

SYNC_DATE=07/26/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

26

108

ICH7-M SMBus Connections

SMC "0" SMBus Connections

SMC "RMT" SMBus Connections


NOTE: SMC RMT bus remains powered and may be active in S3 state

64

=PP3V3_S0_SMBUS_SB

64

R27001

ICH7-M

2.0K

U2100
(MASTER)

23

SMB_CLK

23

SMB_DATA

5%
1/16W
MF-LF
402 2

SMBUS_SB_SCL

R2701
2.0K

5%
1/16W
MF-LF
2 402

Clock Chip

SMC

CY28445-5: U3301
(Write: 0xD2 Read: 0xD3)

U5800
(MASTER)

SMB_CK410_CLK

32

45

SMB_0_CLK

SMB_CK410_DATA

32

45

SMB_0_DATA

MAKE_BASE=TRUE

SMBUS_SB_SDA
MAKE_BASE=TRUE

=PP3V3_S0_SMBUS_SMC_0

R27501
2.0K

5%
1/16W
MF-LF
402 2

64

2.0K

SMBUS_SMC_0_SCL
MAKE_BASE=TRUE

SMBUS_SMC_0_SDA
MAKE_BASE=TRUE

SKIN TEMP
MAX6695: U6250

=I2C_SODIMMA_SCL

28

THRM_DIMM1_SMB_CLK

49

=I2C_SODIMMA_SDA

28

THRM_DIMM1_SMB_DATA

49

29

45

SMB_RMT_CLK

45

SMB_RMT_DATA

=SMB_AIRPORT_CLK

64

=PP3V3_S0_SMBUS_SMC_MLB

43

=SMB_AIRPORT_DATA

43

R27601

SMC

2.0K

U5800
(MASTER)

GEYSER
J4900
=SMB_GEYSER_CLK

40

=SMB_GEYSER_DATA

40

U5800
(MASTER)

45

SMB_MLB_CLK

45

SMB_MLB_DATA

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
2 402

ADT7461: U1001
(Write: 0x98 Read: 0x99)

m
il
5

SMBUS_SMC_MLB_SCL

MAKE_BASE=TRUE

SMBUS_SMC_MLB_SDA

MAKE_BASE=TRUE

SMB_THRM_CLK

10

SMB_THRM_DATA

10

SMB_BSA_CLK

45

SMB_BSA_DATA

THRM_DIMM0_SMB_DATA

e
r

ATS/ALS
=SMBUS_ATS_SCL

67

=SMBUS_ATS_SDA

67

=PP3V42_G3H_SMBUS_SMC_BSA

R27801
8.2K

5%
1/16W
MF-LF
402 2

Battery

R2781
8.2K

J8250

5%
1/16W
MF-LF
2 402

SMBUS_SMC_BSA_SCL

=SMBUS_BATT_SCL

65

=SMBUS_BATT_SDA

65

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE

SMC "Battery B" SMBus Connections


SMC

U5800
(MASTER)

U6200
(SEE TABLE)

THRM_DIMM0_SMB_CLK

AMBIENT THERMAL

CPU Temp

R2761
2.0K

45

Top-Case

y
r
SMBUS_SMC_RMT_SDA

Top-Case SMBus Connections:

SMC "MLB" SMBus Connections

J5300

SMBUS_SMC_RMT_SCL
MAKE_BASE=TRUE

SMC

5%
1/16W
MF-LF
2 402

MAKE_BASE=TRUE

64

AIRPORT

2.0K

SMC "Battery A" SMBus Connections

J2900
(Write: 0xA4 Read: 0xA5)

=I2C_SODIMMB_SDA

R2771

5%
1/16W
MF-LF
402 2

a
n
i

SO-DIMM "B"

2.0K

U5800
(MASTER)

5%
1/16W
MF-LF
2 402

J2800
(Write: 0xA0 Read: 0xA1)

29

R27701

SMC

R2751

SO-DIMM "A"

=I2C_SODIMMB_SCL

=PP3V3_S3_SMBUS_SMC_RMT

45
49
45

=PP3V3_S0_SMBUS_SMC_BSB
1

R2782
100K

64

R2783
100K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

SMB_BSB_CLK
SMB_BSB_DATA

49

M42 SMBUS CONNECTIONS


SYNC_MASTER=ENET

SYNC_DATE=08/30/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

27

108

7
64 29 28 19

28

MEM_VREF_A

3
1

C2820
2.2UF

20%
4V
2 X5R
402

C2800
0.1uF

20%
10V
2 CERM
402

15
15

MEM_A_DQ<6>
MEM_A_DQ<7>

7
9

15
15

11

MEM_A_DQS_N<0>
MEM_A_DQS_P<0>

13
15

15
15

17

MEM_A_DQ<3>
MEM_A_DQ<2>

19
21

15
15

23

MEM_A_DQ<13>
MEM_A_DQ<8>

25
27

15
15

29

MEM_A_DQS_N<1>
MEM_A_DQS_P<1>

31
33

15
15

35

MEM_A_DQ<10>
MEM_A_DQ<9>

37
39
41

15
15

43

MEM_A_DQ<24>
MEM_A_DQ<25>

45
47

15
15

49

MEM_A_DQS_N<3>
MEM_A_DQS_P<3>

51
53

15
15

55

MEM_A_DQ<31>
MEM_A_DQ<27>

57
59

15
15

61

MEM_A_DQ<22>
MEM_A_DQ<19>

63
65

15

67

MEM_A_DM<2>
NC

69
71

15

15

73

MEM_A_DQ<20>
MEM_A_DQ<17>

75
77

30 14

79

MEM_CKE<0>

81

NC
30 15

83
85

MEM_A_BS<2>

87
30 15
30 15
30 15

89

MEM_A_A<12>
MEM_A_A<9>
MEM_A_A<8>

91
93
95

30 15
30 15
30 15

97

MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<1>

99
101
103

30 15
30 15
30 15

105

MEM_A_A<10>
MEM_A_BS<0>
MEM_A_WE_L

107
109
111

30 15
30 14

113

MEM_A_CAS_L
MEM_CS_L<1>

115
117

30 14

15

123

MEM_A_DQ<37>
MEM_A_DQ<32>

125
127

15
15

129

MEM_A_DQS_N<4>
MEM_A_DQS_P<4>

131
133

15
15

135

MEM_A_DQ<38>
MEM_A_DQ<39>

137
139

15

141

MEM_A_DQ<44>
MEM_A_DQ<41>

P
15

15

15
15

15
15

15
15

15
15

15
15

15

MEM_A_DM<5>

MEM_A_DQ<47>
MEM_A_DQ<43>
MEM_A_DQ<63>
MEM_A_DQ<56>

MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<48>
MEM_A_DQ<49>

143
145
147
149
151
153
155
157
159
161

NC

163
165
167
169
171
173
175
177
179
181
183
185

MEM_A_DM<6>

187
15

64 29

15

=PPSPD_S0_MEM
1

C2822
2.2UF

20%
4V
2 X5R
402

189

MEM_A_DQ<52>
MEM_A_DQ<55>

191
193

C2821
0.1uF

20%
10V
2 CERM
402

27
27

VSS1
DQ0
DQ1

OMIT
CRITICAL
F-RT-TH2

VSS4
DQS0*
DQS0
VSS6
DQ2
DQ3
VSS8
DQ8

DQ4
DQ5
VSS2
DM0
VSS5
DQ6
DQ7
VSS7
DQ12
DQ13
VSS9

DQ9

DM1

VSS10
DQS1*

VSS11
CK0

DQS1

CK0*

VSS12
DQ10

VSS13
DQ14

DQ11
VSS14

DQ15
VSS15
KEY

VSS16

VSS17

DQ16

DQ20

DQ17
VSS18

DQ21
VSS19

DQS2*

NC0

DQS2
VSS21

DM2
VSS22

DQ18

DQ22

DQ19
VSS23

DQ23
VSS24

DQ24
DQ25

DQ28
DQ29

VSS25

VSS26

DM3
NC1

DQS3*
DQS3

VSS27

VSS28

DQ26
DQ27

DQ30
DQ31

VSS29
CKE0
VDD0

VSS30
NC/CKE1
VDD1

NC2
BA2

NC/A15
NC/A14

VDD2

VDD3

A12
A9

A11
A7

=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL

195
197
199

=PP1V8_S3_MEM

A6

VDD4
A5

VDD5
A4

A3

A2

A1
VDD6

A0
VDD7

A10/AP
BA0

BA1
RAS*

WE*

S0*

VDD8
CAS*

VDD9
ODT0

NC/S1*

NC/A13

VDD10
NC/ODT1

VDD11
NC3

VSS31

VSS32

DQ32
DQ33

DQ36
DQ37

VSS33
DQS4*

VSS34
DM4

DQS4

VSS35

VSS36
DQ34

DQ38
DQ39

DQ35

VSS37

VSS38
DQ40

DQ44
DQ45

DQ41

VSS39

VSS40
DM5

DQS5*
DQS5

VSS41
DQ42

VSS42
DQ46

DQ43

DQ47

VSS43
DQ48

VSS44
DQ52

DQ49

DQ53

VSS45
NC_TEST

VSS46
CK1

VSS47

CK1*

DQS6*
DQS6

VSS48
DM6

VSS49
DQ50

VSS50
DQ54

DQ51

DQ55

VSS51
DQ56

VSS52
DQ60

DQ57

DQ61

VSS53
DM7

VSS54
DQS7*

VSS55

DQS7
VSS56
DQ62

DQ58
DQ59
VSS57
SDA

DQ63
VSS58

SCL

SA0

VDDSPD

SA1

19 28 29 64

2
4

MEM_A_DQ<5>
MEM_A_DQ<1>

15

DDR2 VRef

15

8
10

MEM_A_DM<0>

15

MEM_A_DQ<0>
MEM_A_DQ<4>

15

One 0.1uF per connector

12
14
16

15
64 61 29 19 16 14

=PP1V8_S3_MEM_NB

18
20

MEM_A_DQ<12>
MEM_A_DQ<14>

22

15

R2800
1K

15

26

MEM_A_DM<1>

15

MEM_CLK_P<0>
MEM_CLK_N<0>

14

30
32

14

34
36

MEM_A_DQ<11>
MEM_A_DQ<15>

38

15
15

40
42
44

MEM_A_DQ<29>
MEM_A_DQ<28>

46

15
15

48
50

DIMM_OVERTEMP_L
MEM_A_DM<3>

52

a
n
i

6 29
15

54
56

MEM_A_DQ<26>
MEM_A_DQ<30>

58

15
15

60
62

MEM_A_DQ<18>
MEM_A_DQ<23>

64

15
15

66
68

MEM_A_DQS_N<2>
MEM_A_DQS_P<2>

70

15
15

72
74

MEM_A_DQ<16>
MEM_A_DQ<21>

76

15
15

78
80

MEM_CKE<1>

14 30

82
84 NC
86 NC

MEM_A_A<15>
MEM_A_A<14>

6
6

88
90

MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<6>

92
94

15 30
15 30
15 30

96
98

MEM_A_A<4>
MEM_A_A<2>
MEM_A_A<0>

100
102

15 30
15 30
15 30

104
106

MEM_A_BS<1>
MEM_A_RAS_L
MEM_CS_L<0>

108
110

15 30
15 30
14 30

112
114

MEM_ODT<0>
MEM_A_A<13>

116

126

R2801
1K

1%
1/16W
MF-LF
2 402

(See Capell Valley pg 47)

Page Notes

Power aliases required by this page:


- =PP1V8_S3_MEM
- =PPSPD_S0_MEM (2.5V - 3.3V)
Signal aliases required by this page:
- =I2C_MEM_SCL
- =I2C_MEM_SDA

BOM options provided by this page:


(NONE)

DDR2 Bypass Caps


(For return current)
64 29 28 19

=PP1V8_S3_MEM

C2809
4.7uF
20%

6.3V
CERM
603

14 30
15 30

122

MEM_A_DQ<36>
MEM_A_DQ<34>

28

to drive MCH and DIMM connectors.

NC

124

MEM_VREF_A

VOLTAGE=0.9V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

Yellow uses 10K divider and TLV2463

118
120

y
r

28

1%
1/16W
MF-LF
402

24

m
il

A8

516-0135

VSS0

J2801

202

=GND_CHASSIS_DIPDIMM_CENTER 6 29

e
r
119

MEM_ODT<1>

121

15

VREF

201

5
DIP DIMM CONN

=PP1V8_S3_MEM

DDR2-SODIMM-STD

C2810

C2811
0.1uF

0.1uF

20%

20%

20%

10V
CERM
402

C2814

10V
CERM
402

C2815

C2812

0.1uF

C2813
0.1uF
20%

10V

CERM
402

10V
CERM
402

15
15

128
130

MEM_A_DM<4>

15

132
134
136

MEM_A_DQ<35>
MEM_A_DQ<33>

15
15

C2816

C2817

0.1uF

0.1uF

1uF

1uF

20%

20%

10%

10%

10V
CERM
402

C2830

10V

CERM
402

6.3V

6.3V
2 CERM

CERM
402

402

138
140
142

MEM_A_DQ<40>
MEM_A_DQ<45>

15
15

15

6.3V
2 CERM

144
146
148

MEM_A_DQS_N<5>
MEM_A_DQS_P<5>

1uF

15

C2831
1uF

10%
402

C2832
1uF

10%

10%

6.3V
2 CERM

6.3V
2 CERM

402

402

150
152
154

MEM_A_DQ<42>
MEM_A_DQ<46>

15
15

156
158
160

MEM_A_DQ<60>
MEM_A_DQ<61>

The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,

15
15

when they get cheaper.

162
164
166

MEM_CLK_P<1>
MEM_CLK_N<1>

14
TABLE_5_HEAD

14

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

168
TABLE_5_ITEM

170

MEM_A_DM<7>

15

516-0149

CONN,200P STD SODIMM OLD REV

J2801

CRITICAL

PVT-DIMM

516-0154

CONN,200P STD SODIMM NEW REV 3.5

J2801

CRITICAL

POST-RAMP-DIMM35

172
174
176

TABLE_5_ITEM

MEM_A_DQ<62>
MEM_A_DQ<59>

15

DDR2 SO-DIMM Connector A

15

178
180
182

MEM_A_DQ<51>
MEM_A_DQ<53>

SYNC_MASTER=MEMORY

SYNC_DATE=06/20/2005

15

NOTICE OF PROPRIETARY PROPERTY

15

184
186
188

MEM_A_DQS_N<6>
MEM_A_DQS_P<6>

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

15
15

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

190
192
194

MEM_A_DQ<50>
MEM_A_DQ<54>

II NOT TO REPRODUCE OR COPY IT


15

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


15

196

SIZE

198

200

APPLE COMPUTER INC.

ADDR=0xA0(WR)/0xA1(RD)

DRAWING NUMBER

SCALE

SHT

=GND_CHASSIS_DIPDIMM_LEFT 6

NONE

REV.

051-7173

C
OF

28

108

7
64 29 28 19

29

=PP1V8_S3_MEM

MEM_VREF_B

3
1

C2920

2.2UF

20%
4V
2 X5R
402

C2900

15

0.1uF

15

20%
10V
2 CERM
402

MEM_B_DQ<1>
MEM_B_DQ<5>

7
9

15
15

11

MEM_B_DQS_N<0>
MEM_B_DQS_P<0>

13
15

15
15

17

MEM_B_DQ<2>
MEM_B_DQ<3>

19
21

15
15

23

MEM_B_DQ<12>
MEM_B_DQ<13>

25
27

15
15

29

MEM_B_DQS_N<1>
MEM_B_DQS_P<1>

31
33

15
15

35

MEM_B_DQ<8>
MEM_B_DQ<10>

37
39
41

15
15

43

MEM_B_DQ<17>
MEM_B_DQ<20>

45
47

15
15

49

MEM_B_DQS_N<2>
MEM_B_DQS_P<2>

51
53

15
15

55

MEM_B_DQ<22>
MEM_B_DQ<18>

57
59

15
15

61

MEM_B_DQ<29>
MEM_B_DQ<27>

63
65

15

67

MEM_B_DM<3>
NC

69
71

15
15

73

MEM_B_DQ<30>
MEM_B_DQ<31>

75
77

30 14

79

MEM_CKE<2>

81

NC
30 15

83
85

MEM_B_BS<2>

87
30 15
30 15
30 15

89

MEM_B_A<12>
MEM_B_A<9>
MEM_B_A<8>

91
93
95

30 15
30 15
30 15

97

MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>

99
101
103

30 15
30 15
30 15

105

MEM_B_A<10>
MEM_B_BS<0>
MEM_B_WE_L

107
109
111

30 15
30 14

113

MEM_B_CAS_L
MEM_CS_L<3>

115
117

30 14

15

123

MEM_B_DQ<58>
MEM_B_DQ<62>

125
127

15
15

129

MEM_B_DQS_N<7>
MEM_B_DQS_P<7>

131
133

15
15

135

MEM_B_DQ<57>
MEM_B_DQ<60>

137
139

15

15

15
15

15
15

15
15

15
15

15
15

15

141

MEM_B_DQ<55>
MEM_B_DQ<50>

P
15

143
145
147

MEM_B_DM<6>

149
151

MEM_B_DQ<52>
MEM_B_DQ<49>

153
155
157

MEM_B_DQ<32>
MEM_B_DQ<37>

MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
MEM_B_DQ<38>
MEM_B_DQ<34>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DM<5>

159
161

NC

163
165
167
169
171
173
175
177
179
181
183
185
187

64 29 28

=PPSPD_S0_MEM
15
15

C2922
2.2UF

20%
4V
2 X5R
402

MEM_B_DQ<41>
MEM_B_DQ<43>

C2921
0.1uF

20%
10V
2 CERM
402

189
191
193

27
27

DQ0

=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL

195
197
199

J2901
F-RT-TH2

DQ1
VSS4
DQS0*
DQS0
VSS6
DQ2
DQ3
VSS8
DQ8
DQ9

VSS0
DQ4
DQ5
VSS2
DM0
VSS5
DQ6
DQ7
VSS7
DQ12
DQ13
VSS9
DM1

VSS10

VSS11

DQS1*
DQS1

CK0
CK0*

VSS12

VSS13

DQ10
DQ11

DQ14
DQ15

VSS14

VSS15
KEY

VSS16
DQ16

VSS17
DQ20

DQ17

DQ21

VSS18
DQS2*

VSS19
NC0

DQS2

DM2

VSS21
DQ18

VSS22
DQ22

DQ19
VSS23

DQ23
VSS24

DQ24

DQ28

DQ25
VSS25

DQ29
VSS26

DM3

DQS3*

NC1
VSS27

DQS3
VSS28

DQ26

DQ30

DQ27
VSS29

DQ31
VSS30

CKE0
VDD0

NC/CKE1
VDD1

NC2

NC/A15

BA2
VDD2

NC/A14
VDD3

A12

A11

=PP1V8_S3_MEM

A7
A6

VDD4

VDD5

A5
A3

A4
A2

A1
VDD6

A0
VDD7

A10/AP

BA1

BA0
WE*

RAS*
S0*

VDD8

VDD9

CAS*
NC/S1*

ODT0
NC/A13

VDD10

VDD11

NC/ODT1
VSS31

NC3
VSS32

DQ32
DQ33

DQ36
DQ37

VSS33

VSS34

DQS4*
DQS4

DM4
VSS35

VSS36

DQ38

DQ34
DQ35

DQ39
VSS37

VSS38

DQ44

DQ40
DQ41

DQ45
VSS39

VSS40
DM5

DQS5*
DQS5

VSS41

VSS42

DQ42
DQ43

DQ46
DQ47

VSS43

VSS44

DQ48
DQ49

DQ52
DQ53

VSS45

VSS46

NC_TEST
VSS47

CK1
CK1*

DQS6*
DQS6

VSS48
DM6

VSS49

VSS50

DQ50
DQ51

DQ54
DQ55

VSS51

VSS52

DQ56
DQ57

DQ60
DQ61

VSS53

VSS54

DM7
VSS55

DQS7*
DQS7

DQ58
DQ59

VSS56
DQ62

VSS57

DQ63
VSS58
SA0

SDA
SCL
VDDSPD

SA1

MEM_B_DQ<0>
MEM_B_DQ<4>

15

One 0.1uF per connector

15

8
10

MEM_B_DM<0>

15
64 61 28 19 16 14

12
14

MEM_B_DQ<6>
MEM_B_DQ<7>

16

=PP1V8_S3_MEM_NB

15

15

20

MEM_B_DQ<15>
MEM_B_DQ<14>

22

R2901
1K

18

1%
1/16W
MF-LF
2 402

15
15

24

MEM_VREF_B 29

26

MEM_B_DM<1>

15

MEM_CLK_P<3>
MEM_CLK_N<3>

14

30
32

14

34
36

MEM_B_DQ<11>
MEM_B_DQ<9>

38

15
15

40
42
44

MEM_B_DQ<21>
MEM_B_DQ<16>

46

15

50

a
n
i

DIMM_OVERTEMP_L
MEM_B_DM<2>

52
54
56

MEM_B_DQ<23>
MEM_B_DQ<19>

58

62

15
15

66
68

MEM_B_DQS_N<3>
MEM_B_DQS_P<3>

70

15
15

72
74

MEM_B_DQ<28>
MEM_B_DQ<26>

76

15

MEM_CKE<3>

84 NC
86 NC

MEM_B_A<15>
MEM_B_A<14>

94
96
98

MEM_B_A<4>
MEM_B_A<2>
MEM_B_A<0>

100
102
104
106

MEM_B_BS<1>
MEM_B_RAS_L
MEM_CS_L<2>

108
110

Signal aliases required by this page:


- =I2C_MEM_SCL
- =I2C_MEM_SDA

BOM options provided by this page:


(NONE)
NOTE: This page does not supply VREF.
The reference voltage must be provided
by another page.

MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<6>

92

Page Notes

Power aliases required by this page:


- =PP1V8_S3_MEM
- =PPSPD_S0_MEM (2.5V - 3.3V)

88
90

1%
1/16W
MF-LF
2 402

(See Capell Valley pg 47)

14 30

82

1K

to drive MCH and DIMM connectors.

15

78
80

15

15

MEM_B_DQ<25>
MEM_B_DQ<24>

64

6 28

15

60

R2902

Yellow uses 10K divider and TLV2463

15

48

VOLTAGE=0.9V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
1

y
r

28

DDR2 Bypass Caps

15 30
15 30

(For return current)

15 30

64 29 28 19

=PP1V8_S3_MEM

15 30
15 30

15 30

C2909
4.7uF
20%

15 30
15 30

6.3V
CERM
603

14 30

112
114

MEM_ODT<2>
MEM_B_A<13>

116

14 30

15 30

118
120

NC

122
124
126

MEM_B_DQ<63>
MEM_B_DQ<59>

15

MEM_B_DM<7>

15

C2910

C2911
0.1uF

0.1uF

20%

20%

20%

10V
CERM
402

C2914

10V
CERM
402

C2915

C2912

0.1uF

C2913
0.1uF
20%

10V

CERM
402

10V
CERM
402

15

128
130

0.1uF

132
134

MEM_B_DQ<61>
MEM_B_DQ<56>

136

20%
2

15
15

CERM
402

C2930

10V

CERM
402

C2917
1uF

10%

20%

10V

C2916
1uF

0.1uF

10%

6.3V

6.3V
2 CERM

CERM
402

402

138
140

MEM_B_DQ<53>
MEM_B_DQ<48>

142

15
15

144
146

MEM_B_DQS_N<6>
MEM_B_DQS_P<6>

148

1uF

10%

10%

6.3V
2 CERM

15
15

C2931

1uF
402

C2932
1uF
10%

6.3V
2 CERM

6.3V
2 CERM

402

402

150
152

MEM_B_DQ<54>
MEM_B_DQ<51>

154

15
15

The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,

156
158

MEM_B_DQ<33>
MEM_B_DQ<36>

160

when they get cheaper.

15
15

TABLE_5_HEAD

PART#

162
164

MEM_CLK_P<2>
MEM_CLK_N<2>

166

170

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION
TABLE_5_ITEM

14

516-0149

CONN,200P STD SODIMM OLD REV

J2901

CRITICAL

PVT-DIMM

516-0154

CONN,200P STD SODIMM NEW REV 3.5

J2901

CRITICAL

POST-RAMP-DIMM35

14

168

MEM_B_DM<4>

TABLE_5_ITEM

15

172
174

MEM_B_DQ<35>
MEM_B_DQ<39>

176

DDR2 SO-DIMM Connector B

15
15

178

SYNC_MASTER=MEMORY

180

MEM_B_DQ<40>
MEM_B_DQ<42>

182

15

186

MEM_B_DQS_N<5>
MEM_B_DQS_P<5>

188

15

=PPSPD_S0_MEM

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
28 29 64

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

15

190
1

192

MEM_B_DQ<46>
MEM_B_DQ<47>

194

15

II NOT TO REPRODUCE OR COPY IT

R2900

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

10K
15

196
198

200

SYNC_DATE=06/20/2005

NOTICE OF PROPRIETARY PROPERTY

15

184

202 =GND_CHASSIS_DIPDIMM_CENTER

DDR2 VREF (FOR CONNECTOR B)

2
4

19 28 29 64

m
il

A9
A8

516-0135

=GND_CHASSIS_DIPDIMM_RIGHT

OMIT
CRITICAL

e
r
119

MEM_ODT<3>

121

15

VREF
VSS1

201

5
DIP DIMM CONN

DDR2-SODIMM-STD

5%
1/16W
MF-LF
402

SIZE

Resistor prevents pwr-gnd short

J2900_SA1

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

6
28

ADDR=0xA4(WR)/0xA5(RD)

SHT
NONE

REV.

051-7173

C
OF

29

108

One cap for each side of every RPAK, one cap for every two discrete resistors
BOMOPTION shown at the top of each group applies to every part below it

64

29 28 14

IN

MEM_CS_L<3..0>
0
1
2
3

RP3000
R3001
RP3001
RP3002

3
56
1
56
2
56
1
56

=PP0V9_S0_MEM_TERM

6
2
7
8

5% 1/16W SM-LF
5% 1/16W MF-LF 402

5% 1/16W SM-LF

D
29 28 14

IN

MEM_CKE<3..0>
0
1
2
3

RP3003
RP3004
RP3005
RP3006

56
56
56
56

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

IN

MEM_ODT<3..0>
0
1
2
3

28 15

IN

MEM_A_A<13..0>
0
1
2
3
4
5
6
7
8
9

10
11
12
13

RP3000
R3009
RP3001
R3011

RP3007
RP3008
RP3007
RP3008
RP3007
RP3008
RP3007
RP3004
RP3008
RP3003
RP3009
RP3004
RP3003
R3025

4
56
1
56
3
56

56

56
56
56
56
56
56
56
56
56
56
56
56
56
56

5% 1/16W SM-LF
5% 1/16W MF-LF 402

IN

MEM_A_BS<2..0>

5% 1/16W SM-LF
5% 1/16W MF-LF 402

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

RP3009
RP3000
RP3003

56
56
56

IN

28 15

IN

28 15

IN

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

RP3000
RP3009
RP3009

5% 1/16W SM-LF
5% 1/16W MF-LF 402

5% 1/16W SM-LF

5% 1/16W SM-LF

e
r
29 15
29 15

29 15

IN

29 15

IN

29 15

IN

IN
IN
IN

29 15

IN

29 15

IN

29 15

IN

29 15

IN

IN

29 15

29 15

29 15

5% 1/16W SM-LF

5% 1/16W SM-LF
5% 1/16W SM-LF

29 15

56
56
56

IN
IN

29 15

IN

29 15

IN

29 15

IN

29 15

IN

29 15

IN

RP3011
RP3010
RP3011
R3035
RP3011
RP3010
RP3006
RP3006
RP3010
RP3005
RP3010
RP3006
RP3005
RP3001

MEM_B_A<0>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<10>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<1>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>

56
56
56

5% 1/16W SM-LF

1
2

RP3002
RP3011
RP3005

RP3001
RP3002
RP3002

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

56
56
56

56
56
56

C3004
20%
10V
CERM
402

20%
10V
CERM
402

C3005
0.1uF

C3006
20%
10V
CERM
402

20%
10V
CERM
402

C3008
20%
10V
CERM
402

C3007
0.1uF

20%
10V
CERM
402

C3009
0.1uF

C3010

0.1uF

20%
10V
CERM
402

20%
10V
CERM
402

C3012

20%
10V
CERM
402

C3014

C3016

20%
10V
CERM
402

C3013
20%
10V
CERM
402

C3015
0.1uF

0.1uF
20%
10V
CERM
402

C3011

0.1uF

0.1uF
20%
10V
CERM
402

0.1uF

0.1uF

20%
10V
CERM
402

C3017
0.1uF

20%
10V
CERM
402

5% 1/16W SM-LF
5% 1/16W MF-LF 402

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

5% 1/16W SM-LF

C3018

0.1uF
2

20%
10V
CERM
402

C3020

20%
10V
CERM
402

C3022

20%
10V
CERM
402

20%
10V
CERM
402

C3021
0.1uF

0.1uF

5% 1/16W SM-LF

C3019
0.1uF

0.1uF
2

y
r

C3003

LAYOUT NOTE:PLACE ONE CAP CLOSE TO EVERY TWO PULLUP RESISTORS TERMINATED
TO PP0V9_S0_MEM_TERM

5% 1/16W SM-LF

MEM_B_BS<2..0>

0.1uF
2

0.1uF

5% 1/16W SM-LF

1
56
1
56
1
56
4
56
3
56
2
56
4
56
4
56
2
56
3
56
4
56

0.1uF

5% 1/16W SM-LF

28 15

20%
10V
CERM
402

20%
10V
CERM
402

a
n
i
1

m
il
0

C3002

C3001
0.1uF

0.1uF

28 15

5
2

20%
10V
CERM
402

0.1uF

5% 1/16W SM-LF

29 28 14

C3000
0.1uF

5% 1/16W SM-LF

20%
10V
CERM
402

C3023
0.1uF

20%
10V
CERM
402

Memory Active Termination

5% 1/16W SM-LF

5% 1/16W SM-LF
5% 1/16W SM-LF

C3024

0.1uF
2

20%
10V
CERM
402

C3025

0.1uF
2

NOTICE OF PROPRIETARY PROPERTY

20%
10V
CERM
402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

30

108

8
Page Notes

Power aliases required by this page:


- =PP5V_S0_MEMVTT
- =PP1V8_S0_MEMVTT
- =PP0V9_S0_MEMVTT_LDO
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

a
n
i

DDR2 Vtt Regulator


C

64

=PP5V_S0_MEMVTT

64

=PP1V8_S3_MEMVTT

R3104
1

220

5%
1/16W
MF-LF
402

If power inputs are not S0,


MEMVTT_EN can be used to
disable MEMVTT in sleep.

PP1V8_S3_MEMVTT_VDDQ

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V

R3100
1K
5%
1/16W
MF-LF
402

C3104

VDDQ

2.2uF
20%
6.3V
CERM1
603

10uF
20%
6.3V
X5R
603

EN

VREF

MEMVTT_VREF

CRITICAL

C3103

VTTS

VTT

10%
16V
X5R
402

C3102
10uF

GND

e
r

VCC

MSOP-8

VTT_IN

0.1uF

10%
6.3V
CERM
402

U3100

MEMVTT_EN

C3100

BD3533FVM

C3101

m
il
2

1uF

MEMVTT_EN_PU
1

y
r

20%
6.3V
X5R
603

=PP0V9_S0_MEM_REG

63 64

CRITICAL

C3105
150UF

20%
6.3V
POLY
SMC-LF

Memory Vtt Supply


SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

31

108

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

120-OHM-0.3A-EMI
1

10UF

402

32 64

C3310
1UF

20%
2 6.3V
X5R
603

10%

2 16V
X5R

=PP3V3_S0_CK410

0402-LF

5%
1/16W
MF-LF
402

C3308 1 C3309
0.1UF

2.2

L3302

R3302
PP3V3_S0_CK410_VDD48

10%
2 6.3V
CERM
402

D
L3301

y
r

120-OHM-0.3A-EMI
64 32

=PP3V3_S0_CK410

PP3V3_S0_CK410_VDD_CPU_SRC

PP3V3_S0_CK410_VDD_PCI

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

0402-LF

C3314

1UF

10UF

10%
6.3V
2 CERM
402

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

C3316 1 C3315 1 C3301 1 C3302 1 C3303 1 C3304


0.1UF

20%
2 6.3V
X5R
603

10%
2 16V
X5R
402

0.1UF

10%
2 16V
X5R
402

0.1UF

0.1UF

10%
2 16V
X5R
402

10%
2 16V
X5R
402

C3305 1 C3306 1 C3317


0.1UF

0.1UF

0.1UF
10%

10%

2 16V
X5R

2 16V
X5R

10%
2 16V
X5R
402

402

402

R3304
1

2.2

10UF

20%
2 6.3V
X5R
603

R3303
PP3V3_S0_CK410_VDDA

PP3V3_S0_CK410_VDD_REF

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

5%
1/16W
MF-LF
402

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

C3312 C3311
1

10UF

0.1UF

a
n
i

C3307
10%

2 16V
X5R

2 16V
X5R

402

402

15PF

C3390

17
28

12

49

35

(EACH POWER PIN PLACED ONE 0.1UF)


(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)

VDD_SRC

C3389

VDD_REF

61
VDD_PCI 67

5X3.2-SM

VDD_CPU

VDD_48

14.31818
NEED TO CHECK CAP VALUE

43

CRITICAL

Y3301

15PF

5%
2 50V
CERM
402

5%
50V
2 CERM
402

OMIT

U3301
SLG8LP436

38

VDD_A
39 VSS_A

PCI_STOP*
CPU_STOP*

QFN

64 32

=PP3V3_S0_CK410
33

CK410_FSB_TEST_MODE

IN

R3301

33

OUT

CK410_PCIF0_CLK

(FW PCI 33MHZ)


10K
5%
(TPM LPC 33MHZ)
1/16W
MF-LF
(SMC LPC 33MHZ)
2402
(NO USED)
33 CK410_PCI5_FCTSEL1
IO
(PORT80 LPC 33MHZ)

(ICH7M PCI 33MHZ)

33
5

OUT

33

OUT

33

OUT

33

OUT
OUT

CK410_PCI1_CLK
CK410_PCI2_CLK
CK410_PCI3_CLK
CK410_PCI4_CLK
(INT PD)

33 5

33 5

CPU_ITP/SRC_11*

36

33 5

CPU_ITP/SRC_11

37

33 5

SRC_0/LCD_CLK*
SRC_0/LCD_CLK

11
10

SRC_1*

14

SRC_1

13
9

27

IN

27

IO

SMB_CK410_CLK
SMB_CK410_DATA

65 PCI_5/FCT_SEL_1

(INT PU) CLKREQ_1*

47 SCL
48 SDA

e
r
CK410_IREF

40 NC

R3300

1%
1/16W
MF-LF
2 402

62

42

33 5

CK410_CPU1_N
CK410_CPU1_P

OUT

CK410_SRC2_N
CK410_SRC2_P

33 5

33 5

SRC_3*

19
18

CK410_SRC3_N
CK410_SRC3_P
CK410_SRC_CLKREQ3_L

59

24

SRC_5

23
60

(INT PU) CLKREQ_5*


SRC_6*
SRC_6

27

52 VSS_REF
31 VSS_SRC

(INT PU) CLKREQ_6*

25

SRC_7*
SRC_7

30
29

SRC_8*

32

SRC_8

33
34

DOT_96*/27M_SS*
DOT_96/27M

33 5
14

33 5

33 5

6
6

CK410_SRC7_N
CK410_SRC7_P

CK410_SRC8_N
33 5 CK410_SRC8_P
CK410_SRC_CLKREQ8_L
33 5

33 5

48M/FS_A

33

54
53

33

26

33

CK410_PD_VTT_PWRGD_L
CK410_USB48_FSA
CK410_CLK14P3M_TIMER
CK410_REF1_FCTSEL0

(CPU HOST 133/167MHZ)

(GMCH HOST 133/167MHZ)


(ITP HOST 133/167MHZ)

OUT
OUT
OUT

(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)


(GPU PCI-E 100 MHZ )

OUT
IN

NEED TO DECIDE THE CLKREQ CONNECTION,TO GPIO?

OUT
OUT

(ICH7M DMI 100 MHZ )


(FOR PCI-E CARD)

IN
OUT
OUT
IN

(ICH SATA 100 MHZ)


(FROM ICH7 GPIO35)

(SIGNAL NAME WILL BE CHANGED POST PROTO TO REMOVE 100M FROM SIGNAL NAME)

OUT
OUT
IN

(GMCH G_CLKIN 100 MHZ )


(FROM GMCH CLK_REQ*)

OUT
OUT

(WIRELESS PCI-E 100 MHZ )

IN
OUT

(NOT USED )

OUT
OUT

(GIGA LAN PCI-E 100 MHZ )

OUT
IN

CK410_DOT96_27M_N
CK410_DOT96_27M_P

REF_0/FS_C/TEST_SEL

CK410_SRC6_N
CK410_SRC6_P
CK410_SRC_CLKREQ6_L

33 5

VTT_PWRGD*/PD

REF_1/FCT_SEL_0
(INT PD)

CK410_SRC5_N
CK410_SRC5_P
CLK_NB_OE_L

33 5

43

OUT

OUT

CK410_SRC4_N
CK410_SRC4_P
SB_CLK100M_SATA_OE_L

(FROM ICH7 GPIO18 STPPCI* )


(FROM ICH7 GPIO20 STPCPU* )

OUT

OUT

33 5

26

OUT

33 5

23

OUT

33 5

20

SRC_5*

(INT PU) CLKREQ_8*

22
21

66 VSS_PCI

(INT PD)

CK410_SRC1_N
6 CK410_SRC1_P
CK410_SRC_CLKREQ1_L
6

15

SRC_4
(INT PU) CLKREQ_4*

69 THRML_PAD

CK410_LVDS_N
CK410_LVDS_P

16

SRC_4*

VSS_48

33 5

IN

OUT

CK410_CPU2_ITP_SRC10_N
CK410_CPU2_ITP_SRC10_P
33 5

IN

CK410_CPU0_N
CK410_CPU0_P

SRC_2*
SRC_2

SRC_3
(INT PU) CLKREQ_3*

46 VSS_CPU

475

33 5

PM_STPPCI_L
PM_STPCPU_L

m
il

8 FS_B_TEST_MODE
57 PCI_1
58 PCI_2
63 PCI_3
64 PCI_4

(PULL UP PIN 68 TO ENABLE ITP HOST CLK)


(ICH SM BUS)

23

41

68 PCIF_0/ITP_EN
1 PCIF_1

CK410_PCIF1_CLK

23

CPU_1*
CPU_1

CRITICAL

51 XTAL_IN
50 XTAL_OUT

56 (INT PU)
55 (INT PU)
44
45

CPU_0*
CPU_0

CK410_XTAL_IN
CK410_XTAL_OUT

5%
1/16W
MF-LF
402

0.1UF

10%

20%
2 6.3V
X5R
603

(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)

OUT
OUT
IN
OUT
OUT

(FROM CPU VCORE PWR GOOD)


(ICH7M USB 48MHZ)
(ICH7M,SIO,LPC REF. 14.318MHZ)

IO

CLOCKS
FCTSEL1
0

FCTSEL0
0

PIN 6
DOT96T

PIN 7
DOT96C

PIN 10
100MT_SST

SYNC_MASTER=CLOCK

PIN 11
100MC_SST

DOT96T

DOT96C

SRCT0

SRCC0

27M NON
SPREAD

27M
SPREAD

SRCT0

SRCC0

OFF LOW

TBD

SRCT0

SRCC0

SYNC_DATE=06/03/2005

NOTICE OF PROPRIETARY PROPERTY

* FOR INT. GRAPHIC SYSTEM

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

* FOR EXT. GRAPHIC SYSTEM

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

33

108

R3429
32

32

IN

CK410_PCI1_CLK

CK410_PCI2_CLK

IN

33

TPM

5%
1/16W
MF-LF
402

IN

CK410_PCI3_CLK

33

38

OUT

33

R3413

(TO FIREWIRE PCI 33MHZ)

CK410_CPU0_P

IN

5%
1/16W
MF-LF
402

R3433
32

PCI_CLK_FW

R3430
PCI_CLK_TPM

OUT

53

PCI_CLK_SMC

OUT

45

CK410_CPU0_N

5%
1/16W
MF-LF
402

CK410_CPU1_P

IN

D
33

IN

32

32 5

PCI_CLK_SB

5%
1/16W
MF-LF
402

CK410_USB48_FSA

IN

33

R3417
32

22

OUT

5%
1/16W
MF-LF
402

CK410_CPU1_N

PCI_CLK_PORT80_LPC

5 47

OUT

IN

(PORT80 LPC 33MHZ)


CK410_SRC6_P

IN

SB_CLK48M_USBCTLR

23

=PP1V05_S0_FSB_NB

1K

2 14

NB_BSEL<0>

5%
1/16W
MF-LF
402

R3401

CPU_BSEL<0>

IN

5%
1/16W
MF-LF
402

NOSTUFF
1

R3469
1K

CK410_SRC2_P

IN

5%
1/16W
MF-LF
402

R3465
=PP1V05_S0_FSB_NB

CK410_SRC8_P

IN

NEED TO CHECK THE BSEL PULLS

1K

5%
1/16W
MF-LF
2 402

R3471
32

OUT

CK410_FSB_TEST_MODE

1K

1K

NB_BSEL<1>

2 14

5%
1/16W
MF-LF
402

OUT

CPU_BSEL<1>

(FROM CPU FS_B)

IN

5%
1/16W
MF-LF
402

R3452
1K

NOSTUFF

e
r

R3473
1K

R3474
IN

32

CK410_CLK14P3M_TIMER

1K

R3475

5%
1/16W
MF-LF
402

1K

2 14

NB_BSEL<2>

5%
1/16W
MF-LF
402

R3454
1K

5%
1/16W
MF-LF
2 402

R3476
56

32

IO

IO

CK410_PCI5_FCTSEL1

CK410_REF1_FCTSEL0
1

R3466

R3467

10K
5%

10K
5%

1/16W
MF-LF
2402

1/16W
MF-LF
2402

SET FCTSEL0,FCTSEL1 TO 00
EVEN THESE TWO PINS INTERNAL PULL DOWN,
CYPRESS RECOMMAND TO ADD EXTERNAL PULLS,

CPU_BSEL<2>

IN

(FROM CPU FS_C)

OUT

NB_CLK100M_GCLKIN_P

33 14

NB_CLK100M_GCLKIN_N
SB_CLK100M_DMI_P

OUT

OUT

22 33

OUT

OUT

OUT

SB_CLK100M_SATA_P

OUT

OUT

P
OUT

23

CK410_DOT96_27M_P

NOSTUFF

R3400

1%
1/16W
MF-LF
402

FSB_CLK_CPU_N

1%
1/16W
MF-LF
402

R3405

NB_CLK_DREFCLKIN_P

49.9 2
1%
1/16W
MF-LF
402

R3402

NB_CLK_DREFCLKIN_N

49.9 2

1%
1/16W
MF-LF
402

33 14

NB_CLK_DREFSSCLKIN_P

NOSTUFF

49.9 2

NOSTUFF

1%
1/16W
MF-LF
402

49.9 2

33 36

33 14

NOSTUFF

1%
1/16W
MF-LF
402

NB_CLK100M_GCLKIN_P

R3408
1

49.9 2

NOSTUFF

1%
1/16W
MF-LF
402

R3406

33 36

NB_CLK100M_GCLKIN_N

33 14

33 22

49.9 2

NOSTUFF

1%
1/16W
MF-LF
402

21 33

SB_CLK100M_DMI_P

R3431
1

49.9 2

NOSTUFF

1%
1/16W
MF-LF
402

R3407
33 22

49.9 2
1

SB_CLK100M_DMI_N

1%
1/16W
MF-LF
402

NOSTUFF

R3436

AIRPORT_CLK100M_PCIE_P

49.9 2
1%
1/16W
MF-LF
402

NOSTUFF

R3437
43 33

AIRPORT_CLK100M_PCIE_N

49.9 2
1%
1/16W
MF-LF
402

33 21

33 14

NB_CLK_DREFCLKIN_P

49.9 2
1%
1/16W
MF-LF
402

NOSTUFF

R3482
(GMCH DISPLAY PLLA 96MHZ)

33 21

SB_CLK100M_SATA_N

33 14

NB_CLK_DREFCLKIN_N

NOSTUFF

R3481

SB_CLK100M_SATA_P

OUT

R3410

R3409

49.9 2
1%
1/16W
MF-LF
402

OUT

CK410_LVDS_P

33 14

5%
1/16W
MF-LF
402

NB_CLK_DREFSSCLKIN_P OUT

(GMCH DISPLAY PLLB FOR LVDS SPREAD 100MHZ)

R3421
CK410_LVDS_N

33 14

NB_CLK_DREFSSCLKIN_N

OUT

CLOCK TERMINATION
SYNC_MASTER=CLOCK

32 5

SYNC_DATE=06/06/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

CK410_SRC_CLKREQ8_L

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
1

R3490

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

1K

5%
1/16W
MF-LF
2 402

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7173

SCALE

# NAPA PLATFORM ONLY SUPPORT 133M/166M CPU SPEED, M42 133MHZ

NOSTUFF

NB_CLK_DREFSSCLKIN_N

5%
1/16W
MF-LF
402

CPU
100M
133M
166M
200M

NOSTUFF

R3420
IN

IN

FS_A
1
1
1
0

49.9 2
1

49.9 2
1

33 14

NOSTUFF R3450,R3451,R3453 FOR MANUAL CPU FREQUENCY


FS_B
0
0
1
1

R3442

5%
1/16W
MF-LF
402

(ICH7M 14.318MHZ)

FS_C
1
0
#
0
0

1%
1/16W
MF-LF
402
NOSTUFF

1%
1/16W
MF-LF
402

R3419

CK410_DOT96_27M_N

49.9 2

49.9 2

FSB_CLK_CPU_P

43 33

5%
1/16W
MF-LF
402

IN

R3403

FSB_CLK_NB_N

22 33

21 33

R3404

NOSTUFF

(ICH7M SATA 100MHZ)

SB_CLK100M_SATA_N

1%
1/16W
MF-LF
402
NOSTUFF

1%
1/16W
MF-LF
402

FSB_CLK_NB_P

33 14

(GIGA-LAN PCI-E 100MHZ)

ENET_CLK100M_PCIE_N

R3478
0

33 14

49.9 2

49.9 2

(ICH7M DMI 100MHZ)

ENET_CLK100M_PCIE_P

33 7

R3438
1

NOSTUFF

NOSTUFF

ENET_CLK100M_PCIE_N

36 33

33 7

R3439

(GMCH G_CLKIN 100MHZ)

SB_CLK100M_DMI_N

OUT

R3418

IN

SB_CLK14P3M_TIMER

5%
1/16W
MF-LF
402

32

5%
1/16W
MF-LF
402

(TO MCH FS_C)

OUT

R3453

CPU_BSEL_R<2>

AIRPORT_CLK100M_PCIE_N

1%
1/16W
MF-LF
402

ENET_CLK100M_PCIE_P

33 12

OUT

1%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

CK410_SRC4_N

IN

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

OUT

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

R3451

NOSTUFF

=PP1V05_S0_FSB_NB

CK410_SRC4_P

R3477

(TO MCH FS_B)

IN

CPU_BSEL_R<1>

64 33 19 12

m
il

R3472

33

R3426

CK410_SRC8_N

IN

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

R3470

11 33

R3440
CPU_XDP_CLK_N

33 12

2 43

R3428

CK410_SRC2_N

IN

36 33

49.9 2

49.9 2
1

y
r

11 33

a
n
i

1
NOSTUFF

(WIRELESS PCI-E 100MHZ)

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
2 402

33 11

OUT

AIRPORT_CLK100M_PCIE_P

R3423

R3427

(FROM CPU FS_A)

CPU_XDP_CLK_P

(ITP HOST 133/167MHZ)


CPU_XDP_CLK_N

33 14

CK410_SRC5_N

IN

5%
1/16W
MF-LF
402

(TO MCH FS_A)

R3450

CPU_BSEL_R<0>

5%
1/16W
MF-LF
402

OUT

R3468
1

2.2K 2

CK410_SRC5_P

12 33

OUT

5%
1/16W
MF-LF
402

R3422
IN

CPU_XDP_CLK_P

R3435
1

1K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
402

43 33

CK410_SRC6_N

IN

33 11

ITP

5%
1/16W
MF-LF
402

12 19 33 64

12 33

OUT

5%
1/16W
MF-LF
402

(TO ICH7M USB 48MHZ)

OUT

R3434

R3480

64 33 19 12

FSB_CLK_NB_N

NOSTUFF

R3415

ITP

CK410_CPU2_ITP_SRC10_N

7 33

OUT

(GMCH HOST 133/167MHZ)

CK410_CPU2_ITP_SRC10_P

IN

R3416
32 5

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

FSB_CLK_NB_P

R3412

(TO ICH7M PCI 33MHZ)

R3463

CK410_PCIF0_CLK

33

FSB_CLK_CPU_N

R3441

5%
1/16W
MF-LF
402

R3432
CK410_PCIF1_CLK

7 33

OUT

(CPU HOST 133/167MHZ)

5%
1/16W
MF-LF
402

R3411

IN

IN

(TO SMC PCI 33MHZ)

FSB_CLK_CPU_P

5%
1/16W
MF-LF
402

R3414
IN

(TO TPM PCI 33MHZ)

C
OF

34

108

y
r

Q3810
FDC638P
64

SM-LF

=PP5V_S5_PATA

PP5V_S0_IDE_PATA

MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.35MM
MIN_NECK_WIDTH=0.25MM

5
4
2

R3865

6.2K
5%
1/16W
MF-LF
2 402

=PP3V3_S0_SB
64 25 22

ODD_PWR_EN_SLOW_START_L

R3876

C3876

SB_GPIO5

ODD_PWR_EN_L

26 22

Q3875

2N7002DW-X-F

SOT-363

MAKE_BASE=TRUE

C3875
0.47UF

10%
2 6.3V
CERM-X5R
402

5%
1/16W
MF-LF
402 2

R3851

5%
1/16W
MF-LF
Per ATA Spec
2 402

R3877

23

100K

21

5%
1/16W
MF-LF
2 402

21
21

21
21
21
21

NC
NC

2
4

21

21

OUT

21

OUT

NO STUFF

C3804 1
10pF

5%
50V
CERM 2
402

21

21

17

20

19

22

21

OUT

IDE_PDDREQ

26

32
34
36

NC 38
40

e
r

IDE_PDD<8>
IDE_PDD<9>
IDE_PDD<10>
IDE_PDD<11>
IDE_PDD<12>
IDE_PDD<13>
IDE_PDD<14>
IDE_PDD<15>

15

18

IDE_CSEL_PD

5%
1/16W
MF-LF
2 402

13

16

IDE_PDA<1>
IDE_PDA<0>
IDE_PDCS1_L

NC

11

14

30

21

12

IDE_PDIOW_L

33K

28

IDE_PDIORDY
IDE_IRQ14

NC

8
10

24

21

R3853

51

IDE_RESET_L
IDE_PDD<7>
IDE_PDD<6>
IDE_PDD<5>
IDE_PDD<4>
IDE_PDD<3>
IDE_PDD<2>
IDE_PDD<1>
IDE_PDD<0>

m
il

ODD detect need less than 100ms include OS latency

M-ST-SM

4.7K

SOT-363

CRITICAL

J3801

5-1775184-0

2N7002DW-X-F

a
n
i

10K

20%
10V
CERM
402

6
D

Q3875

ODD_PWR_EN_SLOW_START

NOSTUFF

R38241

0.1UF
ODD_PWR_EN_SLOW_START_L_R

5%
1/16W
MF-LF
2 402

SB_GPIO5 IS PULLED HIGH

10K

5%
1/16W
MF-LF
402

10K

=PP3V3_S0_PATA

R3825
1

=PP5V_S0_IDE_PATA

64

21

21
21
21
21
21
21
21

21
23

IDE_PDIOR_L

21

25
27

IDE_PDDACK_L 21
SMC_ODD_DETECT

29
31

Indicates disk presence, to SMC

NC

33

IDE_PDA<2>
IDE_PDCS3_L

35

21
21

37
39

42

41

44

43

46

45

48

47

50

49

NOSTUFF
1

NC

NC

C3805
0.1uF
10V

52

NC

NOSTUFF
1

C3806
10uF

20%
6.3V
2 X5R
603

20%

2 CERM
402

516S0339

R3858
0

5%
1/16W
MF-LF
2 402

PER ATA SPEC

R3859

PLACE C3805/C3806 CLOSE TO JC901 FOR PP5V_PATA.


APPLY A WIDE TRACE SHAPE FROM JC901 TO C3805/C3806.
MIN_NECK & MIN_LINE WIDTH
ARE CONTROLLED BY PP5V_RUN 1MM / 0.6MM.

6.2K

5%
1/16W
MF-LF
2 402

PER ATA7 SPEC

PATA CONNECTOR

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

38

108

SATA CONNECTOR
Place L3901 near J3901

518S0390

VALUE=3900PF IN REFERENCE SCHEM

L3901
90-OHM-300mA

CRITICAL

SATA_C_R2D_F_P

CAPS TO BE SAME DISTANCE


FROM SB WITHIN EACH PAIR
21 SATA_C_R2D_C_P

C3903

2012H

R3900
1

0.0047UF

J3901

402

SATA_C_R2D_F_N

20247-019E

F-ST-SM
20

C3901

21

SATA_C_R2D_C_N

0.0047UF

100

23

5%
1/16W
MF-LF
402

IN

SATA_C_DET_L

IN

y
r

IN

402

SYM_VER-1

PLACE NEAR ICH7 PIN

1
2

SATA_C_R2D_P
SATA_C_R2D_N

SATA_C_D2R_C_N
SATA_C_D2R_C_P

L3902

C3900
1
2

402

C3902

=PP5V_S0_SATA
NC

NOSTUFF
1

C3920
0.1uF

SATA_C_D2R_P

OUT

R3901
24.9

a
n
i

SYM_VER-1

1%
1/16W
MF-LF
2 402

64

C3921

PLACE L3902 NEAR SB

10uF
20%
2 6.3V
X5R
603

2 10V
CERM

13

SATA_RBIAS_PN

OUT

NOSTUFF

20%

12

SATA_C_D2R_N

MAKE_BASE=TRUE

21

402

11

SATA_C_D2R_F_P

0.0047UF

10

21

0.0047UF

90-OHM-300mA
2012H

SATA_C_D2R_F_N

402

14
15
16
17
18
19

NC
NC
NC

SYSTEM (SLEEP) LED FILTER

21

L3912

600-OHM-300MA
6

SYS_LED_ANODE_L

GND_CHASSIS_SATA

SYS_LED_ANODE

(TO IR RECEIVER)
PP5V_S3_SYSLED_F

C3950

41

C3923

10%
50V
CERM
402

C3922

100

=PP5V_S3_SYSLED

46 64

5%
1/16W
MF-LF
402

4.7UF

20%
6.3V
2 CERM
603

ALTERNATE FOR
PART NUMBER

BOM OPTION

155S0227

155S0164

OUT

GV3902

HOLE-VIA-P5RP25

GV3904

HOLE-VIA-P5RP25

HOLE-VIA-P5RP25

GV3905

GV3906

HOLE-VIA-P5RP25

HOLE-VIA-P5RP25

GV3907

GV3908

HOLE-VIA-P5RP25

HOLE-VIA-P5RP25

e
r

PART NUMBER

OUT

SATA DIFF PAIR GND VIAS

GV3903

m
il

0.01UF
10%
16V
CERM
402

R3950
1

SATA_RBIAS_P

HOLE-VIA-P5RP25

470PF
IR_RX_OUT

SATA_RBIAS_N

21

GV3901

5 46

0402
1

21

REF DES

L3901,L3902

TABLE_ALT_HEAD

COMMENTS:

TABLE_ALT_ITEM

KEEP MAG.LAYER IN BOM

SATA CONNECTOR

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

39

108

PLACE C4100-C4106 NEAR PINS AVDLL0-AVDLL6.

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.22MM

SCHEME MATCHES DOC MVL100258-01

37

L4100
FERR-120-OHM-1.5A

VOLTAGE=2.5V

PP2V5_S3_ENET_AVDD

=PP2V5_S3_ENET

64

0402-LF
1

C4100

C4103

0.1UF

10%
16V
X5R
402

0.1UF

10%
16V
X5R
402

C4105

0.1UF

10%
16V
X5R
402

C4104

C4106

0.001UF

10%
16V
X5R
402

10%
50V
CERM
402

0.001UF

0.1UF

10%
50V
CERM
402

C4107

10%
16V
X5R
402

PLACE C4107 NEAR U4101 AVDD

=PP3V3_S3_ENET

y
r

36 64

PLACE C4110 AND C4111 WITHIN


12 MIL OF U4101 PIN 49 AND 50

SWITCH_VAUX

OUT

NC

24

NC

25

HSDACP
HSDACN

CTRL25

CTRL12

ENET_CTRL25
ENET_CTRL12

1%
1/16W
MF-LF
402

4.75K

NO PULL-UP NEEDED

ENET_RSET

16

NC

59

NC

60

NC

62

NC

63

ANALOG

TESTMODE

VDD25
TX_P

49

TX_N

50

RX_P
RX_N

54

33

REFCLKN

56

33

43 23

26

20

MDIN1

21

MDIP2
MDIN2

26

MDIP3

30

MDIN3

31

OUT
OUT

C4111

C4112

0.1UF

0.1UF
1
1

ENET_CLK100M_PCIE_P
ENET_CLK100M_PCIE_N

MDIP1

PCIE_A_D2R_P
PCIE_A_D2R_N

PCIE_A_R2D_P
PCIE_A_R2D_N

55

17

22

22

PCIE_WAKE_L
ENET_RST_L

27

37

37

37

ENET_VPD_CLK
ENET_VPD_DATA

38

TWSI

VPD_DATA

41

TEST

PU_VDDO_TTL0
PU_VDDO_TTL1

42

SPI_DI

35

NC

SPI_DO
SPI_CLK

34

NC

37

NC

SPI_CS

36

NC

36

m
il

36

ENET_PU_VDD_TTL0 36
ENET_PU_VDD_TTL1 36

43

ASF IS UNAVAILABLE ON 8053

INTERNAL PULL-UP

XTALI

15

XTALO

14

ENET_XTALI
ENET_XTALO

CRITICAL

1. KEEP ENET_XTALI AND ENET_XTALO

65

C4150

5%
50V
CERM
402

C4151
15PF

5%
50V
CERM
402

=PP3V3_S3_ENET

PLACE C4127-C4134 NEAR PINS VDD0-VDD7 ON U4101


SCHEME MATCHES DOC MVL100258-01

=PP1V2_S3_ENET

C4127
0.1UF

10%
16V
X5R
402

C4128
0.1UF

10%
16V
X5R
402

C4129

0.1UF
2

10%
16V
X5R
402

C4130
0.1UF

10%
16V
X5R
402

P
36

ENET_PU_VDD_TTL0

36

ENET_PU_VDD_TTL1

C4131

0.001UF

10%
50V
CERM
402

C4132

R4130

10%
50V
CERM
402

R4131

4.7K

4.7K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

64 36

R4104

49.9

49.9

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

R4103

R4119

49.9

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

ENET_MDI2

C4115

0.001UF

10%
50V
CERM
402

10%
50V
CERM
402

C4133

0.001UF
2

10%
50V
CERM
402

ENET_MDI_P<1>
ENET_MDI_N<1>

IO

ENET_MDI_P<2>
ENET_MDI_N<2>

IO

ENET_MDI_P<3>
ENET_MDI_N<3>

IO

IO

IO

IO

IO

R4117
49.9

1%
1/16W
MF-LF
402

C4118
0.001UF

10%
50V
CERM
402

PLACE RESISTORS CLOSE TO U4101

36 64

64 36

=PP3V3_S3_ENET
PLACE C4140 NEAR U4102 VCC
1

C4140
0.1UF

10%
16V
X5R
402

OMIT

CRITICAL 8
VCC
3 E2
2 NC1
U4102 SDA
1 NC0
M24C08 SCL
7 WC*
SO8

PLACE C4135-C4139 NEAR VDDO_TTL0-VDD_TTL4 ON U4101


SCHEME MATCHES DOC MVL100258-01

VSS

=PP3V3_S3_ENET

C4134

0.001UF
2

IO

1
1

ENET_MDI_P<0>
ENET_MDI_N<0>

ENET_MDI3

C4117

0.001UF

10%
50V
CERM
402

R4118

49.9

1%
1/16W
MF-LF
402

0.001UF

49.9

1%
1/16W
MF-LF
402

ENET_MDI1

C4116

R4120

49.9

0.001UF

R4105

49.9

ENET_MDI0

2. DO NOT ROUTE UNDER CRYSTAL

15PF

R4106

TRACE LENGTH <12MIL

1
2

e
r
1

10%
16V
X5R
402

a
n
i

402
X5R
16V
10%

IN

37

Y4101

0.1UF

0.1UF

IN

37

25.0000M

C4126

IN

IN

37

SM-3.2X2.5MM

C4113

PCIE_A_R2D_C_P
PCIE_A_R2D_C_N

37

IN

OUT

NC NC

22

37

VPD_CLK

TEST

MAIN CLK

22

PLACE C4113 AND C4112 WITHIN


12 MIL OF U2100 E27 AND E28

18

THRML_PAD

MEDIA

SPI

64 36

X5R
10%
16V

402

53

MDIP0
MDIN0

402

REFCLKP

WAKE*
PERST*

LED

LED_LINK1000*
LINK*

46

64

19

22

PCI EXPRESS

LED_ACT*
LED_LINK10/100*

TSTPT

10%
16V
X5R

88E8053

RSET

29

AVDDL0

28

32

51

AVDDL2
AVDDL1

52

AVDDL4
AVDDL3

57

AVDDL5

AVDD

AVDDL6

23

45

U4101

C4135

0.1UF

10%
50V
CERM
402

10%
16V
X5R
402

C4136

0.1UF
2

10%
16V
X5R
402

C4137

0.1UF
2

10%
16V
X5R
402

C4138

0.001UF

0.001UF
2

10%
50V
CERM
402

C4139

NC

CRITICAL

5%
1/16W
MF-LF
402

VMAIN_AVLBL
SWITCH_VCC

OMIT

PCIE_A_D2R_C_N

4.7K

11

47
NC

VDDO_TTL1
VDDO_TTL0

VAUX_AVLBL

40

LOM_DISABLE*

12

PCIE_A_D2R_C_P

R4122

OUT

R4102

10

QFN

OPTIONAL EXTERNAL LDO

64

=PP3V3_S3_ENET
=PP3V3_S0_ENET

VDDO_TTL2

5%
1/16W
MF-LF
402
64 36

VDDO_TTL4
VDDO_TTL3

61

VDD0

13

VDD2
VDD1

33

39

VDD3

44

ENET_LOM_DIS_L

48

58

VDD5
VDD4

VDD6

SB_GPIO30 1

VDD7

R4107
22

10%
16V
X5R

402

4.7K

C4110
0.1UF

NOSTUFF

R4123

=PP3V3_S3_ENET

36 64

5%
1/16W
MF-LF
2 402

4.7K

R4101=PP1V2_S3_ENET

5%
1/16W
MF-LF
402

64 36

10%
6.3V
CERM
402

C4102

0.1UF

1UF
2

C4101

ENET_VPD_DATA

36

ENET_VPD_CLK

36

NOSTUFF
1

R4124
0

5%
1/16W
MF-LF
2 402

ETHERNET CONTROLLER

10%
50V
CERM
402

SYNC_MASTER=ENET

SYNC_DATE=12/06/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

41

108

y
r

L4250
120-OHM-0.3A-EMI
1
36 PP2V5_S3_ENET_AVDD

2PP2V5_S3_ENET_AVDD_F

PLACE ONE CAP AT EACH PIN 3 AND 6 OF TRANSFORMERS

0402-LF
1

C4200

C4201

C4202

0.1UF

0.1UF

0.1UF

10%
16V
X5R
402

10%
16V
X5R
402

10%
16V
X5R
402

C4203
0.1UF
10%
16V
X5R
402

a
n
i

PLACE ONE CAP NEAR EACH PIN 3 AND 6 OF TRANSFORMERS

C4204

C4205

C4206

0.001UF

0.001UF

0.001UF

10%
50V
CERM
402

10%
50V
CERM
402

10%
50V
CERM
402

C4207
0.001UF
10%
50V
CERM
402

CROSS-OVERS ARE IN SCHEMATIC TO EASE ROUTING

C
CRITICAL
1000BT-824-00275

T4201
36

ENET_MDI_P<0>

IO

36

ENET_MDI_N<0>

IO

XFR-SM

36

36

CHIP
SIDE

NC1
NC2

LINE
SIDE

ENET_MDI_TRAN_P<0>

15

ENET_MDI_TRAN_N<0>

14

3
4

16

NC4
NC3

ENET_CENTER_TAP<0>

m
il

13
12

11

ENET_MDI_P<1>

10

IO

IO

ENET_MDI_N<1>

ENET_CENTER_TAP<1>

ENET_MDI_TRAN_P<1>

ENET_MDI_TRAN_N<1>

CRITICAL
1000BT-824-00275

T4202
XFR-SM

ENET_MDI_P<3>

IO

36

ENET_MDI_N<3>

15

IO

14

36

36

NC1
NC2

LINE
SIDE

CHIP
SIDE

36

16

NC4
NC3

e
r

12

11

ENET_MDI_P<2>

10

IO

IO

ENET_MDI_N<2>

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

BOM OPTION

157S0037

157S0011

REF DES

COMMENTS:

TABLE_ALT_ITEM

T4201,T4202

E&E AND DELTA TRANSFORMER

ENET_CENTER_TAP<2>

ENET_CENTER_TAP<3>

R4200

R4201

75

75

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

RJ45
819B-3608-M280
10

F-RT-SM
SYM_VER-2

1
2
3
4
5
6
7
8

514S0119

ENET_MDI_TRAN_N<3>

ENET_MDI_TRAN_P<2>

ENET_MDI_TRAN_N<2>

R4202

75

J4200

ENET_MDI_TRAN_P<3>

13

OMIT
CRITICAL

R4203
75

1%
1/16W
MF-LF
402

ENET_BOB_SMITH_CAP
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM

C4210

0.001UF

20%
2KV
CERM
1808

=GND_CHASSIS_RJ45

OUT

ETHERNET CONNECTOR
SYNC_MASTER=ENET

C4211

0.001UF

10%
2 50V
CERM
402

C4212

SYNC_DATE=11/14/2005

NOTICE OF PROPRIETARY PROPERTY

0.001UF

10%
2 50V
CERM
402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

PLACE C4211 AND C4212


ON EACH SIDE OF J4200

SIZE

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION
TABLE_5_ITEM

514S0143

CONN,8P RJ-45 JACK,MIDPLANE,MG3,LF

J4200

CRITICAL

APPLE COMPUTER INC.

NORMAL

CONN,8P RJ-45 JACK,MIDPLANE,BLACK,LF

J4200

CRITICAL

FANCY

SHT
NONE

REV.

051-7173

SCALE

TABLE_5_ITEM

514S0144

DRAWING NUMBER

C
OF

42

108

PAGE NOTES
MOBILE TURNS OFF CONTROLLER POWER DURING SLEEP
0.001A DURING SLEEP

INPUT
=PP3V3_S0_FW - 3.3V POWER FOR FIREWIRE (MOBILE: OFF DURING SLEEP)
=PP3V3_S0_PCI - 3.3V POWER FOR PCI FIREWIRE (MOBILE: OFF DURING SLEEP)
PCI_GNT3_L - PCI GRANT FROM SB
PCI_CLK_FW - NEED TO REFERENCE TO ALIAS PAGE
PCI_RST_L - PCI RESET FROM SB
FW_PC0 - FIREWIRE POWER CLASS IDENTIFIER

64

=PP3V3_S3_FW
PLACE ONE CAP PER TWO PINS STARTING WITH C4424 ON VDD0
1

C4424

10UF

PCI_AD<0..31>,PCI_C_BE_L<0..3>,PCI_FRAME_L,PCI_IRDY_L,PCI_TRDY_L,
PCI_DEVSEL_L, PCI_STOP_L, PCI_PAR, PCI_PERR_L, PCI_SERR_L
FW_A_TPA_P/N, FW_A_TPB_P/N, FW_A_TPBIAS - PORT 0 FIREWIRE DIFF PAIRS
FW_B_TPA_P/N, FW_B_TPB_P/N, FW_B_TPBIAS - PORT 1 FIREWIRE DIFF PAIRS
FW_C_TPA_P/N, FW_C_TPB_P/N, FW_C_TPBIAS - PORT 2 FIREWIRE DIFF PAIRS

C4418
0.1UF

L4400

PCI_REQ3_L - PCI REQUEST TO SB


PM_CLKRUN_L - CLOCK-RUN PCI PROTOCOL
INT_PIRQD_L - INTERRUPT TO SB
PCI_PME_FW_L - DEDICATED PME FOR FIREWIRE (SB GPIO1)

C4422

C4426

C4428

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C4430

0.1UF

C4432
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

y
r

PLACE ONE CAP PER TWO PINS STARTING WITH C4416 ON VDDA0

600-OHM-300MA

OUTPUT

0.1UF

20%
2 10V
CERM
402

20%
2 6.3V
X5R
603

INPUT/OUTPUT

PP3V3_S3_FW_AVDD

0402

C4416

C4417

10UF

0.1UF

20%
2 6.3V
X5R
603

C4429
0.1UF

10%
2 16V
X5R
402

10%
2 16V
X5R
402

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM

C4425
0.1UF

10%
2 16V
X5R
402

PAGE HISTORY

64

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22
22

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

e
r

IO

P
IN

22

PCI_RST_L

IO

22

IO

22

22

IO

22

IO

22

IO

22

IO
IO

R44311
22

5%
1/16W
MF-LF
402 2

IO
IO
IO
IO
IO

OUT
IN

IO
IO

IN

R4432
1

100

22
26
22

26
22
26
22
26
22
26
22

26 22
22
26
22
26
22

33

IO

PCI_AD7
PCI_AD8
PCI_AD9

PCI_PAR
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_DEVSEL_L
PCI_STOP_L
FW_PCI_IDSEL
PCI_REQ3_L
PCI_GNT3_L
PCI_PERR_L
PCI_SERR_L

E2
E1
M8
N9

PCI_CLK_FW
PM_CLKRUN_L

PCI_AD10

PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18

XI

A5

FW_XI

XO

B5

FW_XO

OUT
OUT

FW_PCI_RST_L
INT_PIRQD_L
22 PCI_PME_FW_L

26 22

390

CRITICAL

Y4403

SM-3.2X2.5MM

24.576MHZ

FW_XO_R

2 4

C4411 1

B4

FW_PWRON_RST_L

R1

A6

FW_R1

SPEC RECOMMENDS 2.49K

R0

TPBIAS0
TPA0_P
TPA0_N

TPB0_P
TPB0_N

PCI_AD19
PCI_AD20

TPBIAS1

PCI_AD21

TPA1_P
TPA1_N

PCI_AD22
PCI_AD23

TPB1_P

PCI_AD24

TPB1_N
TPBIAS2

PCI_AD25
PCI_AD26

TPA2_P
TPA2_N
TPB2_P

PCI_AD27
PCI_AD28

TPB2_N

PCI_AD29

FW_R0

B7

B8
A9
B9
B10
A10
D8
A11
B11
B12
A12
C13
C11
C12
D13
D12

39

39

39

39
39

6
6
6
6
6
6
6
6
6
6

R4452

C4420
0.1UF

10%
2 16V
X5R
402

2.1K

1%
1/16W
MF-LF
2 402

FW_A_TPBIAS
FW_A_TPA_P
FW_A_TPA_N
FW_A_TPB_P
FW_A_TPB_N
FW_B_TPBIAS
FW_B_TPA_P
FW_B_TPA_N
FW_B_TPB_P
FW_B_TPB_N
FW_C_TPBIAS
FW_C_TPA_P
FW_C_TPA_N
FW_C_TPB_P
FW_C_TPB_N

C4412

15pF

5%
50V
CERM 2
402

RESET*

5%
2 50V
CERM
402

NEED TO CHECK CRYSTAL LOAD CAPACITANCE

R4420
510K

5%
1/16W
MF-LF
2 402

IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

IO
IO
IO

PCI_AD30
PCI_AD31

PCI_CBE1*
PCI_CBE2*
PCI_CBE3*

MODE_420

PCI_FRAME*
PCI_IRDY*

MODE_A

PCI_TRDY*

PC0

PCI_DEVSEL*
PCI_STOP*

PC1
PC2
CONTENDER

PCI_IDSEL

CARDBUSN
MPCI_ACTN_323

PCI_REQ*
PCI_GNT*
PCI_PERR*

TEST0

PCI_SERR*

TEST1

MANUFACTURING TEST PINS

G2 PCI_CLK
D1 CLKRUN*

PTEST
SE
SM

1%
1/16W
MF-LF
402

22

BGA

m
il

PCI_AD<19>
IO

U4400
FW32306

PCI_AD5
PCI_AD6

197S0030 3.2MMX2.5MM

15pF

CRITICAL

PCI_AD3
PCI_AD4

VDDA5

22

OMIT

PCI_AD2

VDDA4
VDDA3

IO

PCI_AD0
PCI_AD1

VDDA2

22

VDDA1
VDDA0

22

IO

VDD9

PCI_PAR

IO

VDD7

N10
N6
M6
N7
N8
M7
L2

22

VDD6
VDD5

PCI_CBE0*

IO

VDD4

22

K12
M9
L3
L1

IO

22

VDD3
VDD2

IO

PCI_C_BE_L<0>
PCI_C_BE_L<1>
PCI_C_BE_L<2>
PCI_C_BE_L<3>

22

IO

PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>

22

IO

R4400
5%
1/16W
MF-LF
402

G13 PCI_VIOS
F10
G10
H10
H12
J13
J12
K13
K10
L12
M13
L11
M12
M11
N12
M10
N11
M4
N5
N4
M3
M2
N3
K4
M1
K2
J4
K1
J2
J1
H2
H4
H1

IO

VDD1

VDD0

CONNECT TO VDD FOR 3.3V OPERATION

a
n
i

=PP3V3_S3_PCI

D10
A13
B13
A7
A8
D6

FIRST REVISION OF PAGE


BGA VERSION OF FW323-06 ADDED
CHANGED INT* TO INT_PIRQD_L (PER ARCHITECTURAL DEFINITION)
CHANGED PCI_ID TO AD19 (PER ARCHITECTURAL DEFINITION)
CHANGED REQ/GNT TO REQ3/GNT3 (PER ARCHITECTURAL DEFINITION)
ADDED 510K PULL-DOWN ON RST* AND REMOVED CONNECTION TO PLT_RST_L
CHANGED CLK,PME,DIFF PAIR NAMES TO BE RE-USE COMPLIANT
REMOVED CONSTRAINT SETS AS THEY WILL BE MANAGED ON BOARD SIDE
REMOVED C4421 - REDUNDANT
BRING OUT PC0 CONNECTION TO BE CONNECTED ON PORT PAGE
CONNECTED PIN E10 TO GND

A2

G4
N1
N2
K5
K6
K7
L13
H13

M5
B6
E12
F13
F12
G12
B1
E10

MODE FOR EXTERNAL LINK

39

FW_PC0

IO

DUAL PORT DEVICES ARE POWER CLASS 4 (100)


SINGLE PORT DEVICES ARE POWER CLASS 0 (000)

LOW = NOT BUS MANAGER


LOW = PCI OPERATION

C2
C1
A4
A3
B3

FIREWIRE CONTROLLER

F1 PCI_RST*
D2 PCI_INTA*
F2 PCI_PME*

SYNC_MASTER=ENET

SYNC_DATE=08/30/2005

NOTICE OF PROPRIETARY PROPERTY

THIS IS FROM ICH-7M

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

VSSA3
VSSA4

VSSA1
VSSA2

VSSA0

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

E13
E9
D9
D7
D5

VSS21
VSS22

VSS20

VSS18
VSS19

VSS17

VSS15
VSS16

VSS11

VSS9
VSS10

VSS8

VSS6
VSS7

VSS4
VSS5

VSS3

VSS1
VSS2

A1
B2
C3
D4
E4
E5
F4
F6
F7
F8
G1
G6
G7
G8
H6
H7
H8
J5
J9
J10
K8
K9
N13

VSS0

PLACE R4432 VERY CLOSE TO PIN B18 OF U2100


VSS12
VSS13
VSS14

5/19/2005
6/20/2005
6/21/2005
6/21/2005
6/21/2005
6/22/2005
6/22/2005
6/22/2005
6/22/2005
6/22/2005
7/26/2005

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

44

108

Page Notes
INPUT:
=PPBUS_FW - PORT POWER
=PP3V3_S5_FW - DIGITAL POWER
=GND_CHASSIS_FW_PORT0 - CHASSIS GROUND
=FWPWR_PWRON - ADDITIONAL POWER CONTROL

INPUT/OUTPUT:
FW_TPA0_P/N,FW_TPB0_P/N,FW_TPBIAS0 - FIREWIRE DIFF PAIRS

OUTPUT:

PPBUS_S5_FWPWRSW_F

FW_PC0 - POWER CLASS IDENTIFIER (SINGLE PORT - TIE LOW)

VOLTAGE=18.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

PPFW_SWITCH

Q4590

PAGE HISTORY
5/19/05
6/22/05
6/22/05
6/22/05
7/26/05
7/26/05
7/26/05
7/26/05
7/26/05
7/26/05
7/26/05

FDC638P

FL4590

INITIAL REVISION
CHANGED DIFF PAIR NAMES TO MATCH REUSE
REMOVED CONSTRAINTS BECAUSE USING ALLEGRO CONST MANAGER
CONNECTED FW_PC0 FOR SINGLE PORT
UPDATED LATE-VG POWER RAIL CIRCUIT FROM M1
CHANGED CONNECTOR PORT NAMING TO PORT0
SWITCHED TO 514-0124 FOR PRE-PROTO CONNECTOR
REMOVED R4520 - IT HASNT BEEN STUFFED FOR MANY PRODUCTS
CHANGED FL4590 TO 1.1A VERSION
REMOVED ETHERNET LOW-POWER MODE CIRCUIT
UPDATED SIGNAL NAMES FOR FW PORT POWER ENABLE

SM-LF

1.1A-24V
64

=PPBUS_S5_FWPWRSW

y
r

VOLTAGE=19V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

D4590
SMB

5
4

MINISMDC

B340LBXF

R4590 1
64

470K

=PP3V3_S0_FW

5%
1/16W
MF-LF
402 2

1394b implementation based on Apple


FireWire Design Guide (FWDG 0.6, 5/14/03)

IF =FWPWR_PWRON IS NC:

PPFW_PORT0_VP_F

5%
1/16W
MF-LF
402 2

SOT-363
1

FWPWR_RUN

VOLTAGE=16.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

330K

L4510

FERR-250-OHM

FWPWR_EN_L

D4591
5

Q4591

OUT

FWPWR_EN

D4591

FW_PC0
65 46 45 5

10K

SMC_PS_ON

SOT23-LF

BAS16TW-X-F

R4594

SOT-363
3

FWPWR_ACIN

C4510

0.001uF

2N7002

1 FOR DUAL PORT

SM

SOT-363

=FWPWR_PWRON

60

MIN_LINE_WIDTH=0.05MM
MIN_NECK_WIDTH=0.05MM

BAS16TW-X-F

0 FOR SINGLE PORT

38

a
n
i
Cable Power

R4591 1

D4591

ENABLES PORT POWER WHEN MACHINE IS RUNNING


OR ON AC AND NOT SHUTDOWN
6

10%
16V
CERM
402

BAS16TW-X-F
2

ENABLES PORT POWER WHEN MACHINE IS RUNNING


OR ON AC
IF =FWPWR_PWRON LOW WHEN OFF:

PORT POWER CLASS

0.01uF
2

MIN_LINE_WIDTH=0.05MM
MIN_NECK_WIDTH=0.05MM

100K
5%
1/16W
MF-LF
402

C4590

FWPWR_EN_L_DIV

R4593 1

5%
1/16W
MF-LF
402

m
il

Enables port power whenever


machine AC Adapter is plugged
or system at run state with battery only

R4595
470K

5%
1/16W
MF-LF
402

PPFW_PORT0_VP

VOLTAGE=16.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

10%
50V
CERM
402

"Snapback" & "Late VG" Protection

39

[LATE VG NOTES]
CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V
IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A 0.5V DROP
38

IO

FW_A_TPBIAS

PP3V3_S5_FWLATEVG

D4520

0.01UF

LATE-VG PROTECTION POWER


PP3V3_S5_FWLATEVG_F

330

NO STUFF
1

SM-1

5%
1/16W
MF-LF
402

C4551

38

P
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.35MM
MIN_NECK_WIDTH=0.25MM

400-OHM-EMI
1

38

IO

PP3V3_S5_FWLATEVG

L4550

R4550

IO

NO STUFF
1

C4552

0.1uF

0.001uF

20%
10V
CERM
402

10%
50V
CERM
402

R4501
56.2

1%
1/16W
MF-LF
2 402

1%
1/16W
MF-LF
2 402

0.33UF

10%
6.3V
CERM-X5R
402

R4502
56.2

1%
1/16W
MF-LF
2 402

0.01UF

10%
16V
CERM 2
402

120-OHM

56.2

1%
1/16W
MF-LF
2 402

0.01UF

D4521
BAV99DW-X-F

1%
1/16W
MF-LF
402

F-RT-TH1

FW_PORT0_TPA_P_FL

FW_PORT0_TPA_N_FL

FW_PORT0_TPB_P_FL

FW_PORT0_TPB_N_FL

SYM_VER-2

FL4521

SOT-363

(PPFW_PORT0_VP)

(GND_FW_PORT0_VGND)

C4523

0.01UF

C4524
0.01UF

10%
50V
2 X7R
603-1

10%
16V
CERM 2
402

(TPA-)

TPI

(TPB+)

TPI#

(TPB-)

0.01uF
10%
16V
CERM
402

(TPA+)

TPO#

VGND
7

C4525

TPO

VP

5
6

1394A

2012

D4521

10%
16V
CERM 2
402

SYM_VER-2

120-OHM

BAV99DW-X-F

C4522 1

4.99K

CRITICAL

FL4520

SOT-363

R4504

J4500
1

OMIT

2012
2

FW_PORT0_TPB_N

R4503

PORT 0
1394A

6
1

FW_PORT0_TPB_P

220PF

39

FW_PORT0_TPA_N

C4501
5%
25V
CERM
402

SOT-363

FW_PORT0_TPA_P

FW_PORT0_TPB

BAV99DW-X-F

C4521

=GND_CHASSIS_FW_UPPER

Plexi: 514-0124
Enclosure: 514-0289

=GND_CHASSIS_FW_DOWN

TABLE_5_HEAD

PART#

=PP3V3_S5_FWLATEVG

IO

38

FW_A_TPA_P
FW_A_TPA_N
FW_A_TPB_P
FW_A_TPB_N

56.2

D4550
SOT23

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION
TABLE_5_ITEM

MMBZ5227B

514-0359

CONN,6P 1394A RCPT,MIDPLANE,MG3,LF

J4500

CRITICAL

NORMAL

514-0316

CONN,6P 1394A RCPT,MIDPLANE,BLACK,LF

J4500

CRITICAL

FANCY

FIREWIRE PORT

TABLE_5_ITEM

64

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.35MM
MIN_NECK_WIDTH=0.25MM

38

R4500

SOT-363

10%
16V
CERM 2
402

C4500

e
r
1

IO

D4520

BAV99DW-X-F

C4520 1

SYNC_MASTER=ENET

SYNC_DATE=11/16/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

CAPS MAY NOT BE NECESSARY.


NO STUFF FOR NOW THOUGH

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

45

108

GEYSER AND DIMM0 REMOTE TEMP SENSORS


D

y
r

L4900

600-OHM-300MA
=PP5V_S3_GEYSER

64

2
0402

R4910
SMC_ONOFF_L

48 46 45

CONN_GEYSER_ONOFF_L
1

C4910
0.1uF

VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM

0.1uF

20%
10V
CERM
402

F-ST-SM

SM

SYM_VER-1

=USB2_GEYSER_N

a
n
i

OMIT

CRITICAL

J4900
53307-1071

L4901
90-OHM
=USB2_GEYSER_P

C4900

20%
10V
2 CERM
402

CRITICAL

CONN_GEYSER_ONOFF_FLTR_L

5%
1/16W
MF-LF
402

MAKE_BASE=TRUE
OUT

1K

PLACE C4900 NEAR J4900

PP5V_S3_GEYSER_F

CONN_GEYSER_USB_P
CONN_GEYSER_USB_N

10

27
27

SMC_LID

PLACE L4901 NEAR J4900

L4902

CRITICAL

D4900
SC-75

600-OHM-300MA
1
2 GEYSER_GND_F
0402

516S0251

49

IN

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
VOLTAGE=0V

THRM_DIMM0_DXN

m
il

RCLAMP0502B

49

IO
IO

5 45 46 65

THRM_DIMM0_DXP1

IN

RESERVE FOR POSSUM BUILD DEBUG USE

3
2

=SMB_GEYSER_CLK
=SMB_GEYSER_DATA

PART#

QTY

516S0482

516S0482

DESCRIPTION

REFERENCE DESIGNATOR(S)

TABLE_5_HEAD

CRITICAL

BOM OPTION
TABLE_5_ITEM

ACES 88646-1071-NS

J4900

CRITICAL

NORMAL

ACES 88646-1071-NS

J4900

CRITICAL

FANCY

TABLE_5_ITEM

e
r

CONNECTOR MISC
SYNC_MASTER=ENET

SYNC_DATE=11/16/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

49

108

PLACE C5100 AND C5101


NEAR U5100 PIN 22 AND 49

D
64

y
r

=PP5V_S3_IR

C5100
0.1UF

C5101
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

22 49

a
n
i

OMIT

VDD

U5100

6
6

20

=USB2_IR_P
=USB2_IR_N

21

CY8C24794
MLF

D+
D-

45

P0_0
P0_1
46
P0_2
53
P0_3
47
P0_4
52
P0_5
48 P0_6
51
P0_7

P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7

41

P2_0
P2_1
P2_2
1
P2_3
43
P2_4
56
P2_5
44
P2_6
55
P2_7

P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7

37

P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7

54

R5100
35

IR_RX_OUT

100
5%
1/16W
MF-LF
402

42

C5102

0.001UF
10%
50V
402

2 CERM

P4_0
P4_1
38
P4_2
5
P4_3
39
P4_4
4
P4_5
40
P4_6
3
P4_7
6

C5102 CLOSE TO U5100 PIN 2

e
r

26
17
27
16
28
15

33

m
il

IR_RX_OUT_F

25
18

24
23

P7_0
P7_7

THRML
PAD

10

34
9

35
8

36
7

29
14
30
13
31
12
32
11

57

VSS

19 50

IR CONTROLLER
SYNC_MASTER=ENET

SYNC_DATE=11/09/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

51

108

USB 2.0 CONNECTORS


42

L5202

PP5V_S3_USB2_EXTA_F
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
VOLTAGE=5V

FERR-120-OHM-1.5A
2

0402-LF

y
r

PLACE L5200 NEAR J5200


ROUTE USB DATA LINES AS DIFFERENTIAL PAIRS
CRITICAL

L5200
90-OHM
SM
SYM_VER-1

64

=PP5V_S5_USB
6

C5213

10uF
20%
6.3V

2 X5R
603

1K

C5250
0.47UF

a
n
i
1

D5200
SC-75

C5208
0.1UF
20%

2 10V
CERM
402

CRITICAL

U5200

CRITICAL
1

C5210

42 6

100UF

2
8
3
5
4

IN

OUT1

20%
2 6.3V
POLY
B2

RCLAMP0502B

OC1*
OUT2

OC2*

PP5V_S3_USB2_EXTA
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM

MSOP
EN1*

PP5V_S3_USB2_EXTB
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM

EN2*

42

GND TPAD

R5251
=EXTBUSB_OC_L

1K

0.47UF

C5209

0.1UF
20%

C5211
100UF

20%
2 6.3V
POLY
B2

10V
402

2 CERM

63

m
il

CRITICAL

NOSTUFF
1

10%
2 6.3V
CERM-X5R
402

PM_SLP_S4_LS5V

e
r

P
PART#

QTY

DESCRIPTION

USB

1 VBUS

PP5V_S3_USB2_EXTA_F
USB2_EXTA_F_N
USB2_EXTA_F_P
USB2_GND_EXTA_F

D-

D+

GND

C5202

0.01UF

C5203
0.01UF

10%
2 16V
CERM
402

10%
2 16V
CERM
402

LAYOUT NOTE:C5202,C5203 ARE EMC BY-PASS CAPS FOR J5200

42 6

=GND_CHASSIS_USB

0402-LF

OMIT

PLACE L5201 NEAR J5201


ROUTE USB DATA LINES AS DIFFERENTIAL PAIRS

CRITICAL

J5201
USB

CRITICAL

F-RT-TH-M42
5

L5201
90-OHM
SM
SYM_VER-1

42

=USB2_EXTB_N

=USB2_EXTB_P

42 6

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
VOLTAGE=5V

FERR-120-OHM-1.5A

2 EXTBUSB_OC_F_L

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
VOLTAGE=0V

J5200
F-RT-TH-M42
5

PP5V_S3_USB2_EXTB_F

L5203

5%
1/16W
MF-LF
402

C5251

=GND_CHASSIS_USB

TPS2042B

10%
6.3V
2 CERM-X5R
402

0402-LF

CRITICAL

2 EXTAUSB_OC_F_L

5%
1/16W
MF-LF
402

FERR-120-OHM-1.5A

20%
10V
CERM
402

R5250
1

C5212

NOSTUFF

=EXTAUSB_OC_L

=USB2_EXTA_P

0.1UF
2

42

L5204

=USB2_EXTA_N

OMIT
CRITICAL

=GND_CHASSIS_USB

PP5V_S3_USB2_EXTB_F
USB2_EXTB_F_N
USB2_EXTB_F_P
USB2_GND_EXTB_F

VBUS

D-

D+

GND

CRITICAL

D5201
SC-75

C5206

0.01UF

10%
2 16V
CERM
402

3
2

C5207
0.01UF

10%
2 16V
CERM
402

LAYOUT NOTE:C5206,C5207 ARE EMC BY-PASS CAPS FOR J5201

RCLAMP0502B
42 6

=GND_CHASSIS_USB

L5205

FERR-120-OHM-1.5A MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
1

VOLTAGE=0V

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

0402-LF
TABLE_5_ITEM

514-0288

CONN,4P USB RCPT,MIDPLANE,MG3,LF

J5200,J5201

CRITICAL

NORMAL

514-0315

CONN,4P USB RCPT,MIDPLANE,BLACK,LF

J5200,J5201

CRITICAL

FANCY

TABLE_5_ITEM

DESCRIPTION:
USB EXTERNAL CONNECTORS

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

52

108

=PP1V5_S0_AIRPORT
1

C5304

C5305

0.1UF
2

20%
10V
CERM
402

0.1UF
2

20%
10V
CERM
402

a
n
i
=PP3V3_S0_AIRPORT

CRITICAL

J5300
AS0B22-S45N-7F
F-ST-SM

C5308

36 23

IN

PCIE_WAKE_L

20%
10V
CERM
402

32

OUT

CK410_SRC_CLKREQ6_L

10
12

33

IN

AIRPORT_CLK100M_PCIE_N

11

33

IN

AIRPORT_CLK100M_PCIE_P

13

14

15

16

17

22
22

OUT
OUT

22

IN

PCIE_B_D2R_P

IN

PCIE_B_R2D_C_N
PCIE_B_R2D_C_P

0.1UF

2 0.1UF

PCIE_B_R2D_N
PCIE_B_R2D_P

C5301
PLACE CAPS < 250 MILS FROM (U2100) SB

e
r

KEY

18

19

20

21

22

PP3V3_S3_AIRPORT_AUX_CONN
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V

24
26

27

28

29

30

SMB_AIRPORT_CONN_CLK

31

32

SMB_AIRPORT_CONN_DATA

33

34

35

36

37

38

40

42

43

44

45

46

47

48

49

50

51

52

AIRPORT_RST_L

IN

5%
1/16W
MF-LF
402

=PP3V3_S3_AIRPORT_AUX
1

C5309

10UF

25

41

20%
10V
CERM
402

R5303

23

39

C5307

26

m
il

PCIE_B_D2R_N

C5300
22

64

0.1UF

0.1UF

54

y
r

0.1UF

20%
10V
CERM
402

64

C5306

20%
6.3V
2 X5R
603

64

C5310
0.1UF

20%
10V
2 CERM
402

402 1/16W
R5301 MF-LF
5%

27

=SMB_AIRPORT_CLK

IO

27

=SMB_AIRPORT_DATA

IO

R5302

1/16W
402
MF-LF 5%

6 =USB2_AIRPORT_N

6 =USB2_AIRPORT_P

IO
IO

SB HAS INTERNAL 15K PULL-DOWNS

53

CONNECT TO M35 MODULE

Plexi: 516S0363
* Enclosure: 516S0406

AIRPORT CONN

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

53

108

y
r

a
n
i

PLACE L5410 NEAR J5400

L5410

PLACE C5498 C5499 NEAR L5410


64

120-OHM-0.3A-EMI
1

=PP3V3_S3_BT

NOSTUFF
NOSTUFF

C5499

0.1UF

10UF
2

20%
6.3V
X5R
603

0402-LF

C5498

20%
10V
CERM
402

PP3V3_S3_BT_F
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V

CRITICAL

J5400

88611-04001

CRITICAL

F-ST-SM
5

L5400
90-OHM
SM

SB HAS INTERNAL 15K PULL-DOWNS

m
il
SYM_VER-1

6
6

=USB2_BT_N
=USB2_BT_P

USB2_BT_F_N

USB2_BT_F_P

3
4

PLACE L5400 NEAR J5400

GND_BT_F

L5411

120-OHM-0.3A-EMI
1

TO M13D SLOT

518S0334

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

0402-LF

PLACE L5411 NEAR J5400

e
r

BLUETOOTH INTERFACE

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

54

108

OMIT
64 48 46 45

OUT

23

OUT
46

46
46
46
66 46 5

OUT

66 46 5

OUT
46
46

53 47 21 5

IO

53 47 21 5

IO

53 47 21 5

IO

53 47 21 5

IN

26

IN

33
53 47 23 5

IN
OUT
OUT

46

OUT

27

IO

53

OUT
46

OUT
46
46

47 46 5

OUT

47 46 5

IN

27

SMC_P20
SMC_P21
SMC_P22
SMC_P23
SMC_BATT_TRICKLE_EN_L
SMC_BATT_CHG_EN
SMC_P26
SMC_P27

D13
D14
D15
E12
E14
E15
E13
F14

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
PCI_CLK_SMC
INT_SERIRQ

IO

53 47 21 5

P61/KIN1*

IO

D9
C9
A9
B9
D8
C8
A8
D7

BGA
(1 OF 4)

P12
P13

P62/KIN2*
P63/KIN3*

P14

P64/KIN4*

P15
P16

P65/KIN5*
P66/IRQ6*/KIN6*

P17

P67/IRQ7*/KIN7*

P20
P21

P70/AN0
P71/AN1

P22

P72/AN2

P23
P24

P73/AN3
P74/AN4

P25

P75/AN5

P26
P27

P76/AN6
P77/AN7

P30/LAD0

P80/PME*

P31/LAD1
P32/LAD2

P81/GA20
P82/CLKRUN*
P83/LPCPD*

P33/LAD3
P34/LFRAME*
P35/LRESET*

P84/IRQ3*/TXD1
P85/IRQ4*/RXD1
P86/IRQ5*/SCK1/SCL1

P36/LCLK
P37/SERIRQ

SMC_DISPLAY_ENABLE
SMC_SYS_LED_16B
SMB_BSB_DATA (BAT B SMBUS DATA)
SMC_TPM_PP (TPM physical presence)
SMC_P44
SMC_BKLIGHT_ENABLE
SMC_P46
SMC_SYS_KBDLED

A5
B5
D5
C3
B1
C2
D3
C1

P40/TMIO
P41/TMO0

SMC_TX_L (Debug feature,16550 Transmit)


SMC_RX_L (Debug feature,16550 Receive)
SMB_0_CLK

G1
G4
F2

P50

P90/IRQ2*
P91/IRQ1*
P92/IRQ0*

P42/SDA1
P43/TMI1/EXSCK1

P93/IRQ12*
P94/IRQ13*

P44/TMO1

P95/IRQ14*
P96/EXCL
P97/IRQ15*/SDA0

P45
P46/PWX0/PWM0

63
65 46 39 5
22
50 22
50 22
50 22
46
6

N12
R13
P13
R14
P14
R15
N13
P15
C7
A7
B7
D6
C6
A6
B6
K4
J2
J1
J3
J4
H2
H1
G2

48
48 5
46
46
66
48
66
46

23
46
53 47 38 23 5
53 47 46 23 5
46
46
27

48 46 40
66 65 46 5
65 46 5
63 23
63 61 60 23
46 23
46
27

SMC_PM_G2_EN
SMC_PS_ON (Enable AC adapter
SPI_ARB
SPI_SCLK
SPI_SI
SPI_SO
SMC_PROCHOT_3_3_L
SMC_CPU_INIT_3_3_L
SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_FWIRE_ISENSE

SMC_WAKE_SCI_L
SMC_TPM_GPIO
PM_CLKRUN_L
PM_SUS_STAT_L
SC_TX_L (Serial Port Transmit)
SC_RX_L (Serial Port Receive)
(BAT B SMBUS CLK)
SMB_BSB_CLK
SMC_ONOFF_L
SMC_BC_ACOK (AC
SMC_BS_ALRT_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
SMC_SUS_CLK
SMB_0_DATA

CRITICAL

OUT

C5802

1
OUT

22UF

20%
6.3V
2 CERM-X5R
805

OUT
OUT

IO

26 23
53 46

IN
IN
OUT

14 6

IN

23

IO

65 46 5

IO

23

OUT

SMC_RCIN_L
BOOT_LPC_SPI_L
PM_SYSRST_L
SMC_TPM_RESET_L
PM_EXTTS_L<0>
PM_THRM_L
SYS_ONEWIRE
PM_BATLOW_L

R3
P3
R2
N3
R1
N2
M4
N1

IN

LAYOUT NOTE:

(VCL IS INTERNAL RAIL)

PLACE R5899, C5820 NEAR SMC PIN N14, N15

SMC_VCL

64 48 46 45

IN

=PP3V42_G3H_SMC

IN SMC_EXTSMI_L
23
OUT SMC_RUNTIME_SCI_L
34 IN SMC_ODD_DETECT (Optical
ISENSE_CAL_EN
48
OUT
46 SMC_EXCARD_CP
46 SMC_EXCARD_PWR_EN
46 SMC_EXCARD_PWR_OC_L
46 SMC_PB7
23

Disk Insert detect)

SMC_FAN_0_CTL
SMC_FAN_1_CTL
OUT
46 SMC_FAN_2_CTL
46 SMC_FAN_3_CTL
46 SMC_FAN_0_TACH
5
IN SMC_FAN_1_TACH
46 SMC_FAN_2_TACH
46 5 SMC_FAN_3_TACH

G14
G15
G13
G12
H14
H15
H13
H12

46

51 5

B
51

IN SMS_X_AXIS
52
IN SMS_Y_AXIS
52
IN SMS_Z_AXIS
46 SMC_PD3
62 46 SMC_NB_ISENSE
61 46 SMC_MEM_ISENSE
46 5 ALS_LEFT
46 ALS_RIGHT

M11
P11
R11
N11
P10
R10
N10
M10

52

(ANALOG_ID)

OMIT

U5800
SMC_H8S2116
BGA
(4 OF 4)
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

G3
H3
K3
L3
N4
M5
N7
M12
M13
L12
K15
J14

NC0
NC1

NC12
NC13

NC2

NC14

NC3
NC4

NC15
NC16

NC5

NC17

NC6
NC7

NC18
NC19

NC8
NC9

NC20
NC21

NC10

NC22

F15
A14
C12
C10
C5
A3
B8
E4
H4
M9
N8

B10
A10
D10
A11
B11
C11
A12
D11

NC
NC
NC
NC
NC

PA2/KIN10*/PS2AC

PE2*/ETDI

PA3/KIN11*/PS2AD
PA4/KIN12*/PS2BC
PA5/KIN13*/PS2BD
PA6/KIN14*/PS2CC
PA7/KIN15*/PS2CD
PB0/LSMI*

PE3*/ETDO
PE4*/ETMS
PF0/IRQ8*/PWM2
PF1/IRQ9*/PWM3
PF2/IRQ10*/TMOY
PF3/IRQ11*/TMOX

PB1/LSCI
PB2

PF4/PWM4
PF5/PWM5

PB3

PF6/PWM6

PB4
PB5

PF7/PWM7
PG0/EXIRQ8*/TMIX
PG1/EXIRQ9*/TMIY

PB6
PB7

PG3/EXIRQ11*/SCL2
PG4/EXIRQ12*/EXSDAA

PC2/TIOCC0/TCLKA/WUE10*
PC3/TIOCD0/TCLKB/WUE11*

PG5/EXIRQ13*/EXSCLA
PG6/EXIRQ14*/EXSDAB

PC4/TIOCA1/WUE12*

PG7/EXIRQ15*/EXSCLB

PC5/TIOCB1/TCLKC/WUE13*
PC6/TIOCA2/WUE14*

PH0/EXIRQ6*

PC7/TIOCB2/TCLKD/WUE15*

PH1/EXIRQ7*
PH2/FWE

PD1/AN9
PD2/AN10
PD3/AN11
PD4/AN12
PD5/AN13
PD6/AN14
PD7/AN15

M7
P6
R6
N6
M6
R5
P5
N5
P9
R9
N9
P8
R8
M8
P7
R7

47 46 5
47 46 5
47 46 5
47 46 5

65 46 40 5
46
66 5

66

50 22

SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS

PH3/EXEXCL

PH4
PH5

E1
F3
K2
C4
D4
B3

27

5%
1/16W
MF-LF
2 402

IN
OUT

27

27

27

27
27

46

46

46 23
52

20%
2 10V
CERM
402

=PP3V42_G3H_SMC

IO

SMC_AVCC_RC

IN
IO

IO

C5820

a
n
i
0.1UF

IO

20%
2 10V
CERM
402

IN
IN

66 62 61 48 46 45

IN
IN
IN
IN

46

U5800
BGA
(3 OF 4)

SMC_RST_L

E3

RES*

SMC_XTAL
SMC_EXTAL

A2
B2

XTAL

IN

46

OUT
IN
IN

OUT

46

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

(To debug card for mode select)

(Should PD)

(Should PU)

NOSTUFF
1

R5802 1R5803
10K

EXTAL

MD2

E2
K1

NMI

F4

ETRST*

L1

MD1

AVSS

P12
R12

(Should PD) (To debug card for mode select)

5%
1/16W
MF-LF
2 402

47 5

SMC_NMI

47 5

SMC_TRST_L
IN

IN

R5898
10K

5%
1/16W
MF-LF
2 402

GND_SMC_AVSS 45

46 48 61 62 66

OUT

46

IO

46

IO
IO
IO

IO
IO
IO

SMC_PROCHOT
SMC_THRMTRIP
SMC_FWE
ALS_GAIN
SMS_INT_L
SMS_ONOFF_L

OUT
OUT

46
46

OUT
OUT

SMC
SYNC_MASTER=SMC

SYNC_DATE=08/18/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

NC

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NC

II NOT TO REPRODUCE OR COPY IT

NC

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

NC
NC

SIZE
NC

NC11

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7173

SCALE

5%
1/16W
MF-LF
2 402

XW5800
SM

m
il
OUT

R5801

10K

46

SMC_MD1
KBC_MDE

R5809

SMC_H8S2116

GND_SMC_AVSS

47 46 5
IN

IO

OMIT

47 5

PIN F1

PP3V3_AVREF_SMC

IO

IN

SPI_CE_L
SMC_PG1
SMB_BSA_DATA
SMB_BSA_CLK
SMB_RMT_DATA
SMB_RMT_CLK
SMB_MLB_DATA
SMB_MLB_CLK

C5806
0.1UF

20%
2 10V
CERM
402

C5807

10%
2 6.3V
CERM-X5R LAYOUT NOTE:
402
PLACE C5807 NEAR

4.7

IN

IN

SMC_DISP_BKLT_B
SMC_DISP_BKLT_A
SMC_LID (LID OPEN/CLOSE SW)
SMC_CPU_RESET_3_3_L
SMC_BATT_ISET
SMC_BATT_VSET
SMC_SYS_ISET
SMC_SYS_VSET

0.1UF

0.47UF

R5899

(CASE OPEN/CLOSE DETECT) 46

e
r

PG2/EXIRQ10*/SDA2

PC0/TIOCA0/WUE8*
PC1/TIOCB0/WUE9*

PD0/AN8

M3
M2
M1
L4
L2

C5805

y
r
1

IN

D1
P4
R4
F12
F13
B13
A13
A4
B4
D2

PE0
PE1*/ETCK

D
64 48 46 45

IN

P51
P52/SCL0

BGA
(2 OF 4)

20%
2 10V
CERM
402

IN

46

U5800

0.1UF

20%
2 10V
CERM
402

IN

P47/PWX1/PWM1

PA0/KIN8*/PA2DC
SMC_H8S2116
PA1/KIN9*/PA2DD

C5804

0.1UF

IN

OMIT
21

C5803

IN

VSS

47 22 5

IN

IN
I/P detect)

=PP3V42_G3H_SMC

OUT
PWR)

AVREF M15

OUT

58

P11

L13
L14
L15
K12
K13
K14
J12
J13

VCL F1

OUT

P60/KIN0*

AVREF M14

23
23

U5800
SMC_H8S2116

VCC A1

IN

P10

VCC P1
VCC J15

IN

59 46

B12
C13
A15
B14
B15
C14
D12
C15

VCC P2

OUT

63 26 5

PM_LAN_ENABLE
SMC_RSTGATE_L
ALL_SYS_PWRGD
RSMRST_PWRGD
SMC_SB_NMI
PM_RSMRST_L
IMVP_VR_ON
PM_PWRBTN_L

AVCC N15

OUT

AVCC N14

23
26

C
OF

58

108

SMC Reset Button / Brownout Detect


64 48 46 45

SMS_INT_L
SMC_TPM_RESET_L
CRITICAL

1K

RN5VD30A-F

R5901

NC

OUT

CD
NC

SMC_TPM_RESET_L

53 45

47 45 5

SMC_RST_L

65 45 5
65 45 5
47 45 5

Debug Power Button


SMC_ONOFF_L

SMC Crystal Circuit

47 45 5

C5920

OUT

47 45 5

R5910

SMC_XTAL

45

CRITICAL

Silk: "PWR BTN"

Y5920
5X3.2-SM

197S0169
SMC_EXTAL

45

45
65 45 40 5

5%
50V
CERM
402

20.00MHZ

5%
1/16W
MF-LF
402 2

5%
50V
CERM
402

45
45

45
45

NOSTUFF

45

R5972
0

45

45

5%
1/16W
MF-LF
402

45

45

VR5965

45

ISL60002-33

PP3V3_AVREF_SMC

SOT23-3

VIN

VOUT

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

CRITICAL

R5948
R5973
R5919
R5930

SMC_PB7

45

45

NOSTUFF
NOSTUFF
NOSTUFF
NOSTUFF
NOSTUFF
NOSTUFF
NOSTUFF
NOSTUFF
NOSTUFF

SMC_P20
SMC_P21
SMC_P22
SMC_P23
SMC_P26
SMC_P27
SMC_P46
SMC_P44
SMC_SYS_KBDLED

NOSTUFF

ALS_GAIN
SMC_GPU_ISENSE
SMC_GPU_VSENSE

C5965 C5966
0.47UF

C5967

66 45 5

0.01uF

66 45 5

10%
2 16V
CERM
402

66 65 45 5

GND_SMC_AVSS

e
r

TABLE_ALT_HEAD

ALTERNATE FOR
PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_ITEM

353S1278

353S1381

VR5965

TI REF3133

45

SMC G3HOT OSCILLATOR


=PP3V42_G3H_SMC_CLK
1

L5910

FERR-120-OHM-0.2A
0603
2

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.425V

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

10K
100K
2.0K
470K
10K
10K
10K
10K

1
1

2
2

10K
100K

1
1

2
2

10K
10K

R5918
R5940
R5942

1
1
1
1
1
1
1
1
1
1
1
1

10K
10K
10K
10K
10K
10K
10K
10K
10K

2
2
2
2
2
2
2
2
2

10K
10K
10K

2
2
2

1
1
1

2
2
2

C5910 1
4.7UF

20%
6.3V 2
CERM
603

C5911

12
VDD

0.1UF

20%
2 10V
CERM
402

U5910
32.768KHZ-9-3.6V
SG-3040LC-SM

NC
NC
NC
NC

OUT

VIO

NC0

NC4

NC1
NC2

NC5
NC6

NC3

NC7

4
5

10K
10K
470K

SMC_EXCARD_PWR_OC_L

10K

R5905
R5906

1
1

2
2

R5924
R5926

1
1

2
2

10K SMC_EXCARD_CP
10K SMC_EXCARD_PWR_EN

R5931
R5932
R5933
R5935
R5937
R5939
R5941

1
1
1
1
1
1
1

2
2
2
2
2
2
2

10K
10K
10K
10K
10K
10K
10K

R5945
R5946

1
1

R5949

R5998
R5999
R5947
R5996
R5943
R5944
R5997

5%
1/16W
MF-LF
402 2

45

PM_SUS_STAT_L
PM_SLP_S5_L

100K
100K

5 23 45 47 53
23 45

45

NOSTUFF

a
n
i

1
1

1
1
1

NOSTUFF
NOSTUFF

10K
10K

ALS_LEFT
ALS_RIGHT

10K

SMC_DISP_BKLT_B

SMC_PROCHOT

CPU_PROCHOT_L

Q5901

45

SMC_THRMTRIP

64 35

SMC_SUS_CLK_R

SMC_TPM_GPIO

SMC_PROCHOT_3_3_L

47 46 45 5

TPM_GPIO1

53

TPM_GPIO2

53

SC_RX_L

45

SC_TX_L

45

NOSTUFF

R5991
0

SMC_RX_L

5%
1/16W
MF-LF
402

SMC_TX_L

R5993
1

Stuff R5992, R5993 for development only

System (Sleep) LED Circuit


=PP5V_S3_SYSLED
CRITICAL
TABLE_5_HEAD

C5951 1
2.2UF

20%
4V
X5R 2
402

OMIT
1

R5951
2.2K

5%
1/16W
MF-LF
402 2

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

R5950

TABLE_5_ITEM

84.5

1%
1/16W
MF-LF
2 402

114S0114

84.5, 1%, 1/16W, MF-LF, 402

R5950

NORMAL

114S0126

115, 1%, 1/16W, MF-LF, 402

R5950

FANCY

TABLE_5_ITEM

SYS_LED_ILIM
C5951 AND R5951 SHOULD BE PLACED CLOSE TO Q5950

Q5950

2N3906
SOT23-LF

SMC SUPPORT

SYS_LED_ANODE

OUT

SYNC_MASTER=SMC

SYNC_DATE=08/23/2005

NOTICE OF PROPRIETARY PROPERTY

SYS_LED_L

OUT

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

Q5952

II NOT TO REPRODUCE OR COPY IT

2N7002

45

IN

SMC_SYS_LED_16B

SOT23-LF

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

197S0166

DRAWING NUMBER

SHT
NONE

REV.

051-7173

SCALE

BOM OPTION

APPLE COMPUTER INC.

5%
1/16W
MF-LF
402

NOSTUFF

45

R5992

7 14 21

5%
1/16W
MF-LF
402

NC
NC
10 NC
11 NC

SM-LF
1

5%
1/16W
MF-LF
402

47 46 45 5

R5911
SMC_SUS_CLK

U5977

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402 2

45

R5990
45

45

4.7K

5%
1/16W
MF-LF
2 402

NOSTUFF

62

45 61

R59521

1K

5 39 45 65

NOSTUFF
45
NOSTUFF

SYS_LED_L_VDIV

22

R5977

V-

45

SOT-363

20%
2 10V
CERM
402

2N7002DW-X-F

SOT-363

NOSTUFF

C5977
0.1uF

45

LMC7211

CPU_PROCHOT_L

Q5901

2N7002DW-X-F

V+

58 46 7

SMC_CPU_RESET_3_3_L

PM_THRMTRIP_L

7 46 58

5%
1/16W
MF-LF
2 402

45

45

SMC_FWIRE_ISENSE

10K

R5976

10K

45

NOSTUFF
NOSTUFF

SMC_NB_ISENSE
SMC_MEM_ISENSE

10K
10K

2
2

NOSTUFF

SMC_CASE_OPEN
SMC_PS_ON

10K
10K

5 45

45

SMC_BATT_VSET
SMC_SYS_VSET

10K
10K

2
2

45

SMC_FAN_0_CTL NOSTUFF 45
SMC_FAN_2_CTL NOSTUFF 45
SMC_FAN_3_CTL NOSTUFF 45
SMC_FAN_0_TACH NOSTUFF 45
SMC_FAN_2_TACH NOSTUFF 45
SMC_FAN_3_TACH NOSTUFF 5 45
SMC_PD3
NOSTUFF
45

2
2

2
2

1
1

GND

U5910 is really a 32.768KHz oscillator

y
r

1K

R5928

PP3V42_G3H_SMC_CLK_F
CRITICAL

SMC 3.3V to 1.05V Level Shifting

45 48 61 62 66

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

PART NUMBER

SMC_BATT_TRICKLE_EN_L
SMC_BATT_CHG_EN
SMC_BC_ACOK

20%
6.3V 2
X5R
603

R5920
R5922
R5923
R5925
R5927
R5929
R5934
R5936
R5938

R5954
R5955
R5988

10uF

10%
2 6.3V
CERM-X5R
402

45 46 48 64

P0V52_SMC_LSREF

R59711

10K
10K

2
2

m
il

GND

=PP3V42_G3H_SMC

1.05V Mid-Reference

5%
1/16W
MF-LF
402

45

SMC_FWE
SMC_LID
SMC_PG1

SMC AVREF Supply

64

6.2K

1
1

15pF

=PP3V42_G3H_SMCVREF

R5980
R5981
R5982
R5983
R5984
R5985
R5986
R5987

45
45

C5921

Is this the best part to use?

SMC_TX_L
SMC_RX_L
SYS_ONEWIRE ONEWIRE_PULLUP_OLD
SMC_BS_ALRT_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK

15pF

NOSTUFF

10K

5%
1/16W
MF-LF
402

47 46 45 5

64

R59701

=PP3V42_G3H_SMC

R5994
R5953

RSMRST_PWRGD
SMC_ONOFF_L

59 45
48 46 45 40

47 46 45 5

5%
1/10W
MF-LF
2 603

Silk: "SMC RST"

10K

OUT

10%
16V
CERM 2
402

48 46 45 40

R5989
64 48 46 45

0.01UF

5%
1/10W
MF-LF
2 603

SMC 1.05V to 3.3V Level Shifting


=PP3V3_S0_SMC_LS

GND

C5901 1

SMS_INT_L

45 23

5%
1/16W
MF-LF
2 402

U5900

SMC_MANUAL_RST_L
NOSTUFF
1

=PP3V3_S3_SMS

R5995

R5900

SOT23-5

=PP3V3_S3_TPM

64 52

VDD

20%
10V
CERM 2
402

64 53

64

0.1uF

THESE NEED TO BE PULLED TO THE PROPER RAIL:

=PP3V42_G3H_SMC

C5900 1

C
OF

59

108

64 5

64 5

y
r

=PP3V42_G3H_LPCPLUS

a
n
i

=PP5V_S0_LPCPLUS
NOSTUFF

CRITICAL

J6000
F-ST-5047
SM1

C
53 45 21 5
53 45 21 5

53 45 21 5
53 45 38 23 5
45 22 5
46 45 5
26 5
45 5
46 45 5
45 5
46 45 5

LPC_AD<0>
LPC_AD<1>
LPC_FRAME_L
PM_CLKRUN_L
BOOT_LPC_SPI_L
SMC_TMS
DEBUG_RST_L
SMC_TRST_L
SMC_TDO
SMC_MD1
SMC_TX_L

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

FWH_INIT_L
5 6 21
PCI_CLK_PORT80_LPC 5 33
LPC_AD<2>
LPC_AD<3>

5 21 45 53

INT_SERIRQ
PM_SUS_STAT_L
SMC_TDI
SMC_TCK
SMC_RST_L
SMC_NMI
SMC_RX_L

5 21 45 53

5 23 45 53
5 23 45 46 53
5 45 46

m
il

SV_SET_UP

516S0002

5 45 46
5 45 46
5 45

5 45 46

GPIO15

5 23

e
r

LPC+ Debug Connector


SYNC_MASTER=NB

SYNC_DATE=06/30/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

60

108

CPU CURRENT SENSE


C6100
470PF
1

R6107
58

IMVP6_DROOP

R6105

5%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

NOSTUFF
1

10%
50V
CERM
402

30.1K2
IMVP6_CPU_ISENSE_P 1

C6104

0.1UF

1M

CPU_ISENSE_R_P

R6108
58

IMVP6_VO

S0T23-3
2

64 58

D
PBUS_S0_SMC_VSENSE

R6152

Q6153
TP0610

R6150
27.4K

1%
1/16W
MF-LF
2 402

S0T23-3
1

46 45 40

PM_SLP_S3

Q6152
TP0610

S0T23-3
1

63

5%
1/16W
MF-LF
2 402

NOSTUFF

SMC_ONOFF_L

PBUS_SMC_VSENSE_EN_L

SMC_PBUS_VSENSE
DRIVEN LOW IN S0

DRIVEN LOW BY SMC


OR POWER BUTTON

45

Q6151

R6151

2N7002

PBUS_SMC_VSENSE_EN

R6153

5.49K

SOT23-LF

10%
6.3V
2 CERM-X5R
402

GND_SMC_AVSS

100K

5%
1/16W
MF-LF
2 402

m
il

C6150
0.22UF

1%
1/16W
MF-LF
2 402

45 46 48 61 62 66

PLACE C6150 NEAR U5800

e
r

Current Sense Calibration Circuit

=PP5V_S0_ISENSECAL

P
R61441
10K

R6140
470K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
402 2

TSOP-LF

SOT-363

Q6101

2N7002DW-X-F

IN

45

ISENSE_CAL_EN
1

R6141

SOT-363

1
2
5
6

1%
1/16W
MF-LF
2 402

GND_SMC_AVSS

B
CPU VOLTAGE SENSE
R6112
64 48 9 8

=PPVCORE_S0_CPU

4.53K2

SMC_CPU_VSENSE 5

1%
1/16W
MF-LF
402

45

C6112
0.22UF

GND_SMC_AVSS

64 48 9 8

45 46 48 61 62 66

=PPVCORE_S0_CPU
1

R6143
1.00
1%
1/4W
MF-LF

2 1206

CPUVCORE_ISENSE_CAL
MIN_LINE_WIDTH=0.50 mm
MIN_NECK_WIDTH=0.20 mm

CPU Current & Voltage Sense


SYNC_MASTER=ENET

SYNC_DATE=08/30/2005

NOTICE OF PROPRIETARY PROPERTY

R6142
470K

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

100K

5%
1/16W
MF-LF
2 402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7173

SCALE

45 46 48 61 62 66

PLACE RC FILTER CLOSE TO SMC

5%
1/16W
MF-LF
402 2

0.22UF

C6101

1
C6103 R6103
1M

C6102

20%
2 6.3V
X5R
402

6
D

45

PLACE RC FILTER CLOSE TO SMC

SI3446DV

2N7002DW-X-F

ISENSE_CAL_EN_L

U6100

SMC_CPU_ISENSE

20%
6.3V
402

Q6100

Q6101

1%
1/16W
MF-LF
402

2 X5R

CRITICAL

ISENSE_CAL_EN_LS5V

LMV2011MF

0.1UF

Switches in fixed load on power supplies to calibrate current sense circuits

64

4.53K2

CPU_ISENSE_OUT_R

=PP3V3_S0_CPUPOWER 64

10%
2 50V
CERM
402

100K

SOT23-5

1%
1/16W
MF-LF
402

470PF

=PP3V42_G3H_SMC
64 46 45

CPU_ISENSE_R_N

R6102

20%
2 10V
CERM
402

y
r

CRITICAL

a
n
i

C6105

20%
2 10V
CERM
402

TP0610
=PPVIN_S5_IMVP6

NOSTUFF

0.1UF

Q6150

R6106

30.1K2
IMVP6_CPU_ISENSE_N 1

5%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

20%
2 10V
CERM
402

PROCESSOR DCIN VOLTAGE SENSE

R6100

C
OF

61

108

DIMM0 TEMPERATURE ZONE


ADDITIONAL NOISE FILTERING

R6203
THRM_DIMM0_3V3_UNFILTERED

47

=PP3V3_S0_THRM_SNR

10 49 64

y
r

1%
1/16W
MF-LF
402

C6202
0.1UF
10%
16V
402

PLACE C6200 AND C6201


NEXT TO DXP AND DXN
THRM_DIMM0_DXP1

OUT

NOSTUFF
1

R6200

IF A SENSOR INPUT IS UNUSED STUFF


THE CORRESPONDING RESISTOR

10%
50V
2 CERM
402

R6201

IF B SENSOR INPUT IS UNUSED STUFF


THE CORRESPONDING RESISTOR

J6250

SMBCLK
ALERT*

0.0022UF

1.
2.
3.
4.

1
2

THRM_DIMM0_SMB_DATA
THRM_DIMM0_SMB_CLK

a
n
i
27

IO
IO

NC

OT2*

10 NC

NC

GND

PLACE U6200 NEAR U1200

BM02B-ACHKS-A-GAN-TF-LF
M-RT-SM
3

27

OT1*

THRM_DIMM0_DXP2

9
7

SMBDATA

C6201

10%
2 50V
CERM
402

5%
1/16W
MF-LF
2 402

CRITICAL

U6200
UMAX

NOSTUFF
1

CRITICAL

MAX6695AUB+C4Y
2 DXP1
3 DXN
4 DXP2

THRM_DIMM0_DXN

OUT

VCC

C6200
0.0022UF

5%
1/16W
MF-LF
2 402
40

PLACE NEXT TO C6202 U6200 PIN 1

40

2 X5R

ROUTE DXP AND DXN DIFFERENTIALLY


DXP AND DXN TRACE LENGTH MUST NOT EXCEED 4 INCHES
ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR
10 MIL TRACE WIDTHS AND 10MIL SPACING BETWEEN THE GAURD

518S0332

NOTE: REPLACE J6250 AND J6251 FROM 518S0332 TO 518S0452


AFTER THIS CHANGE, THE SCHEAMTIC DOES NOT MATCH THE PCB ON THESE TWO LOCATIONS.

m
il

DIMM1 TEMPERATURE ZONE

Q6200

BC846BM3T5G
SOT732-3

IF A SENSOR INPUT IS UNUSED STUFF


THE CORRESPONDING RESISTOR

CRITICAL

J6251

BM02B-ACHKS-A-GAN-TF-LF
M-RT-SM
3

R6252

THRM_DIMM1_3V3_UNFILTERED

C6252

47

=PP3V3_S0_THRM_SNR

10 49 64

1%
1/16W
MF-LF
402

0.1UF
10%

2 16V
X5R

402

THRM_DIMM1_DXP1

PLACE NEXT TO C6252 U6250 PIN 1

e
r
3

PLACE C6250 AND C6251


NEXT TO DXP AND DXN
PLACE R6250 AND R6251
AWAY FROM U6250 BUT CLOSE TO
C6250 AND C6251

C6250

VCC

0.0022UF

10%
50V
2 CERM
402

THRM_DIMM1_DXN

U6250

CRITICAL

MAX6695AUB+C4Y
UMAX

2 DXP1
3 DXN
4 DXP2

SMBDATA
SMBCLK

9
7

ALERT*

OT1*
OT2*

27

THRM_DIMM1_SMB_DATA
THRM_DIMM1_SMB_CLK

27

IO
IO

NC
5 NC
10 NC

GND
NOSTUFF

PLACE UNDER J2900

R6251
0

5%
1/16W
MF-LF
2 402

C6251

PLACE U6250 IN BATTERY CHARGER AREA

0.0022UF

10%
50V
2 CERM
402

THRM_DIMM1_DXP2

518S0332

1.
2.
3.
4.

ROUTE DXP AND DXN DIFFERENTIALLY


DXP AND DXN TRACE LENGTH MUST NOT EXCEED 4 INCHES
ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR
10 MIL TRACE WIDTHS AND 10MIL SPACING BETWEEN THE GAURD

TEMPERATURE SENSE
SYNC_MASTER=ENET

SYNC_DATE=11/09/2005

NOTICE OF PROPRIETARY PROPERTY

NOTE: REPLACE J6250 AND J6251 FROM 518S0332 TO 518S0452


AFTER THIS CHANGE, THE SCHEAMTIC DOES NOT MATCH THE PCB ON THESE TWO LOCATIONS.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

62

108

64

=PP3V3_S5_ROM
1

20%

2 10V
CERM

3.3K

5%
1/16W
MF-LF
402 2

402

5%
1/16W
MF-LF
402 2

y
r

0.1UF

R63021 R63011
3.3K

C6312

R6308
CRITICAL

10K

OMIT

5%
1/16W
MF-LF
402

VDD

U6301
16MBIT

R6307
1

SPI_CE_L

a
n
i
6

22pF
5%
50V
402

NOSTUFF
1

C6308 R6309
22pF
10K

5%
2 50V
CERM
402

SI

SCK

SPI_SI_R

SST25VF016B

SPI_WP_L
SPI_HOLD_L

C6309

2 CERM

R6306

SOI

SPI_SCLK_R

5%
1/16W
MF-LF
402

45 22

SPI_SCLK

CE*
WP*
HOLD*

SO

5%
1/16W
MF-LF
402

R6309 IS NOT NEEDED WHEN SHARING SPI FLASH WITH


ICH7M AND TEKOA(LAN CHIP)

47

SPI_SI

22 45

SPI_SO

22 45

5%

R6303 1/16W
MF-LF

VSS

45 22

47

SPI_SO_R

47

5%
1/16W
MF-LF
402

402

C6301
22pF
5%

2 50V
CERM

C6311
22pF

402

5%

2 50V
CERM

402

R6307 AND R6306 SHOULD BE PLACED LESS THAN 100 MILS FORM ICH7M
R6303 SHOULD BE PLACED LESS THAN 100 MILS FORM FLASH ROM

m
il

e
r

SPI BOOTROM
SYNC_MASTER=MASTER

SYNC_DATE=5/23/05

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

63

108

y
r

a
n
i

64 5

=PP5V_S0_FAN_RT

64 5

=PP3V3_S0_FAN_RT

CRITICAL

1
R6560
47K

45 5

R6565
47K
1

SMC_FAN_1_TACH

m
il

5%
1/16W
MF-LF
4022

88611-04001
F-ST-SM
NC 5
1

FAN_RT_TACH

5%
1/16W
MF-LF
402

5V DC
TACH

3
4

NC

R6561
100K

MOTOR CONTROL
GND

518S0334

5%
1/16W
MF-LF
4022

45 5

J6501

Q6560
2N7002

SOT23-LF

2 S

SMC_FAN_1_CTL
5

FAN_RT_PWM

e
r

Fan
SYNC_MASTER=ENET

SYNC_DATE=11/10/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

65

108

PAGE NOTES
INPUT
=PP3V3_S3_SMS - 3.3V POWER FOR SMS (STAYS ALIVE IN SLEEP)
SMS_ONOFF_L - CONNECT TO SMC TO BE ABLE TO PUT SMS INTO LOW-POWER MODE

OUTPUT
SMS_ACC_*_AXIS - ACCELEROMETER OUTPUT TO SCU

PAGE HISTORY

5/19/2005
7/26/2005
7/26/2005
7/26/2005

- FIRST REVISION OF PAGE


- REMOVED BOM TABLE AND UPDATED SYMBOL TO KXM52-2050
- CONNECTED PD PIN TO SMCS SMS_ONOFF_L
-

y
r

a
n
i

Desired Orientation
(Placed on board bottom side)
Package Top

64 46

=PP3V3_S3_SMS

+X

C6620 1

+Z (up)

0.1uF

ACCEL_KIONIX
CRITICAL 8

20%
10V
CERM 2
402

VDD

U6620
KXM52-2050
QFN
OUTPUTX 2

10 SELF
TEST

45

+Y

SMS_ONOFF_L
NC

ACCEL_ST1

R6650
10K

5%
1/16W
MF-LF
402 2

ACCEL_ST

S0T23-3

e
r

Q6650
SOT23-LF

Q6651
TP0610

2N7002

S
D

ACCEL_ST

RSVD
RSVD

DNC 1

NC

OMIT

RSVD
RSVD

THRML
PAD

3 12 15

OUTPUTZ 14

GND

5 PARITY

4
6
7
11

100K

ST_ACCEL_ON_L

OUTPUTY 13

m
il

R66521
5%
1/16W
MF-LF
402 2

9 PS

OMIT

C6604

0.033uF

10%
2 16V
X5R
402

C6605

0.033uF

10%
2 16V
X5R
402

SMS_X_AXIS

45

SMS_Y_AXIS

45

SMS_Z_AXIS

45

OMIT

C6606

PART#

QTY

DESCRIPTION

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

0.033uF

10%
2 16V
X5R
402

TABLE_5_ITEM

132S0131

0.033UF,10%,16V,402

C6604,C6605,C6606

ACCEL_KIONIX

132S0042

0.01UF,10%,16V,402

C6604,C6605,C6606

ACCEL_ST

TABLE_5_ITEM

PP3V3_S3_ST_ACCEL

SMC_ACC_SELFTEST-->is a test signal


0 -->Normal operation
1 -->Self test

SMS_ACC_SELFTEST

ACCEL_ST
CRITICAL

VDD

U6650

LIS3L02AL
LGA

1 ST

R6621

VOUTX 7
VOUTY 6

4 RSRVD1
5 RSVRD2

10K

VOUTZ 2

5%
1/16W
MF-LF
2 402

GND

Desired Orientation
(Placed on board bottom side)
1

Package Top
+Z (up)

+X
+Y

SMS
SYNC_MASTER=SMC

SYNC_DATE=08/23/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

66

108

64

TPM

C6700
0.1UF

10%
16V
2 X5R
402

CRITICAL
TPM
IO

47 45 21 5

IO

47 45 21 5

IO

33

IN

47 46 45 23 5

IN

NOSTUFF
47 45 23 5

R6700

SMC_TPM_PP

45

47 45 38 23 5

IO
IN

TPM

46

46

15pF

CRITICAL

21

PM_SUS_STAT_L
INT_SERIRQ
PM_CLKRUN_L

28
27

22
16

15

SMC_TPM_PP_R
TPM_GPIO1
TPM_GPIO2
TPM_XTALI
TPM_XTALO

32.768K
4

SM-LF

197S0098

5%
50V
CERM
402
TPM

R6798
26

IN

TPM_LRESET_L

5%
1/16W
MF-LF
402

R6799

IN

SMC_TPM_RESET_L

5%
1/16W
MF-LF
402

TSSOP

VDD

LAD2
LAD3

3V0
3V1
3V2

10
19
24

VDD

VNC

LFRAME*

VBAT

NC

12

NC

TPM

NC

SERRIRQ
CLKRUN/GPIO*
PP/GPIO

GPIO_EXPRESS_00

5%
1/16W
MF-LF
2 402

(INT PD)

PP

GPIO

GPIO/SM_DAT
NC
GPIO/SM_CLK

13

XTALI/32K_IN

14

XTALO

10%
16V
2 X5R
402

C6702

NOSTUFF

0.1UF

10%
16V
2 X5R
402

5%
1/8W
MF-LF
2 805

TPM

C6703

10%
16V
2 X5R
402

NOTE:
SINCE CURRENT OF VSB IS NOT YET ON SPEC,
1/8W (R6704/R6705) IS USED FOR NOW

R6705

0.1UF

R6702

10K

6
1

TPM
1

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM

NC

LRESET*
LPCPD*

0.1UF

PP3V3_S0_TPM_3VSB

VSB

LCLK

C6701

TPM

R6704
1

=PP3V3_S3_TPM

46 64

5%
1/8W
MF-LF
805

TPM_BADD
TESTBI/BADD/GPIO
TESTBI/BADD

TESTI

9
8

NOSTUFF

GND

R6703

10K

5%
1/16W
MF-LF
2 402

e
r
TPM_RST_L

NOSTUFF

46 45

VDD

m
il

Y6795

15pF

LAD1

TPM

C6796

U6700

GPIO2

TPM

5%
50V
CERM
TPM
402

PCI_CLK_TPM
LPC_FRAME_L

NC

C6795
1

17

LAD0

CLKRUN*

5%
1/16W
MF-LF
402

23
20

3VSB

IN

47 45 21 5

26

4 GND0
11 GND1
18 GND2
25 GND3

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>

IO

47 45 21 5

TPM

a
n
i
1

47 45 21 5

y
r

=PP3V3_S0_TPM

TPM
SYNC_MASTER=SMC

SYNC_DATE=07/18/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

67

108

AUDIO CODEC
APPLE P/N 353S1458

2
0402

CRITICAL

CRITICAL

C6800 1

10UF

0.001uF

20%

10%
2 50V
CERM
402

6.3V 2
X5R
603

21 5

IN

21 5

IN

21 5

IN

C6801

0.001uF

ACZ_SDATAIN<0>

OUT

39

6
10
5

54
54

55
55

57
55

SDATAIN

57
57

44

AUD_BI_PORT_C_L
AUD_BI_PORT_C_R

23
24

PORT-C_L

AUD_BI_PORT_D_L
AUD_BI_PORT_D_R

35

PORT-D_L_HP
PORT-D_R_HP

18

57 21 5

12

R6800
100K

13

SENSE_B

34

HP

PORT-A_R_HP

16

VREFOUT-A
PORT-E_L

37
14

PORT-E_R

15

VREFOUT-B
PORT-B_L

28
21

PORT-B_R

22

VOLUME_DOWN
PC_BEEP

VREFOUT-C
VREFOUT-D

29

27

RESET*

VREF_FILT
AFILT1
AFILT2
CAP2

31
33

AUD_VREF_FILT
AUD_ANALOG_FILT_1
AUD_ANALOG_FILT_2
AUD_BYPASS

NC1

40

AUD_JDREF

NC2

43

MIC1

MIC2

17

10%
2 16V
X5R
402

32

30

R6801
0

5%
1/16W
MF-LF
2 402

STUFFING OPTIONS FOR ALC882 CODEC


64 57 56 55 54

R6850
55

OUT

AUD_GPIO_0

VOL_UP

54

5%
1/16W
MF-LF
402

=GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V

AUD_GPIO_0_R

54

5%
1/16W
MF-LF
402
NO STUFF

R6851
57

OUT

AUD_GPIO_1

VOL_DOWN

54

5%
1/16W
MF-LF
402

R6853
1

AUD_GPIO_1_R

5%
1/16W
MF-LF
402

54

P
64 55

64 57 56 54

64 57 56 55 54

MIN_LINE_WIDTH=0.60 MM
MIN_NECK_WIDTH=0.20 MM
L6800
VOLTAGE=5V
FERR-220-OHM
=PP5V_S0_AUDIO
1
2

C6853

10%
X5R 2
402

=PP3V3_S0_AUDIO

22

AUD_SPDIF_OUT 56
AUD_SPDIF_IN

AUD_BI_PORT_F_L
AUD_BI_PORT_F_R

AUD_BI_PORT_E_L
AUD_BI_PORT_E_R

AUD_BI_PORT_B_L
AUD_BI_PORT_B_R

CRITICAL

R68541
20.0K

1%
1/16W
MF-LF
402 2

C6804 1
10uF

20%
6.3V 2
TANT
SMA-LF

100K

56

57
57
57
57

57
57

57
57

57

57

CRITICAL

57

5%
1/16W
MF-LF
2 402

C6812

0.001uF

10%
2 50V
CERM
402

CRITICAL

C6806
1000pF

5%
25V
2 CERM
603

CRITICAL

CRITICAL

C6813

10%
2 50V
CERM
402

10%
50V
2 CERM
402

CRITICAL

CRITICAL

CRITICAL

C6805

C6810 1

C6807 1

1000pF

5%
25V
CERM 2
603

C6833

0.001uF

0.001uF

10uF

10UF

20%
6.3V 2
TANT
SMA-LF

20%

6.3V 2
TANT

SMA-LF

B
USING DC OFFSET SCREENED PART AS PRIMARY OPTION
TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

BOM OPTION

REF DES

COMMENTS:

353S1345

353S1458

U6800

DC OFFSET SCREEN PRTS

TABLE_ALT_ITEM

CRITICAL
TPS79501

SOT223-6
2 IN
OUT 4
1 EN
NR/FB 5

GND
3

1%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=4.5V
PP4V5_AUDIO_ANALOG 54 57

VR6800

R6802
1K

16V

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
5V_REG_IN
AUD_4V5_SHDN_L

0402

54 55 56 57 64

PLACE R6809 CLOSE TO COMBO JACK

NO STUFF

CRITICAL
0.1UF

e
r

R6852

NC
NC

AUD_ALC_COUT

NO STUFF

NO STUFF

NC

m
il

C6821

AUD_VREF_PORT_B

=GND_AUDIO_CODEC

a
n
i

39
41

PORT-A_L_HP

PORT-F_L_HP
PORT-F_R_HP

0.1UF

5%
1/16W
MF-LF
2 402

SENSE_A

LO

CRITICAL

R6809

10%
50V
2 CERM
402

5%
1/16W
MF-LF
402

VOLUME_UP

11

U6800
STAC92204XR

CD-R

2
3

ACZ_RST_L

IN

47

CD-L
CD-G

19
20

y
r

AUD_SENSE_A
AUD_SENSE_B
AUD_BI_PORT_A_L
AUD_BI_PORT_A_R

0.001uF

47UF

20%
6.3V 2
POLY
CASE-B3-LF

AUD_SPDIF_OUT_R

PORT-C_R

36

BEEP

GPIO3/SPDIFIN

CRITICAL

GPIO1

C6836

R6808
48

7 DVSS3
4 DVSS2

54

10%
2 50V
CERM
402

CRITICAL
1

PLACE CLOSE TO U6800


SPDIF-OUT

GPIO2
GPIO0

45
46

C6803 1

LQFP

AUD_GPIO_2
AUD_GPIO_0_R
AUD_GPIO_1_R

VOL_UP
VOL_DOWN

54

SDATA_OUT
SDATA_IN

BAL_IN_L
BAL_IN_COM
BAL_IN_R

57

SYNC

CRITICAL

C6830

0.001uF

47UF

BIT_CLK

CRITICAL
1

20%
6.3V 2
POLY
CASE-B3-LF

ACZ_BITCLK
ACZ_SYNC
ACZ_SDATAOUT

5%
1/16W
MF-LF
402

C6802 1

10%
50V
2 CERM
402

R6807
21 5

CRITICAL

C6835

AVDD1 25
AVDD2 38

L6801

FERR-220-OHM

26 AVSS1
42 AVSS3

64 57 56 54

PP4V5_AUDIO_ANALOG 54 57
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=4.5V

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
PP3V3_AUDIO_CODEC
CRITICAL

DVDD_CORE1 1
DVDD_CORE3 9

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
=PP3V3_S0_AUDIO

C6823

R6810

GND
TAB

78.7K

1%
1/16W
MF-LF
2 402

10%
2 16V
X5R
402

C6822 1
10UF

C6825
15pF

5%
2 50V
CERM
402

VREG_FB

0.1UF

CRITICAL

CRITICAL
1

R6811
29.4K

AUDIO: CODEC

1%
1/16W
MF-LF
2 402

20%
6.3V 2
X5R
603

SYNC_MASTER=M42AUDIO

=GND_AUDIO_CODEC

SYNC_DATE=08/05/2006

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

4.5V POWER SUPPLY FOR CODEC

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

68

108

7
SATELLITE

& SUB TWEETER AMPLIFIER

SATELLITE
SUB

D
64 55

5
APN:353S1595

442 Hz < FC < 736 Hz


169 Hz < FC < 282 Hz

SPEAKER OUTPUT EMI FILTERS

VOLTAGE=5V
MIN_LINE_WIDTH=0.60 MM
MIN_NECK_WIDTH=0.20 MM
=PP5V_S0_AUDIO_PWR

55

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_P_OUT

150uF

20%
6.3V
POLY 2
SMC-LF

64 56 55

55

64 54

VOLTAGE=5V
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
=PP5V_S0_AUDIO

CRITICAL

CRITICAL

C7207 1

AUD_BI_PORT_C_R
54

IN

10%
16V
X5R 2
402

55

1
VDD

AUD_SPKRAMP_INR_L

2 IN+
3 IN-

MAX9705_R_N

64 56 55

64 55
55

OUTSYNC

CRITICAL

55

SPKRAMP_R_P_OUT
SPKRAMP_R_N_OUT

8
9
6
1

R7201
100

GND PGND PAD


7
4
11

0.018UF

VOLTAGE=0V
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
=GND_AUDIO_CODEC

20%
POLY
CASE-B3-LF

2 6.3V

THRML

CRITICAL

C7211 1

64 57 56 55 54

OUT+

5 SHDN*

AUD_SPKRAMP_SHUTDOWN_L

47UF

20%
6.3V
X5R 2
603

TDFN1

10%
16V
X7R
402

5%
1/16W
MF-LF

m
il

=PP5V_S0_AUDIO_PWR
PP5V_S0_AUDIO_F

CRITICAL

C7208

C7204

1
VDD

0.1UF

C7220

FERR-1000-OHM
AUD_BI_PORT_C_L
IN

AUD_SPKRAMP_INL_L

0.018UF

0402

55

10%
16V
X5R 2
402

CRITICAL

L7220

AUD_SPKRAMP_SHUTDOWN_L

U7220

55

e
r
0.018UF

64 56 55

64 55

55

=GND_AUDIO_PWR
=PP5V_S0_AUDIO_PWR
PP5V_S0_AUDIO_F

P
CRITICAL

L7230

C7230

FERR-1000-OHM
AUD_BI_PORT_D_R
54

IN

AUD_SPKRAMP_INSUB_L

2
0402

FERR-1000-OHM
IN

AUD_GPIO_0

2
0402
1

R7210
10K

5%
1/16W
MF-LF
402 2
64 57 56 55 54

64 56 55

=GND_AUDIO_CODEC
=GND_AUDIO_PWR

10%
16V
X7R
402

L7211

54

0.047UF

OUT+
OUT-

CRITICAL SYNC

5 SHDN*

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRCONN_R_N_OUT

NO STUFF
CRITICAL
1

OUT

56

OUT

56

C7261
100PF

5%
2 50V
CERM
402

RIGHT SATELLITE
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRCONN_L_P_OUT

R7270
0

5%
1/16W
MF-LF
402

NO STUFF
CRITICAL
1

C7270
100PF

5%
2 CERM
402
50V

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_N_OUT

64 56 55

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRCONN_L_N_OUT

R7271
2

NO STUFF
CRITICAL

5%
1/16W
MF-LF
402

OUT

56

C7271
100PF

5%
2 50V
CERM
402

=GND_AUDIO_PWR

LEFT SATELLITE

SPKRAMP_L_P_OUT 55
SPKRAMP_L_N_OUT 55
SPKRAMP_SYNC2 55

55

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_P_OUT

SPKRAMP_THERMPLANE

CRITICAL

C7206

CRITICAL
1
VDD

0.1UF

10%
16V
X5R 2
402

U7230

NO STUFF
CRITICAL
1

OUT

56

C7280
100PF

5%
50V
2 CERM
402
64 56 55

=GND_AUDIO_PWR

55

55

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_N_OUT

C7205

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRCONN_SUB_N_OUT

R7281
2

5%
1/16W
MF-LF
402

NO STUFF
CRITICAL
1

OUT

56

C7281
100PF

5%
2 50V
CERM
402

120UF

20%
6.3V
X5R 2
603

5%
1/16W
MF-LF
402

CRITICAL

10UF

10
PVDD

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRCONN_SUB_P_OUT

R7280

THRML

C7209 1

55

GND PGND PAD


4
11
7

20%
2 6.3V
POLY
CASE-B2

64 56 55

=GND_AUDIO_PWR

MAX9705
TDFN1

AUD_SPKRAMP_INSUB
MAX9705_SUB_N

AUD_SPKRAMP_SHUTDOWN_L

100PF

=GND_AUDIO_PWR

20%
2 6.3V
POLY
CASE-B3-LF

10%
16V
X7R 2
402

=GND_AUDIO_CODEC

C7260

5%
2 50V
CERM
402

R7261

55

C7203
47UF

20%
6.3V 2
X5R
603

MAX9705

C7221 1

=GND_AUDIO_PWR

CRITICAL

10UF

10
PVDD

2 IN+
3 IN-

MAX9705_L_N

55

D
56

NO STUFF
CRITICAL

TDFN1

AUD_SPKRAMP_INL

10%
16V
X7R
402

CRITICAL

64 57 56 55 54

5%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_P_OUT

SPKRAMP_SYNC1 55

SPKRAMP_THERMPLANE

=GND_AUDIO_PWR

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_N_OUT

55

64 56 55

2 402

10%
16V
X7R 2
402

CRITICAL

54

C7201

MAX9705

0.018UF AUD_SPKRAMP_INR
1

10uF

10
PVDD

U7210

C7210

0402

CRITICAL

C7202 1

0.1UF
CRITICAL

FERR-1000-OHM

55

64 56 55

0402

L7210

=GND_AUDIO_PWR

a
n
i

PP5V_S0_AUDIO_F

VOLTAGE=5V
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM

L7200

FERR-220-OHM

y
r

C7200

64 56 55

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRCONN_R_P_OUT
OUT

R7260
5%
1/16W
MF-LF
402

NO STUFF
CRITICAL
1

VOLTAGE=0V
MIN_LINE_WIDTH=0.60 MM
MIN_NECK_WIDTH=0.20 MM
=GND_AUDIO_PWR

2 IN+
3 IN-

OUT+

OUTCRITICAL SYNC
5 SHDN*

THRML
GND PGND PAD
7
4
11

CRITICAL

C7231 1

SUB-TWEETER

SPKRAMP_SUB_P_OUT 55
SPKRAMP_SUB_N_OUT 55
SPKRAMP_SYNC1 55

8
9
6
1

R7202
100

5%
1/16W
MF-LF

2 402

0.047UF

10%
16V
X7R 2
402

AUDI0: SPEAKER AMP

SPKRAMP_SYNC2 55
SPKRAMP_THERMPLANE

55

SYNC_MASTER=M42AUDIO

SYNC_DATE=08/05/2006

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

XW7200
SM
64 56 55

=GND_AUDIO_PWR

II NOT TO REPRODUCE OR COPY IT

SPKRAMP_THERMPLANE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


55

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

72

108

MIC CONNECTOR
CRITICAL

APN:514S0392

J7301
48227-0301
M-RT-SM1
4

AUDIO JACK 1: LO/HP CONNECTOR, SPDIF TX


L7390

56

FERR-220-OHM

64 57 54

=PP3V3_S0_AUDIO

56

AUD_SPDIF_OUT

0402

L7300

J7300

C7307

SHLD_PIN

0.047uF

10%
16V
X7R 2
402

L7304

FERR-1000-OHM

0.047uF
10%

16V

2 X7R

FERR-1000-OHM
AUD_CONNJ1_RING_F

402

AUD_CONNJ1_RING

0402

0402

L7306

FERR-1000-OHM
1

AUD_CONNJ1_TIP

L7307

AUD_CONNJ1_TIP_F

AUD_CONNJ1_SLEEVEDET

AUD_CONNJ1_SLEEVEDET_F

100PF

5%
50V
CERM 2
402

56

C7300

GND_AUDIO_SPDIF_DGND

CRITICAL

1UF

DZ7300

10%
2 6.3V
CERM
402

C7304 1

5%
50V
CERM 2
402

5%
50V
CERM 2
402

100PF

0405

R7391
0

DZ7301

5.6V-15A

C7301
100PF

0405
2

AUD_J1_SLEEVEDET_R

R7301

100PF

5%
2 CERM
402
50V

CHASSIS_AUDIO_JACK_ISOL

C7303
0.001uF

10%
2 CERM
402
50V

4.7

AUD_J1_TIPDET_R

5%
1/16W
MF-LF
402

CRITICAL

5%
1/16W
MF-LF
402
56

C7302 1

5.6V-15A
2

10K

5%
1/16W
MF-LF
402

NO STUFF

AUD_PORTA_L

R7300

0402

C7306

C7305
100PF

5%
2 50V
CERM
402

XW7305
SM
=GND_CHASSIS_AUDIO_JACK

m
il

R7320

CHASSIS_AUDIO_JACK_ISOL

56

56

CHASSIS_AUDIO_JACK_ISOL

AUD_J2_OPT_OUT
56

10

5%
1/16W
MF-LF
402

PP3V3_S0_AUDIO_SPDIF
APN:514-0291
APN:514-0318

J7350

2
4

8
7
6
9
10

100PF

5%
CERM 2
402
50V

C7350
1UF

10%
2 6.3V
CERM
402
56

C7351

P
1

10uF

CRITICAL

DZ7350
0405

57

55

IN

55

IN

=GND_AUDIO_CODEC

55

IN

55

IN

CRITICAL

J7303

SPKR_SHIELD

88611-04001
F-ST-SM
5

1
2
3
4

APN:518S0334

AUDIO SHIELD FILL


XW7302
SM

AUDIO_SHIELD_PLANE

CHASSIS_AUDIO_JACK_ISOL

56

CHASSIS_AUDIO_JACK_ISOL

56

CHASSIS_AUDIO_JACK_ISOL

56

XW7303
SM
1

XW7304
SM

54 55 56 57 64

NO STUFF

R7382
2

AUD_SPDIF_IN

OUT

SPKRCONN_SUB_P_OUT
SPKRCONN_SUB_N_OUT
SPKRCONN_R_P_OUT
SPKRCONN_R_N_OUT

5%
1/16W
MF-LF
402

54

MIC EMI FILTER


L7370

OUT

MIC_LO

MIC_LO_F

57
57

OUT

MIC_HI

BI

57

57

OUT

MIC_SHIELD

MIC_HI_F

0402

L7374

L7375

0402

100PF
AUD_J2_SLEEVEDET_R

OUT

5%
50V
CERM 2
402

57

C7355 1

5%
CERM 2
402

5%
CERM 2
402

100PF

C7352
100PF

5%
2 50V
CERM
402

50V

C7354

0.001uF

10%
50V
2 CERM
402

100PF

5%
50V
CERM 2
402

C7372 1
100PF

5%
50V
CERM 2
402

CHASSIS_AUDIO_JACK_ISOL

R7351

100PF

50V

56

MIC_HI_CONN 56

FERR-1000-OHM
1
2 MIC_SHLD_CONN 56

MIC_SHIELD_F

0402

5%
1/16W
MF-LF
402

C7353 1

0402

R7350

4.7

AUD_J2_TIPDET_R

OUT

57

5%
1/16W
MF-LF
402
1

C7356
100PF

5%
2 50V
CERM
402

AUDIO: JACK

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION
TABLE_5_ITEM

514-0290

CONN,3.5MM COMBO AUDIO OUT,RA,MG3,LF

J7300

CRITICAL

NORMAL

514-0291

CONN,3.5MM COMBO AUDIO IN,RA,MG3,LF

J7350

CRITICAL

NORMAL

514-0317

CONN,3.5MM COMBO AUDIO OUT,RA,BLACK,LF

J7300

CRITICAL

FANCY

514-0318

CONN,3.5MM COMBO AUDIO IN,RA,BLACK,LF

J7350

CRITICAL

FANCY

SYNC_MASTER=M42AUDIO

SYNC_DATE=08/05/2006

TABLE_5_ITEM

NOTICE OF PROPRIETARY PROPERTY


TABLE_5_ITEM

AUDIO JACK 2: LINE IN CONNECTOR, SPDIF RX

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

TABLE_5_ITEM

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7173

SCALE

56

L7373

FERR-1000-OHM

AUD_PORTF_L

MIC_LO_CONN

FERR-1000-OHM

C7370 1 C7371
10K

0402

L7372

BI

0402

FERR-1000-OHM

AUD_PORTF_R

FERR-1000-OHM

0402

FERR-1000-OHM

0402

57

L7356

L7371

FERR-1000-OHM

0402

AUD_CONNJ2_SLEEVEDET_F

5%
1/16W
MF-LF
402

L7354

FERR-1000-OHM

CRITICAL

OUT

57

=GND_AUDIO_PWR

0402

OUT

64 55

FERR-1000-OHM

L7357

SPKRCONN_L_P_OUT
SPKRCONN_L_N_OUT

0402

AUD_CONNJ2_TIP_F

0405

603

CHASSIS_AUDIO_JACK_ISOL

5.6V-15A

6.3V

5.6V-15A

56

FERR-1000-OHM

DZ7351

20%

2 X5R

GND_AUDIO_SPDIF_DGND

L7355

AUD_CONNJ2_RING_F

0402

AUD_CONNJ2_SLEEVEDET

NO STUFF

C7357

e
r
L7353

57

BI

AUD_CONNJ2_TIPDET_F

FERR-1000-OHM

AUD_CONNJ2_RING

5
1

IN

L7351

0402

F-ST-SM
3

FERR-220-OHM

FERR-1000-OHM
1

54 55 56 57 64

AUD_CONNJ2_SLEEVE_F

L7352

AUD_CONNJ2_TIP
AUD_CONNJ2_TIPDET

0402

5%
1/16W
MF-LF
402

F-RT-TH

SHLD_PIN
SHLD_PIN

R7322

AUDIO-IN

VCC
GND
VOUT

L7350

FERR-220-OHM

AUD_CONNJ2_SLEEVE
NO STUFF

OMIT
CRITICAL

R7349

IN

55

XW7301
SM

AUD_J2_COM

=GND_AUDIO_CODEC

5%
1/16W
MF-LF
402

55

XW7300
SM

AUD_J1_COM

NO STUFF
6

88611-02001

R7380

57

BI

a
n
i

2
0402

FERR-1000-OHM

10

AUD_PORTA_R

FERR-1000-OHM

2
0402

8
9

CRITICAL

J7302

NO STUFF

L7305

y
r

AUD_CONNJ1_TIPDET_F

APN:518S0332

L7303

C7308

SPEAKER CONNECTOR

0402

SHLD_PIN

AUD_CONNJ1_TIPDET

F-RT-TH
2
3

1
7

2
0402-LF

FERR-1000-OHM

AUDIO-OUT

AUD_CONNJ1_SLEEVE_F

L7302

5%
1/16W
MF-LF
402

OMIT
CRITICAL

FERR-120-OHM-1.5A

2
0402-LF

R7321

APN:514-0290
APN:514-0317

VCC
GND
VIN

AUD_CONNJ1_SLEEVE
NO STUFF

PP3V3_S0_AUDIO_SPDIF

54

L7301

FERR-120-OHM-1.5A
56

56

IN

MIC_LO_CONN
MIC_HI_CONN
MIC_SHLD_CONN

C
OF

73

108

PORT A DETECT
OUT AUD_SENSE_B

57 54

OUT AUD_SENSE_A
57

PORT E DETECT(E TELLS H TO TURN ON)


CODEC PORT ASSIGNMENTS

PP3V3_S0_AUDIO_F

R7405

39.2K
1

AUD_OUTJACK_INSERT_L

470K

5%
1/16W
MF-LF
402

AUD_PORTA_DET_L

5%
1/16W
MF-LF
402

NC

Q7401
2N7002DW-X-F

SOT-363

SOT-363

0.1UF

PORT A HP/LO

10V

20%
CERM

402

PP3V3_S0_AUDIO_F

100K 2

57

270K

57 56

AUD_J1_SLEEVEDET_R

Q7400

R7404

5.11K

SOT-363

1%
1/16W
MF-LF
402

C7402

4
57 54

10%

a
n
i

PP4V5_AUDIO_ANALOG

2N7002DW-X-F
5

AUD_J1_SLEEVEDET_R

R7414

AUD_SENSE_A

1%
1/16W
MF-LF
402

AUD_SENSE_B

16V

402

C7404

57 54

CERM
402

PORT G DETECT

AUD_SENSE_B

64 57 56 55 54

20%
10V

=GND_AUDIO_CODEC

NO STUFF

57 54

R7415

PP3V3_S0_AUDIO_F

20.0K
1%
1/16W
MF-LF

NO STUFF
1
1

R7460

R7411

5%
1/16W
MF-LF
2 402

Q7402

R7412
IN

47K

AUD_J2_TIPDET_R

56

IN

SOT-363

NO STUFF
1
4

C7411

C7412
0.01UF
10%

0.1UF
20%
CERM

m
il

2N7002DW-X-F

Q7402

16V

2 CERM

10V

402

402

=GND_AUDIO_CODEC

AUD_J2_SLEEVEDET_R

MIC INPUT CIRCUITRY


R7450
6.8K
1

R7451
56

IN

1/16W
MF-LF

5%
402

1
1/16W
MF-LF
CRITICAL

5%
402

2
2

5%
1/16W
MF-LF
402

IN

54

C7452

MIC_LO

AUD_BI_PORT_B_R

54

0.001UF
50V

CERM
402

=GND_AUDIO_CODEC

56

IN

MIC_SHIELD

5%
1/16W
MF-LF
402

R7454
0
1

=GND_CHASSIS_AUDIO_MIC

5%
1/16W
MF-LF
402

AUD_PORTA_R

POLY
B2

HP/LO DE-POP SWITCH

APN:353S1459

R7438
1

AUD_GPIO_1

5%
1/16W
MF-LF
402

AUD_BI_PORT_A_L

BI

4.7

C2
VCC

AUD_BI_PORT_A_R

BI

U7400

5%
1/10W
MF-LF
603

C1

4.7

5%
1/10W
MF-LF
603

MAX9890
CEXT C3

SHDN*

MAX9890_CEXT

MAX9890_INL

B1 INLCRITICALOUTL A1

AUD_PORTA_L_R

57

MAX9890_INR

B3 INR

UCSP1 OUTR A3

AUD_PORTA_R_R

57

R74391
10K

0.1UF
20%
10V

402

=GND_AUDIO_CODEC

PP3V3_S0_AUDIO_F

57

C7400

CRITICAL

PORT F LI

0.1UF
20%

CERM
402

54

BI

C7432

R7432

10V

4.7

AUD_BI_PORT_F_L

64 57 56 55 54

3.3uF

AUD_PORTF_L_R

5%
1/16W
MF-LF
402

10%
10V
CERM-X5R
805-1

AUD_PORTF_L

BI

56

AUD_PORTF_R

BI

56

R7436
47.0K

1%
1/16W
MF-LF
2 402

=GND_AUDIO_CODEC
1

R7437
47.0K

CRITICAL

C7433

R7433
54

BI

AUD_BI_PORT_F_R

4.7

3.3uF
AUD_PORTF_R_R

5%
1/16W
MF-LF
402

OUT AUD_BI_PORT_E_R

BAL_IN_COM
BAL_IN_R
BAL_IN_L

OUT

54

OUT

54

OUT

54

OUT AUD_BI_PORT_D_L

AUDIO: JACK TRANSLATORS


1

SYNC_MASTER=M42AUDIO

R7440
20K

5%
1/16W
MF-LF
2 402

CRITICAL

C7440

0.1UF
16V

CRITICAL

CRITICAL

C7441

C7445

0.1UF

10%
X5R
402

1%
1/16W
MF-LF
402

10%
10V
CERM-X5R
805-1

UNUSED CODEC ANALOG PORT TERMINATIONS

OUT AUD_BI_PORT_E_L

10%
2

16V

X5R
402

CRITICAL
1

0.1UF

0.1UF
10%
16V
X5R
402

C7446

CRITICAL
1

16V

X5R
402

C7447
0.1UF

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

10%

10%
2

SYNC_DATE=08/05/2006

NOTICE OF PROPRIETARY PROPERTY

16V

X5R
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

=GND_AUDIO_CODEC

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7173

SCALE

C7435

2 CERM

5%
1/16W
MF-LF
402 2

SIZE

NO STUFF

=GND_AUDIO_CODEC

64 57 56 55 54

20%

6.3V

CRITICAL

54

54

1%
1/16W
MF-LF
2 402

0402

54

54 55 56 57 64

NO STUFF

R7453

ACZ_RST_L

64 57 56 55 54

PLACE C7452 NEAR U6800

10%

XW7400

NO STUFF

56

R7435
47.0K

100UF

54

AUD_BI_PORT_B_L
MAKE_BASE=TRUE

CRITICAL

SM
56

CRITICAL

R7452
100K

10%
CERM
402

10% 16V
X5R 402

0.001UF
50V

MIC_IN

C7451

C7450
0.1uF

330

MIC_HI

AUD_VREF_PORT_B

=PP3V3_S0_AUDIO

64 57 56 55 54

BI

1%
1/16W
MF-LF
402

FERR-1000-OHM

e
r

C7431

R7431

54

CRITICAL

R7430

L7400

64 56 54

IN

54

56

47.0K

POLY
B2

BI

R7434

PP4V5_AUDIO_ANALOG

IN

54

SOT-363

NC

2 402

2N7002DW-X-F
5

AUD_J2_DET_RC

5%
1/16W
MF-LF
402

64 57 56 55 54

1%
1/16W
MF-LF
2 402

AUD_PORTG_DET_L

5%
1/16W
MF-LF

20.0K

56

R7413

54 21 5

2 402

270K

AUD_INJACK_INSERT_L

470K

AUD_PORTA_R_R

CERM
402

1
57

57

0.1UF

20%

PORT F DETECT

=GND_AUDIO_CODEC

54 57

C7414

0.1UF
10V

64 57 56 55 54

5.11K

2 CERM

=GND_AUDIO_CODEC

AUD_PORTA_L
1

6.3V

57 54

0.01UF

64 57 56 55 54

20%

5%
1/16W
MF-LF
2 402

AUD_PORTA_L_R

AUD_J1_SLEEVEDET_INV

5%
1/16W
MF-LF
402

R7461

IN

C7430
100UF

57 56

CRITICAL

=GND_AUDIO_CODEC

R7403
57

y
r

C7401

2N7002DW-X-F

SOT-363

2
64 57 56 55 54

AUD_J1_DET_RC

AUD_PORTE_DET_L

Q7401

2N7002DW-X-F

47K
1

NC

Q7400

R7402
AUD_J1_TIPDET_R

1%
1/16W
MF-LF

2 402

IN

39.2K

1%
1/16W
MF-LF
2 402

R7401

PORT A :HEADPHONE/LINE OUT


PORT B :MICROPHONE ON BOTH CH (ADC 0)
PORT C :SPEAKER AMP
PORT D :UNUSED
PORT E :SW USES TO TRIGGER DIGITAL OUT
PORT F :LINE IN (ADC 1)
CD INPUT :UNUSED

R7406

56

A2 GND

57 54

C
OF

74

108

1
TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

BOM OPTION

REF DES

COMMENTS:

128S0093

128S0092

C7501,C7508

KEMET T520V336M016ATE0457650

128S0093

128S0092

C7509,C7517

KEMET T520V336M016ATE0457650

TABLE_ALT_ITEM

TABLE_ALT_ITEM

=PP5V_S0_IMVP6

64

10
5%
1/16W
MF-LF
402

1uF
10%
16V
X5R
603

PPVIN_S5_IMVP6_VIN

R7520
5%
1/16W
MF-LF
402

PM_DPRSLPVR

IN

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

C7596

DPRSTP*

2-Phase CCM

1-Phase CCM

1-Phase DCM

NO STUFF

4.02K

470K
402

R7527

58 9
58 9

58 9

2
1

ERT-J0EV474J

C7510

IMVP6_NTC_R

58 9

R7506

5%
1/16W
MF-LF
402

CPU_PROCHOT_L
1

R7519

IN

63 62

IN

499

1%
1/16W
MF-LF
402
26

FROM SMC

45
26 14

IN
OUT

147K

0.015uF

1%
1/16W
MF-LF
402
1

58

42
41
40
39
38
37

46
45
2
3

VR_PWRGD_CK410_L
IMVP_VR_ON
VR_PWRGOOD_DELAY
IMVP6_VR_TT
IMVP6_NTC

OUT

R7508

C7505
10%
16V
X7R
402

43

CPU_DPRSTP_L
IMVP_DPRSLPVR
CPU_PSI_L
1V51V05S0_PGOOD

IN

58 9

21 7

NO STUFF

46
7

58 9

1%
1/16W
MF-LF
2 402

0.01uF
10%
16V
CERM
402
1

58 9

R7545
499

NO STUFF

22

58 5

VID5

U7500

5
6

BOOT2

QFN

VID3
VID2

UGATE1

CRITICAL
PHASE1

VID0

LGATE1
PGND1

R7509
1.82K

1%
1/16W
MF-LF
402

470pF
10%
50V
CERM
402

58

R7513

58 5

2.0K
IMVP6_VDIFF_RC
1

12

IMVP6_FB2
IMVP6_FB
IMVP6_COMP
IMVP6_VW

58

NO STUFF

58

11
10
9

1%
1/16W
MF-LF
402

DPRSLPVR

25

R7511

58

IMVP6_LGATE1

58

IMVP6_UGATE2

58

IMVP6_PHASE2

LGATE2 30

58

IMVP6_LGATE2

VR_TT*

IMVP6_ISEN2

19

58

IMVP6_VSUM
IMVP6_OCSET
IMVP6_VO
IMVP6_DROOP

VSUM
OCSET 8

RBIAS

VO

58
58
48
58
48

18
16

58

IMVP6_DFB

RTN

COMP

14

R7518

15

1K

VW

NC

C7531

1%
1/16W
MF-LF
402

e
r
TPAD

49

GND_IMVP6_SGND

0.068UF

10%
10V
CERM
402

58

NO STUFF

R7514

C7507

47PF

(IMVP6_COMP)

Note 1: C7532,C7533 = 27.4 Ohm For Validating CPU Only.

4.42K
1%
1/16W
MF-LF
402

P
2

61.9K

R7510

OMIT

XW7500
SM

C7529
180pF

0.018UF

C7521
0.22uF

R7523

58
58
58
58
58
58

IMVP6_PHASE1
IMVP6_BOOT1
IMVP6_UGATE1
IMVP6_LGATE1
IMVP6_ISEN1
IMVP6_FET_RC1
IMVP6_VSUM_R1
IMVP6_VO_R1

MIN_NECK_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM

58
58
58
58
58
58

5%
50V
CERM
402

IMVP6_PHASE2
IMVP6_BOOT2
IMVP6_UGATE2
IMVP6_LGATE2
IMVP6_ISEN2
IMVP6_FET_RC2
IMVP6_VSUM_R2
IMVP6_VO_R2

20%
16V
2
POLY
CASED2E-SM

C7599

R7504
1

0.22uF

5%
1/16W
MF-LF
402

10%
6.3V
CERM-X5R
402

R7501
3.65K

1%
1/16W
MF-LF
402

CRITICAL

MPC1055LR36
DCR=0.8mOHM

HAT2168H

(IMVP6_PHASE2)

CRITICAL

Q7503

Q7505

0.36uH-30A-0.80mOhm
SM

NO STUFF

LFPAK

LFPAK

R7502
1

1%
1/16W
MF-LF
402

2
2
1
1

5%
1/8W
MF-LF
805

R7505

IMVP6_FET_RC2

10K

0.033UF

10%
16V
X5R
402

C7528

10%
6.3V
CERM-X5R
402

0.33uF

R7515
11K

1%
1/16W
MF-LF
402

IMVP6_VO_R

R7531

NO STUFF

C7502

NO STUFF
1

0.0022UF
10%
50V
CERM
402

D7501

0.0022UF
2

B340LBXF

10%
50V
CERM
402

R7507
1
5%
1/16W
MF-LF
402

10%
6.3V
CERM-X5R
402

NO STUFF

CRITICAL

C7592

C7504
0.22uF

1%
1/16W
MF-LF
402

58

R7530
1%
1/16W
MF-LF
402

L7501

HAT2165H

HAT2165H

11.5K

CRITICAL

LFPAK

C7511

0.0047UF

SMB
2

10%
25V
CERM
402

R7543
3.65K

1%
1/16W
MF-LF
402

10KOHM-5%
0603-LF

(IMVP6_ISEN2)

(IMVP6_VSUM)

ERT-J1VR103J

(IMVP6_VO)
TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

353S1465

ISL6262

U7500

M42

353S1461

ISL9504

U7500

M42A

TABLE_5_ITEM

5%
1/16W
MF-LF
402

CPU_VCCSENSE_P
CPU_VCCSENSE_N

8 58

58

8 58

58 9
58
58
58 48
58 48
58
58
58 5

MIN_NECK_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM

58
58
58
58 5
58
58 8
58 8
58
58

IMVP6_OCSET
CPU_VID_R<0..6>
IMVP6_VSUM
GND_IMVP6_SGND
IMVP6_VO
IMVP6_DROOP
IMVP6_DFB
IMVP6_SOFT
IMVP6_RBIAS
IMVP6_VDIFF
IMVP6_FB2
IMVP6_FB
IMVP6_COMP
IMVP6_VW
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_RTN
IMVP6_VSEN

MIN_LINE_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.50 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM

MIN_NECK_WIDTH
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM

IMVP6 CPU VCore Regulator


SYNC_MASTER=POWER

SYNC_DATE=07/13/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-7173

SCALE

BOM OPTION
TABLE_5_ITEM

R7522

MIN_LINE_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM

1uF
10%
16V
X5R
603

Q7502

CRITICAL

R7516

C7508
33UF

20%
16V
POLY
CASED2E-SM

5%
1/16W
MF-LF
2 402

48 58
64

CRITICAL

C7501

R0802/R0803 **on the CPU page** protect the IMVP6 if the CPU is not installed

10%
6.3V
CERM-X5R
402

SMB

33UF

10%
16V
X7R
402

C7503

10K

1%
1/16W
MF-LF
402

3.92K

IMVP6 CPU VCORE REGULATOR


MIN_LINE_WIDTH
1.5 MM
0.25 MM
1.5 MM
1.5 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM

C7534

C7533

R7500

10%
25V
CERM
402

B340LBXF

(IMVP6_VO)

0.01UF

5%
50V
CERM
402

R7517

5.11K

1%
1/16W
MF-LF
402

10%
50V
CERM
402

10%
16V
CERM
402

C7516

10%
16V
X5R
402

C7513

m
il
NO STUFF

FB2
VSEN

0.001uF

17

CRITICAL

CRITICAL

VDIFF

FB

10%
50V
CERM
402

C7512

0.0047UF

D7500

0.0022UF

58

NO STUFF

C7590

10%
50V
CERM
402

NTC

SOFT

C7500

0.0022UF

58

NO STUFF

ISEN2 23

=PPVIN_S5_IMVP6

C7532

390pF

PGOOD

10%
50V
CERM
402

a
n
i
1

(GND)

29

MPC1055LR36
DCR=0.8mOHM

(IMVP6_ISEN1)

28

PGND2

(IMVP6_VW)

NO STUFF

(GND)

33

58

IMVP6_COMP_RC

32

UGATE2 27

VR_ON

0.033UF

IMVP6_PHASE1

IMVP6_ISEN1

21

C7514

1%
1/16W
MF-LF
402

58

58

PHASE2

VSS

34

24

ISEN1

PGD_IN

1%
1/16W
MF-LF
402
58

IMVP6_UGATE1

(IMVP6_FB)

58

0.22uF

10%
6.3V
2 CERM-X5R
402

10%
6.3V
CERM-X5R
402

PSI*

1.40K

58

35

0.22uF

DPRSTP*

DFB

C7506

13

IMVP6_VDIFF

26

5%
1/16W
MF-LF
402

VID1

DROOP
58

C7527
1

IMVP6_BOOT1
IMVP6_BOOT2

58

VID4 ISL6262-SCRN

CLK_EN*

R7525

PVCC
BOOT1 36

3V3

44

VDD

64

SM

IMVP6_FET_RC1

C7515

=PPVOUT_S0_IMVP6_REG

0.36uH-30A-0.80mOhm

5%
1/8W
MF-LF
805

OMIT

47

IMVP6_RBIAS

36A MAX CURRENT


2

L7500

R7503
1

31

VID6

48

IMVP6_SOFT

LFPAK

2 IMVP6_BOOT2_RC

CPU_VID_R<6>
CPU_VID_R<5>
CPU_VID_R<4>
CPU_VID_R<3>
CPU_VID_R<2>
CPU_VID_R<1>
CPU_VID_R<0>

HAT2165H
4

NO STUFF

5%
1/16W
MF-LF
402

0.1uF

VIN

R7526

Q7504

HAT2165H

IMVP6_BOOT1_RC

R7524

20

1%
1/16W
MF-LF
402

y
r

CRITICAL

10%
16V
X5R
402

NO STUFF

CRITICAL

1-Phase DCM

LFPAK

C7530

5%
1/16W
MF-LF
402

GND_IMVP6_SGND

IMVP6_VSEN

R7521

PP3V3_S0_IMVP6_3V3

10

58

CRITICAL

(IMVP6_PHASE1)

IMVP6_RTN

1uF
10%
16V
X5R
603

Q7501

=PP3V3_S0_IMVP6

20%
16V
POLY
CASED2E-SM

C7518

33UF

20%
16V
POLY
CASED2E-SM

0.01UF
10%
16V
CERM
402

C7517

33UF

CRITICAL
1

C7509

HAT2168H

Operation Mode

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
64

PSI*

Q7500
LFPAK

4.7uF
20%
6.3V
CERM
603

=PPVIN_S5_IMVP6

DPRSLPVR

C7535

10
23 14

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

C7526

CRITICAL

CRITICAL

PP5V_S0_IMVP6_VDD

R7512

64 58 48

=PPVIN_S5_IMVP6

64 58 48

C
OF

75

108

5V/3.3V POWER SUPPLY

y
r
2

=PPVIN_S5_5V3V3S5
64 63

CRITICAL
2

R7621

0.1uF

1%
1/16W
MF-LF
402

C7640

33UF

C7609

1.02K

20%
16V
2
POLY
CASED2E-SM

10%
16V
X5R
402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
1

a
n
i
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

PP5V_S5_5V3V3S5_INTVCC

2
1

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

Q7620

4
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

64

L7620

4.7UH-6.5A

10%
2 16V
X5R
402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

PP3V3_S5_REG_P

CRITICAL

CRITICAL

C7652

C7651

20%
6.3V
POLY
SMC-LF

20%
6.3V
CERM-X5R
805

Q7621

3V3S5_BG

22

NC 3

<Rc>
R7627

1
1

C7629

63.4K

10%
50V
CERM
402

20.0K
2

NO STUFF

R7625

10K

1%
1/16W
MF-LF
2 402

GND_5V3V3S5_SGND

P
59

DESCRIPTION

REFERENCE DESIGNATOR(S)

152S0133

4.7UH,+/-20%,40mOHM,3mm

152S0365

4.7UH,+/-20%,40mOHM,2.8mm

59

FAIRCHILD FDM6296

CRITICAL

U7600

SW1

C7630
0.1uF

10%
16V
X5R
402

TABLE_5_HEAD

SW2

LTC3728LXC

BG1

QFN

5VS5_SW

15

5VS5_BG

BG2 18

12
SENSE2+
11
SENSE2-

SENSE1-

VOSENSE2

C7605
1

1uF

10%
6.3V
CERM
402

NC4 32

NC
NC
NC
NC

L7620

3V3_IND_2MM8

ALTERNATE FOR
PART NUMBER

BOM OPTION

REF DES

128S0092

C7680,C7640

376S0445

Q7620,Q7621

376S0445

Q7660,Q7661

OPEN-SAWTOOTH
1
2

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

OMIT

CRITICAL

CRITICAL

Q7661

STL8NH3LL

10%
50V
CERM
402

C7665

C7669

180PF

0.001UF

20%
6.3V
CERM-X5R
805

59

C7692
150uF

20%
2 6.3V
POLY
SMC-LF

<Ra>
R7667

5%
50V
CERM
402

1%
1/16W
MF-LF
402

NO STUFF

<Rb>
R7668

105K

5VS5_ITH_RC

5%
25V
CERM
402

1
1

0.1uF
10%
16V
X5R
402

22UF

2 3

10%
50V
CERM
402

PP5V_S5_REG_P
CRITICAL

C7690 C7691
22UF

CRITICAL

20%
2 6.3V
CERM-X5R
805

PWRFLT-3P3X3P3

0.001uF

64

VOLTAGE=5V

NO STUFF

C7661

=PP5V_S5_REG

JUMPER

IHLP2525/4.2UH
DCR=32 MOHM

R7665

20.0K

C7666
100PF

1%
1/16W
MF-LF
2 402

5%
2 50V
CERM
402

C7668

20.0K

0.001UF

10%
50V
CERM
402

XW7600

1%
1/16W
MF-LF
2 402

I629

5V3V3S5_PGOOD

RSMRST_PWRGD
45 46

MAKE_BASE=TRUE

PP5V_S5_5V3V3S5_INTVCC

C7602

C7601

20%
6.3V
CERM
603

1uF

10%
2 6.3V
CERM
402

4.7UF

R7606
2

5V3V3S5_FCB

5V3V3S3_CONT
1

R7607
0

5%
1/16W
MF-LF
2 402

COMMENTS:

KEMET T520V336M016ATE0457650

59

VOLTAGE=5V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

30.1K

0
5%
1/16W
MF-LF
2 402

R7603

C7607

5V3V3S5_FSEL

59

59

C7604

R7604

1%
1/16W
MF-LF
402

10%
2 16V
CERM
402

5.62K

0.01uF

10%
2 16V
CERM
402

1%
1/16W
MF-LF
402

0.01uF

5V / 3.3V Power Supply


SYNC_MASTER=POWER

SYNC_DATE=07/13/2005

NOTICE OF PROPRIETARY PROPERTY

VISHAY SI7806ADN

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

TABLE_ALT_ITEM

376S0448

XW7660

SM

TABLE_ALT_ITEM

376S0448

5A MAX CURRENT

4.2UH

SM

TABLE_ALT_ITEM

128S0093

CRITICAL

L7680

Vout = 0.8V * (1 + Ra / Rb)

TABLE_ALT_HEAD

PART NUMBER

1 2

5V3V3S3_SKIP

FET_FDN6296

PWRFLT-3P3X3P3

TABLE_5_ITEM

STL8NH3LL

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

BOM OPTION

3V3_IND_3MM

OMIT

59

C7670

Q7660

C7689

10%
6.3V
CERM-X5R
402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

220PF

NC1 10
NC2 16
NC3 29

10%
16V
X5R
402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

NC

INTVCC 20

0.22UF

2.74K
1%
1/16W
MF-LF
402

C7632

R7666

0.1uF

PGOOD 27

21 EXTVCC

1%
1/16W
MF-LF
402
2

5VS5_RUNSS

RUN_SS2 13

4 FCB

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

5VS5_ITH

ITH2 8

ITH1

28 RUN_SS1

R7669

5VS5_VOSNS

976

R7664 1
5%
1/16W
MF-LF
402

C7664

5V3V3S5_FSEL

PLLFLTR 2

PLLIN

PP5V_S5_REG_P

L7620

Q7620,Q7621,Q7660,Q7661

BOOST2

5VS5_BOOST

17

3_3VOUT 7

5V3V3S5_FCB

10%
50V
CERM
402

10%
50V
CERM
402

Vout = 0.8V * (1 + Rc / Rd)

376S0445

0.001uF

3V3S5_RUNSS

3V3S5_ITH_RC

C7628

VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

QTY

C7625

220PF

0.001uF

1%
1/16W
MF-LF
2 402

PART#

e
r

C76261

5%
2 25V
CERM
402

<Rd>
R7628

BOOST1

1 VOSENSE1
5

3V3S5_ITH
63

5%
50V
CERM
402

3V3S5_VOSNS

0.001UF

180PF

1%
1/16W
MF-LF
2 402

3 2

31

C7621

PWRFLT-3P3X3P3

5VS5_TG

TG2 14

TG1

30 SENSE1+

NO STUFF

STL8NH3LL

10%
50V
CERM
402

m
il
25

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

OMIT

22UF

3V3S5_SW

CRITICAL

C7650
20%
6.3V
CERM-X5R
805

DCR=40 mOHM

CRITICAL

22UF

150uF

IHLP2525/4.7uH

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

26

24

3V3S5_BOOST

JUMPER

0.001uF

VIN

3V3S5_TG

0.1uF

2 1

L812HW

OPEN-SAWTOOTH
1
2

=PP3V3_S5_REG

10%
50V
CERM
402

C7624

C7662

1%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

5%
1/16W
MF-LF
2 402

0.001uF

PGND

XW7620

5VS5_BOOST_RC

19

PWRFLT-3P3X3P3

OMIT
CRITICAL

C7622

R7670
1M

10%
2 16V
X5R
603

5%
1/16W
MF-LF
2 402

THRML_PAD

STL8NH3LL

5%
1/16W
MF-LF
402

1uF

1M

R7624

23

OMIT

CRITICAL

C7600

R7630

SGND

CMDSH-3

3V3S5_BOOST_RC

D7664

1%
1/16W
MF-LF
402

59

SOD-323

SOD-323

3.32K

10%
16V
X5R
402

CMDSH-3

R7626

0.1uF

4A MAX CURRENT

VOLTAGE=12V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

D7624

C7631

PP5V_S5_5V3V3S5_INTVCC
CRITICAL

PPVIN_S5_5V3V3S5_R
CRITICAL

5VS5_SNS_P

33

59

20%
16V
POLY
CASED2E-SM

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

1.5K

1%
1/16W
MF-LF
402
2
1

10%
6.3V
CERM-X5R
402

5VS5_SNS_N

1%
1/16W
MF-LF
2 402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

R7629

R7600
10

3V3S5_SNS_P

R7661

715

0.22UF

C7680
33UF

10%
16V
X5R
603

3V3S5_SNS_N

1uF

1uF
10%
16V
X5R
603

C7608

CRITICAL

C7681

C7641

VISHAY SI7806ADN

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

76

108

ENETPWR_EN
60

CRITICAL

U7700

R7750

=PPBUS_S5_YUKON_CTRL

470K

R7751

ENETPWR_EN

470K
5%
1/16W
MF-LF
2 402

60

SOT-363

10%
2 50V
CERM
402

Q7750

=PP3V3_S0_2V5S0
64

Q7750 HAS A BUILT-IN BODY DIODE

5%
1/16W
MF-LF
402

m
il

5%
1/16W
MF-LF
402

LOGIC

1
3

SOT23-5
IN
OUT

0.3A MAX CURRENT

SHDN_L

BP

PM_SLP_S4_L

FWPWR_EN_L

S3 | S0

~S0 | ~SMC_PS_ON

S3 ON BATTERY

TRUE (3.3V)

TRUE (PBUS 12.6V)

S0 OR S3 ON AC

TRUE (3.3V)

FALSE (0V)

ENETPWR_EN

POWER YUKON

TRUE (PBUS 12.6V)


FALSE (0V)

FALSE (0V)

TRUE (3.3V)

S5 ON AC

FALSE (0V)

TRUE (PBUS 12.6V)

TRUE (PBUS 12.6V)

FALSE (0V)

S5 ON BATT

FALSE (0V)

FALSE (0V)

TRUE (PBUS 12.6V)

FALSE (0V)

64

4 2V5S0_BP

GND

C7704

C7705
4.7uF

0.01uF

20%
2 6.3V
CERM
603

10%
16V
CERM
402

CRITICAL

U7720
MAX8516

ENETPWR_EN

C7720
1uF

10%
6.3V
2 CERM
402

NC
NC
NC

63 64

FB 7

1 EN

60

=PP1V2_S3_REG

OUT0 8
OUT1 9

2 IN0
3 IN1

<Ra>
1
R7720

1%
1/16W
MF-LF
2 402

20%
2 6.3V
CERM
603

5.11K

4 NC0
5 NC1
10 NC2
GND

0.5A MAX CURRENT

SOP

=PP1V8_S3_1V2S3

NOTE: IF CHANGE TO STUFFING R7753 THEN ENETPWR_EN IS BUFFERED PM_SLP_S4_L

63 64

VOLTAGE=2.5V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm

1.2V REGULATOR

e
r

PM_SLP_S3BATT

=PP2V5_S0_REG

THRML
PAD

1V2_FB

NOSTUFF

R7753

NAME

20%
2 6.3V
CERM
603

10%
16V
CERM
402

C7702
4.7uF

0.01uF

MAX8887

C7703

20%
2 6.3V
CERM
603

FWPWR_EN_L_R

C7701

11

GND

4.7uF

R7752
FWPWR_EN_L 1

BP

U7701

39

SHDN_L

CRITICAL

SOT-363

64

VOLTAGE=2.5V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm

2V5S3_BP

a
n
i

0.0022UF

2N7002DW-X-F

PM_SLP_S4_L

=PP2V5_S3_REG

63 61 45 23

SOT23-5
OUT

6
D

IN

4.7uF

C7750

Q7750

2N7002DW-X-F

PM_SLP_S3BATT

C7700

20%
2 6.3V
CERM
603

3
D

64 60

0.3A MAX CURRENT

MAX8887

=PP3V3_S3_2V5S3

5%
1/16W
MF-LF
2 402

y
r

=PP3V3_S3_2V5S3
64 60

64

2.5V REGULATORS

YUKON POWER CONTROL

C7721
4.7UF

<Rb>
R7721
3.65K

1%
1/16W
MF-LF
2 402

Vout = 0.5V * (1 + Ra / Rb)

2.5V/1.2V Regulator
SYNC_MASTER=ENET

SYNC_DATE=12/06/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

77

108

1.8V POWER SUPPLY


64

CRITICAL
1

=PP5V_S5_1V8S3
1

R7804

C7801

10%
16V
X5R
603

C7802

R7807

20%
6.3V
CERM1
603

GND_1V8S3_SGND

1V8S3_FSET

7 FSET

1V8S3_FCCM

4 EN
3 FCCM

PM_SLP_S4_L
NC
5

1V8S3_COMP

C7800

R7805
0

1V8S3_FB

R7808
100K

5%
1/16W
MF-LF
2 402

UG 14 1V8S3_UG

BOOT 13 1V8S3_BOOT
PHASE 15 1V8S3_PHASE
ISEN 9 1V8S3_ISEN

16 PGOOD
5 COMP

0.01UF

10%
16V
CERM
402

57.6K

1%
1/16W
MF-LF
2 402

6 FB

10%
50V
CERM
402

0.0022UF

2 1V8S3_BOOT_RC 1

22PF

5%
50V
CERM
402

XW7800
SM

61

R1-

V+

8 R1+
3

0.1uF

10%
16V
X5R
402

R7810

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

2.49K

1%
1/16W
MF-LF
402

C7810

IRF7832PBF

MEM_ISENSE

CRITICAL

R2

INA326EA-250

MEM_ISENSE_R2

4.53K

45 46

C7805
0.22UF

1%
1/16W
MF-LF
402

20%
6.3V
X5R
402

GND_SMC_AVSS

R7863

100K

SMC_MEM_ISENSE

R7803

U7801

PLACE RC CLOSE TO SMC


2

45 46 48 62 66

C7864
0.001UF

1%
1/16W
MF-LF
402

10%
50V
CERM
402

8A MAX CURRENT

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm

=PP1V8_S3_REG

CRITICAL

L7820

5 6 7 8

CRITICAL

SM

C7843

CRITICAL

CRITICAL

C7840

D7820

B340LBXF

20%
2 6.3V
CERM-X5R
805

SMB
1

1.53uH

22UF

CRITICAL

Q7821

PLACE C7804 NEAR U7801 PIN 7

V-

NC

CRITICAL

20%
2.5V-ESR9V
POLY
CASE-D2E-LF

CRITICAL
1

C7842
330UF

20%
2.5V-ESR9V
POLY
CASE-D2E-LF

R7801

5%
1/16W
MF-LF
402

<Ra>
R7821
4.02K

PP1V8_S3_R
1

22UF

20%
6.3V
CERM-X5R
805

64

NO STUFF
0

330uF

C7841

0.001uF
10%
50V
CERM
402

SO-8

C7809

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

NO STUFF

IRF7821PBF

Placement Note:

5%
1/16W
MF-LF
402

MSOP

1 2 3

R7800

2.2

5%
1/16W
MF-LF
402

PGND 10

e
r

C7807

10%
16V
X5R
402

Q7820

m
il

QFN

100

MEM_ISENSE_R1_P

U7800

R7860

2.0K

1%
1/10W
MF-LF
603

=PP3V3_S3_PDCISENS 64

R7861

0.1UF

CRITICAL

THRML
PAD

C7808

1/4W
MF-LF
1206

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

ISL6269

17

1V8S3_COMP_R

R7806

10%
16V
X5R
603

0.005 1
1%

5 6 7 8

VCC

8 VO

1%
1/16W
MF-LF
2 402

R7802

20%
6.3V
CERM1
603

LG 11 1V8S3_LG

=PP1V8_S3_MEM_NB

MEM_ISENSE_R1_N

1uF

2.2UF

CRITICAL
1 VIN

5%
1/16W
MF-LF
402

12

PVCC
61

NO STUFF 1

2.2UF

1uF

5%
1/16W
MF-LF
402

20%
16V
POLY
CASED2E-SM

C7831

C7804

64
29
28
19
14
16

NO STUFF

C7806

33UF

1V8S3_VCC

C7830

=PP1V8_S3_MEM_NB_SENSE

64

63 60 45 23

a
n
i

=PPVIN_S5_1V8S3

64

y
r
MEM_ISENSE_VCC

NO STUFF2

1%
1/16W
MF-LF
402

C7803
0.0047uF

10%
25V
CERM
402

1 2 3

SO-8

<Rb>
R7822
2.0K

GND_1V8S3_SGND

1%
1/16W
MF-LF
402

Vout = 0.6V * (1 + Ra / Rb)

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

BOM OPTION

REF DES

COMMENTS:

128S0093

128S0092

C7830

KEMET T520V336M016ATE0457650

PART NUMBER

ALTERNATE FOR
PART NUMBER

BOM OPTION

REF DES

COMMENTS:

128S0094

128S0060

C7842,C7843

PANASONIC EEFSX0D331ER

128S0095

128S0060

C7842,C7843

PANASONIC EEFSX0D331XE

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

1.8V Supply
SYNC_MASTER=POWER

SYNC_DATE=07/13/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

78

108

1.5V/1.05V POWER SUPPLY


2

10%
6.3V
CERM-X5R
402

a
n
i

1%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

R7929

1V05S0_SNS_P

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

4.53K

1%
1/16W
MF-LF
402
2
1

62

PP5V_S5_1V51V05S0_INTVCC

D7924

1V5S0_BOOST_RC

R7930

0
4
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

C7950

20%
6.3V
CERM-X5R
805

330UF

20%
2.5V-ESR9V
POLY
CASE-D2E-LF

D104C/2.8uH
DCR=10.7 mOhm

22UF

Q7921

NO STUFF

IRF7832PBF

C7921

SO-8
2

2
1

<Rc>
R7927

180PF

17.8K

1%
1/16W
MF-LF
2 402

CRITICAL
3 2 1

SMB

C7926

20.0K

1%
1/16W
MF-LF
2 402

NO STUFF

C7928

470pF

5%
50V
CERM
402

62

R7925

VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

GND_1V51V05S0_SGND
=PP5V_1V51V05S0_VCC
64

=PP1V05_S0_CPU_NB
2

64

NB_ISENSE_VCC

C7990

R7902

1%
1/4W
MF-LF
1206

20%
2 6.3V
CERM-X5R
805

0.002

22UF

CRITICAL

NB_ISENSE_R1_N

R7992
2.0K

1%
1/10W
MF-LF
603

NB_ISENSE_R1_P

C7991

C7903

22UF

0.1UF

20%
2 6.3V
CERM-X5R
805

10%
16V
X5R
402

V+

R1-

8 R1+
3

=PP3V3_S0_PDCISENS

3_3VOUT 7

4 FCB

INA326EA-250
MSOP

NB_ISENSE_R2

SMC_NB_ISENSE

R7905

4.53K
1%
1/16W
MF-LF
402

10%
6.3V
CERM-X5R
402

R7966

63

NC1 10
NC2 16
NC3 29
NC4 32

Q7960
IRF7821PBF

IRF7832PBF
SO-8

CRITICAL2

C7965

NC

SMB

C7969

R7991
100K

1%
1/16W
MF-LF
402

10%
50V
CERM
402

5%
25V
CERM
402

C7970

1%
1/16W
MF-LF
2 402

0.1uF
10%
16V
X5R
402

R7965
33.2K

C7966

47PF

6.34K

C7968
0.001uF

5%
2 50V
CERM
402

10%
50V
CERM
402

=PP3V3_S0_1V51V05S0

<Rb>
R7968
20.0K

1%
1/16W
MF-LF
2 402

C7905
1

1uF

B
64

R7901
10K

5%
1/16W
MF-LF
2 402

Vout = 0.8V * (1 + Ra / Rb)


1

1V51V05S0_PGOOD

58 63

XW7900

PP5V_S5_1V51V05S0_INTVCC

SM

10%
6.3V
CERM
402

C7902

C7901

20%
6.3V
CERM
603

1uF

10%
2 6.3V
CERM
402

4.7UF

1V51V05S0_SKIP

R7906
5%
1/16W
2 MF-LF
402

1V51V05S0_FCB

5%
1/16W
MF-LF
2 402

R7903

62

VOLTAGE=5V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

30.1K

1V51V05S0_CONT
1
R7907
0

45 46

1%
1/16W
MF-LF
402

1V51V05S0_FSEL

62

C7907

1%
1/16W
MF-LF
402

10%
2 16V
CERM
402

5.62K

0.01uF

10%
2 16V
CERM
402

R7904

62

C7904
0.01uF

1.5V / 1.05V Power Supply


SYNC_MASTER=POWER

SYNC_DATE=07/13/2005

NOTICE OF PROPRIETARY PROPERTY

20%
6.3V
X5R
402

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

BOM OPTION

128S0092

REF DES

COMMENTS:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

45 46 48 61 66

C7999

128S0093

C7980,C7940

KEMET T520V336M016ATE0457650

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

0.001UF
2

<Ra>
R7967

2 1%
1/16W
MF-LF
402

NO STUFF

C7906

GND_SMC_AVSS
1

0.0022UF

TABLE_ALT_ITEM

330UF

0.22UF
2

C7992

20%
2 2.5V-ESR9V
POLY
CASE-D2E-LF

1V05S0_ITH_RC

220PF
2

B240-X-F
1 2 3

330PF

C7989

CRITICAL

1.53uH
SM
PCI-1050
DCR=6.3 mOHM

D7961

10%
50V
CERM
402

5 64

VOLTAGE=1.05V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

L7960

Q7961

0.001uF

1V05S0_RUNSS

=PP1V05_S0_REG

CRITICAL

CRITICAL

10%
50V
CERM
402

8A MAX CURRENT

SO-8

5 6 7 8

C7961

NC
NC
NC
NC

CRITICAL

1 2 3

62

NO STUFF

2.1K
1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

1V05S0_ITH

INTVCC 20

R7969

698

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

PLACE RC CLOSE TO SMC


1

0.22UF

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

PGOOD 27

21 EXTVCC

10%
16V
X5R
402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

PLACE C7903 NEAR U7901 PIN 7

NB_ISENSE

C7932

0.1uF

Placement Note:

U7901

RUN_SS2 13

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

1V05S0_VOSNS

5%
1/16W
MF-LF
402

CRITICAL

R2

100

V-

64 66

11

C7964

1V51V05S0_FSEL

12

R7990

CRITICAL
2

10%
16V
X5R
402

VOSENSE2

28 RUN_SS1

C7930

1V05S0_BG

ITH2 8

0.1uF

1%
1/16W
MF-LF
402

BG2 18

SENSE2-

ITH1

1V51V05S0_FCB

24.3K

=PP1V05_S0_CPU_NB_SENSE 1

1 VOSENSE1

10%
50V
CERM
402

10%
50V
CERM
402

Vout = 0.8V * (1 + Rc / Rd)

64

C7925

1V05S0_SW

SENSE2+

5%
1/16W
MF-LF
402

1V05S0_BOOST

PLLFLTR 2

1V5S0_ITH

1V5S0_ITH_RC

0.001UF
2

47pF

<Rd>
1
R7928

QFN

1V5S0_VOSNS

1V5S0_RUNSS

63 5

LTC3728LXC

BG1

30 SENSE1+
31 SENSE1-

e
r

1V05S0_TG

17

10%
50V
CERM
402

15

SW2

R7964

0.001uF

10%
6.3V
CERM-X5R
402

5 6 7 8

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

0.22UF

1%
1/16W
MF-LF
402

1V05S0_BOOST_RC

C7962

m
il
22

U7900

NC 3 PLLIN

10%
50V
1 CERM
402

5%
50V
CERM
402

1V5S0_BG

0.001uF

D7921
B240-X-F

C7929

25 SW1

BOOST2

CRITICAL

PGND

1V5S0_SW

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

CRITICAL

SM

5%
1/16W
MF-LF
2 402

TG2 14

TG1

24 BOOST1

THRML_PAD

C7952

8 7 6 5

2.8UH

CRITICAL

CRITICAL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

L7920

26

1V5S0_BOOST
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

1M

VIN

1V5S0_TG

CRITICAL

PP1V5_S0_REG_P

10%
50V
CERM
402

R7970

10%
2 16V
X5R
603

19

JUMPER
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

SO-8

0.001uF

C7924

10%
2 16V
X5R
402

IRF7821PBF
1

0.1uF

Q7920

XW7920
=PP1V5_S0_REG

3 2 1

CRITICAL

6A MAX CURRENT

5%
1/16W
MF-LF
2 402

C7922

5%
1/16W
MF-LF
402

1uF

1M

R7924

23

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

C7900

C7908

523

2
8 7 6 5

SGND

CMDSH-3

33

1%
1/16W
MF-LF
402

D7964

SOD-323

SOD-323

1.43K

10%
6.3V
CERM-X5R
402

62

CRITICAL

CMDSH-3

R7926

0.22uF

OPEN-SAWTOOTH
1
2

VOLTAGE=12V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

CRITICAL

C7931

PP5V_S5_1V51V05S0_INTVCC

PPVIN_S5_1V51V05S0_R

R7961

20%
16V
POLY
CASED2E-SM

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

10

1V5S0_SNS_P

33UF

R7900

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

C7980

1V05S0_SNS_N

1V5S0_SNS_N

1uF
10%
16V
X5R
603

0.22uF

1%
1/16W
MF-LF
402
1

20%
16V
POLY
CASED2E-SM

10%
16V
X5R
603

CRITICAL

C7981

1uF

33UF

R7921 C7909

1.07K

C7941

C7940

CRITICAL
1
2

64

y
r

=PPVIN_S5_1V51V05S0

64

II NOT TO REPRODUCE OR COPY IT

10%
50V
CERM
402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

BOM OPTION

128S0094

128S0060

REF DES

COMMENTS:
SIZE

DRAWING NUMBER

REV.

TABLE_ALT_ITEM

C7952,C7992

PANASONIC EEFSX0D331ER

APPLE COMPUTER INC.

TABLE_ALT_ITEM

128S0095

128S0060

C7952,C7992

PANASONIC EEFSX0D331XE

051-7173

SCALE

SHT
NONE

C
OF

79

108

=PP5V_S3_FET

POWER CONTROL SIGNALS


64

These rails are monitored by LTC2908

CRITICAL

State

SMC_PM_G2_ENABLE

PM_SLP_S4_L

PM_SLP_S3_L

Run
(S0)

Q8000
FDC638P
SM-LF

MAKE_BASE=TRUE

Sleep
(S3)

Soft-Off
(S5)

Battery Off
(G3Hot)

64 63

=PP5V_S5_PWRCTL

=P5VS3_EN_L

R8032

R8033

Q8031

=P3V3S3_EN_L

5%
1/16W
MF-LF
402
1
2

0.01UF

Q8060

OMIT

SOT23-LF

Q8059

2N7002DW-X-F

R8056

100K

SOT-363

=P5VS0_EN

5%
1/16W
MF-LF
2 402

R8005

C8005

5%
1/16W
MF-LF
402

10%
25V
X5R
402
1

0.1UF

10K
1

P5VS0_EN_RC

CRITICAL

Q8015
OMIT

STL8NH3LL

m
il
64

=PP3V3_S5_P3V3S0

1V5S0_RUNSS 5

62

Q8061

2N7002DW-X-F

64 63

=PP3V42_G3H_PWRCTL

48

PM_SLP_S3

R8059

470K

=P3V3S0_EN

5%
1/16W
MF-LF
402

1V05S0_RUNSS

Q8062

PM_SLP_S3_L

1
1

R8058
100K

SOT23-LF

62

e
r
R8031

Q8061

100K

2N7002DW-X-F

SOT-363

5%
1/16W
MF-LF
2 402

64 59

C8015

5%
1/16W
MF-LF
402

10%
25V
X5R
402
1

0.1UF

P3V3S0_EN_RC

=PPVIN_S5_5V3V3S5

5%
1/16W
MF-LF
402

MAKE_BASE=TRUE

PM_SLP_S3_LS12V6_L

R8030
100K

5%
1/16W
MF-LF
2 402

PM_SLP_S3_LS12V6

Q8030

64 60

SOT23-LF 3

=PP1V2_S3_REG

CRITICAL

=PP5V_S5_PWRCTL

SOT-6

MAKE_BASE=TRUE

PM_SLP_S3_LS5V

5%
1/16W
MF-LF
402

63 45 23

=PP3V42_G3H_REG

C8092

<Ra>
1
R8091

5%
50V
CERM
402

MOSFET

STL8NH3LL

CHANNEL

N-TYPE

RDS(ON)

15 mOhm @10V

LOADING

3 A

1%
1/16W
MF-LF
2 402

Q8031

C8025
0.01UF

=P1V8S0_EN_L 1

10%
16V
CERM
402
1

P1V8S0_EN_L_RC

22UF

Vout = 1.25V * (1 + Ra / Rb)

ALL SYSTEM PWRGD CIRCUIT


62 58

1V51V05S0_PGOOD

64

3.3V S0 FET
MOSFET

STL8NH3LL

CHANNEL

N-TYPE

RDS(ON)

15 mOhm @10V

LOADING

2 A

64 60

=PP2V5_S0_REG

C8060

20%
10V
CERM
402

0.1UF

1
5

V1

20%
2 10V
CERM
402

V2

CRITICAL

U8070

7 V3

C8061
0.1UF

=PP3V3_S0_ALLSYSPG

LTC2908

6 VADJ1

RST* 2

1
8 VADJ2

1.2V S0 FET

GND
1

MOSFET

2N7002

CHANNEL

N-TYPE

RDS(ON)

13.5 Ohm

LOADING

Nothing

R8065

THRML
PAD
9

549K

ALL_SYS_PWRGD

3
C8062 U8080
MC74VHC1G08
SC70

20%
2 10V
CERM
402

S0PWRGD_0V9_DIV
=PP0V9_S0_MEM_REG

100K
1%

68.1K
1%
1/16W
MF-LF
402

1.8V S0 FET
SI3447BDV

CHANNEL

P-TYPE

RDS(ON)

72 mOhm @1.8V

LOADING

320 mA

R8062

R8061

64

MOSFET

5 26 45

0.1UF

1%
1/16W
MF-LF
2 402

64 31

=PP1V8_S0_FET

S0PWRGD_OK

64

LLP

3 V4

1/16W
MF-LF
402

S0PWRGD_1V2_DIV
1

C8093

20%
2 6.3V
CERM-X5R
805

200K

4
2

64

CRITICAL
1

10%
25V
X5R
1206-1

=PP1V8_S3_P1V8S0

1%
1/16W
MF-LF
2 402

P3V42G3H_FB

6
64

348K

22pF

C8090

64

SI3447BDV

SOT-363

R8064

R8063

100K
1%

124K
1%
1/16W
MF-LF
402

1/16W
MF-LF
402

R8025

100K

PM_SLP_S3_L

Q8025

1
2N7002DW-X-F

R8050

1 A

=P1V2S0_EN

<Rb>
1
R8092

10UF

SOT-363

64 63

PP1V2_S0

2N7002DW-X-F

PM_SLP_S3_L

y
r

CDPH4D19F-SM

NC

2N7002

Q8030

63 45 23

65 mOhm @2.5V

33uH

CRITICAL

Q8063

2N7002

63 45
23

IN

R8015

100K

SOT-363

RDS(ON)

=PP3V3_S0_FET

PWRFLT-3P3X3P3
3

1.5V/1.05V S0 RUN/SS CONTROL

P-TYPE

5 PP3V42G3H_SW
7

L8090

GND
4

5V S0 FET

59

2N7002

CHANNEL

=PP5V_S0_FET

SMC_PM_G2_EN

=PP5V_S5_P5VS0

FDC638P

0.22uF

10%
6.3V
CERM-X5R
402

SW
BIAS

a
n
i

STL8NH3LL

3V3S5_RUNSS

45

Q8005

64

MOSFET

LOADING

CRITICAL

5%
1/16W
MF-LF
402

IN

10%
16V
CERM
402
1

P3V3S3_EN_L_RC

470K

C8091

6
BOOST

SHDN* TSOT23-8

1
64

3.3V S3 FET

C8010

100K

59

P3V42G3H5_BOOST

FB

PWRFLT-3P3X3P3

R8057

3
VIN

NC

6
5
2
1

R8010

SOT-363

=PPVIN_G3H_P3V42G3H

LT3470

=PP3V3_S3_FET

2N7002DW-X-F

5 G
SMC_PM_G2_EN_L

64

SM-LF

Q8059

=PP3V42_G3H_PWRCTL1

100 mA

64 63

LOADING

SOT-363

5%
1/16W
MF-LF
402

5VS5_RUNSS 5

48 mOhm @4.5V

2N7002DW-X-F

100K

5V/3.3V S5 RUN/SS CONTROL

P-TYPE

RDS(ON)

Q8010
FDC638P

=PP3V3_S5_P3V3S3

64

CHANNEL

CRITICAL

5%
1/16W
MF-LF
402

PM_SLP_S4_L

0.0022uF
10%
50V
CERM
402
1

U8090

61 60 45 23

FDC638P

CRITICAL

10K

5%
1/16W
MF-LF
402

P5VS3_EN_L_RC

Supply needs to guarantee 3.31V delivered to SMC VRef generator

MOSFET

R8000

100K

PM_SLP_S4_LS5V

64

5V S3 FET

C8000

3.425V "G3Hot" SUPPLY

6
5
2
1

=PP5V_S5_P5VS3

100K
6

5%
1/16W
MF-LF
402

S3/S0 FETS, G3H SUPPLY

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

376S0445

FAIRCHILD FDM6296

Q8005,Q8015

SYNC_MASTER=ENET

FET_FDN6296

SYNC_DATE=08/30/2005

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

TABLE_ALT_HEAD

2N7002DW-X-F

PART NUMBER

ALTERNATE FOR
PART NUMBER

BOM OPTION

376S0448

376S0445

SOT-363

REF DES

COMMENTS:

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


TABLE_ALT_ITEM

Q8005,Q8015

VISHAY SI7806ADN

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

80

108

7
"S0" RAILS

PPVCORE_CPU_S0
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=0.9V

(REGULATOR OUTPUT CPU VCORE PWR)


58

=PPVOUT_S0_IMVP6_REG
(CPU VCORE PWR)

(LDO OUTPUT 0.9V PWR)


(DDR2 TERMINATION 0.9V PWR)

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=1.05V

(REGULATOR OUTPUT 1.05V PWR)


62 5

PP5V_S0

=PP1V05_S0_REG
(ICH CPU I/O 1.05V PWR)
(ICH VCORE 1.05V PWR)

63

=PP1V05_S0_SB_CPU_IO
=PPVCORE_S0_SB
=PP1V05_S0_CPU_NB_SENSE

21 24 25
24 25
62

PP1V05_S0_CPU_NB
62

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=1.05V

=PP1V05_S0_CPU_NB
(MCH CORE 1.05V PWR)
(CPU FSB 1.05V PWR)
(MCH FSB 1.05V PWR)
(MCH FSB 1.05V PWR)

=PPVCORE_S0_NB
=PP1V05_S0_CPU
=PP1V05_S0_FSB_NB
=PP1V05_S0_NB_VTT
=PP1V05_S0_NB
PP1V5_S0
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=1.5V

(REGULATOR OUTPUT 1.5V PWR)


62

=PP1V5_S0_REG

(CPU AVDD
(MCH PCIE GRAPHICS O/P COMPENSATION
(MCH DDR DLL&IO, FSB HSIO&IO
(MCH DIGITAL DIVIDER IN HMPLL
(MCH LVDS DIGITAL
(HOST/MEMORY PLL
(MCH TVDAC DEDICATED/QUIET
(MCH 3GIO[PCIE/DMI]
(MCH 3GIO PLL
(ICH LOGIC&IO[ARX]
(ICH SATA PLL
(ICH LOGIC&IO[ATX]
(ICH USB PLL
(ICH USB CORE
(ICH LOGIC&IO

1.5V PWR)
1.5V PWR)
PWR 1.5V)
1.5V PWR)
1.5V PWR)
1.5V PWR)
PWR 1.5V)
1.5V PWR)
1.5V PWR)
1.5V PWR)
1.5V PWR)
1.5V PWR)
1.5V PWR)
1.5V PWR)
1.5V PWR)

(WIRELESS CARD 1.5V PWR)

(DDR2 TERMINATION REGULATOR 1.8V SWITCH PWR)


(TMDS 1.8V PWR)

=PP2V5_S0_REG
(MCH H/V SYNC
(MCH LVDS DATA/CLK TX
(MCH PCIE/DMI BAND GAP
(MCH LVDS ANALOG
(MCH CRTDAC ANALOG
(TMDS

2.5V
2.5V
2.5V
2.5V
2.5V
2.5V

PWR)
PWR)
PWR)
PWR)
PWR)
PWR)

(COME FROM S5 TO S0 MOSFET)

=PP3V3_S0_FET
(MCH HV BUFFER 3.3V PWR)

(ICH GPIO PULLS 3.3V PWR)


(ICH IO BUFFER 3.3V PWR)
(ICH PCI I/O 3.3V PWR)
(ICH IDE I/O 3.3V PWR)
(ICH PCI PULLS 3.3V PWR)
(ICH PM PULLS 3.3V PWR)
(PATA PULLS 3.3V PWR)
(SATA 3.3V PWR)
(MCH PULLS 3.3V PWR)
(ICH LAN I/F 3.3V PWR, NEED TO CHECK INTEL)
(ICH INTEL HDA CORE 3.3V PWR)
(DIMM SPD 3.3V PWR)
(CLOCK GENERATOR 3.3V PWR)
(WIRELESS CARD 3.3V PWR)
(TPM 3.3V PWR)
(AUDIO 3.3V PWR)
(TMDS 3.3V PWR)
(CPU THERMAL SENSOR 3.3V PWR)
(ISL6262 3V3)

(FIREWIRE DIGITAL 3.3V PWR)

PP1V2_S3

19

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V

63 60

=PP1V2_S3_REG
(ENET 1.2V PWR)

PP3V42_G3H

31

55

63

=PP3V42_G3H_REG

y
r

58
62

(LPC DEBUG BOARD)

68 69
5 51
67

(SMC 32.768KHz OSC)


(SMC 3.3V PWR)

48

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=1.8V

(REGULATOR OUTPUT 1.8V PWR)

16 17 19

61

=PP1V8_S3_REG

17 19

(DDR2 DIMM 1.8V PWR)


17 19
19
19
19

a
n
i
36

66

=PP1V8_S3_MEM
=PP1V8_S3_P1V8S0
=PP1V8_S3_MEMVTT
=PP1V8_S3_MEM_NB_SENSE
=PP1V8_S3_1V2S3

19
19
24 25

19 28 29
63
31

61

60

66

24 25

61 29 28 19 16 14

=PP1V8_S3_MEM_NB

PP1V8_S3_MEM_NB

(MCH DDR2 1.8V PWR)

24 25
24 25

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=1.8V

24 25
24 25

PP2V5_S3

25

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=2.5V

(REGULATOR OUTPUT 2.5V PWR)

43

(ENET 2.5V PWR)

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.16 MM
VOLTAGE=3.3V

=PP3V3_S3_FET

68

(ETHERNET 3.3V PWR)


(BLUETOOTH 3.3V PWR)
(ACCELEROMETER 3.3V PWR)
(TPM 3.3V SUSPEND PWR)
(TPS62050 VIN)
(FIREWIRE CHIP PCI SIGNAL INDICATOR)

17 19
17 19
17 19
17 19

e
r

19
68
19

63

17 19
22 25 34
21 23
24 25
24 25

P
24 25
26
26
34
46

14 19 20
24 25

24 25
28 29
32
43

53

54 56 57

=PP5V_S3_FET

(ISL6269 PVCC)
(SYSTEM LED PWR)
(USB IO PORT 5V PWR)
(USB IR CONTROLLER 5V PWR)

10 49

=PP5V_S3_SYSLED
=PP5V_S3_CAMERA
=PP5V_S3_IR
=PP5V_S3_GEYSER

63
65
5 47
26
65 66
46
45 46 48

=PPBUS_S5_INV

67

=PPVIN_S5_IMVP6

48 58

=PPVIN_S5_1V51V05S0

62

=PPVIN_S5_5V3V3S5
=PPVIN_S5_1V8S3
=PPBUS_S5_FWPWRSW
=PPBUS_S5_YUKON_CTRL

(LTC3728 VIN)
(ISL6269 VIN)
(FIREWIRE PORT PBUS PWR)
(YUKON POWER CONTROL)

PP18V5_G3H
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.5V

=PP18V5_G3H_INRUSH

59 63
61
39
60

=PP18V5_G3H_CHGR

(DC-IN OUTPUT 18.5V PWR)


(CHARGER INPUT 18.5V PWR)
(SMC INPUT 18.5V PWR)

66

27
36
44

46 52

46 53

DCIN G3HOT

60
38
26

PPDCIN_G3H

43

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
VOLTAGE=18.5V

38
61

65
66

=PPDCIN_G3H
=PPVBATT_G3H

=PPVIN_G3H_P3V42G3H

63

GND RAILS

35 46
67

XW8101
SM

41
40
57 56 55 54

=GND_AUDIO_CODEC

GND_AUDIO_CODEC

MAKE_BASE=TRUE

XW8102
SM
56 55

=GND_AUDIO_PWR

GND_AUDIO_PWR

MAKE_BASE=TRUE

PP3V3_S5
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
VOLTAGE=3.3V

=PP3V3_S5_REG

58
26

27
27

PWR)
PWR)
PWR)
PWR)
PWR)
PWR)
PWR)

=PP3V3_S5_SB
=PP3V3_S5_SB_USB
=PP3V3_S5_SB_PM
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S5_SB_VCCSUS3_3_USB
=PP3V3_S5_SB_IO
=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA
=PP3V3_S5_ROM
=PP3V3_S5_P3V3S3
=PP3V3_S5_P3V3S0
=PP3V3_S5_FWLATEVG
=PP3V3_S5_LCD

23 25
22
11 23 26
24 25
24 25
22
24
50
63

Power Conn / Alias

63
39

SYNC_MASTER=ENET

SYNC_DATE=11/16/2005

67

NOTICE OF PROPRIETARY PROPERTY

27
63

PP5V_S5

5 51

(REGULATOR OUTPUT 5 PWR)

67
59

=PP5V_S5_REG

66

48
27
62
60
39

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
VOLTAGE=5V

=PP5V_S5_SB
=PP5V_S5_P5VS3
=PP5V_S5_PWRCTL
=PP5V_S5_P5VS0
=PP5V_S5_USB
=PP5V_S5_PATA
(PATA
=PP5V_S5_1V8S3

62 66

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

25

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

63
63

SIZE
63
42

5V PWR)

APPLE COMPUTER INC.

34

DRAWING NUMBER

SHT

61

NONE

REV.

051-7173

SCALE

36

27

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
VOLTAGE=12.6V

ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)

(ICH USB CTL PULLS 3.3V


(ICH PM 3.3V
(ICH SUSPEND 3.3V
(ICH SUSPEND USB 3.3V
(ICH SUSPEND PULLS 3.3V
(ICH INTEL HDA SUSPEND 3.3V
(SPI BOOTROM

68 69

=PP3V3_S3_SMBUS_SMC_RMT
=PP3V3_S3_ENET
=PP3V3_S3_BT
=PP3V3_S3_SMS
=PP3V3_S3_TPM
=PP3V3_S3_2V5S3
=PP3V3_S3_PCI
=PP3V3_S3_RSTGATE
=PP3V3_S3_AIRPORT_AUX
=PP3V3_S3_FW
=PP3V3_S3_PDCISENS
PP5V_S3
5

36

PPBUSB_G3H

(INVERTER PBUS PWR)


(ISL6262 VIN)
(LTC3728 VIN)

"S5" RAILS

(REGULATOR OUTPUT 3.3V PWR)

59

65

=PPBUSB_G3H

46

PBUS HOT

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
VOLTAGE=5V

(COME FROM S5 TO S3 MOSFET)

=PP2V5_S3_ENET
PP3V3_S3

(COME FROM S5 TO S3 MOSFET)

m
il

=PP2V5_S3_REG

=PPBUSA_G3H

=PP3V42_G3H_SMCVREF
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_LIDSWITCH
=PP3V42_G3H_LPCPLUS
=PP3V42_G3H_SB_RTC
=PP3V42_G3H_ACIN
=PP3V42_G3H_SMC_CLK
=PP3V42_G3H_SMC

5 47
19

=PP1V2_S3_ENET

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.425V

54 55

PP1V8_S3

8 9
13 19

60

=PP3V3_S0_NB_VCC_HV
=PP3V3_S0_SB
=PP3V3_S0_SB_GPIO
=PP3V3_S0_SB_VCC3_3
=PP3V3_S0_SB_VCC3_3_PCI
=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S0_SB_PCI
=PP3V3_S0_SB_PM
=PP3V3_S0_PATA
=PP3V3_S0_SMC_LS
=PP3V3_S0_NB
=PP3V3_S0_SB_VCCLAN3_3
=PP3V3_S0_SB_3V3_1V5_VCCHDA
=PPSPD_S0_MEM
=PP3V3_S0_CK410
=PP3V3_S0_AIRPORT
=PP3V3_S0_TPM
=PP3V3_S0_AUDIO
=PP3V3_S0_TMDS
=PP3V3_S0_THRM_SNR
=PP3V3_S0_IMVP6
=PP3V3_S0_RSTBUF
=PP3V3_S0_SMBUS_SB
=PP3V3_S0_SMBUS_SMC_0
=PP3V3_S0_SMBUS_SMC_MLB
=PP3V3_S0_ALLSYSPG
=PP3V3_S0_FAN_RT
=PP3V3_S0_LCD
=PP3V3_S0_PBATTISENS
=PP3V3_S0_PDCISENS
=PP3V3_S0_CPUPOWER
=PP3V3_S0_SMBUS_SMC_BSB
=PP3V3_S0_1V51V05S0
=PP3V3_S0_2V5S0
=PP3V3_S0_FW
=PP3V3_S0_ENET

35

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.32MM
VOLTAGE=1.2V

(LDO OUTPUT 1.2V PWR)

=PP2V5_S0_NB_VCCSYNC
=PP2V5_S0_NB_VCC_TXLVDS
=PP2V5_S0_NB_VCCA_3GBG
=PP2V5_S0_NB_VCCA_LVDS
=PP2V5_S0_NB_CRTDAC
=PP2V5_S0_TMDS
=PP2V5_S0_NB_DISP_PLL
PP3V3_S0

63

17 19

=PP1V8_S0_TMDS
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=2.5V

(COME FROM S3 TO S0 MOSFET)


63 60

12 19 33

63

PP2V5_S0

25

"S3"
RAILS
ON IN RUN AND SLEEP

7 8 9 11

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=1.8V

(COME FROM S3 TO S0 MOSFET)

=PP1V8_S0_FET

G3 HOT

=PP5V_S0_SB
=PP5V_S0_SATA
=PP5V_S0_MEMVTT
=PP5V_S0_AUDIO
=PP5V_S0_AUDIO_PWR
=PP5V_S0_LPCPLUS
=PP5V_S0_NB_TVDAC
=PP5V_S0_IMVP6
=PP5V_1V51V05S0_VCC
=PP5V_S0_TMDS
=PP5V_S0_FAN_RT
=PP5V_S0_LCD
=PP5V_S0_ISENSECAL

16 19

=PP1V5_S0_CPU
=PP1V5_S0_NB_PCIE
=PP1V5_S0_NB_VCCAUX
=PP1V5_S0_NB_VCCD_HMPLL
=PP1V5_S0_NB_VCCD_LVDS
=PP1V5_S0_NB_PLL
=PP1V5_S0_NB
=PP1V5_S0_NB_TVDAC
=PP1V5_S0_NB_3G
=PP1V5_S0_NB_3GPLL
=PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V5_S0_SB_VCCSATAPLL
=PP1V5_S0_SB_VCC1_5_A_ATX
=PP1V5_S0_SB_VCCUSBPLL
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
=PP1V5_S0_SB_VCC1_5_A
=PP1V5_S0_SB
=PP1V5_S0_AIRPORT
PP1V8_S0

63

=PP5V_S0_FET
(SATA 5V PWR)
(DDR2 TERMINATION)
(AUDIO 5V PWR)
(AUDIO SPEAKER 5V PWR)
(LPC DEBUG BOARD 5V PWR)
(MCH TV 3.3V LDO)
(ISL6262 VDD)
(LTC3728LXC EXTVCC)
(TMDS 5V PWR)

30

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=5V

(COME FROM S5 TO S0 MOSFET)


5

=PP0V9_S0_MEM_TERM
PP1V05_S0

8 9 48

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=0.9V

=PP0V9_S0_MEM_REG

=PPVCORE_S0_CPU
PP0V9_S0

63 31

ONLY ON IN RUN

C
OF

81

108

DC-JACK INTERFACE
D

PPDCIN_G3H_R

87438-0543

6AMP-24V
PP18V5_DCIN_F

VOLTAGE=18.5V
MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.20 MM

ONEWIRE_PWR_EN_L

NC

=GND_DCIN_CHGND

66 65 46 45 5

SMC_BC_ACOK 5

ADAPTER_SENSE

5%
1/16W
MF-LF
402

Q8210
2N7002DW-X-F

OVP

SYS_ONEWIRE

100K

ONEWIRE_PWR_EN_L_DIV

G S

66 65 64

a
n
i

=PP3V42_G3H_ACIN

ONEWIRE_PWRCTL

Q8240
TP0610

ACIN DETECTION

5%
1/16W
MF-LF
402

R8206

S0T23-3

102K

SOT-363

1%
1/16W
MF-LF
2 402

R8208
102K

1%
1/16W
MF-LF
2 402

66 65 64

ONEWIRE_PULLUP
1

R8298

Q8220

2
PP3V42_ONEWIRE

2N7002DW-X-F

R8232
24.3K

TP0610

5%
1/16W
MF-LF

ONEWIRE_EN

ONEWIRE_PU_PROT

R8296

5%
1/16W
MF-LF
402

Q8299

2N7002

R8200

100K

SOT23-LF
2

C8203

0.001UF

5%
1/16W
MF-LF
2 402

20%
50V
2 CERM
402

C8230

10%
2 25V
X5R
402

R8207

1%
1/16W
MF-LF
2 402

R8231
100K

R8209
57.6K

1%
1/16W
MF-LF
2 402

Q8220

2N7002DW-X-F
SOT-363

ONEWIRE_PU_EN

SC70

LMC7211
SM-LF
1

SMC_BC_ACOK

V-

5%
1/16W
MF-LF
402

R8213
470K

5%
1/16W
MF-LF
2 402

S1

=PP18V5_G3H_INRUSH
64

VOLTAGE=18.5V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.20 MM

7
6
5

R8297
0

C8217

0.22UF
20%
25V

2 X5R

603

ACIN_ENABLE_L_DIV
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM

R8214

MC74VHC1G08

ONEWIRE_PU_ACOK

m
il

LM397

U8250

U8200

5%
1/16W
MF-LF
2 402

SOT23-5

1
ONEWIRE_ESD

V-

R8210

10.7K

SMC_PS_ON

1M

V+

U8290

ACIN_DIV

5%
1/16W
MF-LF
2 402

ONEWIRE_DCIN_DIV

CRITICAL

0
D

ONEWIRE_PULLUP

R8233
100K

1%
1/16W
MF-LF
2 402

0.1UF

2 402
ONEWIRE_OV

ONEWIRE_PU_EN_L

R8203
10K

S0T23-3

R8201
1K

1%
1/16W
MF-LF
2 402

Q8298

5%
1/16W
MF-LF
2 402

SOT-363

ONEWIRE_PULLUP

100K

46 45 39 5

V+

=PP3V42_G3H_ACIN 2

0.1UF

10%
2 25V
X5R
402

ACIN_1V20_REF

PP18V5_DCIN_ONEWIRE

2.0K
5%
1/16W
MF-LF
402

C8218

CRITICAL

D4
D3
D2
D1

GATE

ONEWIRE_PULLUP 1

R8299

S3
S2

y
r
SO-8

ONEWIRE_ALWAYSON

R8202

5%
2 1/16W
MF-LF
402

R8211

ONEWIRE_PWRCTL
100K

SI4405DY-E3

R8204

ONEWIRE_PWRCTL
3

SC-75

46 45 5

0.01uF

PP18V5_DCIN

C8202

10%
2 25V
X7R
402

RCLAMP0502B
6

D8200

VOLTAGE=18.5V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.20 MM

1206

Q8250

INRUSH LIMITER

F8200

M-RT-SM

CRITICAL

CRITICAL

ACIN_ENABLE_GATE

J8200

D
64

5%
1/8W
MF-LF
805

SOT-363

CRITICAL

=PPDCIN_G3H

47

BAS16TW-X-F

CRITICAL

R8205

D8201
518S0287

330K

5%
1/16W
MF-LF
2 402

ACIN_ENABLE_L

6
D
G

Q8210
2N7002DW-X-F

SOT-363
1

5%
1/16W
MF-LF
2 402

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

BOM OPTION

REF DES

COMMENTS:

376S0466

376S0410

Q8250

VISHAY SI4413ADY

TABLE_ALT_ITEM

BATTERY INTERFACE

e
r

L8209

0402
64

=PP3V42_G3H_LIDSWITCH

P
2

600-OHM-300MA

10

12

L8207

14

600-OHM-300MA

16

0402
1

PP3V42_G3H_LIDSWITCH_F
GND_SMC_LID_F

SMC_LID_F

L8208

0402

SMC_LID

20

J8250

SMBUS_BATT_SCL_F
SMBUS_BATT_SDA_F
SMC_BS_ALRT_L_F
5 BATT_POS
5 BATT_NEG

7
9

11

L8202

120-OHM-0.3A-EMI
0402-LF
1

13

17

C8211

0.001UF

19

10%
2 50V
CERM
402

65 6

=SMBUS_BATT_SCL

27

L8203

15

CRITICAL

600-OHM-300MA
46 45 40 5

18

C8205

0.001UF

10%
2 50V
CERM
402

C8209

0.001UF

10%
2 50V
CERM
402

C8215
47pF

5%
2 50V
CERM
402

C8206
47pF

5%
2 50V
CERM
402

120-OHM-0.3A-EMI
0402-LF
1

=SMBUS_BATT_SDA

27

L8204

120-OHM-0.3A-EMI
0402-LF

=GND_BATT_CHGND

SMC_BS_ALRT_L

DC-In & Battery Connectors

127216FA020

F-ST-SM1

A
1

C8220
0.01uF

10%
2 16V
CERM
402

L8201
1

0.01uF

=GND_BATT_CHGND

SYNC_DATE=07/13/2005

SM-LF

MLB TOP VIEW

C8221

10%
2 16V
CERM
402

SYNC_MASTER=POWER

FERR-50-OHM
2

PIN 1

NOTICE OF PROPRIETARY PROPERTY

BATT_POS_F
66

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

L8205

FERR-50-OHM

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

SM-LF

II NOT TO REPRODUCE OR COPY IT

6 65

LID HALL EFFECT SENSOR

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

82

108

PBUS SUPPLY / BATTERY CHARGER

CRITICAL
SI4405DY-E3
SO-8

=PP18V5_G3H_CHGR

CHGR_VDD

2
5

34.8K
1%
1/16W
MF-LF
402

5%
50V
CERM
402

C8340

0.1UF
2

10%
25V
X5R
402

R8342

R8306

66

VCOMP

CHGR_VADJ

9
2

CHGR_CSOP

21

CHGR_CSON

22

SOT-363

5%
1/16W
MF-LF
402

C8302

7
6

45 5

R8341

10K

10K

1%
1/16W
MF-LF
2 402

1%
1/16W
MF-LF
2 402

SMC_BATT_ISET1

1%
1/16W
MF-LF
2 402

R8363

CHGR_CHLIM
1

1%
1/16W
MF-LF
402

10%
25V
X5R
402
66

C8328
20%
4V
X5R
402

128S0093

128S0092

KEMET T520V336M016ATE0457650

376S0466

376S0410

Q8300,Q8320

VISHAY SI4413ADY
VISHAY SI4413ADY

R8364

28

CHGR_BOOT_RC

5%
1/16W
MF-LF
402

CHGR_VADJ

66

66

R8365

5%
1/16W
MF-LF
402
2

R8351

0.1UF

100K

100K

1%
1/16W
MF-LF
2 402

1%
1/16W
MF-LF
2 402

BAS16TW-X-F
SOT-363
6

m
il
5

LFPAK

NO STUFF

NO STUFF
1
C8316

C8317

0.001uF
10%
50V
CERM
402

1%
1/16W
MF-LF
402

4.53K

66 5

C8320

0.01uF

C8321

0.1UF

10%
16V
CERM
402

NO STUFF

C8322

0.01UF

10%
16V
X5R
402

R8330

470K

10%
16V
CERM
402

1%
1/16W
MF-LF
2 402

=PP3V42_G3H_ACIN

CRITICAL
2

R8324
100K
1%
1/16W
MF-LF
402

0.5%
1W
MF
0612

PPVBAT_G3H_CHGR_REG

CRITICAL

L8300
4.7UH

C8308
33UF

SM

PPVBAT_G3H_CHGR_OUT

C8309

20%
2 16V
ELEC
6.3X5.5SM1

POLY
CASED2E-SM

C8310
33UF

20%
16V
POLY
CASED2E-SM

Placement Note:
3

U8375
1

CRITICAL

2
1

C8318
0.22UF

S1

8 PPVBATT_G3H_PRE

C8324
10%
16V
CERM
402

10K

1%
1/16W
MF-LF
402

BATT_POS_F

D8201

PPVBATT_G3H_R

BAS16TW-X-F
SOT-363

Q8321

1%
1/16W
MF-LF
402

64

47

5%
1/8W
MF-LF
805

SI4405DY-E3
SO-8
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM

R8323

SOT-363

1%
1/16W
MF-LF
402

45 5 SMC_BATT_CHG_EN
46

Q8324

PBUS Supply/Battery Charger

2N7002DW-X-F
SOT-363

S
G

SYNC_MASTER=SMC
SMC_BATT_TRICKLE_EN_L

SYNC_DATE=08/19/2005

5 45 46

NOTICE OF PROPRIETARY PROPERTY

4
1

0.1UF
2

=PPVBATT_G3H

R8304

BYPASS_R_DRV

2N7002DW-X-F

C8323

45 46 48 61 62 66

65

4
1

20%
6.3V
X5R
402

35.7K

SOT-363

R8325

C8372
0.22UF

CRITICAL

BYPASS_R_GATE

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM

R8322
39.2K

0.01uF

45

GATE

D4
D3
D2
D1

S1

1%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

S3
S2

3
5
1

5%
1/16W
MF-LF
402

4.53K

GND

10%
6.3V
CERM
402

SMC_BATT_ISENSE

BATT_RC

6
2

R8371

CRITICAL

GATE

10%
10V
CERM
402

GND_SMC_AVSS

5%
3W
MF
2525

SO-8

D4
D3
D2
D1

1 BATT_ISENSE

27

SI4405DY-E3

SOT-363

SMC_BC_ACOK

C8375

OUT

R8320

Q8320

NO STUFF

SOT23-5

V+

1uF
2

S3
S2

PLACE RC CLOSE TO SMC

INA193
5

64 =PP3V3_S0_PBATTISENS

Place near R8308

VIN+ VIN-

10%
2 50V
CERM
603

Q8324
3

2N7002DW-X-F

5 66

0.0022uF

1/10W
MF-LF
603

R8331

BATT_FET_DRAIN

Q8322

64

CRITICAL
1

C8381

2N7002DW-X-F

SOT-363
2

64

=PPBUSA_G3H

2 CHGR_PHASE_RC

R8381

49.9
1%

Q8322

BAS16TW-X-F
5

=PPBUSB_G3H

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

100UF

20%

2 16V

CRITICAL

BATT_ENABLE_L
6

D8322
66

45 46 48 61 62 66

7AMP

330K

20%
6.3V
X5R
402

1206

BATT_FET_GATE

65 64

0.22UF

0.01

PPVBAT_G3H_CHGR_OUT
1

45

C8371

GND_SMC_AVSS

SM

SOT23-LF

65 46 45 5

R8370

F8300

CRITICAL

XW8300

2N7002

GND_CHGR_SGND

10%
25V
X5R
1206-1

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

Q8350

10UF

NC

C8307

SMC_DCIN_ISENSE

R8308

HAT2165H

0.1UF

R8350

10%
25V
X5R
1206-1

LFPAK

10%
25V
X5R
402

CHGR_VDD

10%
25V
X5R
1206-1

HAT2168H

C8303

Q8302

1%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
402

10UF

Q8301

2.2

CRITICAL

R8352

CRITICAL

C8306

CRITICAL

R8310

CHGR_LGATE

100K

D8322

DCSET

TABLE_ALT_ITEM

Q8321

24

10UF

e
r

NO STUFF
1

TABLE_ALT_ITEM

376S0410

DCPRN

12

2
5

NO STUFF

376S0466

CHGR_PHASE

PP18V5_S5_CHGR_SW_R

C8305

PLACE RC CLOSE TO SMC

DCIN_ISENSE

GND

10%
6.3V
CERM
402

CRITICAL

CRITICAL

1%
1/16W
MF-LF
402

10%
2 25V
X5R
402

COMMENTS:
TABLE_ALT_ITEM

C8308,C8310

R8302

TABLE_ALT_HEAD

REF DES

CHGR_UGATE

16

VREF

NO STUFF

BOM OPTION

15

LGATE
EN

100K

PHASE

CSON
CHLIM

U8370 OUT
INA193

V+

1uF

0.5%
1W
MF
0612
2
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

5%
1/16W
MF-LF
402

CHGR_CSIN

C8370

R8397
0.02

18

CHGR_SGATE

CHGR_BOOT

ALTERNATE FOR
PART NUMBER

20

14

ACSET

R8305

19

GND_CHGR_SGND

CHLIM circuit (R8362, R8363, C8328) subject to change


pending M1 resolution (100mV offset, radar 4221420)

PART NUMBER

18

CSIN

2.2uF

24.9K

0.1UF
2

C8341

1%
1/16W
MF-LF
402

SGATE
CSIP

VADJ
DCIN
ISL6255AHRZ
CELLS
QFN
BOOT
CSOP
UGATE

27

CHGR_DCIN

29

1%
1/16W
MF-LF
402

R8344
100K

100K

90.9K

1%
1/16W
MF-LF
2 402

R8343

R8309

R8362

270

CHGR_VREF

SOD-123

CHGR_BGATE

ACPRN

10%
25V
X5R
402

0.1UF

B0530WXF

25

23

C8304

D8300

17

CHGR_ACPRN

CHGR_ACSET

R8311

a
n
i
1

BGATE

U8300

0.0082uF
10%
25V
2 X7R
402

CHGR_VCOMP

CHGR_ACSET_RC

1%
1/16W
MF-LF
2 402

ACLIM
ICOMP CRITICAL

CHGR_ICOMP

5%
50V
CERM
402

2.2

93.1K

ICM

=PP3V3_S0_PDCISENS

SOT23-5

VDDP

C8326
120pF

D8322

BAS16TW-X-F

VDD

CHGR_ACLIM

NO STUFF

1%
1/16W
MF-LF
402

Placement Note:
PLACE NEAR R8397

CRITICAL
64 62

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM

10%
6.3V
CERM
402

VIN+ VIN-

1UF

PGND

0.022uF
10%
16V
CERM-X5R
402
1
2

CHGR_VCOMP_CC

150pF

C8301

C8325

100

NO STUFF

5%
1/16W
MF-LF
402

GND

1%
1/16W
MF-LF
2 402

R8367

11

88.7K

100K

R8301
R8340

CHGR_ICOMP_RC

R8303

1%
1/16W
MF-LF
2 402

C8312

4.7

13

R8300

10

NO STUFF
1

CHGR_VDDP

PPVDCIN_G3H_PRE

CHGR_ICM_R

5%
1/16W
MF-LF
402

10%
16V
X5R
402

10%
6.3V
CERM
402

IRLML5203-2.6A

1
2

0.033UF

1UF

SM

10%
50V
CERM
402
1

C8311

Q8340

0.0033uF

R8312

CHGR_VCOMP_RC

10%
6.3V
CERM
402

C8300

S1

CHGR_EN_L

C8313

CHGR_ICM

CLOSE TO PIN 26
1

1%
1/16W
MF-LF
402
2

1UF

CHGR_EN

3.32K

S3
S2

GATE

C8327

26

R8361

CHGR_DCPRN

1%
1/16W
MF-LF
402

CHGR_DCSET

R8360
4.99K
3

D4
D3
D2
D1

THRML_PAD

45

SMC_SYS_ISET

66

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

64

y
r

Q8300

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

20%
10V
CERM
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

83

108

=PP5V_S0_LCD

64

R9400
100K

FERR-120-OHM-1.5A
=PPBUS_S5_INV 1
2

Q9405

R9401

100K 2 INV_PWREN_L1

Q9406

LVDS_BKLTEN

y
r

0402-LF

L9400

120-OHM-0.3A-EMI

C9414

0.0022UF

PP5V_INV_F

VOLTAGE=5V
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM

0402-LF

10%
50V
CERM
402

L9401

120-OHM-0.3A-EMI

a
n
i

1
67 64

=PP3V3_S0_LCD

0402-LF

13

5%
2 50V
CERM
402

MC74VHC1G08

U9453

LVDS_BKLTCTL

SC70
4

BKLIGHT_CTL

INVERTER_BUF

C9459
0.1UF
10%
16V
X5R
402

C
INVERTER_UNBUF

R9428
0

Q9403

R9402

FDC638P

100K

R9423
10K
5%
1/16W
MF-LF
402

Q9404

IN

2
1

LCDVDD_PWREN_L_R

C9413
0.0033UF
1

R9414

1%
1/16W
MF-LF
2 402

e
r

5%
1/16W
MF-LF
2 402

13
13

67 64

=PP3V3_S0_LCD
NOSTUFF

NOSTUFF

R9415 R9416
10K

5%
1/16W
MF-LF
2 402

LVDS_CLKCTLA
LVDS_CLKCTLB

10K

5%
1/16W
MF-LF
2 402

LVDS_DDC_CLK
LVDS_DDC_DATA

5%
1/16W
MF-LF
2 402

13
13

13

LVDS_IBG

C9403
100PF

5%
2 50V
CERM
402

VOLTAGE=3.3V

0402-LF

INV_BKLIGHT_PWM_L

3
4

518S0334

C9400
100PF

5%
1 50V
CERM
402

THIS GND CONECTS TO CHASSIS GND

INVT_CHGND

LCD + CAMERA

CONNECTOR

C9409
0.001uF
1

CRITICAL

10%
50V
CERM
402

MIN_LINE_WIDTH=0.30 MM

J9401

S-050162B
F-RT-SM
25

=GND_CHASSIS_LVDS

23

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

PP3V3_S0_LCD_F

=PP3V3_S0_LCD

MIN_LINE_WIDTH=0.25 MM

3
4

(LVDS DDC POWER)


MIN_NECK_WIDTH=0.20 MM

0402-LF

L9408

INV_GND

PP3V3_LCDVDD_SW_F

13

IO

13

IO

13

IO

13

IO

13

IO

13

IO

13

IO

13

IO

CRITICAL

L9407

LVDS_A_DATA_N<0>
LVDS_A_DATA_P<0>
LVDS_A_DATA_N<1>
LVDS_A_DATA_P<1>
LVDS_A_DATA_N<2>
LVDS_A_DATA_P<2>
LVDS_A_CLK_N
LVDS_A_CLK_P

7
8
9
10
11
12
13
14
15

90-OHM
SM

LCD I/F

16

SYM_VER-1

IO

=USB2_CAMERA_P

IO

=USB2_CAMERA_N

USB2_CAMERA_CONN_P
USB2_CAMERA_CONN_N

17
18

CAMERA I/F

19
20

PP5V_S3_CAMERA_F

FERR-120-OHM-1.5A
2
=PP5V_S3_CAMERA 1

VOLTAGE=5V
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 MM

0402-LF

27

IO

27

IO

=SMBUS_ATS_SCL
=SMBUS_ATS_SDA

C9416

0.001uF
10%
50V
CERM
402

C9415
10%
50V
CERM
402

22

=GND_CHASSIS_LVDS

C9410

2 50V
CERM

0.001uF
2

21

24
67 6

R9413
1

100PF

67 6

L9405

64

C9402

5%
50V
2 CERM
402

120-OHM-0.3A-EMI

67 64

F-ST-SM
5

L9404

LVDS REFERENCE CURRENT,1.5K OHM PULL DOWN RESISTOR NEEDED

LVDS_VREFH
LVDS_VREFL

CRITICAL

J9400

FERR-120-OHM-1.5A

64 67

R9408 R9409
10K

10K

13

10UF

=PP3V3_S0_LCD

10%
50V
CERM
402

100K

13

C9412

20%
6.3V
2 X5R
603

10%
16V
2 X5R
402

C9411
0.1UF

SOT23-LF

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM

2N7002

LVDS_VDDEN

PP3V3_LCDVDD_SW

LCDVDD_PWREN_L

m
il

SM-LF

5%
1/16W
MF-LF
402
2

13

5%
1/16W
MF-LF
402

=PP3V3_S5_LCD

C9401
100PF

INVERTER_BUF

64

88611-04001

SOT23-LF

INVERTER CONNECTOR

2N7002

IN

PPBUS_ALL_INV_CONN

FERR-120-OHM-1.5A

S0T23-3

1%
1/16W
MF-LF
402

L9402

TP0610
G

VOLTAGE=12.6V
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM

0402-LF

INV_PWREN_F_L1

L9403

64

1%
1/16W
MF-LF
2 402

13

PP5V_INV
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=5V

26

Plexi: 516S0212
*Enclosure: 518S0364

0.001uF
10%
402

1.5K 2

INVERTER,LVDS,TMDS

1%
1/16W
MF-LF
402

SYNC_MASTER=GRAPHIC

C9408

0.001uF

SYNC_DATE=06/06/2005

NOTICE OF PROPRIETARY PROPERTY

10%
50V
2 CERM
402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

94

108

7
L9506

69 68 64

L9501

120-OHM-0.3A-EMI
2
=PP3V3_S0_TMDS 1

PP3V3_S0_ANALOG_TMDS_F

68 64

68

120-OHM-0.3A-EMI
1
2
=PP1V8_S0_TMDS

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

0402-LF

PP1V8_S0_TMDS_F

C9536
0.001UF

10%
2 50V
CERM
402

C9537
0.001UF
10%

50V
2 CERM

402

C9538

C9539

0.1UF
10%
2 16V
X5R
402

0.1UF

0402-LF

C9540

C9507

C9508

0.1UF

10UF

10%
2 16V
X5R
402

68

69 68

20%
2 6.3V
X5R
603

10%
2 50V
CERM
402

C9509

0.001UF

10%
2 16V
X5R
402

C9510

0.1UF

C9511

0.001UF

10%
2 16V
X5R
402

C9512

0.1UF

10%
2 50V
CERM
402

0.001UF
10%
2 50V
CERM
402

10%
2 16V
X5R
402

68 64

=PP1V8_S0_TMDS

C9530

C9531

0.001UF
10%

0.1UF

0.1UF

10%

10%

2 50V
CERM

2 16V
X5R

402

402

C9500

0.001UF

10%

2 16V
X5R

2 50V
CERM

0.001UF
10%

C9502

0.1UF

402

C9503
0.1UF

10%

10%

2 16V
X5R

2 50V
CERM

402

402

C9501

402

TMDS_TX_P<1>

PP3V3_S0_PVCC1_TMDS_F

68

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM

0402-LF
1

C9532

C9533

0.001UF
10%

2 50V
CERM

C9506

0.1UF

0.1UF

10%

10%

2 16V
X5R

2 16V
X5R

402

402

L9505

MCH SDVO CHANNEL R,G,B,CLK SIGNAL TO TMDS CHIP


68

PLACE THE CAP NEAR THE NB SIDE

20%
603

13

13

IN
IN
IN

PEG_R2D_C_P<2>
PEG_R2D_C_N<2>
PEG_R2D_C_P<3>

C9541
0.1UF
10%

2 16V
X5R

PLACE IT CLOSE TO CONNECTOR

=PP5V_S0_TMDS
2

C9519

0.1UF

10% 16V
X5R 402

BAV99DW-X-F
SOT-363

64

=PP2V5_S0_TMDS
13

R9501

TMDS_HTPLG 1 2.2K 2

3.3K

5%
1/16W
MF-LF
402
2

5%
1/16W
MF-LF
402 2

IO

R9500

IN

R9502

3.3K

IO

69

13

BAV99DW-X-F
SOT-363

PEG_D2R_P<1>
PEG_D2R_N<1>

C9520

0.1UF
10% 16V
X5R 402
1

0.1UF
10%

2 16V
X5R

C9543
0.1UF
10%

2 16V
X5R

402

402

C9544
0.1UF
10%

2 16V
X5R
402

C9545
0.1UF
10%

2 16V
X5R
402

C9546
0.1UF
10%

2 16V
X5R
402

C9547
0.1UF
10%

2 16V
X5R
402

PP3V3_S0_PVCC2_TMDS_F
PP3V3_S0_PVCC1_TMDS_F

C9548

TMDS_TX_P<2>

0.1UF
10%
402

TMDS_SDR_P
TMDS_SDR_N
TMDS_SDG_P
TMDS_SDG_N
TMDS_SDB_P
TMDS_SDB_N
TMDS_SDC_P
TMDS_SDC_N

TMDS_INT_P
TMDS_INT_N

49.9 2

R9539

TMDS_TX<2>

49.9 2
1%
1/16W
MF-LF
402

C9524

0.001UF
10%

2 50V
CERM

402

R9510

TMDS_TX_CLK_P
1

C9526

49.9 2

R9540

TMDS_TX_CLK

1%
1/16W
MF-LF
402

10pF

49.9 2 TMDS_TX_CLK_N
1%
1/16W
MF-LF
402

C9525

0.001UF

5%
2 50V
CERM
402

68 69

NOSTUFF

C9527
10pF

10%
2 50V
CERM
402

5%

2 50V
CERM

402

C9526,C9527 close to CHIP

26

TMDS_RST_L

ADDRESS=0X70 NC
IF HIGH, ADDRESS=0X72

R9503
1K

0.1UF

U9500

37 SDR_P
38 SDR_N

SIL1362ACLU
LQFP

40 SDG_P
41 SDG_N
43 SDB_P
44 SDB_N

SDVO RCVR
CORE

10%

2 16V
X5R

64 68 69

C9505
10UF
20%

2 6.3V
X5R

402

603

PP3V3_S0_ANALOG_TMDS_F

17

69 68

TX0_N
TX1_P

16

69 68

20
19

69 68

23

69 68

22
14

69 68

TX2_N
TXC_P
TXC_N

13

EXT_SWING

25

46 SDC_P
47 SDC_N

68

69 68

69 68
69 68

TMDS_TX_P<0> OUT
TMDS_TX_N<0> OUT
TMDS_TX_P<1> OUT
TMDS_TX_N<1> OUT
TMDS_TX_P<2> OUT
TMDS_TX_N<2> OUT
TMDS_TX_CLK_P OUT
TMDS_TX_CLK_N OUT

R9504
249

1%
1/16W
MF-LF
2 402

B
=PP3V3_S0_TMDS 64

68 69

32 SDI_P
33 SDI_N

5 SDSCL
4 SDSDA
6 A1

TX0_P

TX1_N
TX2_P

DIFF SIG
DATA

I2C MASTER
INTER SCLDDC

SDADDC

2 RESET*

SDVO_CTRLCLK
SDVO_CTRLDATA

C9521

CRITICAL

TMDS_EXT_RES 35 EXT_RES

14

14

1%
1/16W
MF-LF
402

=PP3V3_S0_TMDS
1

2 16V
X5R

TMDS CHIP SDVO INPUT INTERRUPT SIGNAL TO MCH

PP5V_S0_DVIPORT

NC

D9500

OUT

TMDS_HTPLG_R

5%
1/16W
MF-LF
402

OUT

C9542

e
r
402

D9500

68

68

PP3V3_S0_ANALOG_TMDS_F
PP1V8_S0_TMDS_F

68

68

PEG_R2D_C_N<3>

69 64

m
il

PEG_R2D_C_N<1>

OVCC 1

13

IN

PEG_R2D_C_P<1>

SPVCC 48

13

IN

69

1%
1/16W
MF-LF
402

C9523

CONFIG/
PRGRM

TEXT MODE

R9505 1R9506

TMDS_EXT_SWING

TMDS_I2C_SCL
TMDS_I2C_SDA

10K

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

TMDS_I2C_SCL AND TMDS_I2C_SDA DONT NEED TO CONNECT


TEST

30

29 HTPLG
3 SPGND

13

IN

TMDS_TX_N<2> 68

68

SVCC0 36
SVCC1 42

13

402

49.9 2

PP3V3_S0_ANALOG_SDVO_F
68 PP1V8_S0_ANALOG_SDVO_F

PEG_R2D_C_N<0>

10%

2 16V
X5R

402

IN

39 SGND0
45 SGND1

13

0.1UF

PVCC1 11
PVCC2 26

10%

2 50V
CERM

C9535

27 PGND2

0.001UF

PEG_R2D_C_P<0>

VCC2 34

C9534

IN

AVCC0 15
AVCC1 21

13

R9509

12 AGND0
18 AGND1
24 AGND2

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM

y
r

10UF

VCC0 10
VCC1 28

PP3V3_S0_PVCC2_TMDS_F

0402-LF

10%
50V
402

C9504

7 GND0
31 GND1

69 68

120-OHM-0.3A-EMI
1
2
64 =PP3V3_S0_TMDS

69

R9538
TMDS_TX<1>

0.001UF

NOSTUFF

49.9 2

2 CERM

69 68

402

1%
1/16W
MF-LF
402

68

a
n
i

L9504

TMDS_TX_N<1> 68

402

ONE 0.1UF AND 0.001UF FOR EACH PIN

120-OHM-0.3A-EMI
2
=PP3V3_S0_TMDS 1

C9522
10%

69 68

69 68 64

69

0.001UF

2 6.3V
X5R

2 16V
X5R

402

TMDS_TX_N<0> 68

2 50V
CERM

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

0402-LF

49.9 2
1%
1/16W
MF-LF
402

R9508

PP1V8_S0_ANALOG_SDVO_F

C9514

49.9 2 TMDS_TX<0>

20%
2 6.3V
X5R
603

69 68

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM

0402-LF

R9537

10UF

120-OHM-0.3A-EMI
68

R9507

C9513

L9500

PP3V3_S0_ANALOG_SDVO_F

1%
1/16W
MF-LF
402

ONE 0.1UF AND 0.001UF FOR EACH PIN

ONE 0.1UF AND 0.001UF FOR EACH PIN

L9503

120-OHM-0.3A-EMI
2
=PP3V3_S0_TMDS 1

TMDS_TX_P<0>

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

1
1

69 68 64

5%
1/16W
MF-LF
2 402

EXTERNAL TMDS

69

SYNC_MASTER=GRAPHIC

SYNC_DATE=06/06/2005

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


69

PP5V_S0_DVIPORT_D

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-7173

C
OF

95

108

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

BOM OPTION

155S0227

155S0164

REF DES

COMMENTS:
TABLE_ALT_ITEM

L9805,L9806,L9807

KEEP

MAG.LAYER IN BOM

Video Connectors
=PP3V3_S0_TMDS

EXTERNAL VIDEO (VGA) INTERFACE

64 68 69

Q9801
2N7002DW-X-F

R98211 R98221
2.2K

2N7002DW-X-F

3
D

SOT-363
6

PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR CONNECTOR

GPU_CRT_DDC_DATA

69

=PP5V_S0_TMDS

400-OHM-EMI

PP5V_S0_TMDS_FUSE

PP5V_S0_DVIPORT

VOLTAGE=5V
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

SM-LF

VOLTAGE=5V
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

=PP3V3_S0_TMDS

L9844

F9804
0.5AMP-13.2V
68 64

a
n
i
1

255

C9804
0.1UF

R9860

20%
10V
2 CERM
402

R9869
CRT_IREF

13

=GND_CHASSIS_TMDS_UPPER

1%
1/16W
MF-LF
402

PP5V_S0_DVIPORT_D

68 69

VOLTAGE=5V
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

SM-1

A 255 OHM 1% RESISTOR IS REQUIRED BETWEEN CRT_IREF


AND GROUND

13

y
r

TMDS(MINI DVI) INTERFACE

Q9801
G

IO

69

IO

13

CRT_DDC_CLK
CRT_DDC_DATA

5%
1/16W
MF-LF
402 2

13

2.2K

5%
1/16W
MF-LF
402 2

Isolation required for DVI power switch

GPU_CRT_DDC_CLK

SOT-363

68

CRT_HSYNC_R

39

C9860
0.1UF

20%
10V
2 CERM
402

8 SN74LVC2G125DCU

R9870

US

VCC

CRT_HSYNC_LS_R

5%
1/16W
MF-LF
402

6 69

U9804

64 68 69

125

CRT_HSYNC_LS

39

VGA_HSYNC

5%
1/16W
MF-LF
402

GND

69

NOSTUFF
1

C9842
33PF
5%
50V
402

2 CERM

PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR THE CONNECTOR

DVI power DIODE on page 95 (D9500)

TV REFERENCE CURRENT,USES AN EXTERNAL RESISTOR OF 5K OHM 1%


TO SET INTERNAL VOLTAGE LEVELS

R98621

R9863

13

4.99K2
1

TV_IREF

1%
1/16W
MF-LF
402

68

13 CRT_VSYNC_R

2.2K

5%
1/16W
MF-LF
402 2

R9868

R9861

2.2K

5%
1/16W
MF-LF
2 402

TMDS_HTPLG

C9808

m
il
0.001uF

10%
50V
2 CERM
402

GPU_CRT_DDC_CLK

C9809
100pF

5%
2 50V
CERM
402

69

GPU_CRT_DDC_DATA

PLACE THE RESISTOR CLOSE TO GMCH

13

R9850

R9851

75

75

1%
1/16W
MF-LF
2 402
13

13

FL9800

69 68 64

=PP3V3_S0_TMDS

1%
1/16W
MF-LF
2 402

0.1UF

R9852

R9853

75

75

1%
1/16W
MF-LF
2 402
13

13

1%
1/16W
MF-LF
2 402

TV_IRTNB

11 S1C
10 S2C

U9801

DB 7

R9856
150

P
EXT_Y_G

NOSTUFF

DC 9

R98641
150

DD 12

14 S1D
13 S2D

IN 1
EN_L 15
GND

CRT_GREEN_L

DA 4

SOP

TS3V330

13

5 S1B
6 S2B

TV_DACB_OUT
CRT_GREEN

1%
1/16W
MF-LF
402 2

16

VCC
2 S1A
3 S2A

3 4

NOSTUFF

10%
16V
2 X5R
402

CRT_BLUE_L

SM-220MHZ-LF

C9839

TV_IRTNA

PLACE THE RESISTOR CLOSE TO GMCH

LCFILTER

EXT_COMPVID_B

CRITICAL

13

e
r

TV_DACA_OUT
CRT_BLUE

1%
1/16W
MF-LF
402 2

EXT_C_R

FL9801

5%
50V
2 CERM
402

69 68

PP5V_S0_DVIPORT

NC
NC

69

C9824
3.3PF

0.25%
50V
2 CERM
402

69

SM-220MHZ-LF

VGA_B
VGA_HSYNC

VGA_G
VGA_VSYNC

VGA_R

A
13

13

R9854
75

13

13

VGA_VSYNC

C9843
402

CRITICAL

L9805

90-OHM-300mA
2012H
2

TMDS_TX_P<2>

68

TMDS_TX_N<2>

68

RT-TH

CRITICAL

25

17

26

TMDS_TX_CONN_P<2>

L9807

90-OHM-300mA
2012H

TMDS_TX_CONN_N<2>
2

18

10

27

19

11

28

20

12

29

TMDS_TX_CONN_P<1>
1

22

14

31

32

24

16

68

TMDS_TX_N<1>

68

4
SYM_VER-1

TMDS_TX_CONN_N<1>
TMDS_TX_CONN_P<0>

CRITICAL

TMDS_TX_CONN_N<0>

90-OHM-300mA
2012H

L9806

13
30

TMDS_TX_P<1>
3

TMDS_TX_P<0>

68

TMDS_TX_N<0>

68

TMDS_TX_CONN_CLK_P

15
1

TMDS_TX_CONN_CLK_N

4
SYM_VER-1

CRITICAL
370-OHM-280MA
SM1
1

C9834

3.3PF

69 6

0.25%
50V
2 CERM
402

FL9802

LCFILTER

=GND_CHASSIS_TMDS_UPPER

=GND_CHASSIS_TMDS_DOWN

TMDS_TX_CLK_P

68

TMDS_TX_CLK_N

68

3
SYM_VER-1

NOSTUFF

SM-220MHZ-LF

C9821
0.1UF

10%
16V
2 X5R
402

3 4
1

MINI-DVI CONNECTOR

C9820
3.3PF

SYNC_MASTER=EUGENE

0.25%
50V
2 CERM
402

SYNC_DATE=05/21/05

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

R9855

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

=SB_GPIO22

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

6
TABLE_5_HEAD

CRITICAL

BOM OPTION

514-0292

PART#

QTY

DESCRIPTION
CONN,32P MINI-DVI RCPT,RA,MG3,LF

REFERENCE DESIGNATOR(S)

J9801

CRITICAL

NORMAL

514-0319

CONN,32P MINI-DVI RCPT,RA,BLACK,LF

J9801

CRITICAL

FANCY

TV_IRTNC

SIZE
TABLE_5_ITEM

TABLE_5_ITEM

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

REV.

051-7173
SHT
NONE

5%

1%
1/16W
MF-LF
2 402

69

NOSTUFF
1

SYM_VER-1

CRT_RED_L

39

5%
1/16W
MF-LF
402

33PF

75

1%
1/16W
MF-LF
2 402

2 50V
CERM

CRT_RED
1

CRT_VSYNC_LS

L9804

1%
1/16W
MF-LF
402 2

TV_DACC_OUT

150

PLACE THE RESISTOR CLOSE TO GMCH

125

NOSTUFF

R98591

J9801

3 4

GND

MINI-DVI

100pF

R9871

US

OMIT
CRITICAL

C9812

LCFILTER

U9804

8 SN74LVC2G125DCU

VCC

CRT_VSYNC_LS_R

33
34
35
36

13

39

5%
1/16W
MF-LF
402

69

C
OF

98

108

8
Title:
Design:
Date:

Basenet Report
m42a
Aug 5 16:01:17 2006

=GND_CHASSIS_RJ45

Base nets and synonyms for m42a_lib.M42A(@m42a_lib.m42a(sch_1))


Base Signal
Synonyms
Location([Zone][dir])

1V2_FB
1V05S0_BG
1V05S0_BOOST
1V05S0_BOOST_RC
1V05S0_COMP
1V05S0_FSET
1V05S0_ITH
1V05S0_ITH_RC
1V05S0_RUNSS
1V05S0_SNS_N
1V05S0_SNS_P
1V05S0_SW
1V05S0_TG
1V05S0_VOSNS
1V5S0_BG
1V5S0_BOOST
1V5S0_BOOST_RC
1V5S0_ITH
1V5S0_ITH_RC
1V5S0_RUNSS
1V5S0_SNS_N
1V5S0_SNS_P
1V5S0_SW
1V5S0_TG
1V5S0_VOSNS
1V8S3_BOOT
1V8S3_BOOT_RC
1V8S3_COMP
1V8S3_COMP_R
1V8S3_FB
1V8S3_FCCM
1V8S3_FSET
1V8S3_ISEN
1V8S3_LG
1V8S3_PHASE
1V8S3_UG
1V8S3_VCC
1V51V05S0_FCB
1V51V05S0_FSEL
1V51V05S0_PGOOD
2V5S0_BP
2V5S3_BP
3V3S5_BG
3V3S5_BOOST
3V3S5_BOOST_RC
3V3S5_COMP
3V3S5_FSET
3V3S5_ITH
3V3S5_ITH_RC
3V3S5_RUNSS
3V3S5_SNS_N
3V3S5_SNS_P
3V3S5_SW
3V3S5_TG
3V3S5_VOSNS
5V3V3S5_FCB
5V3V3S5_FSEL
5VS5_BG
5VS5_BOOST
5VS5_BOOST_RC
5VS5_ITH
5VS5_ITH_RC
5VS5_RUNSS
5VS5_SNS_N
5VS5_SNS_P
5VS5_SW
5VS5_TG
5VS5_VOSNS
5V_REG_IN
=EXTBUSB_OC_L

1V2_FB - @m42a_lib.M42A
1V05S0_BG - @m42a_lib.M42A
1V05S0_BOOST - @m42a_lib.M42A
1V05S0_BOOST_RC - @m42a_lib.M42A
1V05S0_COMP - @m42a_lib.M42A
1V05S0_FSET - @m42a_lib.M42A
1V05S0_ITH - @m42a_lib.M42A
1V05S0_ITH_RC - @m42a_lib.M42A
1V05S0_RUNSS - @m42a_lib.M42A
1V05S0_SNS_N - @m42a_lib.M42A
1V05S0_SNS_P - @m42a_lib.M42A
1V05S0_SW - @m42a_lib.M42A
1V05S0_TG - @m42a_lib.M42A
1V05S0_VOSNS - @m42a_lib.M42A
1V5S0_BG - @m42a_lib.M42A
1V5S0_BOOST - @m42a_lib.M42A
1V5S0_BOOST_RC - @m42a_lib.M42A
1V5S0_ITH - @m42a_lib.M42A
1V5S0_ITH_RC - @m42a_lib.M42A
1V5S0_RUNSS - @m42a_lib.M42A
1V5S0_SNS_N - @m42a_lib.M42A
1V5S0_SNS_P - @m42a_lib.M42A
1V5S0_SW - @m42a_lib.M42A
1V5S0_TG - @m42a_lib.M42A
1V5S0_VOSNS - @m42a_lib.M42A
1V8S3_BOOT - @m42a_lib.M42A
1V8S3_BOOT_RC - @m42a_lib.M42A
1V8S3_COMP - @m42a_lib.M42A
1V8S3_COMP_R - @m42a_lib.M42A
1V8S3_FB - @m42a_lib.M42A
1V8S3_FCCM - @m42a_lib.M42A
1V8S3_FSET - @m42a_lib.M42A
1V8S3_ISEN - @m42a_lib.M42A
1V8S3_LG - @m42a_lib.M42A
1V8S3_PHASE - @m42a_lib.M42A
1V8S3_UG - @m42a_lib.M42A
1V8S3_VCC - @m42a_lib.M42A
1V51V05S0_FCB - @m42a_lib.M42A
1V51V05S0_FSEL - @m42a_lib.M42A
1V51V05S0_PGOOD - @m42a_lib.M42A
2V5S0_BP - @m42a_lib.M42A
2V5S3_BP - @m42a_lib.M42A
3V3S5_BG - @m42a_lib.M42A
3V3S5_BOOST - @m42a_lib.M42A
3V3S5_BOOST_RC - @m42a_lib.M42A
3V3S5_COMP - @m42a_lib.M42A
3V3S5_FSET - @m42a_lib.M42A
3V3S5_ITH - @m42a_lib.M42A
3V3S5_ITH_RC - @m42a_lib.M42A
3V3S5_RUNSS - @m42a_lib.M42A
3V3S5_SNS_N - @m42a_lib.M42A
3V3S5_SNS_P - @m42a_lib.M42A
3V3S5_SW - @m42a_lib.M42A
3V3S5_TG - @m42a_lib.M42A
3V3S5_VOSNS - @m42a_lib.M42A
5V3V3S5_FCB - @m42a_lib.M42A
5V3V3S5_FSEL - @m42a_lib.M42A
5VS5_BG - @m42a_lib.M42A
5VS5_BOOST - @m42a_lib.M42A
5VS5_BOOST_RC - @m42a_lib.M42A
5VS5_ITH - @m42a_lib.M42A
5VS5_ITH_RC - @m42a_lib.M42A
5VS5_RUNSS - @m42a_lib.M42A
5VS5_SNS_N - @m42a_lib.M42A
5VS5_SNS_P - @m42a_lib.M42A
5VS5_SW - @m42a_lib.M42A
5VS5_TG - @m42a_lib.M42A
5VS5_VOSNS - @m42a_lib.M42A
5V_REG_IN - @m42a_lib.M42A
=EXTBUSB_OC_L - @m42a_lib.M42A
USB_C_OC_L - @m42a_lib.M42A
EXTBUSB_OC_L - @m42a_lib.M42A
=FWPWR_PWRON
=FWPWR_PWRON - @m42a_lib.M42A
NC_FWPWR_PWRON - @m42a_lib.M42A
=GND_BATT_CHGND
=GND_BATT_CHGND - @m42a_lib.M42A
=GND_CHASSIS_AUDIO_JACK @m42a_lib.M42A
=GND_CHASSIS_AUDIO_MIC @m42a_lib.M42A
=GND_CHASSIS_DIPDIMM_LEFT @m42a_lib.M42A
GND_CHASSIS_IO - @m42a_lib.M42A
=GND_CHASSIS_USB - @m42a_lib.M42A
=GND_CHASSIS_FW_DOWN @m42a_lib.M42A
GND_CHASSIS_IO - @m42a_lib.M42A
=GND_CHASSIS_USB - @m42a_lib.M42A
=GND_CHASSIS_FW_DOWN @m42a_lib.M42A
=GND_CHASSIS_DIPDIMM_LEFT @m42a_lib.M42A
=GND_CHASSIS_AUDIO_SPKRCONN @m42a_lib.M42A
=GND_CHASSIS_AUDIO_SHIELD3 @m42a_lib.M42A
=GND_CHASSIS_AUDIO_SHIELD2 @m42a_lib.M42A
=GND_CHASSIS_AUDIO_SHIELD1 @m42a_lib.M42A
=GND_CHASSIS_AUDIO_MIC @m42a_lib.M42A
=GND_CHASSIS_AUDIO_JACK @m42a_lib.M42A
=GND_CHASSIS_DIPDIMM =GND_CHASSIS_DIPDIMM_CENTER _CENTER
@m42a_lib.M42A
GND_CHASSIS_CENTER - @m42a_lib.M42A
=GND_CHASSIS_DIPDIMM =GND_CHASSIS_DIPDIMM_RIGHT _RIGHT
@m42a_lib.M42A
GND_CHASSIS_RIGHT - @m42a_lib.M42A
=GND_CHASSIS_FW_UPPE =GND_CHASSIS_FW_UPPER R
@m42a_lib.M42A
=GND_CHASSIS_TMDS_DOWN @m42a_lib.M42A
GND_CHASSIS_IO1 - @m42a_lib.M42A
=GND_CHASSIS_TMDS_DOWN @m42a_lib.M42A
=GND_CHASSIS_LVDS
=GND_CHASSIS_LVDS - @m42a_lib.M42A

60A3
62B4
62B4
62C3
5D7
5D7
62B4
62B3
62B4 63B7
62C3
62C3
62B4
62C4
62B4
62B5
62B5
62C6
62B5
62B5
5D7 62B5 63B7
62C6
62C6
62B5
62C5
62B5
61B5
61C4
5D7 61B6
61B6
61B6
61B6
5D7 61C6
61B5
61B5
61B5
61C5
61C6
62A3 62B5
62A2 62B4
58C7 62A1 63C2
60C3
60C3
59B5
59B5
59C6
5D7
5D7
59B5
59B5
59B5 63C7
59C6
59C6
59B5
59C5
59B5
59A3 59B5
59A2 59B4
59B4
59B4
59C3
59B4
59B3
5D7 59B4 63C7
59C3
59C3
59B4
59C4
59B4
54A5
6C2 42C8
6C1 22C4 22D8
6C2
6D2 39C6
6D1
6D8 65A6 65A6
6D8 56B8

=P1V2S0_EN

=P1V8S0_EN_L
=P3V3S3_EN_L

=PP1V05_S0_FSB_NB

=PP1V05_S0_NB - @m42a_lib.M42A
=PP1V05_S0_CPU_NB - @m42a_lib.M42A
=PP1V05_S0_NB_VTT - @m42a_lib.M42A
=PP1V05_S0_CPU - @m42a_lib.M42A
=PPVCORE_S0_NB - @m42a_lib.M42A
PP1V05_S0_CPU_NB - @m42a_lib.M42A
=PPVCORE_S0_NB - @m42a_lib.M42A
=PP1V05_S0_NB_VTT - @m42a_lib.M42A
=PP1V05_S0_NB - @m42a_lib.M42A
=PP1V05_S0_CPU_NB - @m42a_lib.M42A
=PP1V05_S0_CPU - @m42a_lib.M42A
=PP1V05_S0_REG

=PP1V5_S0_NB

6D8 28A5

6C7 6D7
6C8 42A2 42A4 42C2 42C4
6C8 39A1
6D8 28A5
6D8
6D8
6D8
6D8

=PP1V8_S3_MEM_NB

6D8 57A6

=PP2V5_S0_NB_CRTDAC
6D8 56B8
6B8 28D5 29A5
6B7
6B8 29D4
6B7
6A6 39A1
6A6 69A3
6A5
6A6 69A3
6C8 67A2 67B2

=PP1V05_S0_REG - @m42a_lib.M42A
=PP1V05_S0_CPU_NB_SENSE @m42a_lib.M42A
=PP1V05_S0_SB_CPU_IO @m42a_lib.M42A
=PPVCORE_S0_SB - @m42a_lib.M42A
PP1V05_S0 - @m42a_lib.M42A
=PPVCORE_S0_SB - @m42a_lib.M42A
=PP1V05_S0_SB_CPU_IO @m42a_lib.M42A
=PP1V05_S0_CPU_NB_SENSE @m42a_lib.M42A
=PP1V5_S0_NB - @m42a_lib.M42A
=PP1V5_S0_NB_PCIE - @m42a_lib.M42A
=PP1V5_S0_AIRPORT - @m42a_lib.M42A
=PP1V5_S0_SB_VCCSATAPLL @m42a_lib.M42A
=PP1V5_S0_SB_VCC1_5_A_ATX @m42a_lib.M42A
=PP1V5_S0_SB_VCCUSBPLL @m42a_lib.M42A
=PP1V5_S0_SB_VCC1_5_A_USB_CORE @m42a_lib.M42A
=PP1V5_S0_SB_VCC1_5_A @m42a_lib.M42A
=PP1V5_S0_SB - @m42a_lib.M42A
=PP1V5_S0_NB_VCCAUX @m42a_lib.M42A
=PP1V5_S0_NB_VCCD_HMPLL @m42a_lib.M42A
=PP1V5_S0_NB_VCCD_LVDS @m42a_lib.M42A
=PP1V5_S0_NB_PLL - @m42a_lib.M42A
=PP1V5_S0_NB_TVDAC - @m42a_lib.M42A
=PP1V5_S0_NB_3G - @m42a_lib.M42A
=PP1V5_S0_NB_3GPLL - @m42a_lib.M42A
=PP1V5_S0_SB_VCC1_5_A_ARX @m42a_lib.M42A
=PP1V5_S0_CPU - @m42a_lib.M42A
=PP1V5_S0_REG - @m42a_lib.M42A
PP1V5_S0 - @m42a_lib.M42A
=PP1V5_S0_SB_VCCUSBPLL @m42a_lib.M42A
=PP1V5_S0_SB_VCCSATAPLL @m42a_lib.M42A
=PP1V5_S0_SB_VCC1_5_A_USB_CORE @m42a_lib.M42A
=PP1V5_S0_SB_VCC1_5_A_ATX @m42a_lib.M42A
=PP1V5_S0_SB_VCC1_5_A_ARX @m42a_lib.M42A
=PP1V5_S0_SB_VCC1_5_A @m42a_lib.M42A
=PP1V5_S0_SB - @m42a_lib.M42A
=PP1V5_S0_REG - @m42a_lib.M42A
=PP1V5_S0_NB_VCCD_LVDS @m42a_lib.M42A
=PP1V5_S0_NB_VCCD_HMPLL @m42a_lib.M42A
=PP1V5_S0_NB_VCCAUX @m42a_lib.M42A
=PP1V5_S0_NB_TVDAC - @m42a_lib.M42A
=PP1V5_S0_NB_PLL - @m42a_lib.M42A
=PP1V5_S0_NB_PCIE - @m42a_lib.M42A
=PP1V5_S0_NB_3GPLL - @m42a_lib.M42A
=PP1V5_S0_NB_3G - @m42a_lib.M42A
=PP1V5_S0_CPU - @m42a_lib.M42A
=PP1V5_S0_AIRPORT - @m42a_lib.M42A
=PP1V8_S3_MEM_NB - @m42a_lib.M42A

6C7 35C8
6C8 37A4
6C8 69A4 69C3
6C7
6C8 65C8
6C7
6C8 65C8
6C8 69A4 69C3
63B5
63B6
63B5
63C5
63B6
63A5
63A6
63C5
42B8 63D6
63D5
42B8 63D6
12A7 12B7 12C2 19D7
33C7 33C8 64D6
19D1 19D7 64C6
62A6 64D8
17D3 19B5 19D7 64C6
7B5 7B6 7D5 7D5 8C7
11B3 11C5 64D6
16C8 16D3 19C8 19D7
64D7
16C8 16D3 19C8 19D7
17D3 19B5 19D7 64C6
19D1 19D7 64C6
62A6 64D8
7B5 7B6 7D5 7D5 8C7
11B3 11C5 64D6
5B2 62B1 64D8
62A8 64D6

=PP3V3_S0_FAN_RT

33B8

9C8
64D6

9C8

21C1 21C1 24C3 25C4 64D6


24D3 25D3 64D6
5B2 64D7
24D3 25D3 64D6
21C1 21C1 24C3 25C4 64D6

=PP3V3_S0_SB_VCCLAN3_3 @m42a_lib.M42A
=PP3V3_S0_SB_3V3_1V5_VCCHDA @m42a_lib.M42A
=PPSPD_S0_MEM - @m42a_lib.M42A
=PP3V3_S0_CK410 - @m42a_lib.M42A
=PP3V3_S0_AIRPORT - @m42a_lib.M42A
=PP3V3_S0_TPM - @m42a_lib.M42A
=PP3V3_S0_AUDIO - @m42a_lib.M42A
=PP3V3_S0_TMDS - @m42a_lib.M42A

62A8 64D6
19C1
13D2
43D3
24B5

19D7 64C6
19D7 64C6
64C6
25D6 64C6

24A5 25C6 64C6


24A5 25B6 64C6

24A3 25C2 64C6

25A8 25C8 64C6


16D1 17B6 19B6 19D7 64C6
17C6 19D7 64C6

17C6 19B8 19D7 64C6


19D7 64C6
19D7 64C6
64C6
64C6
25D6 64C6

PP1V8_S3_MEM_NB - @m42a_lib.M42A
=PP2V5_S0_NB_CRTDAC @m42a_lib.M42A
=PP2V5_S0_NB_VCCA_3GBG @m42a_lib.M42A
=PP2V5_S0_NB_VCC_TXLVDS @m42a_lib.M42A
=PP2V5_S0_NB_DISP_PLL @m42a_lib.M42A
=PP2V5_S0_NB_VCCA_LVDS @m42a_lib.M42A
=PP2V5_S0_TMDS - @m42a_lib.M42A
=PP2V5_S0_NB_VCCSYNC @m42a_lib.M42A
=PP2V5_S0_REG - @m42a_lib.M42A
PP2V5_S0 - @m42a_lib.M42A
=PP2V5_S0_TMDS - @m42a_lib.M42A
=PP2V5_S0_REG - @m42a_lib.M42A

8B7 9D8 64C6


62B8 64C8
5B2 64C7
24A5 25B6 64C6
24B5 25D6 64C6
24A3 25B2 64C6
24A5 25C6 64C6
24B5 25D6 64C6
24A3 25C2 64C6

17D6 19B8 19D7 64B6

@m42a_lib.M42A
=PP3V42_G3H_PWRCTL - @m42a_lib.M42A
PP3V42_G3H - @m42a_lib.M42A
=PP3V42_G3H_SMC_CLK @m42a_lib.M42A
=PP3V42_G3H_SMCVREF @m42a_lib.M42A
=PP3V42_G3H_SMC - @m42a_lib.M42A

17D6 19B6 19D7 64B6


17C6 19C7 19D1 64B6
17D6 19B7 19D7 64B6
19D6 64B6
5D2 51C4 64A6
36C8 64A6
39C6 64A6
60C4 64A6
62B1 64A6
27B1 64A6
26B4 64A6
27D8 64A6
27D5 64A6
27C5 64A6
63B1 64A6
64A6 67B5 67B5 67B7 67C6
64A6 66B3
62A5
48C2
22B5
21C3
24B5

64A6
64A6
25D8
21D3
24B5

66C4

25A8 25C8 64C6


62B8 64C8
17C6 19B8 19D7 64C6
17C6 19D7 64C6

16D1 17B6 19B6 19D7 64C6


19A8 19D7 64C6
19C6 19D7 64C6
13D2 19D7 64C6
19A5 64C6
19B5 64C6
8B7 9D8 64C6
43D3 64C6
14C2 16B6 19D7 28D2 29D2
61C2 64C6
64C4
19D4 19D7 64B6
17D6 19B7 19D7 64B6
=PP3V42_G3H_LPCPLUS
17D6 19B8 19D7 64B6
19D6 64B6
17C6 19C7 19D1 64B6
64B6 68B7
17D6 19B6 19D7 64B6
60C2 63B3 64B8
5B2 64B7
64B6 68B7
60C2 63B3 64B8

34C8 64B6
23B2 23D5 64B6
25B8 25C6 64B6

24B3 25A4 64B6


24C3 25B4 64B6
26D1
26B6
34C2
46D3
14C7
20B4
24D3

64B6
26B8 64B6
64A6
64A6
14D6 19C7 20A4 20B4
64A6
25D3 64A6

24C3 25C4 64A6

28A7 29A3 29A7


32C7 32D3 32D8
43C3 64A6
53D4 64A6
54A6 54D7 56D8
64A6 68B1 68B2
68D8 68D8 69B7
=PP3V3_S0_THRM_SNR - @m42a_lib.M42A 10C4 49B3 49D3
=PP3V3_S0_IMVP6 - @m42a_lib.M42A
58D8 64A6
=PP3V3_S0_NB_VCC_HV 17C6 19B7 19C7
@m42a_lib.M42A
=PP3V3_S0_FET - @m42a_lib.M42A
63C3 64B8
PP3V3_S0 - @m42a_lib.M42A
5A2 64B7
=PPSPD_S0_MEM - @m42a_lib.M42A
28A7 29A3 29A7
=PP3V3_S0_TPM - @m42a_lib.M42A
53D4 64A6
=PP3V3_S0_TMDS - @m42a_lib.M42A
64A6 68B1 68B2
68D8 68D8 69B7
=PP3V3_S0_THRM_SNR - @m42a_lib.M42A 10C4 49B3 49D3
=PP3V3_S0_SMC_LS - @m42a_lib.M42A
46D3 64A6
=PP3V3_S0_SMBUS_SMC_MLB 27C5 64A6
@m42a_lib.M42A
=PP3V3_S0_SMBUS_SMC_BSB 27B1 64A6
@m42a_lib.M42A
=PP3V3_S0_SMBUS_SMC_0 27D5 64A6
@m42a_lib.M42A
=PP3V3_S0_SMBUS_SB - @m42a_lib.M42A 27D8 64A6
=PP3V3_S0_SB_VCCLAN3_3 24D3 25D3 64A6
@m42a_lib.M42A
=PP3V3_S0_SB_VCC3_3_PCI 24B3 25A4 64B6
@m42a_lib.M42A
=PP3V3_S0_SB_VCC3_3_IDE 24C3 25B4 64B6
@m42a_lib.M42A
=PP3V3_S0_SB_VCC3_3 24B5 24B5 25B8
@m42a_lib.M42A
=PP3V3_S0_SB_PM - @m42a_lib.M42A
26B6 26B8 64B6
=PP3V3_S0_SB_PCI - @m42a_lib.M42A
26D1 64B6
=PP3V3_S0_SB_GPIO - @m42a_lib.M42A 21C3 21D3 23B2
=PP3V3_S0_SB_3V3_1V5_VCCHDA 24C3 25C4 64A6
@m42a_lib.M42A
=PP3V3_S0_SB - @m42a_lib.M42A
22B5 25D8 34C8
=PP3V3_S0_RSTBUF - @m42a_lib.M42A
26B4 64A6
=PP3V3_S0_PDCISENS - @m42a_lib.M42A 62A5 64A6 66C4
=PP3V3_S0_PBATTISENS 64A6 66B3
@m42a_lib.M42A
=PP3V3_S0_PATA - @m42a_lib.M42A
34C2 64A6
=PP3V3_S0_NB_VCC_HV 17C6 19B7 19C7
@m42a_lib.M42A
=PP3V3_S0_NB - @m42a_lib.M42A
14C7 14D6 19C7
20B4 64A6
=PP3V3_S0_LCD - @m42a_lib.M42A
64A6 67B5 67B5
=PP3V3_S0_IMVP6 - @m42a_lib.M42A
58D8 64A6
=PP3V3_S0_FW - @m42a_lib.M42A
39C6 64A6
=PP3V3_S0_FET - @m42a_lib.M42A
63C3 64B8
=PP3V3_S0_ENET - @m42a_lib.M42A
36C8 64A6
=PP3V3_S0_CPUPOWER - @m42a_lib.M42A 48C2 64A6
=PP3V3_S0_CK410 - @m42a_lib.M42A
32C7 32D3 32D8
=PP3V3_S0_AUDIO - @m42a_lib.M42A
54A6 54D7 56D8
=PP3V3_S0_ALLSYSPG - @m42a_lib.M42A 63B1 64A6
=PP3V3_S0_AIRPORT - @m42a_lib.M42A 43C3 64A6
=PP3V3_S0_2V5S0 - @m42a_lib.M42A
60C4 64A6
=PP3V3_S0_1V51V05S0 62B1 64A6
@m42a_lib.M42A
=PP3V42_G3H_LPCPLUS 5D2 47C6 64D1
@m42a_lib.M42A
=PP3V42_G3H_SMCVREF 46C8 64D1
@m42a_lib.M42A
=PP3V42_G3H_SMC - @m42a_lib.M42A
45D2 45D3 45D3
46D8 48C8 64D1
=PP3V42_G3H_SB_RTC - @m42a_lib.M42A 26D6 64D1
=PP3V42_G3H_ACIN - @m42a_lib.M42A
64D1 65C4 65C8
=PP3V42_G3H_SMC_CLK 46A8 64D1
@m42a_lib.M42A
=PP3V42_G3H_LIDSWITCH 64D1 65A8
@m42a_lib.M42A
=PP3V42_G3H_REG - @m42a_lib.M42A
63D1 64D3
=PP3V42_G3H_SMBUS_SMC_BSA 27C3 64D1

m
il

24A3 25B2 64C6

19C6
19A8
19B5
19A5
24B5

=PP2V5_S0_NB_VCC_TXLVDS @m42a_lib.M42A
=PP2V5_S0_NB_VCCSYNC @m42a_lib.M42A
=PP2V5_S0_NB_VCCA_LVDS @m42a_lib.M42A
=PP2V5_S0_NB_VCCA_3GBG @m42a_lib.M42A
=PP2V5_S0_NB_DISP_PLL @m42a_lib.M42A
=PP3V3_S0_FAN_RT - @m42a_lib.M42A
=PP3V3_S0_ENET - @m42a_lib.M42A
=PP3V3_S0_FW - @m42a_lib.M42A
=PP3V3_S0_2V5S0 - @m42a_lib.M42A
=PP3V3_S0_1V51V05S0 @m42a_lib.M42A
=PP3V3_S0_SMBUS_SMC_BSB @m42a_lib.M42A
=PP3V3_S0_RSTBUF - @m42a_lib.M42A
=PP3V3_S0_SMBUS_SB - @m42a_lib.M42A
=PP3V3_S0_SMBUS_SMC_0 @m42a_lib.M42A
=PP3V3_S0_SMBUS_SMC_MLB @m42a_lib.M42A
=PP3V3_S0_ALLSYSPG - @m42a_lib.M42A
=PP3V3_S0_LCD - @m42a_lib.M42A
=PP3V3_S0_PBATTISENS @m42a_lib.M42A
=PP3V3_S0_PDCISENS - @m42a_lib.M42A
=PP3V3_S0_CPUPOWER - @m42a_lib.M42A
=PP3V3_S0_SB - @m42a_lib.M42A
=PP3V3_S0_SB_GPIO - @m42a_lib.M42A
=PP3V3_S0_SB_VCC3_3 @m42a_lib.M42A
=PP3V3_S0_SB_VCC3_3_PCI @m42a_lib.M42A
=PP3V3_S0_SB_VCC3_3_IDE @m42a_lib.M42A
=PP3V3_S0_SB_PCI - @m42a_lib.M42A
=PP3V3_S0_SB_PM - @m42a_lib.M42A
=PP3V3_S0_PATA - @m42a_lib.M42A
=PP3V3_S0_SMC_LS - @m42a_lib.M42A
=PP3V3_S0_NB - @m42a_lib.M42A

=PP3V42_G3H_SMBUS_SMC_BSA @m42a_lib.M42A
=PP3V42_G3H_SB_RTC - @m42a_lib.M42A
=PP3V42_G3H_REG - @m42a_lib.M42A
=PP3V42_G3H_PWRCTL - @m42a_lib.M42A
=PP3V42_G3H_LIDSWITCH @m42a_lib.M42A
=PP3V42_G3H_ACIN - @m42a_lib.M42A
=PP5V_S0_FAN_RT
=PP5V_S0_FAN_RT - @m42a_lib.M42A
=PP5V_S0_ISENSECAL - @m42a_lib.M42A
=PP5V_S0_LCD - @m42a_lib.M42A
=PP5V_S0_TMDS - @m42a_lib.M42A
=PP5V_S0_IMVP6 - @m42a_lib.M42A
=PP5V_1V51V05S0_VCC @m42a_lib.M42A
=PP5V_S0_NB_TVDAC - @m42a_lib.M42A
=PP5V_S0_LPCPLUS - @m42a_lib.M42A
=PP5V_S0_AUDIO_PWR - @m42a_lib.M42A
=PP5V_S0_AUDIO - @m42a_lib.M42A
=PP5V_S0_MEMVTT - @m42a_lib.M42A
=PP5V_S0_FET - @m42a_lib.M42A
=PP5V_S0_SATA - @m42a_lib.M42A
=PP5V_S0_SB - @m42a_lib.M42A
PP5V_S0 - @m42a_lib.M42A
=PP5V_S0_TMDS - @m42a_lib.M42A
=PP5V_S0_SB - @m42a_lib.M42A
=PP5V_S0_SATA - @m42a_lib.M42A
=PP5V_S0_NB_TVDAC - @m42a_lib.M42A
=PP5V_S0_MEMVTT - @m42a_lib.M42A
=PP5V_S0_LPCPLUS - @m42a_lib.M42A
=PP5V_S0_LCD - @m42a_lib.M42A
=PP5V_S0_ISENSECAL - @m42a_lib.M42A
=PP5V_S0_IMVP6 - @m42a_lib.M42A
=PP5V_S0_FET - @m42a_lib.M42A
=PP5V_S0_AUDIO_PWR - @m42a_lib.M42A
=PP5V_S0_AUDIO - @m42a_lib.M42A
=PP5V_1V51V05S0_VCC @m42a_lib.M42A
=PP5V_S0_IDE_PATA
=PP5V_S0_IDE_PATA - @m42a_lib.M42A
PP5V_S0_IDE_PATA - @m42a_lib.M42A
=PPDCIN_G3H
=PPDCIN_G3H - @m42a_lib.M42A
=PPVBATT_G3H - @m42a_lib.M42A
=PPVIN_G3H_P3V42G3H @m42a_lib.M42A
PPDCIN_G3H - @m42a_lib.M42A
=PPVIN_G3H_P3V42G3H @m42a_lib.M42A
=PPVBATT_G3H - @m42a_lib.M42A
=SMBUS_ATS_SCL
=SMBUS_ATS_SCL - @m42a_lib.M42A
SMBUS_SMC_RMT_SCL - @m42a_lib.M42A
SMB_RMT_CLK - @m42a_lib.M42A
SMBUS_SMC_RMT_SCL - @m42a_lib.M42A
=SMBUS_ATS_SDA
=SMBUS_ATS_SDA - @m42a_lib.M42A
SMBUS_SMC_RMT_SDA - @m42a_lib.M42A
SMB_RMT_DATA - @m42a_lib.M42A
SMBUS_SMC_RMT_SDA - @m42a_lib.M42A
=SMB_AIRPORT_CLK
=SMB_AIRPORT_CLK - @m42a_lib.M42A
=SMB_GEYSER_CLK - @m42a_lib.M42A
SMBUS_SB_SCL - @m42a_lib.M42A
=I2C_SODIMMB_SCL - @m42a_lib.M42A
SMB_CLK - @m42a_lib.M42A
=I2C_SODIMMA_SCL - @m42a_lib.M42A
SMB_CK410_CLK - @m42a_lib.M42A
SMB_CLK - @m42a_lib.M42A
SMB_CK410_CLK - @m42a_lib.M42A
SMBUS_SB_SCL - @m42a_lib.M42A
=SMB_GEYSER_CLK - @m42a_lib.M42A
=I2C_SODIMMB_SCL - @m42a_lib.M42A
=I2C_SODIMMA_SCL - @m42a_lib.M42A
=SMB_AIRPORT_DATA
=SMB_AIRPORT_DATA - @m42a_lib.M42A
=SMB_GEYSER_DATA - @m42a_lib.M42A
SMBUS_SB_SDA - @m42a_lib.M42A
=I2C_SODIMMB_SDA - @m42a_lib.M42A
SMB_DATA - @m42a_lib.M42A
=I2C_SODIMMA_SDA - @m42a_lib.M42A
SMB_CK410_DATA - @m42a_lib.M42A
SMB_DATA - @m42a_lib.M42A
SMB_CK410_DATA - @m42a_lib.M42A
SMBUS_SB_SDA - @m42a_lib.M42A
=SMB_GEYSER_DATA - @m42a_lib.M42A
=I2C_SODIMMB_SDA - @m42a_lib.M42A
=I2C_SODIMMA_SDA - @m42a_lib.M42A
=USB2_AIRPORT_N
=USB2_AIRPORT_N - @m42a_lib.M42A
USB_H_N - @m42a_lib.M42A
USB2_AIRPORT_N - @m42a_lib.M42A
=USB2_AIRPORT_P
=USB2_AIRPORT_P - @m42a_lib.M42A
USB_H_P - @m42a_lib.M42A
USB2_AIRPORT_P - @m42a_lib.M42A
=USB2_CAMERA_N
=USB2_CAMERA_N - @m42a_lib.M42A
USB_D_N - @m42a_lib.M42A
USB2_CAMERA_N - @m42a_lib.M42A
=USB2_CAMERA_P
=USB2_CAMERA_P - @m42a_lib.M42A
USB_D_P - @m42a_lib.M42A
USB2_CAMERA_P - @m42a_lib.M42A
ACIN_1V20_REF
ACIN_1V20_REF - @m42a_lib.M42A
ACIN_DIV
ACIN_DIV - @m42a_lib.M42A
ACIN_ENABLE_GATE
ACIN_ENABLE_GATE - @m42a_lib.M42A
ACIN_ENABLE_L
ACIN_ENABLE_L - @m42a_lib.M42A
ACIN_ENABLE_L_DIV
ACIN_ENABLE_L_DIV - @m42a_lib.M42A
ACZ_BITCLK
ACZ_BITCLK - @m42a_lib.M42A
ACZ_RST_L
ACZ_RST_L - @m42a_lib.M42A
ACZ_SDATAIN<0>
ACZ_SDATAIN<0> - @m42a_lib.M42A
ACZ_SDATAOUT
ACZ_SDATAOUT - @m42a_lib.M42A
ACZ_SYNC
ACZ_SYNC - @m42a_lib.M42A
ADAPTER_SENSE
ADAPTER_SENSE - @m42a_lib.M42A
AIRPORT_CLK100M_PCIE AIRPORT_CLK100M_PCIE_N _N
@m42a_lib.M42A
AIRPORT_CLK100M_PCIE AIRPORT_CLK100M_PCIE_P _P
@m42a_lib.M42A
AIRPORT_RST_L
AIRPORT_RST_L - @m42a_lib.M42A
ALL_SYS_PWRGD
ALL_SYS_PWRGD - @m42a_lib.M42A
ALS_GAIN
ALS_GAIN - @m42a_lib.M42A
ALS_LEFT
ALS_LEFT - @m42a_lib.M42A
ALS_RIGHT
ALS_RIGHT - @m42a_lib.M42A
AUDIO_SHIELD_PLANE
AUDIO_SHIELD_PLANE - @m42a_lib.M42A

64A6
64A6

57B5 64A6
68C8 68C8
69D1 69D5
64A6
64B6

64A6

68C8 68C8
69D1 69D5
64A6

25C6 64B6

23D5 64B6

64B6

64B6
20A4 20B4
67B7 67C6

64A6
57B5 64A6

46D1 46D5

66A5

63B8 63C8 64D1


5A2 64D1
46A8 64D1
46C8 64D1
45D2 45D3 45D3 46D1 46D5
46D8 48C8 64D1
27C3 64D1
26D6
63D1
63B8
64D1

64D1
64D3
63C8 64D1
65A8

64D1 65C4 65C8 66A5


5D2 51C4 64D3
48A8 64D3
64D3 67D7
64D3 68B7 69C6
58D8 64D3
62A8 64D3

y
r

a
n
i

64D6

e
r

6D8 57A6

6C7 6D7
6C8 42A2 42A4 42C2 42C4
6C8 39A1

GND_CHASSIS_SATA - @m42a_lib.M42A
=GND_CHASSIS_RJ45 - @m42a_lib.M42A
=GND_CHASSIS_TMDS_UPPER @m42a_lib.M42A
GND_CHASSIS_DCIN - @m42a_lib.M42A
=GND_DCIN_CHGND - @m42a_lib.M42A
GND_CHASSIS_DCIN - @m42a_lib.M42A
=GND_DCIN_CHGND - @m42a_lib.M42A
=GND_CHASSIS_TMDS_UPPER @m42a_lib.M42A
=P1V2S0_EN - @m42a_lib.M42A
PM_SLP_S3_LS12V6_L - @m42a_lib.M42A
=P3V3S0_EN - @m42a_lib.M42A
=P5VS0_EN - @m42a_lib.M42A
PM_SLP_S3_LS12V6_L - @m42a_lib.M42A
=P1V8S0_EN_L - @m42a_lib.M42A
PM_SLP_S3_LS5V - @m42a_lib.M42A
=P3V3S3_EN_L - @m42a_lib.M42A
PM_SLP_S4_LS5V - @m42a_lib.M42A
=P5VS3_EN_L - @m42a_lib.M42A
PM_SLP_S4_LS5V - @m42a_lib.M42A
=PP1V05_S0_FSB_NB - @m42a_lib.M42A

19C4 19C7 64D3


5D2 47C6 64D3
55B8 55B8 55D8 64D3
54A6 55C8 64D3
31C6 64D3
63C3 64D6
35C6 64D3
25D8 64D3
5A2 64D4
64D3 68B7 69C6
25D8 64D3
35C6 64D3
19C4 19C7 64D3
31C6 64D3
5D2 47C6 64D3
64D3 67D7
48A8 64D3
58D8 64D3
63C3 64D6
55B8 55B8 55D8 64D3
54A6 55C8 64D3
62A8 64D3

34C5
34D3
64B3 65D3
64B3 66B2
63D3 64B1
64B1
63D3 64B1

64B3 66B2
27D1 67A2
27D2
27D3 45B5
27D2
27C1 67A2
27D2
27D3 45B5
27D2
27C6 43B4
27B6 40C4
27D7
27C6 29A6
23D5 27D8
27D6 28A6
27D6 32B6
23D5 27D8
27D6 32B6
27D7
27B6 40C4
27C6 29A6
27D6 28A6
27C6 43B4
27B6 40C4
27D7
27C6 29A6
23D5 27D8
27C6 28A6
27D6 32B6
23D5 27D8
27D6 32B6
27D7
27B6 40C4
27C6 29A6
27C6 28A6
6B2 43B4
6B1 22C2
6B2
6B2 43B4
6B1 22C2
6B2
6C2 67A4
6C1 22C2
6C2
6C2 67B4
6C1 22C2
6C2
65C4
65C4
5C1 65C3
65C2
65C1
5C1 21C7 54D7
5C1 21C7 54C7 57C3
5D1 21C7 54D7
5D1 21C7 54D7
5C1 21C7 54D7
65C7
33B2 33C4 43C6

33B2 33D4 43C6


26B1 43C4
5B2 26A5 45D8 63B1
45B5 46C6
5A7 45A8 46C3
45A8 46C3
56C3
99

8
AUD_4V5_SHDN_L
AUD_ALC_COUT
AUD_ANALOG_FILT_1
AUD_ANALOG_FILT_2
AUD_BI_PORT_A_L
AUD_BI_PORT_A_R
AUD_BI_PORT_B_L

AUD_BI_PORT_C_L
AUD_BI_PORT_C_R
AUD_BI_PORT_D_L
AUD_BI_PORT_D_R
AUD_BI_PORT_E_L
AUD_BI_PORT_E_R
AUD_BI_PORT_F_L
AUD_BI_PORT_F_R
AUD_BYPASS
AUD_CONNJ1_RING
AUD_CONNJ1_RING_F
AUD_CONNJ1_SLEEVE
AUD_CONNJ1_SLEEVEDET
AUD_CONNJ1_SLEEVEDET
_F
AUD_CONNJ1_SLEEVE_F
AUD_CONNJ1_TIP
AUD_CONNJ1_TIPDET
AUD_CONNJ1_TIPDET_F
AUD_CONNJ1_TIP_F
AUD_CONNJ2_RING
AUD_CONNJ2_RING_F
AUD_CONNJ2_SLEEVE
AUD_CONNJ2_SLEEVEDET
AUD_CONNJ2_SLEEVEDET
_F
AUD_CONNJ2_SLEEVE_F
AUD_CONNJ2_TIP
AUD_CONNJ2_TIPDET
AUD_CONNJ2_TIPDET_F

AUD_CONNJ2_TIP_F
AUD_GPIO_0
AUD_GPIO_0_R
AUD_GPIO_1
AUD_GPIO_1_R
AUD_GPIO_2
AUD_INJACK_INSERT_L
AUD_J1_COM
AUD_J1_DET_RC
AUD_J1_SLEEVEDET_INV
AUD_J1_SLEEVEDET_R
AUD_J1_TIPDET_R
AUD_J2_COM
AUD_J2_DET_RC
AUD_J2_OPT_OUT
AUD_J2_SLEEVEDET_R
AUD_J2_TIPDET_R
AUD_JDREF
AUD_OUTJACK_INSERT_L

AUD_PORTA_DET_L
AUD_PORTA_L
AUD_PORTA_L_R
AUD_PORTA_R
AUD_PORTA_R_R
AUD_PORTE_DET_L
AUD_PORTF_L
AUD_PORTF_L_R
AUD_PORTF_R
AUD_PORTF_R_R
AUD_PORTG_DET_L
AUD_SENSE_A
AUD_SENSE_B
AUD_SPDIF_IN
AUD_SPDIF_OUT
AUD_SPDIF_OUT_R
AUD_SPKRAMP_INL
AUD_SPKRAMP_INL_L
AUD_SPKRAMP_INR
AUD_SPKRAMP_INR_L
AUD_SPKRAMP_INSUB
AUD_SPKRAMP_INSUB_L
AUD_SPKRAMP_SHUTDOWN
_L
AUD_VREF_FILT
AUD_VREF_PORT_B
BAL_IN_COM
BAL_IN_L
BAL_IN_R
BATT_ENABLE_L
BATT_FET_DRAIN
BATT_FET_GATE
BATT_IN
BATT_ISENSE
BATT_NEG
BATT_POS
BATT_POS_F
BATT_RC
BEEP
BIOS_REC
BKLIGHT_CTL
BOOT_LPC_SPI_L
BYPASS_R_DRV
BYPASS_R_GATE
CHASSIS_AUDIO_JACK_I
SOL
CHGR_ACLIM
CHGR_ACPRN
CHGR_ACSET
CHGR_ACSET_RC
CHGR_BGATE
CHGR_BOOT
CHGR_BOOT_RC
CHGR_CHLIM
CHGR_CSIN
CHGR_CSON
CHGR_CSOP

7
AUD_4V5_SHDN_L - @m42a_lib.M42A
AUD_ALC_COUT - @m42a_lib.M42A
AUD_ANALOG_FILT_1 - @m42a_lib.M42A
AUD_ANALOG_FILT_2 - @m42a_lib.M42A
AUD_BI_PORT_A_L - @m42a_lib.M42A
AUD_BI_PORT_A_R - @m42a_lib.M42A
AUD_BI_PORT_B_L - @m42a_lib.M42A
AUD_BI_PORT_B_R - @m42a_lib.M42A
AUD_BI_PORT_C_L - @m42a_lib.M42A
AUD_BI_PORT_C_R - @m42a_lib.M42A
AUD_BI_PORT_D_L - @m42a_lib.M42A
AUD_BI_PORT_D_R - @m42a_lib.M42A
AUD_BI_PORT_E_L - @m42a_lib.M42A
AUD_BI_PORT_E_R - @m42a_lib.M42A
AUD_BI_PORT_F_L - @m42a_lib.M42A
AUD_BI_PORT_F_R - @m42a_lib.M42A
AUD_BYPASS - @m42a_lib.M42A
AUD_CONNJ1_RING - @m42a_lib.M42A
AUD_CONNJ1_RING_F - @m42a_lib.M42A
AUD_CONNJ1_SLEEVE - @m42a_lib.M42A
AUD_CONNJ1_SLEEVEDET @m42a_lib.M42A
AUD_CONNJ1_SLEEVEDET_F @m42a_lib.M42A
AUD_CONNJ1_SLEEVE_F @m42a_lib.M42A
AUD_CONNJ1_TIP - @m42a_lib.M42A
AUD_CONNJ1_TIPDET - @m42a_lib.M42A
AUD_CONNJ1_TIPDET_F @m42a_lib.M42A
AUD_CONNJ1_TIP_F - @m42a_lib.M42A
AUD_CONNJ2_RING - @m42a_lib.M42A
AUD_CONNJ2_RING_F - @m42a_lib.M42A
AUD_CONNJ2_SLEEVE - @m42a_lib.M42A
AUD_CONNJ2_SLEEVEDET @m42a_lib.M42A
AUD_CONNJ2_SLEEVEDET_F @m42a_lib.M42A
AUD_CONNJ2_SLEEVE_F @m42a_lib.M42A
AUD_CONNJ2_TIP - @m42a_lib.M42A
AUD_CONNJ2_TIPDET - @m42a_lib.M42A
AUD_CONNJ2_TIPDET_F @m42a_lib.M42A
AUD_CONNJ2_TIP_F - @m42a_lib.M42A
AUD_GPIO_0 - @m42a_lib.M42A
AUD_GPIO_0_R - @m42a_lib.M42A
AUD_GPIO_1 - @m42a_lib.M42A
AUD_GPIO_1_R - @m42a_lib.M42A
AUD_GPIO_2 - @m42a_lib.M42A
AUD_INJACK_INSERT_L @m42a_lib.M42A
AUD_J1_COM - @m42a_lib.M42A
AUD_J1_DET_RC - @m42a_lib.M42A
AUD_J1_SLEEVEDET_INV @m42a_lib.M42A
AUD_J1_SLEEVEDET_R - @m42a_lib.M42A
AUD_J1_TIPDET_R - @m42a_lib.M42A
AUD_J2_COM - @m42a_lib.M42A
AUD_J2_DET_RC - @m42a_lib.M42A
AUD_J2_OPT_OUT - @m42a_lib.M42A
AUD_J2_SLEEVEDET_R - @m42a_lib.M42A
AUD_J2_TIPDET_R - @m42a_lib.M42A
AUD_JDREF - @m42a_lib.M42A
AUD_OUTJACK_INSERT_L @m42a_lib.M42A
AUD_PORTA_DET_L - @m42a_lib.M42A
AUD_PORTA_L - @m42a_lib.M42A
AUD_PORTA_L_R - @m42a_lib.M42A
AUD_PORTA_R - @m42a_lib.M42A
AUD_PORTA_R_R - @m42a_lib.M42A
AUD_PORTE_DET_L - @m42a_lib.M42A
AUD_PORTF_L - @m42a_lib.M42A
AUD_PORTF_L_R - @m42a_lib.M42A
AUD_PORTF_R - @m42a_lib.M42A
AUD_PORTF_R_R - @m42a_lib.M42A
AUD_PORTG_DET_L - @m42a_lib.M42A
AUD_SENSE_A - @m42a_lib.M42A
AUD_SENSE_B - @m42a_lib.M42A
AUD_SPDIF_IN - @m42a_lib.M42A
AUD_SPDIF_OUT - @m42a_lib.M42A
AUD_SPDIF_OUT_R - @m42a_lib.M42A
AUD_SPKRAMP_INL - @m42a_lib.M42A
AUD_SPKRAMP_INL_L - @m42a_lib.M42A
AUD_SPKRAMP_INR - @m42a_lib.M42A
AUD_SPKRAMP_INR_L - @m42a_lib.M42A
AUD_SPKRAMP_INSUB - @m42a_lib.M42A
AUD_SPKRAMP_INSUB_L @m42a_lib.M42A
AUD_SPKRAMP_SHUTDOWN_L @m42a_lib.M42A
AUD_VREF_FILT - @m42a_lib.M42A
AUD_VREF_PORT_B - @m42a_lib.M42A
BAL_IN_COM - @m42a_lib.M42A
BAL_IN_L - @m42a_lib.M42A
BAL_IN_R - @m42a_lib.M42A
BATT_ENABLE_L - @m42a_lib.M42A
BATT_FET_DRAIN - @m42a_lib.M42A
BATT_FET_GATE - @m42a_lib.M42A
BATT_IN - @m42a_lib.M42A
BATT_ISENSE - @m42a_lib.M42A
BATT_NEG - @m42a_lib.M42A
BATT_POS - @m42a_lib.M42A
BATT_POS_F - @m42a_lib.M42A
BATT_RC - @m42a_lib.M42A
BEEP - @m42a_lib.M42A
BIOS_REC - @m42a_lib.M42A
BKLIGHT_CTL - @m42a_lib.M42A
BOOT_LPC_SPI_L - @m42a_lib.M42A
BYPASS_R_DRV - @m42a_lib.M42A
BYPASS_R_GATE - @m42a_lib.M42A
CHASSIS_AUDIO_JACK_ISOL @m42a_lib.M42A
CHGR_ACLIM - @m42a_lib.M42A
CHGR_ACPRN - @m42a_lib.M42A
CHGR_ACSET - @m42a_lib.M42A
CHGR_ACSET_RC - @m42a_lib.M42A
CHGR_BGATE - @m42a_lib.M42A
CHGR_BOOT - @m42a_lib.M42A
CHGR_BOOT_RC - @m42a_lib.M42A
CHGR_CHLIM - @m42a_lib.M42A
CHGR_CSIN - @m42a_lib.M42A
CHGR_CSON - @m42a_lib.M42A
CHGR_CSOP - @m42a_lib.M42A

54A5
54B5
54C4
54C4
54C1
54C1
54C1
54C1
54C7
54C7
54C7
54C7
54C1
54C1
54C1
54C1
54C4
56C7
56C6
56D7
56C7

CHGR_DCIN
CHGR_DCPRN
CHGR_DCSET
CHGR_EN
CHGR_EN_L
CHGR_ICM
CHGR_ICM_R
CHGR_ICOMP
CHGR_ICOMP_RC
CHGR_LGATE
CHGR_PHASE
CHGR_PHASE_RC
CHGR_SGATE
CHGR_UGATE
CHGR_VADJ
CHGR_VCOMP
CHGR_VCOMP_CC
CHGR_VCOMP_RC
CHGR_VDD
CHGR_VDDP
CHGR_VREF
CK410_CLK14P3M_TIMER

57C3
57B3
57A6
57A6
55B8
55C8
57A5
55A8
57A5
57A5
57B3
57A3

56C6
CK410_CPU0_N
CK410_CPU0_P
CK410_CPU1_N
CK410_CPU1_P
CK410_CPU2_ITP_SRC10
_N
CK410_CPU2_ITP_SRC10
_P
CK410_DOT96_27M_N
CK410_DOT96_27M_P
CK410_FSB_TEST_MODE

56D5
56C7
56D7
56D6
56C6
56B7
56B6
56B7
56A7

CK410_IREF
CK410_LVDS_N
CK410_LVDS_P
CK410_PCI1_CLK
CK410_PCI2_CLK
CK410_PCI3_CLK
CK410_PCI4_CLK
CK410_PCI4_CLK_SPN
CK410_PCI5_FCTSEL1
CK410_PCIF0_CLK
CK410_PCIF1_CLK
CK410_PD_VTT_PWRGD_L

56A6
56B6
56B7
56B7
56B6
56B6
54B8
54B7
54B8
54A7
54C7
57C7

55A8
54C7
57C3
54C7

CK410_REF1_FCTSEL0
CK410_SRC1_N

56C4
57D7
57C7
56C3
56C3
56B4
57B7
56B7
56A4
56A4
54C4
57D7
57D5
56C3
57B1
56C3
57B1
57D5
56B4
57B2
56B4
57A2
57C5
54C1
54C1
54C1
54D1
54D4
55B6
55B7
55C6
55C7
55A6
55A7

CK410_SRC1_P

57C6 57C8
57D8

CK410_SRC2_N
CK410_SRC2_P
CK410_SRC3_N
CK410_SRC3_P
CK410_SRC4_N
CK410_SRC4_P
CK410_SRC5_N
CK410_SRC5_P
CK410_SRC6_N
CK410_SRC6_P
CK410_SRC7_N

57B8
57B8

57D1
57D3
57C1
57C3

CK410_SRC7_P
CK410_SRC8_N
CK410_SRC8_P
CK410_SRC_CLKREQ1_L

57B1
57A1

CK410_SRC_CLKREQ3_L
57C5 57D8
57C4 57C8 57D8
56B3
56D3

CK410_SRC_CLKREQ6_L
CK410_SRC_CLKREQ8_L

55A6 55B8 55C8


54C4
54C1 57A6
54C7 57A3
54C7 57A3
54C7 57A3
66A4
66A5
66A4
5D1
66B2
5D1 65A6
5D1 65A6
65A2 66B2
66A5
54C6
23A6 23C5
67C4
5C2 22B3 45C8 47C6
66A3
66A3
56A3 56A8 56B1 56B6 56B6
56C1 56C1 56C8
66C6
66B6
66C6
66C8
66C5
66C5
66C4
66B6
66C5
66C6
66C6

CK410_USB48_FSA
CK410_XTAL_IN
CK410_XTAL_OUT
CLK_NB_OE_L
CONN_GEYSER_ONOFF_FL
TR_L
CONN_GEYSER_USB_N
CONN_GEYSER_USB_P
CPUVCORE_ISENSE_CAL

CHGR_DCIN - @m42a_lib.M42A
CHGR_DCPRN - @m42a_lib.M42A
CHGR_DCSET - @m42a_lib.M42A
CHGR_EN - @m42a_lib.M42A
CHGR_EN_L - @m42a_lib.M42A
CHGR_ICM - @m42a_lib.M42A
CHGR_ICM_R - @m42a_lib.M42A
CHGR_ICOMP - @m42a_lib.M42A
CHGR_ICOMP_RC - @m42a_lib.M42A
CHGR_LGATE - @m42a_lib.M42A
CHGR_PHASE - @m42a_lib.M42A
CHGR_PHASE_RC - @m42a_lib.M42A
CHGR_SGATE - @m42a_lib.M42A
CHGR_UGATE - @m42a_lib.M42A
CHGR_VADJ - @m42a_lib.M42A
CHGR_VCOMP - @m42a_lib.M42A
CHGR_VCOMP_CC - @m42a_lib.M42A
CHGR_VCOMP_RC - @m42a_lib.M42A
CHGR_VDD - @m42a_lib.M42A
CHGR_VDDP - @m42a_lib.M42A
CHGR_VREF - @m42a_lib.M42A
CK410_CLK14P3M_TIMER @m42a_lib.M42A
CK410_CPU0_N - @m42a_lib.M42A
CK410_CPU0_P - @m42a_lib.M42A
CK410_CPU1_N - @m42a_lib.M42A
CK410_CPU1_P - @m42a_lib.M42A
CK410_CPU2_ITP_SRC10_N @m42a_lib.M42A
CK410_CPU2_ITP_SRC10_P @m42a_lib.M42A
CK410_DOT96_27M_N - @m42a_lib.M42A
CK410_DOT96_27M_P - @m42a_lib.M42A
CK410_FSB_TEST_MODE @m42a_lib.M42A
CK410_IREF - @m42a_lib.M42A
CK410_LVDS_N - @m42a_lib.M42A
CK410_LVDS_P - @m42a_lib.M42A
CK410_PCI1_CLK - @m42a_lib.M42A
CK410_PCI2_CLK - @m42a_lib.M42A
CK410_PCI3_CLK - @m42a_lib.M42A
CK410_PCI4_CLK - @m42a_lib.M42A
CK410_PCI4_CLK_SPN - @m42a_lib.M42A
CK410_PCI5_FCTSEL1 - @m42a_lib.M42A
CK410_PCIF0_CLK - @m42a_lib.M42A
CK410_PCIF1_CLK - @m42a_lib.M42A
CK410_PD_VTT_PWRGD_L @m42a_lib.M42A
VR_PWRGD_CK410_L - @m42a_lib.M42A
CK410_REF1_FCTSEL0 - @m42a_lib.M42A
CK410_SRC1_N - @m42a_lib.M42A
CK410_SRC1_N_SPN - @m42a_lib.M42A
CK410_SRC1_P - @m42a_lib.M42A
CK410_SRC1_P_SPN - @m42a_lib.M42A
CK410_SRC2_N - @m42a_lib.M42A
CK410_SRC2_P - @m42a_lib.M42A
CK410_SRC3_N - @m42a_lib.M42A
CK410_SRC3_N_SPN - @m42a_lib.M42A
CK410_SRC3_P - @m42a_lib.M42A
CK410_SRC3_P_SPN - @m42a_lib.M42A
CK410_SRC4_N - @m42a_lib.M42A
CK410_SRC4_P - @m42a_lib.M42A
CK410_SRC5_N - @m42a_lib.M42A
CK410_SRC5_P - @m42a_lib.M42A
CK410_SRC6_N - @m42a_lib.M42A
CK410_SRC6_P - @m42a_lib.M42A
CK410_SRC7_N - @m42a_lib.M42A
CK410_SRC7_N_SPN - @m42a_lib.M42A
CK410_SRC7_P - @m42a_lib.M42A
CK410_SRC7_P_SPN - @m42a_lib.M42A
CK410_SRC8_N - @m42a_lib.M42A
CK410_SRC8_P - @m42a_lib.M42A
CK410_SRC_CLKREQ1_L @m42a_lib.M42A
CK410_SRC_CLKREQ1_L_SPN @m42a_lib.M42A
CK410_SRC_CLKREQ3_L @m42a_lib.M42A
CK410_SRC_CLKREQ3_L_SPN @m42a_lib.M42A
CK410_SRC_CLKREQ6_L @m42a_lib.M42A
CK410_SRC_CLKREQ8_L @m42a_lib.M42A
CK410_USB48_FSA - @m42a_lib.M42A
CK410_XTAL_IN - @m42a_lib.M42A
CK410_XTAL_OUT - @m42a_lib.M42A
CLK_NB_OE_L - @m42a_lib.M42A
CONN_GEYSER_ONOFF_FLTR_L @m42a_lib.M42A
CONN_GEYSER_USB_N - @m42a_lib.M42A
CONN_GEYSER_USB_P - @m42a_lib.M42A
CPUVCORE_ISENSE_CAL @m42a_lib.M42A
CPU_A20M_L - @m42a_lib.M42A
CPU_BSEL<0> - @m42a_lib.M42A
CPU_BSEL<1> - @m42a_lib.M42A
CPU_BSEL<2> - @m42a_lib.M42A
CPU_BSEL_R<0> - @m42a_lib.M42A
CPU_BSEL_R<1> - @m42a_lib.M42A
CPU_BSEL_R<2> - @m42a_lib.M42A
CPU_COMP<0> - @m42a_lib.M42A
CPU_COMP<1> - @m42a_lib.M42A
CPU_COMP<2> - @m42a_lib.M42A
CPU_COMP<3> - @m42a_lib.M42A
CPU_DPRSTP_L - @m42a_lib.M42A
CPU_DPSLP_L - @m42a_lib.M42A
CPU_FERR_L - @m42a_lib.M42A
CPU_GTLREF - @m42a_lib.M42A
CPU_IGNNE_L - @m42a_lib.M42A
CPU_INIT_L - @m42a_lib.M42A
CPU_INTR - @m42a_lib.M42A
CPU_ISENSE_OUT_R - @m42a_lib.M42A
CPU_ISENSE_R_N - @m42a_lib.M42A
CPU_ISENSE_R_P - @m42a_lib.M42A
CPU_NMI - @m42a_lib.M42A
CPU_PROCHOT_L - @m42a_lib.M42A
CPU_PSI_L - @m42a_lib.M42A
CPU_PWRGD - @m42a_lib.M42A
CPU_RCIN_L - @m42a_lib.M42A
CPU_SMI_L - @m42a_lib.M42A
CPU_STPCLK_L - @m42a_lib.M42A
CPU_TEST1 - @m42a_lib.M42A
CPU_TEST2 - @m42a_lib.M42A

5C7
5C7
5C7
5C7
5C7

32C4
32C4
32C4
32C4
32C4

CPU_THERMAL_SCREW_DO
WN
CPU_THERMAL_SCREW_RI
GHT
CPU_THERMAL_SCREW_UP
CPU_THERMD_N
CPU_THERMD_P
CPU_THERMTRIP_R
CPU_VCCSENSE_N
CPU_VCCSENSE_P
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
CPU_VID_R<0>
CPU_VID_R<0..6>
CPU_VID_R<1>
CPU_VID_R<2>
CPU_VID_R<3>
CPU_VID_R<4>
CPU_VID_R<5>
CPU_VID_R<6>
CPU_XDP_CLK_N
CPU_XDP_CLK_P
CRB_SV_DET
CRT_BLUE
CRT_DDC_CLK
CRT_DDC_DATA
CRT_GREEN
CRT_HSYNC_LS
CRT_HSYNC_LS_R
CRT_HSYNC_R
CRT_IREF
CRT_RED
CRT_VSYNC_LS
CRT_VSYNC_LS_R
CRT_VSYNC_R
DCIN_ISENSE
DEBUG_RST_L
DMI_IRCOMP_R
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
ENETPWR_EN
ENET_BOB_SMITH_CAP
ENET_CENTER_TAP<0>
ENET_CENTER_TAP<1>
ENET_CENTER_TAP<2>
ENET_CENTER_TAP<3>
ENET_CLK100M_PCIE_N

33D5
33D5
33D5
33D5
33D5

5C7 32C4 33D5


5C7 32A4 33B5
5C7 32A4 33B5
32C6 33B8
32B6
5C7 32B4 33A5
5C7 32B4 33A5
32B6 33D8
32B6 33D8
32B6 33D8
32B6
5C7
32B6 33A8
32B7 33D8
5C7 32B6 33D8
26A8 32A4
26A7 58C7
32A4 33A8
6B4 32B4
5C7 6B3
6B4 32B4
5C7 6B3
5C7 32B4 33C5
5C7 32B4 33C5
6B4 32B4
5C7 6B3
6B4 32B4
5C7 6B3
5C7 32B4 33B5
5C7 32B4 33B5
5C7 32B4 33C5
5C7 32B4 33C5
5C7 32B4 33C5
5C7 32B4 33D5
6B4 32B4
5C7 6B3
6B4 32B4
5C7 6B3
5B7 32A4 33C5
5B7 32A4 33C5
6B4 32B4
5B7 6B3

6B4 32B4
5B7 6B3

32B4 43C6

5B7 32A4 33A5


32A4 33C8
32C6
32C6
14B6 32B4
40C6

CPU_THERMAL_SCREW_DOWN @m42a_lib.M42A
CPU_THERMAL_SCREW_RIGHT @m42a_lib.M42A
CPU_THERMAL_SCREW_UP @m42a_lib.M42A
CPU_THERMD_N - @m42a_lib.M42A
CPU_THERMD_P - @m42a_lib.M42A
CPU_THERMTRIP_R - @m42a_lib.M42A
CPU_VCCSENSE_N - @m42a_lib.M42A
CPU_VCCSENSE_P - @m42a_lib.M42A
CPU_VID<0> - @m42a_lib.M42A
CPU_VID<1> - @m42a_lib.M42A
CPU_VID<2> - @m42a_lib.M42A
CPU_VID<3> - @m42a_lib.M42A
CPU_VID<4> - @m42a_lib.M42A
CPU_VID<5> - @m42a_lib.M42A
CPU_VID<6> - @m42a_lib.M42A
CPU_VID_R<0> - @m42a_lib.M42A
CPU_VID_R<0..6> - @m42a_lib.M42A
CPU_VID_R<1> - @m42a_lib.M42A
CPU_VID_R<2> - @m42a_lib.M42A
CPU_VID_R<3> - @m42a_lib.M42A
CPU_VID_R<4> - @m42a_lib.M42A
CPU_VID_R<5> - @m42a_lib.M42A
CPU_VID_R<6> - @m42a_lib.M42A
CPU_XDP_CLK_N - @m42a_lib.M42A
CPU_XDP_CLK_P - @m42a_lib.M42A
CRB_SV_DET - @m42a_lib.M42A
CRT_BLUE - @m42a_lib.M42A
CRT_DDC_CLK - @m42a_lib.M42A
CRT_DDC_DATA - @m42a_lib.M42A
CRT_GREEN - @m42a_lib.M42A
CRT_HSYNC_LS - @m42a_lib.M42A
CRT_HSYNC_LS_R - @m42a_lib.M42A
CRT_HSYNC_R - @m42a_lib.M42A
CRT_IREF - @m42a_lib.M42A
CRT_RED - @m42a_lib.M42A
CRT_VSYNC_LS - @m42a_lib.M42A
CRT_VSYNC_LS_R - @m42a_lib.M42A
CRT_VSYNC_R - @m42a_lib.M42A
DCIN_ISENSE - @m42a_lib.M42A
DEBUG_RST_L - @m42a_lib.M42A
DMI_IRCOMP_R - @m42a_lib.M42A
DMI_N2S_N<0> - @m42a_lib.M42A
DMI_N2S_N<1> - @m42a_lib.M42A
DMI_N2S_N<2> - @m42a_lib.M42A
DMI_N2S_N<3> - @m42a_lib.M42A
DMI_N2S_P<0> - @m42a_lib.M42A
DMI_N2S_P<1> - @m42a_lib.M42A
DMI_N2S_P<2> - @m42a_lib.M42A
DMI_N2S_P<3> - @m42a_lib.M42A
DMI_S2N_N<0> - @m42a_lib.M42A
DMI_S2N_N<1> - @m42a_lib.M42A
DMI_S2N_N<2> - @m42a_lib.M42A
DMI_S2N_N<3> - @m42a_lib.M42A
DMI_S2N_P<0> - @m42a_lib.M42A
DMI_S2N_P<1> - @m42a_lib.M42A
DMI_S2N_P<2> - @m42a_lib.M42A
DMI_S2N_P<3> - @m42a_lib.M42A
ENETPWR_EN - @m42a_lib.M42A
ENET_BOB_SMITH_CAP - @m42a_lib.M42A
ENET_CENTER_TAP<0> - @m42a_lib.M42A
ENET_CENTER_TAP<1> - @m42a_lib.M42A
ENET_CENTER_TAP<2> - @m42a_lib.M42A
ENET_CENTER_TAP<3> - @m42a_lib.M42A
ENET_CLK100M_PCIE_N @m42a_lib.M42A
ENET_CLK100M_PCIE_P @m42a_lib.M42A
ENET_CTRL12 - @m42a_lib.M42A
ENET_CTRL12_SPN - @m42a_lib.M42A
ENET_CTRL25 - @m42a_lib.M42A
ENET_CTRL25_SPN - @m42a_lib.M42A
ENET_LOM_DIS_L - @m42a_lib.M42A
ENET_MDI0 - @m42a_lib.M42A
ENET_MDI1 - @m42a_lib.M42A
ENET_MDI2 - @m42a_lib.M42A
ENET_MDI3 - @m42a_lib.M42A
ENET_MDI_N<0> - @m42a_lib.M42A
ENET_MDI_N<1> - @m42a_lib.M42A
ENET_MDI_N<2> - @m42a_lib.M42A
ENET_MDI_N<3> - @m42a_lib.M42A
ENET_MDI_P<0> - @m42a_lib.M42A
ENET_MDI_P<1> - @m42a_lib.M42A
ENET_MDI_P<2> - @m42a_lib.M42A
ENET_MDI_P<3> - @m42a_lib.M42A
ENET_MDI_TRAN_N<0> - @m42a_lib.M42A
ENET_MDI_TRAN_N<1> - @m42a_lib.M42A
ENET_MDI_TRAN_N<2> - @m42a_lib.M42A
ENET_MDI_TRAN_N<3> - @m42a_lib.M42A
ENET_MDI_TRAN_P<0> - @m42a_lib.M42A
ENET_MDI_TRAN_P<1> - @m42a_lib.M42A
ENET_MDI_TRAN_P<2> - @m42a_lib.M42A
ENET_MDI_TRAN_P<3> - @m42a_lib.M42A
ENET_PU_VDD_TTL0 - @m42a_lib.M42A
ENET_PU_VDD_TTL1 - @m42a_lib.M42A
ENET_RSET - @m42a_lib.M42A
ENET_RST_L - @m42a_lib.M42A
ENET_VPD_CLK - @m42a_lib.M42A
ENET_VPD_DATA - @m42a_lib.M42A
ENET_XTALI - @m42a_lib.M42A
ENET_XTALO - @m42a_lib.M42A
EXTAUSB_OC_F_L - @m42a_lib.M42A
EXTBUSB_OC_F_L - @m42a_lib.M42A
EXT_COMPVID_B - @m42a_lib.M42A
EXT_C_R - @m42a_lib.M42A
EXT_Y_G - @m42a_lib.M42A
FAN_RT_PWM - @m42a_lib.M42A
FAN_RT_TACH - @m42a_lib.M42A
FSB_ADSTB_L<0> - @m42a_lib.M42A
FSB_ADSTB_L<1> - @m42a_lib.M42A
FSB_ADS_L - @m42a_lib.M42A
FSB_A_L<3> - @m42a_lib.M42A
FSB_A_L<4> - @m42a_lib.M42A
FSB_A_L<5> - @m42a_lib.M42A
FSB_A_L<6> - @m42a_lib.M42A
FSB_A_L<7> - @m42a_lib.M42A
FSB_A_L<8> - @m42a_lib.M42A
FSB_A_L<9> - @m42a_lib.M42A
FSB_A_L<10> - @m42a_lib.M42A
FSB_A_L<11> - @m42a_lib.M42A
FSB_A_L<12> - @m42a_lib.M42A
FSB_A_L<13> - @m42a_lib.M42A

ENET_CTRL12
ENET_CTRL25

ENET_LOM_DIS_L
ENET_MDI0
ENET_MDI1
ENET_MDI2
ENET_MDI3
ENET_MDI_N<0>
ENET_MDI_N<1>
ENET_MDI_N<2>
ENET_MDI_N<3>
ENET_MDI_P<0>
ENET_MDI_P<1>
ENET_MDI_P<2>
ENET_MDI_P<3>
ENET_MDI_TRAN_N<0>
ENET_MDI_TRAN_N<1>
ENET_MDI_TRAN_N<2>
ENET_MDI_TRAN_N<3>
ENET_MDI_TRAN_P<0>
ENET_MDI_TRAN_P<1>
ENET_MDI_TRAN_P<2>
ENET_MDI_TRAN_P<3>
ENET_PU_VDD_TTL0
ENET_PU_VDD_TTL1
ENET_RSET
ENET_RST_L
ENET_VPD_CLK
ENET_VPD_DATA
ENET_XTALI
ENET_XTALO
EXTAUSB_OC_F_L
EXTBUSB_OC_F_L
EXT_COMPVID_B
EXT_C_R
EXT_Y_G
FAN_RT_PWM
FAN_RT_TACH
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
FSB_ADS_L
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>

40C6
40C6
48A5

7C8 21C4
7B4 33C6
7B4 33B6
7B4 33B6
33C7
33B7
33B7
7B3
7B3
7B3
7B3
7B3 21C4 58C7
7B3 21C4
7C8 21C2
7B4
7C8 21C4
7D6 21C4
7C8 21C4
48C3
48C3
48C3
7C8 21C4
7C6 46B5 46C2 58C8
7A3 58C7
7B3 21C4
21C4
7C8 21C4
7C8 21C4
7B4
7B4

6A8
6A7
6A7
7C6 10B6
7C6 10B6
21C2
8B6 58A4 58A5
8B6 58A4 58A5
8B7 9C3
8B7 9C3
8B7 9C3
8B7 9C3
8B7 9C3
8B7 9D3
8B7 9D3
9C2 58C7
58A4
9C2 58C7
9C2 58C7
9C2 58C7
9C2 58C7
9D2 58C7
9D2 58C7
11B3 33D2 33D3
11B3 33D2 33D3
23B6 23C3
13B5 69B8
13B5 69D7
13B5 69D7
13B5 69A8
69C2
69C3
13B5 69C3
13B5 69C8
13B5 69A8
69C2
69C3
13B5 69C3
66C3
5C2 26B1 47C6
22C2
14B4 22D2
14B4 22D2
14B4 22D2
14B4 22D2
14B4 22D2
14B4 22D2
14B4 22D2
14B4 22D2
14B4 22D2
14B4 22D2
14B4 22D2
14B4 22D2
14B4 22D2
14B4 22D2
14B4 22D2
14B4 22D2
60B5 60C5 60D4
37A5
37C6
37B6
37B6
37B6
33C3 33D2 36C6

FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_BNR_L
FSB_BPRI_L
FSB_BREQ0_L
FSB_CLK_CPU_N
FSB_CLK_CPU_P
FSB_CLK_NB_N
FSB_CLK_NB_P
FSB_CPURST_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DINV_L<0>
FSB_DINV_L<1>
FSB_DINV_L<2>
FSB_DINV_L<3>
FSB_DPWR_L
FSB_DRDY_L
FSB_DSTBN_L<0>
FSB_DSTBN_L<1>
FSB_DSTBN_L<2>
FSB_DSTBN_L<3>
FSB_DSTBP_L<0>
FSB_DSTBP_L<1>
FSB_DSTBP_L<2>
FSB_DSTBP_L<3>
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_HITM_L
FSB_HIT_L
FSB_IERR_L
FSB_LOCK_L
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_SLPCPU_L
FSB_TRDY_L
FWH_INIT_L

FSB_A_L<14> - @m42a_lib.M42A
FSB_A_L<15> - @m42a_lib.M42A
FSB_A_L<16> - @m42a_lib.M42A
FSB_A_L<17> - @m42a_lib.M42A
FSB_A_L<18> - @m42a_lib.M42A
FSB_A_L<19> - @m42a_lib.M42A
FSB_A_L<20> - @m42a_lib.M42A
FSB_A_L<21> - @m42a_lib.M42A
FSB_A_L<22> - @m42a_lib.M42A
FSB_A_L<23> - @m42a_lib.M42A
FSB_A_L<24> - @m42a_lib.M42A
FSB_A_L<25> - @m42a_lib.M42A
FSB_A_L<26> - @m42a_lib.M42A
FSB_A_L<27> - @m42a_lib.M42A
FSB_A_L<28> - @m42a_lib.M42A
FSB_A_L<29> - @m42a_lib.M42A
FSB_A_L<30> - @m42a_lib.M42A
FSB_A_L<31> - @m42a_lib.M42A
FSB_BNR_L - @m42a_lib.M42A
FSB_BPRI_L - @m42a_lib.M42A
FSB_BREQ0_L - @m42a_lib.M42A
FSB_CLK_CPU_N - @m42a_lib.M42A
FSB_CLK_CPU_P - @m42a_lib.M42A
FSB_CLK_NB_N - @m42a_lib.M42A
FSB_CLK_NB_P - @m42a_lib.M42A
FSB_CPURST_L - @m42a_lib.M42A
FSB_DBSY_L - @m42a_lib.M42A
FSB_DEFER_L - @m42a_lib.M42A
FSB_DINV_L<0> - @m42a_lib.M42A
FSB_DINV_L<1> - @m42a_lib.M42A
FSB_DINV_L<2> - @m42a_lib.M42A
FSB_DINV_L<3> - @m42a_lib.M42A
FSB_DPWR_L - @m42a_lib.M42A
FSB_DRDY_L - @m42a_lib.M42A
FSB_DSTBN_L<0> - @m42a_lib.M42A
FSB_DSTBN_L<1> - @m42a_lib.M42A
FSB_DSTBN_L<2> - @m42a_lib.M42A
FSB_DSTBN_L<3> - @m42a_lib.M42A
FSB_DSTBP_L<0> - @m42a_lib.M42A
FSB_DSTBP_L<1> - @m42a_lib.M42A
FSB_DSTBP_L<2> - @m42a_lib.M42A
FSB_DSTBP_L<3> - @m42a_lib.M42A
FSB_D_L<0> - @m42a_lib.M42A
FSB_D_L<1> - @m42a_lib.M42A
FSB_D_L<2> - @m42a_lib.M42A
FSB_D_L<3> - @m42a_lib.M42A
FSB_D_L<4> - @m42a_lib.M42A
FSB_D_L<5> - @m42a_lib.M42A
FSB_D_L<6> - @m42a_lib.M42A
FSB_D_L<7> - @m42a_lib.M42A
FSB_D_L<8> - @m42a_lib.M42A
FSB_D_L<9> - @m42a_lib.M42A
FSB_D_L<10> - @m42a_lib.M42A
FSB_D_L<11> - @m42a_lib.M42A
FSB_D_L<12> - @m42a_lib.M42A
FSB_D_L<13> - @m42a_lib.M42A
FSB_D_L<14> - @m42a_lib.M42A
FSB_D_L<15> - @m42a_lib.M42A
FSB_D_L<16> - @m42a_lib.M42A
FSB_D_L<17> - @m42a_lib.M42A
FSB_D_L<18> - @m42a_lib.M42A
FSB_D_L<19> - @m42a_lib.M42A
FSB_D_L<20> - @m42a_lib.M42A
FSB_D_L<21> - @m42a_lib.M42A
FSB_D_L<22> - @m42a_lib.M42A
FSB_D_L<23> - @m42a_lib.M42A
FSB_D_L<24> - @m42a_lib.M42A
FSB_D_L<25> - @m42a_lib.M42A
FSB_D_L<26> - @m42a_lib.M42A
FSB_D_L<27> - @m42a_lib.M42A
FSB_D_L<28> - @m42a_lib.M42A
FSB_D_L<29> - @m42a_lib.M42A
FSB_D_L<30> - @m42a_lib.M42A
FSB_D_L<31> - @m42a_lib.M42A
FSB_D_L<32> - @m42a_lib.M42A
FSB_D_L<33> - @m42a_lib.M42A
FSB_D_L<34> - @m42a_lib.M42A
FSB_D_L<35> - @m42a_lib.M42A
FSB_D_L<36> - @m42a_lib.M42A
FSB_D_L<37> - @m42a_lib.M42A
FSB_D_L<38> - @m42a_lib.M42A
FSB_D_L<39> - @m42a_lib.M42A
FSB_D_L<40> - @m42a_lib.M42A
FSB_D_L<41> - @m42a_lib.M42A
FSB_D_L<42> - @m42a_lib.M42A
FSB_D_L<43> - @m42a_lib.M42A
FSB_D_L<44> - @m42a_lib.M42A
FSB_D_L<45> - @m42a_lib.M42A
FSB_D_L<46> - @m42a_lib.M42A
FSB_D_L<47> - @m42a_lib.M42A
FSB_D_L<48> - @m42a_lib.M42A
FSB_D_L<49> - @m42a_lib.M42A
FSB_D_L<50> - @m42a_lib.M42A
FSB_D_L<51> - @m42a_lib.M42A
FSB_D_L<52> - @m42a_lib.M42A
FSB_D_L<53> - @m42a_lib.M42A
FSB_D_L<54> - @m42a_lib.M42A
FSB_D_L<55> - @m42a_lib.M42A
FSB_D_L<56> - @m42a_lib.M42A
FSB_D_L<57> - @m42a_lib.M42A
FSB_D_L<58> - @m42a_lib.M42A
FSB_D_L<59> - @m42a_lib.M42A
FSB_D_L<60> - @m42a_lib.M42A
FSB_D_L<61> - @m42a_lib.M42A
FSB_D_L<62> - @m42a_lib.M42A
FSB_D_L<63> - @m42a_lib.M42A
FSB_HITM_L - @m42a_lib.M42A
FSB_HIT_L - @m42a_lib.M42A
FSB_IERR_L - @m42a_lib.M42A
FSB_LOCK_L - @m42a_lib.M42A
FSB_REQ_L<0> - @m42a_lib.M42A
FSB_REQ_L<1> - @m42a_lib.M42A
FSB_REQ_L<2> - @m42a_lib.M42A
FSB_REQ_L<3> - @m42a_lib.M42A
FSB_REQ_L<4> - @m42a_lib.M42A
FSB_RS_L<0> - @m42a_lib.M42A
FSB_RS_L<1> - @m42a_lib.M42A
FSB_RS_L<2> - @m42a_lib.M42A
FSB_SLPCPU_L - @m42a_lib.M42A
FSB_TRDY_L - @m42a_lib.M42A
FWH_INIT_L - @m42a_lib.M42A
SMC_CPU_INIT_3_3_L - @m42a_lib.M42A
FWH_MFG_MODE - @m42a_lib.M42A
FWPWR_ACIN - @m42a_lib.M42A

33C3 33D2 36C6


6A4 36C8
6A3
6A4 36C8
6A3
36D8
36B5
36B4
36B4
36B3
36C3 37C8
36C3 37B8
36C3 37B8
36C3 37B8
36C3 37C8
36C3 37B8
36C3 37B8
36C3 37B8
37C5
37B5
5A7 37B5
37B5
37C5
37B5
5A7 37B5
5A7 37B5
36A6 36C6
36A6 36B6
36C8
26A1 36C6
36A2 36C6
36A2 36C6
36B6
36B6
42C8
42C8
69B6
69A6
69A6
5D2 51B3
5D2 51C3
7D8 12C4
7C8 12C4
7D6 12C4
7D8 12D4
7D8 12D4
7D8 12D4
7D8 12D4
7D8 12D4
7D8 12D4
7D8 12D4
7D8 12D4
7D8 12D4
7D8 12D4
7D8 12D4

FWH_MFG_MODE
FWPWR_ACIN

7D8 12D4
7D8 12D4
7D8 12C4
7C8 12C4
7C8 12C4
7C8 12C4
7C8 12C4
7C8 12C4
7C8 12C4
7C8 12C4
7C8 12C4
7C8 12C4
7C8 12C4
7C8 12C4
7C8 12C4
7C8 12C4
7C8 12C4
7C8 12C4
7D6 12C4
7D6 12C4
7D6 12C4
7C6 33C2 33D3
7C6 33C2 33D3
12A6 33C2 33D3
12A6 33D2 33D3
7D6 11B5 12C4
7D6 12B4
7D6 12B4
7C4 12B4
7B4 12B4
7C3 12B4
7B3 12B4
7B3 12B4
7D6 12B4
7C4 12B4
7B4 12B4
7C3 12B4
7B3 12B4
7C4 12B4
7B4 12B4
7C3 12B4
7B3 12B4
7C4 12D6
7C4 12D6
7C4 12D6
7C4 12D6
7C4 12D6
7C4 12D6
7C4 12D6
7C4 12D6
7C4 12D6
7C4 12D6
7C4 12D6
7C4 12D6
7C4 12D6
7C4 12C6
7C4 12C6
7C4 12C6
7C4 12C6
7C4 12C6
7B4 12C6
7B4 12C6
7B4 12C6
7B4 12C6
7B4 12C6
7B4 12C6
7B4 12C6
7B4 12C6
7B4 12C6
7B4 12C6
7B4 12C6
7B4 12C6
7B4 12C6
7B4 12C6
7C3 12C6
7C3 12C6
7C3 12C6
7C3 12C6
7C3 12C6
7C3 12C6
7C3 12C6
7C3 12B6
7C3 12B6
7C3 12B6
7C3 12B6
7C3 12B6
7C3 12B6
7C3 12B6
7C3 12B6
7C3 12B6
7C3 12B6
7C3 12B6
7B3 12B6
7B3 12B6
7B3 12B6
7B3 12B6
7B3 12B6
7B3 12B6
7B3 12B6
7B3 12B6
7B3 12B6
7B3 12B6
7B3 12B6
7B3 12B6
7B3 12B6
7B3 12B6
7D6 12B4
7D6 12B4
7D6
7D6 12B4
7D8 12B4
7D8 12B4
7D8 12A4
7D8 12A4
7D8 12A4
7D6 12A4
7D6 12A4
7D6 12A4
7A3 12A4
7D6 12A4
5C2 6B2 21C4 47C5
6B1 45D5
23A6 23C5
39C6

y
r

a
n
i

m
il
ENET_CLK100M_PCIE_P

e
r

CPU_A20M_L
CPU_BSEL<0>
CPU_BSEL<1>
CPU_BSEL<2>
CPU_BSEL_R<0>
CPU_BSEL_R<1>
CPU_BSEL_R<2>
CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<2>
CPU_COMP<3>
CPU_DPRSTP_L
CPU_DPSLP_L
CPU_FERR_L
CPU_GTLREF
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_ISENSE_OUT_R
CPU_ISENSE_R_N
CPU_ISENSE_R_P
CPU_NMI
CPU_PROCHOT_L
CPU_PSI_L
CPU_PWRGD
CPU_RCIN_L
CPU_SMI_L
CPU_STPCLK_L
CPU_TEST1
CPU_TEST2

66C5
66B5
66B5
66B5
66A6
66C6
66C6
66C6
66C7
66C5
66C5
66B4
66C5
66C5
66B6 66C6
66C6
66C7
66C7
66B6 66D6
66C5
66B6
32A4 33B8

100

8
FWPWR_EN
FWPWR_EN_L
FWPWR_EN_L_DIV
FWPWR_EN_L_R
FWPWR_RUN
FW_A_TPA_N
FW_A_TPA_P
FW_A_TPBIAS
FW_A_TPB_N
FW_A_TPB_P

FW_B_TPA_N
FW_B_TPA_P
FW_B_TPBIAS
FW_B_TPB_N
FW_B_TPB_P
FW_C_TPA_N
FW_C_TPA_P
FW_C_TPBIAS
FW_C_TPB_N
FW_C_TPB_P

FW_PCI_IDSEL
FW_PCI_RST_L
FW_PORT0_TPA_N_FL
FW_PORT0_TPA_P_FL
FW_PORT0_TPB
FW_PORT0_TPB_N_FL
FW_PORT0_TPB_P_FL
FW_PWRON_RST_L
FW_R0
FW_R1
FW_XI
FW_XO
FW_XO_R
GEYSER_GND_F
GND_1V8S3_SGND
GND_1V51V05S0_SGND
GND_5V3V3S5_SGND
GND_AUDIO_CODEC

GND_AUDIO_PWR

FWPWR_EN - @m42a_lib.M42A
FWPWR_EN_L - @m42a_lib.M42A
FWPWR_EN_L_DIV - @m42a_lib.M42A
FWPWR_EN_L_R - @m42a_lib.M42A
FWPWR_RUN - @m42a_lib.M42A
FW_A_TPA_N - @m42a_lib.M42A
FW_PORT0_TPA_N - @m42a_lib.M42A
FW_A_TPA_P - @m42a_lib.M42A
FW_PORT0_TPA_P - @m42a_lib.M42A
FW_A_TPBIAS - @m42a_lib.M42A
FW_A_TPB_N - @m42a_lib.M42A
FW_PORT0_TPB_N - @m42a_lib.M42A
FW_A_TPB_P - @m42a_lib.M42A
FW_PORT0_TPB_P - @m42a_lib.M42A
FW_B_TPA_N - @m42a_lib.M42A
FW_B_TPA_N_SPN - @m42a_lib.M42A
FW_B_TPA_P - @m42a_lib.M42A
FW_B_TPA_P_SPN - @m42a_lib.M42A
FW_B_TPBIAS - @m42a_lib.M42A
FW_B_TPBIAS_SPN - @m42a_lib.M42A
FW_B_TPB_N - @m42a_lib.M42A
FW_B_TPB_N_SPN - @m42a_lib.M42A
FW_B_TPB_P - @m42a_lib.M42A
FW_B_TPB_P_SPN - @m42a_lib.M42A
FW_C_TPA_N - @m42a_lib.M42A
FW_C_TPA_N_SPN - @m42a_lib.M42A
FW_C_TPA_P - @m42a_lib.M42A
FW_C_TPA_P_SPN - @m42a_lib.M42A
FW_C_TPBIAS - @m42a_lib.M42A
FW_C_TPBIAS_SPN - @m42a_lib.M42A
FW_C_TPB_N - @m42a_lib.M42A
FW_C_TPB_N_SPN - @m42a_lib.M42A
FW_C_TPB_P - @m42a_lib.M42A
FW_C_TPB_P_SPN - @m42a_lib.M42A
FW_PCI_IDSEL - @m42a_lib.M42A
FW_PCI_RST_L - @m42a_lib.M42A
FW_PORT0_TPA_N_FL - @m42a_lib.M42A
FW_PORT0_TPA_P_FL - @m42a_lib.M42A
FW_PORT0_TPB - @m42a_lib.M42A
FW_PORT0_TPB_N_FL - @m42a_lib.M42A
FW_PORT0_TPB_P_FL - @m42a_lib.M42A
FW_PWRON_RST_L - @m42a_lib.M42A
FW_R0 - @m42a_lib.M42A
FW_R1 - @m42a_lib.M42A
FW_XI - @m42a_lib.M42A
FW_XO - @m42a_lib.M42A
FW_XO_R - @m42a_lib.M42A
GEYSER_GND_F - @m42a_lib.M42A
GND_1V8S3_SGND - @m42a_lib.M42A
GND_1V51V05S0_SGND - @m42a_lib.M42A
GND_5V3V3S5_SGND - @m42a_lib.M42A
GND_AUDIO_CODEC - @m42a_lib.M42A
=GND_AUDIO_CODEC - @m42a_lib.M42A

GND_AUDIO_PWR - @m42a_lib.M42A
=GND_AUDIO_PWR - @m42a_lib.M42A

GND_AUDIO_SPDIF_DGND GND_AUDIO_SPDIF_DGND @m42a_lib.M42A


GND_BT_F
GND_BT_F - @m42a_lib.M42A
GND_CHASSIS_CPU
GND_CHASSIS_CPU - @m42a_lib.M42A
GND_CHASSIS_FANSCREW GND_CHASSIS_FANSCREW @m42a_lib.M42A
GND_CHGR_SGND
GND_CHGR_SGND - @m42a_lib.M42A
GND_IMVP6_SGND
GND_IMVP6_SGND - @m42a_lib.M42A
GND_SMC_AVSS
GND_SMC_AVSS - @m42a_lib.M42A

GND_SMC_LID_F
GPU_CRT_DDC_CLK
GPU_CRT_DDC_DATA
IDE_CSEL_PD
IDE_IRQ14
IDE_PDA<0>
IDE_PDA<1>
IDE_PDA<2>
IDE_PDCS1_L
IDE_PDCS3_L
IDE_PDD<0>
IDE_PDD<1>
IDE_PDD<2>
IDE_PDD<3>
IDE_PDD<4>
IDE_PDD<5>
IDE_PDD<6>
IDE_PDD<7>
IDE_PDD<8>
IDE_PDD<9>
IDE_PDD<10>
IDE_PDD<11>
IDE_PDD<12>
IDE_PDD<13>
IDE_PDD<14>
IDE_PDD<15>
IDE_PDDACK_L
IDE_PDDREQ
IDE_PDIORDY
IDE_PDIOR_L
IDE_PDIOW_L
IDE_RESET_L
IMVP6_BOOT1
IMVP6_BOOT1_RC
IMVP6_BOOT2
IMVP6_BOOT2_RC
IMVP6_COMP
IMVP6_COMP_RC
IMVP6_CPU_ISENSE_N
IMVP6_CPU_ISENSE_P
IMVP6_DFB
IMVP6_DROOP
IMVP6_FB
IMVP6_FB2
IMVP6_FET_RC1
IMVP6_FET_RC2
IMVP6_ISEN1
IMVP6_ISEN2
IMVP6_LGATE1
IMVP6_LGATE2
IMVP6_NTC
IMVP6_NTC_R
IMVP6_OCSET
IMVP6_PHASE1

7
39C5
39C4 60C8
39C5
60C7
39C6
38B3 39B6
39B5
38B3 39B6
39B5
38B3 39B6
38B3 39B6
39B5
38B3 39B6
39B5
6D2 38B3
5B7 6D1
6D2 38B3
5B7 6D1
6D2 38B3
5B7 6D1
6D2 38B3
5B7 6D1
6D2 38B3
5B7 6D1
6D2 38B3
5B7 6D1
6D2 38B3
5B7 6D1
6D2 38B3
5B7 6D1
6D2 38B3
5B7 6D1
6D2 38B3
5B7 6D1
38A5
38A5
39B2
39B2
39A5
39B2
39B2
38C3
38B3
38C3
38C3
38C3
38C3
40C5
61B5 61C6
62B7
59B7
5D1 64B2
54A6 54B6
55C8 56B3
57B3 57B3
57C5 57C8
5D1 64B2
55A3 55A5
55B8 55C3
55D8 56C2
56A8 56C8

54D2
56B5
57B5
57D8

55A8 55B8
57A5 57A6
57B8 57C3
64B3

55A8 55B3 55B3


55C3 55C8 55D3
64B3

IMVP6_PHASE2
IMVP6_RBIAS
IMVP6_RTN
IMVP6_SOFT
IMVP6_UGATE1
IMVP6_UGATE2
IMVP6_VDIFF
IMVP6_VDIFF_RC
IMVP6_VO
IMVP6_VO_R
IMVP6_VO_R1
IMVP6_VO_R2
IMVP6_VR_TT
IMVP6_VSEN
IMVP6_VSUM
IMVP6_VSUM_R1
IMVP6_VSUM_R2
IMVP6_VW
IMVP_DPRSLPVR
IMVP_VR_ON
INT_PIRQA_L
INT_PIRQB_L
INT_PIRQC_L
INT_PIRQD_L
INT_SERIRQ
INVT_CHGND
INV_BKLIGHT_PWM_L
INV_GND
INV_PWREN_F_L
INV_PWREN_L
IR_RX_OUT
IR_RX_OUT_F
ISENSE_CAL_EN
ISENSE_CAL_EN_L
ISENSE_CAL_EN_LS5V
ITPRESET_L
ITP_TDO
J2900_SA1
KBC_MDE
LCDVDD_PWREN_L
LCDVDD_PWREN_L_R
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
LVDS_A_CLK_N
LVDS_A_CLK_P
LVDS_A_DATA_N<0>
LVDS_A_DATA_N<1>
LVDS_A_DATA_N<2>
LVDS_A_DATA_P<0>
LVDS_A_DATA_P<1>
LVDS_A_DATA_P<2>
LVDS_BKLTCTL
LVDS_BKLTEN
LVDS_B_CLK_N
LVDS_B_CLK_P
LVDS_B_DATA_N<0>

44B4
6B8
6B8

LVDS_B_DATA_N<1>
LVDS_B_DATA_N<2>

66A5 66B7
58A4 58B7 58C8
45C2 45C4 46B6 48A1 48B5
48C1 61C1 62A5 66B1 66C2
GND_SMC_LID_F - @m42a_lib.M42A
65A7
GPU_CRT_DDC_CLK - @m42a_lib.M42A
69B6 69D5
GPU_CRT_DDC_DATA - @m42a_lib.M42A
69B6 69D5
IDE_CSEL_PD - @m42a_lib.M42A
34B4
IDE_IRQ14 - @m42a_lib.M42A
21B6 34B6
IDE_PDA<0> - @m42a_lib.M42A
21B5 34B5
IDE_PDA<1> - @m42a_lib.M42A
21B5 34B5
IDE_PDA<2> - @m42a_lib.M42A
21B5 34B3
IDE_PDCS1_L - @m42a_lib.M42A
21B5 34B5
IDE_PDCS3_L - @m42a_lib.M42A
21B5 34B3
IDE_PDD<0> - @m42a_lib.M42A
21C5 34C5
IDE_PDD<1> - @m42a_lib.M42A
21B5 34C5
IDE_PDD<2> - @m42a_lib.M42A
21B5 34C5
IDE_PDD<3> - @m42a_lib.M42A
21B5 34C5
IDE_PDD<4> - @m42a_lib.M42A
21B5 34C5
IDE_PDD<5> - @m42a_lib.M42A
21B5 34C5
IDE_PDD<6> - @m42a_lib.M42A
21B5 34C5
IDE_PDD<7> - @m42a_lib.M42A
21B5 34C5
IDE_PDD<8> - @m42a_lib.M42A
21B5 34C3
IDE_PDD<9> - @m42a_lib.M42A
21B5 34C3
IDE_PDD<10> - @m42a_lib.M42A
21B5 34C3
IDE_PDD<11> - @m42a_lib.M42A
21B5 34C3
IDE_PDD<12> - @m42a_lib.M42A
21B5 34C3
IDE_PDD<13> - @m42a_lib.M42A
21B5 34C3
IDE_PDD<14> - @m42a_lib.M42A
21B5 34C3
IDE_PDD<15> - @m42a_lib.M42A
21B5 34C3
IDE_PDDACK_L - @m42a_lib.M42A
21B6 34B3
IDE_PDDREQ - @m42a_lib.M42A
21B6 34B6
IDE_PDIORDY - @m42a_lib.M42A
21B6 34B6
IDE_PDIOR_L - @m42a_lib.M42A
21B6 34C3
IDE_PDIOW_L - @m42a_lib.M42A
21B6 34B5
IDE_RESET_L - @m42a_lib.M42A
23A3 34C5
IMVP6_BOOT1 - @m42a_lib.M42A
58A8 58C6
IMVP6_BOOT1_RC - @m42a_lib.M42A
58D5
IMVP6_BOOT2 - @m42a_lib.M42A
58A6 58C6
IMVP6_BOOT2_RC - @m42a_lib.M42A
58C5
IMVP6_COMP - @m42a_lib.M42A
5D7 58A4 58B7
IMVP6_COMP_RC - @m42a_lib.M42A
58B8
IMVP6_CPU_ISENSE_N - @m42a_lib.M42A 48C4
IMVP6_CPU_ISENSE_P - @m42a_lib.M42A 48D4
IMVP6_DFB - @m42a_lib.M42A
58A4 58B6
IMVP6_DROOP - @m42a_lib.M42A
48D5 58A4 58B6
IMVP6_FB - @m42a_lib.M42A
58A4 58B7
IMVP6_FB2 - @m42a_lib.M42A
58A4 58B7
IMVP6_FET_RC1 - @m42a_lib.M42A
58A8 58C2
IMVP6_FET_RC2 - @m42a_lib.M42A
58A6 58B2
IMVP6_ISEN1 - @m42a_lib.M42A
58A8 58C6
IMVP6_ISEN2 - @m42a_lib.M42A
58A6 58C6
IMVP6_LGATE1 - @m42a_lib.M42A
58A8 58C6
IMVP6_LGATE2 - @m42a_lib.M42A
58A6 58C6
IMVP6_NTC - @m42a_lib.M42A
58C7
IMVP6_NTC_R - @m42a_lib.M42A
58C7
IMVP6_OCSET - @m42a_lib.M42A
58A4 58B6
IMVP6_PHASE1 - @m42a_lib.M42A
58A8 58C6

LVDS_B_DATA_P<0>
LVDS_B_DATA_P<1>
LVDS_B_DATA_P<2>
LVDS_CLKCTLA
LVDS_CLKCTLB
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_IBG
LVDS_VDDEN
MAX9705_L_N
MAX9705_R_N
MAX9705_SUB_N
MAX9890_CEXT
MAX9890_INL
MAX9890_INR
MEMVTT_EN
MEMVTT_VREF
MEM_A_A<0>
MEM_A_A<13..0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>

IMVP6_PHASE2 - @m42a_lib.M42A
IMVP6_RBIAS - @m42a_lib.M42A
IMVP6_RTN - @m42a_lib.M42A
IMVP6_SOFT - @m42a_lib.M42A
IMVP6_UGATE1 - @m42a_lib.M42A
IMVP6_UGATE2 - @m42a_lib.M42A
IMVP6_VDIFF - @m42a_lib.M42A
IMVP6_VDIFF_RC - @m42a_lib.M42A
IMVP6_VO - @m42a_lib.M42A
IMVP6_VO_R - @m42a_lib.M42A
IMVP6_VO_R1 - @m42a_lib.M42A
IMVP6_VO_R2 - @m42a_lib.M42A
IMVP6_VR_TT - @m42a_lib.M42A
IMVP6_VSEN - @m42a_lib.M42A
IMVP6_VSUM - @m42a_lib.M42A
IMVP6_VSUM_R1 - @m42a_lib.M42A
IMVP6_VSUM_R2 - @m42a_lib.M42A
IMVP6_VW - @m42a_lib.M42A
IMVP_DPRSLPVR - @m42a_lib.M42A
IMVP_VR_ON - @m42a_lib.M42A
INT_PIRQA_L - @m42a_lib.M42A
INT_PIRQB_L - @m42a_lib.M42A
INT_PIRQC_L - @m42a_lib.M42A
INT_PIRQD_L - @m42a_lib.M42A
INT_SERIRQ - @m42a_lib.M42A
INVT_CHGND - @m42a_lib.M42A
INV_BKLIGHT_PWM_L - @m42a_lib.M42A
INV_GND - @m42a_lib.M42A
INV_PWREN_F_L - @m42a_lib.M42A
INV_PWREN_L - @m42a_lib.M42A
IR_RX_OUT - @m42a_lib.M42A
IR_RX_OUT_F - @m42a_lib.M42A
ISENSE_CAL_EN - @m42a_lib.M42A
ISENSE_CAL_EN_L - @m42a_lib.M42A
ISENSE_CAL_EN_LS5V - @m42a_lib.M42A
ITPRESET_L - @m42a_lib.M42A
ITP_TDO - @m42a_lib.M42A
J2900_SA1 - @m42a_lib.M42A
KBC_MDE - @m42a_lib.M42A
LCDVDD_PWREN_L - @m42a_lib.M42A
LCDVDD_PWREN_L_R - @m42a_lib.M42A
LPC_AD<0> - @m42a_lib.M42A
LPC_AD<1> - @m42a_lib.M42A
LPC_AD<2> - @m42a_lib.M42A
LPC_AD<3> - @m42a_lib.M42A
LPC_FRAME_L - @m42a_lib.M42A
LVDS_A_CLK_N - @m42a_lib.M42A
LVDS_A_CLK_P - @m42a_lib.M42A
LVDS_A_DATA_N<0> - @m42a_lib.M42A
LVDS_A_DATA_N<1> - @m42a_lib.M42A
LVDS_A_DATA_N<2> - @m42a_lib.M42A
LVDS_A_DATA_P<0> - @m42a_lib.M42A
LVDS_A_DATA_P<1> - @m42a_lib.M42A
LVDS_A_DATA_P<2> - @m42a_lib.M42A
LVDS_BKLTCTL - @m42a_lib.M42A
LVDS_BKLTEN - @m42a_lib.M42A
LVDS_B_CLK_N - @m42a_lib.M42A
LVDS_B_CLK_N_SPN - @m42a_lib.M42A
LVDS_B_CLK_P - @m42a_lib.M42A
LVDS_B_CLK_P_SPN - @m42a_lib.M42A
LVDS_B_DATA_N<0> - @m42a_lib.M42A
LVDS_B_DATA_N0_SPN - @m42a_lib.M42A
LVDS_B_DATA_N<1> - @m42a_lib.M42A
LVDS_B_DATA_N1_SPN - @m42a_lib.M42A
LVDS_B_DATA_N<2> - @m42a_lib.M42A
LVDS_B_DATA_N2_SPN - @m42a_lib.M42A
LVDS_B_DATA_P<0> - @m42a_lib.M42A
LVDS_B_DATA_P0_SPN - @m42a_lib.M42A
LVDS_B_DATA_P<1> - @m42a_lib.M42A
LVDS_B_DATA_P1_SPN - @m42a_lib.M42A
LVDS_B_DATA_P<2> - @m42a_lib.M42A
LVDS_B_DATA_P2_SPN - @m42a_lib.M42A
LVDS_CLKCTLA - @m42a_lib.M42A
LVDS_CLKCTLB - @m42a_lib.M42A
LVDS_DDC_CLK - @m42a_lib.M42A
LVDS_DDC_DATA - @m42a_lib.M42A
LVDS_IBG - @m42a_lib.M42A
LVDS_VDDEN - @m42a_lib.M42A
MAX9705_L_N - @m42a_lib.M42A
MAX9705_R_N - @m42a_lib.M42A
MAX9705_SUB_N - @m42a_lib.M42A
MAX9890_CEXT - @m42a_lib.M42A
MAX9890_INL - @m42a_lib.M42A
MAX9890_INR - @m42a_lib.M42A
MEMVTT_EN - @m42a_lib.M42A
MEMVTT_VREF - @m42a_lib.M42A
MEM_A_A<0> - @m42a_lib.M42A
MEM_A_A<13..0> - @m42a_lib.M42A
MEM_A_A<1> - @m42a_lib.M42A
MEM_A_A<2> - @m42a_lib.M42A
MEM_A_A<3> - @m42a_lib.M42A
MEM_A_A<4> - @m42a_lib.M42A
MEM_A_A<5> - @m42a_lib.M42A
MEM_A_A<6> - @m42a_lib.M42A
MEM_A_A<7> - @m42a_lib.M42A
MEM_A_A<8> - @m42a_lib.M42A
MEM_A_A<9> - @m42a_lib.M42A
MEM_A_A<10> - @m42a_lib.M42A
MEM_A_A<11> - @m42a_lib.M42A
MEM_A_A<12> - @m42a_lib.M42A
MEM_A_A<13> - @m42a_lib.M42A
MEM_A_A<14> - @m42a_lib.M42A
MEM_A_A14_SPN - @m42a_lib.M42A
MEM_A_A<15> - @m42a_lib.M42A
MEM_A_A15_SPN - @m42a_lib.M42A
MEM_A_BS<0> - @m42a_lib.M42A
MEM_A_BS<2..0> - @m42a_lib.M42A
MEM_A_BS<1> - @m42a_lib.M42A
MEM_A_BS<2> - @m42a_lib.M42A
MEM_A_CAS_L - @m42a_lib.M42A
MEM_A_DM<0> - @m42a_lib.M42A
MEM_A_DM<1> - @m42a_lib.M42A
MEM_A_DM<2> - @m42a_lib.M42A
MEM_A_DM<3> - @m42a_lib.M42A
MEM_A_DM<4> - @m42a_lib.M42A
MEM_A_DM<5> - @m42a_lib.M42A
MEM_A_DM<6> - @m42a_lib.M42A
MEM_A_DM<7> - @m42a_lib.M42A
MEM_A_DQ<0> - @m42a_lib.M42A
MEM_A_DQ<1> - @m42a_lib.M42A
MEM_A_DQ<2> - @m42a_lib.M42A
MEM_A_DQ<3> - @m42a_lib.M42A
MEM_A_DQ<4> - @m42a_lib.M42A
MEM_A_DQ<5> - @m42a_lib.M42A

MEM_A_BS<0>
MEM_A_BS<2..0>
MEM_A_BS<1>
MEM_A_BS<2>
MEM_A_CAS_L
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>

MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_RAS_L
MEM_A_WE_L
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>

53C6

53C6
53C6
53C6
53C6
53C6

MEM_A_DQ<6> - @m42a_lib.M42A
MEM_A_DQ<7> - @m42a_lib.M42A
MEM_A_DQ<8> - @m42a_lib.M42A
MEM_A_DQ<9> - @m42a_lib.M42A
MEM_A_DQ<10> - @m42a_lib.M42A
MEM_A_DQ<11> - @m42a_lib.M42A
MEM_A_DQ<12> - @m42a_lib.M42A
MEM_A_DQ<13> - @m42a_lib.M42A
MEM_A_DQ<14> - @m42a_lib.M42A
MEM_A_DQ<15> - @m42a_lib.M42A
MEM_A_DQ<16> - @m42a_lib.M42A
MEM_A_DQ<17> - @m42a_lib.M42A
MEM_A_DQ<18> - @m42a_lib.M42A
MEM_A_DQ<19> - @m42a_lib.M42A
MEM_A_DQ<20> - @m42a_lib.M42A
MEM_A_DQ<21> - @m42a_lib.M42A
MEM_A_DQ<22> - @m42a_lib.M42A
MEM_A_DQ<23> - @m42a_lib.M42A
MEM_A_DQ<24> - @m42a_lib.M42A
MEM_A_DQ<25> - @m42a_lib.M42A
MEM_A_DQ<26> - @m42a_lib.M42A
MEM_A_DQ<27> - @m42a_lib.M42A
MEM_A_DQ<28> - @m42a_lib.M42A
MEM_A_DQ<29> - @m42a_lib.M42A
MEM_A_DQ<30> - @m42a_lib.M42A
MEM_A_DQ<31> - @m42a_lib.M42A
MEM_A_DQ<32> - @m42a_lib.M42A
MEM_A_DQ<33> - @m42a_lib.M42A
MEM_A_DQ<34> - @m42a_lib.M42A
MEM_A_DQ<35> - @m42a_lib.M42A
MEM_A_DQ<36> - @m42a_lib.M42A
MEM_A_DQ<37> - @m42a_lib.M42A
MEM_A_DQ<38> - @m42a_lib.M42A
MEM_A_DQ<39> - @m42a_lib.M42A
MEM_A_DQ<40> - @m42a_lib.M42A
MEM_A_DQ<41> - @m42a_lib.M42A
MEM_A_DQ<42> - @m42a_lib.M42A
MEM_A_DQ<43> - @m42a_lib.M42A
MEM_A_DQ<44> - @m42a_lib.M42A
MEM_A_DQ<45> - @m42a_lib.M42A
MEM_A_DQ<46> - @m42a_lib.M42A
MEM_A_DQ<47> - @m42a_lib.M42A
MEM_A_DQ<48> - @m42a_lib.M42A
MEM_A_DQ<49> - @m42a_lib.M42A
MEM_A_DQ<50> - @m42a_lib.M42A
MEM_A_DQ<51> - @m42a_lib.M42A
MEM_A_DQ<52> - @m42a_lib.M42A
MEM_A_DQ<53> - @m42a_lib.M42A
MEM_A_DQ<54> - @m42a_lib.M42A
MEM_A_DQ<55> - @m42a_lib.M42A
MEM_A_DQ<56> - @m42a_lib.M42A
MEM_A_DQ<57> - @m42a_lib.M42A
MEM_A_DQ<58> - @m42a_lib.M42A
MEM_A_DQ<59> - @m42a_lib.M42A
MEM_A_DQ<60> - @m42a_lib.M42A
MEM_A_DQ<61> - @m42a_lib.M42A
MEM_A_DQ<62> - @m42a_lib.M42A
MEM_A_DQ<63> - @m42a_lib.M42A
MEM_A_DQS_N<0> - @m42a_lib.M42A
MEM_A_DQS_N<1> - @m42a_lib.M42A
MEM_A_DQS_N<2> - @m42a_lib.M42A
MEM_A_DQS_N<3> - @m42a_lib.M42A
MEM_A_DQS_N<4> - @m42a_lib.M42A
MEM_A_DQS_N<5> - @m42a_lib.M42A
MEM_A_DQS_N<6> - @m42a_lib.M42A
MEM_A_DQS_N<7> - @m42a_lib.M42A
MEM_A_DQS_P<0> - @m42a_lib.M42A
MEM_A_DQS_P<1> - @m42a_lib.M42A
MEM_A_DQS_P<2> - @m42a_lib.M42A
MEM_A_DQS_P<3> - @m42a_lib.M42A
MEM_A_DQS_P<4> - @m42a_lib.M42A
MEM_A_DQS_P<5> - @m42a_lib.M42A
MEM_A_DQS_P<6> - @m42a_lib.M42A
MEM_A_DQS_P<7> - @m42a_lib.M42A
MEM_A_RAS_L - @m42a_lib.M42A
MEM_A_WE_L - @m42a_lib.M42A
MEM_B_A<0> - @m42a_lib.M42A
MEM_B_A<1> - @m42a_lib.M42A
MEM_B_A<2> - @m42a_lib.M42A
MEM_B_A<3> - @m42a_lib.M42A
MEM_B_A<4> - @m42a_lib.M42A
MEM_B_A<5> - @m42a_lib.M42A
MEM_B_A<6> - @m42a_lib.M42A
MEM_B_A<7> - @m42a_lib.M42A
MEM_B_A<8> - @m42a_lib.M42A
MEM_B_A<9> - @m42a_lib.M42A
MEM_B_A<10> - @m42a_lib.M42A
MEM_B_A<11> - @m42a_lib.M42A
MEM_B_A<12> - @m42a_lib.M42A
MEM_B_A<13> - @m42a_lib.M42A
MEM_B_A<14> - @m42a_lib.M42A
MEM_B_A14_SPN - @m42a_lib.M42A
MEM_B_A<15> - @m42a_lib.M42A
MEM_B_A15_SPN - @m42a_lib.M42A
MEM_B_BS<0> - @m42a_lib.M42A
MEM_B_BS<2..0> - @m42a_lib.M42A
MEM_B_BS<1> - @m42a_lib.M42A
MEM_B_BS<2> - @m42a_lib.M42A
MEM_B_CAS_L - @m42a_lib.M42A
MEM_B_DM<0> - @m42a_lib.M42A
MEM_B_DM<1> - @m42a_lib.M42A
MEM_B_DM<2> - @m42a_lib.M42A
MEM_B_DM<3> - @m42a_lib.M42A
MEM_B_DM<4> - @m42a_lib.M42A
MEM_B_DM<5> - @m42a_lib.M42A
MEM_B_DM<6> - @m42a_lib.M42A
MEM_B_DM<7> - @m42a_lib.M42A
MEM_B_DQ<0> - @m42a_lib.M42A
MEM_B_DQ<1> - @m42a_lib.M42A
MEM_B_DQ<2> - @m42a_lib.M42A
MEM_B_DQ<3> - @m42a_lib.M42A
MEM_B_DQ<4> - @m42a_lib.M42A
MEM_B_DQ<5> - @m42a_lib.M42A
MEM_B_DQ<6> - @m42a_lib.M42A
MEM_B_DQ<7> - @m42a_lib.M42A
MEM_B_DQ<8> - @m42a_lib.M42A
MEM_B_DQ<9> - @m42a_lib.M42A
MEM_B_DQ<10> - @m42a_lib.M42A
MEM_B_DQ<11> - @m42a_lib.M42A
MEM_B_DQ<12> - @m42a_lib.M42A
MEM_B_DQ<13> - @m42a_lib.M42A
MEM_B_DQ<14> - @m42a_lib.M42A
MEM_B_DQ<15> - @m42a_lib.M42A
MEM_B_DQ<16> - @m42a_lib.M42A

MEM_B_A<15>
MEM_B_BS<0>
MEM_B_BS<2..0>
MEM_B_BS<1>
MEM_B_BS<2>
MEM_B_CAS_L
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>

15D7 28D6
15D7 28D6
15C7 28D6
15C7 28D6
15C7 28D6
15C7 28D4
15C7 28D4
15C7 28D6
15C7 28D4
15C7 28D4
15C7 28C4
15C7 28C6
15C7 28C4
15C7 28C6
15C7 28C6
15C7 28C4
15C7 28C6
15C7 28C4
15C7 28D6
15C7 28C6
15C7 28C4
15C7 28C6
15C7 28C4
15C7 28D4
15C7 28C4
15C7 28C6
15C7 28B6
15C7 28B4
15B7 28B4
15B7 28B4
15B7 28B4
15B7 28B6
15B7 28B6
15B7 28B6
15B7 28B4
15B7 28B6
15B7 28A4
15B7 28A6
15B7 28B6
15B7 28B4
15B7 28A4
15B7 28A6
15B7 28A6
15B7 28A6
15B7 28A4
15B7 28A4
15B7 28A6
15B7 28A4
15B7 28A4
15B7 28A6
15B7 28A6
15B7 28A6
15B7 28A6
15B7 28A4
15A7 28A4
15A7 28A4
15A7 28A4
15A7 28A6
15C5 28D6
15C5 28D6
15C5 28C4
15C5 28C6
15C5 28B6
15C5 28B4
15C5 28A4
15C5 28A6
15C5 28D6
15C5 28D6
15C5 28C4
15C5 28C6
15C5 28B6
15C5 28B4
15C5 28A4
15C5 28A6
15B5 28B4
15B5 28B6
15C2 29B4
15C2 29B6
15C2 29B4
15B2 29B6
15B2 29B4
15B2 29B6
15B2 29C4
15B2 29C4
15B2 29C6
15B2 29C6
15B2 29B6
15B2 29C4
15B2 29C6
15B2 29B4
6A4 29C4
6A3
6A4 29C4
6A3
15D2 29B6
30A6
15D2 29B4
15D2 29C6
15D2 29B6
15D2 29D4
15D2 29D4
15D2 29C4
15C2 29C6
15C2 29A4
15C2 29A6
15C2 29A6
15C2 29B4
15D4 29D4
15D4 29D6
15D4 29D6
15D4 29D6
15D4 29D4
15D4 29D6
15D4 29D4
15D4 29D4
15C4 29D6
15C4 29D4
15C4 29D6
15C4 29D4
15C4 29D6
15C4 29D6
15C4 29D4
15C4 29D4
15C4 29C4

MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>
MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
MEM_B_RAS_L
MEM_B_WE_L
MEM_CKE<0>
MEM_CKE<3..0>
MEM_CKE<1>
MEM_CKE<2>
MEM_CKE<3>
MEM_CLK_N<0>
MEM_CLK_N<1>
MEM_CLK_N<2>
MEM_CLK_N<3>
MEM_CLK_P<0>
MEM_CLK_P<1>
MEM_CLK_P<2>
MEM_CLK_P<3>
MEM_CS_L<0>
MEM_CS_L<3..0>
MEM_CS_L<1>
MEM_CS_L<2>
MEM_CS_L<3>
MEM_ISENSE
MEM_ISENSE_R1_N
MEM_ISENSE_R1_P
MEM_ISENSE_R2
MEM_ISENSE_VCC
MEM_ODT<0>
MEM_ODT<3..0>
MEM_ODT<1>
MEM_ODT<2>
MEM_ODT<3>
MEM_RCOMP
MEM_RCOMP_L
MEM_VREF_A
MEM_VREF_B
MEM_VREF_NB_0
MEM_VREF_NB_1
MIC_HI
MIC_HI_CONN
MIC_HI_F
MIC_IN
MIC_LO
MIC_LO_CONN
MIC_LO_F
MIC_SHIELD
MIC_SHIELD_F
MIC_SHLD_CONN
MM1573DN_NR
NB_BSEL<0>
NB_BSEL<1>
NB_BSEL<2>
NB_CFG<3>

MEM_B_DQ<17> - @m42a_lib.M42A
MEM_B_DQ<18> - @m42a_lib.M42A
MEM_B_DQ<19> - @m42a_lib.M42A
MEM_B_DQ<20> - @m42a_lib.M42A
MEM_B_DQ<21> - @m42a_lib.M42A
MEM_B_DQ<22> - @m42a_lib.M42A
MEM_B_DQ<23> - @m42a_lib.M42A
MEM_B_DQ<24> - @m42a_lib.M42A
MEM_B_DQ<25> - @m42a_lib.M42A
MEM_B_DQ<26> - @m42a_lib.M42A
MEM_B_DQ<27> - @m42a_lib.M42A
MEM_B_DQ<28> - @m42a_lib.M42A
MEM_B_DQ<29> - @m42a_lib.M42A
MEM_B_DQ<30> - @m42a_lib.M42A
MEM_B_DQ<31> - @m42a_lib.M42A
MEM_B_DQ<32> - @m42a_lib.M42A
MEM_B_DQ<33> - @m42a_lib.M42A
MEM_B_DQ<34> - @m42a_lib.M42A
MEM_B_DQ<35> - @m42a_lib.M42A
MEM_B_DQ<36> - @m42a_lib.M42A
MEM_B_DQ<37> - @m42a_lib.M42A
MEM_B_DQ<38> - @m42a_lib.M42A
MEM_B_DQ<39> - @m42a_lib.M42A
MEM_B_DQ<40> - @m42a_lib.M42A
MEM_B_DQ<41> - @m42a_lib.M42A
MEM_B_DQ<42> - @m42a_lib.M42A
MEM_B_DQ<43> - @m42a_lib.M42A
MEM_B_DQ<44> - @m42a_lib.M42A
MEM_B_DQ<45> - @m42a_lib.M42A
MEM_B_DQ<46> - @m42a_lib.M42A
MEM_B_DQ<47> - @m42a_lib.M42A
MEM_B_DQ<48> - @m42a_lib.M42A
MEM_B_DQ<49> - @m42a_lib.M42A
MEM_B_DQ<50> - @m42a_lib.M42A
MEM_B_DQ<51> - @m42a_lib.M42A
MEM_B_DQ<52> - @m42a_lib.M42A
MEM_B_DQ<53> - @m42a_lib.M42A
MEM_B_DQ<54> - @m42a_lib.M42A
MEM_B_DQ<55> - @m42a_lib.M42A
MEM_B_DQ<56> - @m42a_lib.M42A
MEM_B_DQ<57> - @m42a_lib.M42A
MEM_B_DQ<58> - @m42a_lib.M42A
MEM_B_DQ<59> - @m42a_lib.M42A
MEM_B_DQ<60> - @m42a_lib.M42A
MEM_B_DQ<61> - @m42a_lib.M42A
MEM_B_DQ<62> - @m42a_lib.M42A
MEM_B_DQ<63> - @m42a_lib.M42A
MEM_B_DQS_N<0> - @m42a_lib.M42A
MEM_B_DQS_N<1> - @m42a_lib.M42A
MEM_B_DQS_N<2> - @m42a_lib.M42A
MEM_B_DQS_N<3> - @m42a_lib.M42A
MEM_B_DQS_N<4> - @m42a_lib.M42A
MEM_B_DQS_N<5> - @m42a_lib.M42A
MEM_B_DQS_N<6> - @m42a_lib.M42A
MEM_B_DQS_N<7> - @m42a_lib.M42A
MEM_B_DQS_P<0> - @m42a_lib.M42A
MEM_B_DQS_P<1> - @m42a_lib.M42A
MEM_B_DQS_P<2> - @m42a_lib.M42A
MEM_B_DQS_P<3> - @m42a_lib.M42A
MEM_B_DQS_P<4> - @m42a_lib.M42A
MEM_B_DQS_P<5> - @m42a_lib.M42A
MEM_B_DQS_P<6> - @m42a_lib.M42A
MEM_B_DQS_P<7> - @m42a_lib.M42A
MEM_B_RAS_L - @m42a_lib.M42A
MEM_B_WE_L - @m42a_lib.M42A
MEM_CKE<0> - @m42a_lib.M42A
MEM_CKE<3..0> - @m42a_lib.M42A
MEM_CKE<1> - @m42a_lib.M42A
MEM_CKE<2> - @m42a_lib.M42A
MEM_CKE<3> - @m42a_lib.M42A
MEM_CLK_N<0> - @m42a_lib.M42A
MEM_CLK_N<1> - @m42a_lib.M42A
MEM_CLK_N<2> - @m42a_lib.M42A
MEM_CLK_N<3> - @m42a_lib.M42A
MEM_CLK_P<0> - @m42a_lib.M42A
MEM_CLK_P<1> - @m42a_lib.M42A
MEM_CLK_P<2> - @m42a_lib.M42A
MEM_CLK_P<3> - @m42a_lib.M42A
MEM_CS_L<0> - @m42a_lib.M42A
MEM_CS_L<3..0> - @m42a_lib.M42A
MEM_CS_L<1> - @m42a_lib.M42A
MEM_CS_L<2> - @m42a_lib.M42A
MEM_CS_L<3> - @m42a_lib.M42A
MEM_ISENSE - @m42a_lib.M42A
MEM_ISENSE_R1_N - @m42a_lib.M42A
MEM_ISENSE_R1_P - @m42a_lib.M42A
MEM_ISENSE_R2 - @m42a_lib.M42A
MEM_ISENSE_VCC - @m42a_lib.M42A
MEM_ODT<0> - @m42a_lib.M42A
MEM_ODT<3..0> - @m42a_lib.M42A
MEM_ODT<1> - @m42a_lib.M42A
MEM_ODT<2> - @m42a_lib.M42A
MEM_ODT<3> - @m42a_lib.M42A
MEM_RCOMP - @m42a_lib.M42A
MEM_RCOMP_L - @m42a_lib.M42A
MEM_VREF_A - @m42a_lib.M42A
MEM_VREF_B - @m42a_lib.M42A
MEM_VREF_NB_0 - @m42a_lib.M42A
MEM_VREF_NB_1 - @m42a_lib.M42A
MIC_HI - @m42a_lib.M42A
MIC_HI_CONN - @m42a_lib.M42A
MIC_HI_F - @m42a_lib.M42A
MIC_IN - @m42a_lib.M42A
MIC_LO - @m42a_lib.M42A
MIC_LO_CONN - @m42a_lib.M42A
MIC_LO_F - @m42a_lib.M42A
MIC_SHIELD - @m42a_lib.M42A
MIC_SHIELD_F - @m42a_lib.M42A
MIC_SHLD_CONN - @m42a_lib.M42A
MM1573DN_NR - @m42a_lib.M42A
NB_BSEL<0> - @m42a_lib.M42A
NB_BSEL<1> - @m42a_lib.M42A
NB_BSEL<2> - @m42a_lib.M42A
NB_CFG<3> - @m42a_lib.M42A
TP_NB_CFG3 - @m42a_lib.M42A
NB_CFG<4> - @m42a_lib.M42A
TP_NB_CFG4 - @m42a_lib.M42A
NB_CFG<5> - @m42a_lib.M42A
NB_CFG<6> - @m42a_lib.M42A
TP_NB_CFG6 - @m42a_lib.M42A
NB_CFG<7> - @m42a_lib.M42A
NB_CFG<8> - @m42a_lib.M42A
TP_NB_CFG8 - @m42a_lib.M42A
NB_CFG<9> - @m42a_lib.M42A

30B6
30B6
30B5
30B5
30B5
30B5
30B5
30B5
30B5
30B5
30B5
30B5
30B5
30A5
30A5
30A5

30A6

NB_CFG<4>
NB_CFG<5>
NB_CFG<6>
NB_CFG<7>
NB_CFG<8>
NB_CFG<9>

15C4 29C6
15C4 29C6
15C4 29C4
15C4 29C6
15C4 29C4
15C4 29C6
15C4 29C4
15C4 29C4
15C4 29C4
15C4 29C4
15C4 29C6
15C4 29C4
15C4 29C6
15C4 29C6
15C4 29C6
15C4 29A6
15C4 29A4
15B4 29A6
15B4 29A4
15B4 29A4
15B4 29A6
15B4 29A6
15B4 29A4
15B4 29A4
15B4 29A6
15B4 29A4
15B4 29A6
15B4 29A6
15B4 29A6
15B4 29A4
15B4 29A4
15B4 29B4
15B4 29A6
15B4 29B6
15B4 29A4
15B4 29A6
15B4 29B4
15B4 29A4
15B4 29B6
15B4 29B4
15B4 29B6
15B4 29B6
15B4 29B4
15A4 29B6
15A4 29B4
15A4 29B6
15A4 29B4
15C2 29D6
15C2 29D6
15C2 29C6
15C2 29C4
15C2 29A6
15C2 29A4
15C2 29B4
15C2 29B6
15C2 29D6
15C2 29D6
15C2 29C6
15C2 29C4
15C2 29A6
15C2 29A4
15C2 29A4
15C2 29B6
15B2 29B4 30A6
15B2 29B6 30A6
14C4 28C6
30D6
14C4 28C4
14C4 29C6
14C4 29C4
14D4 28D4
14D4 28A4
14D4 29A4
14D4 29D4
14D4 28D4
14D4 28A4
14D4 29A4
14D4 29D4
14C4 28B4
30D6
14C4 28B6
14C4 29B4
14C4 29B6
61C2
61C3
61C3
61C2
61C2
14C4 28B4
30D6
14C4 28B6
14C4 29B4
14C4 29B6
14C4
14C4
28D1 28D7
29D1 29D7
14C2 19C7
14C2 19C6
56B3 57A8
56B1 56D3
56B2
57A7
56B3 57A8
56B1 56D3
56B2
56B3 57A8
56B2
56B1 56D3
19C3
14C6 33C7
14C6 33B7
14C6 33B7
6D4 14C6
6D3
6D4 14C6
6D3
14C6 20C7
6D4 14C6
6D3
14C6 20C7
6D4 14C6
6D3
14C6 20B7

y
r

a
n
i

m
il

e
r

MEM_A_A<15>

58A6 58C6
5D7 58A4 58B7
58A4 58B6
58A4 58C7
58A8 58C6
58A6 58C6
58A4 58B7
58B7
48C5 58A4 58B6
58B4
58A8
58A6
58C7
58A4 58B5
58A4 58C6
58A8
58A6
58A4 58B7
58C7
45D8 58C7
22A7 26C3
22A7 26C3
22A7 26C3
22A7 26C3 38A5
5C2 23C8 45C8 47C5
6D8 67C2
5B1 67D2
5B1 67D2
67D6
67D6
35C6 41C6
41C5
45B8 48A8
48A7
48A6
11B3
11B3
29A4
45C2
67B7
67B6
5D2 21D4 45D8 47C6
5D2 21D4 45D8 47C6
5C2 21D4 45D8 47C5
5C2 21D4 45D8 47C5
5C2 21C5 45C8 47C6
13D5 67B2
13C5 67B2
13C5 67B2
13C5 67B2
13C5 67B2
13C5 67B2
13C5 67B2
13C5 67B2
13D5 67C6
13D5 67D7
6D6 13C5
5A7 6D5
6D6 13C5
5A7 6D5
6D6 13C5
5A7 6D5
6D6 13C5
5A7 6D5
6D6 13C5
5A7 6D5
6D6 13C5
6D5
6D6 13C5
5A7 6D5
6D6 13C5
5A7 6D5
13D5 67A7
13D5 67A7
13D5 67B6
13D5 67B6
13D5 67A6
13D5 67B7
55B6
55C6
55A6
57B1
57B2
57B2
31B5
31C4
15C5 28B4
30C6
15C5 28B6
15C5 28B4
15B5 28B6
15B5 28B4
15B5 28B6
15B5 28C4
15B5 28C4
15B5 28C6
15B5 28C6
15B5 28B6
15B5 28C4
15B5 28C6
15B5 28B4
6A4 28C4
6A3
6A4 28C4
6A3
15D5 28B6
30C6
15D5 28B4
15D5 28C6
15D5 28B6 30B6
15D5 28D4
15D5 28D4
15D5 28C6
15C5 28C4
15C5 28B4
15C5 28B6
15C5 28A6
15C5 28A4
15D7 28D4
15D7 28D4
15D7 28D6
15D7 28D6
15D7 28D4
15D7 28D4

101

8
NB_CFG<10>
NB_CFG<11>
NB_CFG<12>
NB_CFG<13>
NB_CFG<14>
NB_CFG<15>
NB_CFG<16>
NB_CFG<17>

NB_CFG<18>
NB_CFG<19>
NB_CFG<20>
NB_CLK100M_GCLKIN_N
NB_CLK100M_GCLKIN_P
NB_CLK_DREFCLKIN_N
NB_CLK_DREFCLKIN_P
NB_CLK_DREFSSCLKIN_N
NB_CLK_DREFSSCLKIN_P
NB_FSB_VREF
NB_FSB_XRCOMP
NB_FSB_XSCOMP
NB_FSB_XSWING
NB_FSB_YRCOMP
NB_FSB_YSCOMP
NB_FSB_YSWING
NB_ISENSE
NB_ISENSE_R1_N
NB_ISENSE_R1_P
NB_ISENSE_R2
NB_ISENSE_VCC
NB_RIGHT_DOWN_SCREW

NB_RST_IN_L_R
NB_SB_SYNC_L
NB_TV_DCONSEL0
NB_TV_DCONSEL1
NB_VCCSM_LF1
NB_VCCSM_LF2
NB_VCCSM_LF4
NB_VCCSM_LF5
NB_VTTLF_CAP1
NB_VTTLF_CAP2
NB_VTTLF_CAP3
ODD_PWR_EN_SLOW_STAR
T
ODD_PWR_EN_SLOW_STAR
T_L
ODD_PWR_EN_SLOW_STAR
T_L_R
ONEWIRE_DCIN_DIV
ONEWIRE_EN
ONEWIRE_ESD
ONEWIRE_OV
ONEWIRE_PU_EN
ONEWIRE_PU_EN_L
ONEWIRE_PWR_EN_L
ONEWIRE_PWR_EN_L_DIV
P0V52_SMC_LSREF
P1V8S0_EN_L_RC
P3V3S0_EN_RC
P3V3S3_EN_L_RC
P3V42G3H5_BOOST
P3V42G3H_FB
P5VS0_EN_RC
P5VS3_EN_L_RC
PATA_PWR_EN_L
PBUS_S0_SMC_VSENSE
PBUS_SMC_VSENSE_EN
PBUS_SMC_VSENSE_EN_L
PCIE_A_D2R_C_N
PCIE_A_D2R_C_P
PCIE_A_D2R_N
PCIE_A_D2R_P
PCIE_A_R2D_C_N
PCIE_A_R2D_C_P
PCIE_A_R2D_N
PCIE_A_R2D_P
PCIE_B_D2R_N
PCIE_B_D2R_P
PCIE_B_R2D_C_N
PCIE_B_R2D_C_P
PCIE_B_R2D_N
PCIE_B_R2D_P
PCIE_C_D2R_N
PCIE_C_D2R_P
PCIE_C_R2D_C_N
PCIE_C_R2D_C_P
PCIE_D_D2R_N
PCIE_D_D2R_P
PCIE_D_R2D_C_N

PCIE_D_R2D_C_P
PCIE_E_D2R_N
PCIE_E_D2R_P
PCIE_E_R2D_C_N
PCIE_E_R2D_C_P
PCIE_F_D2R_N
PCIE_F_D2R_P
PCIE_F_R2D_C_N

7
NB_CFG<10> - @m42a_lib.M42A
TP_NB_CFG10 - @m42a_lib.M42A
NB_CFG<11> - @m42a_lib.M42A
TP_NB_CFG11 - @m42a_lib.M42A
NB_CFG<12> - @m42a_lib.M42A
TP_NB_CFG12 - @m42a_lib.M42A
NB_CFG<13> - @m42a_lib.M42A
TP_NB_CFG13 - @m42a_lib.M42A
NB_CFG<14> - @m42a_lib.M42A
TP_NB_CFG14 - @m42a_lib.M42A
NB_CFG<15> - @m42a_lib.M42A
TP_NB_CFG15 - @m42a_lib.M42A
NB_CFG<16> - @m42a_lib.M42A
NB_CFG<17> - @m42a_lib.M42A
TP_NB_CFG17 - @m42a_lib.M42A
NB_CFG<18> - @m42a_lib.M42A
NB_CFG<19> - @m42a_lib.M42A
NB_CFG<20> - @m42a_lib.M42A
NB_CLK100M_GCLKIN_N @m42a_lib.M42A
NB_CLK100M_GCLKIN_P @m42a_lib.M42A
NB_CLK_DREFCLKIN_N - @m42a_lib.M42A
NB_CLK_DREFCLKIN_P - @m42a_lib.M42A
NB_CLK_DREFSSCLKIN_N @m42a_lib.M42A
NB_CLK_DREFSSCLKIN_P @m42a_lib.M42A
NB_FSB_VREF - @m42a_lib.M42A
NB_FSB_XRCOMP - @m42a_lib.M42A
NB_FSB_XSCOMP - @m42a_lib.M42A
NB_FSB_XSWING - @m42a_lib.M42A
NB_FSB_YRCOMP - @m42a_lib.M42A
NB_FSB_YSCOMP - @m42a_lib.M42A
NB_FSB_YSWING - @m42a_lib.M42A
NB_ISENSE - @m42a_lib.M42A
NB_ISENSE_R1_N - @m42a_lib.M42A
NB_ISENSE_R1_P - @m42a_lib.M42A
NB_ISENSE_R2 - @m42a_lib.M42A
NB_ISENSE_VCC - @m42a_lib.M42A
NB_RIGHT_DOWN_SCREW @m42a_lib.M42A
NB_RST_IN_L_R - @m42a_lib.M42A
NB_SB_SYNC_L - @m42a_lib.M42A
NB_TV_DCONSEL0 - @m42a_lib.M42A
NB_TV_DCONSEL1 - @m42a_lib.M42A
NB_VCCSM_LF1 - @m42a_lib.M42A
NB_VCCSM_LF2 - @m42a_lib.M42A
NB_VCCSM_LF4 - @m42a_lib.M42A
NB_VCCSM_LF5 - @m42a_lib.M42A
NB_VTTLF_CAP1 - @m42a_lib.M42A
NB_VTTLF_CAP2 - @m42a_lib.M42A
NB_VTTLF_CAP3 - @m42a_lib.M42A
ODD_PWR_EN_SLOW_START @m42a_lib.M42A
ODD_PWR_EN_SLOW_START_L @m42a_lib.M42A
ODD_PWR_EN_SLOW_START_L_R @m42a_lib.M42A
ONEWIRE_DCIN_DIV - @m42a_lib.M42A
ONEWIRE_EN - @m42a_lib.M42A
ONEWIRE_ESD - @m42a_lib.M42A
ONEWIRE_OV - @m42a_lib.M42A
ONEWIRE_PU_EN - @m42a_lib.M42A
ONEWIRE_PU_EN_L - @m42a_lib.M42A
ONEWIRE_PWR_EN_L - @m42a_lib.M42A
ONEWIRE_PWR_EN_L_DIV @m42a_lib.M42A
P0V52_SMC_LSREF - @m42a_lib.M42A
P1V8S0_EN_L_RC - @m42a_lib.M42A
P3V3S0_EN_RC - @m42a_lib.M42A
P3V3S3_EN_L_RC - @m42a_lib.M42A
P3V42G3H5_BOOST - @m42a_lib.M42A
P3V42G3H_FB - @m42a_lib.M42A
P5VS0_EN_RC - @m42a_lib.M42A
P5VS3_EN_L_RC - @m42a_lib.M42A
PATA_PWR_EN_L - @m42a_lib.M42A
PBUS_S0_SMC_VSENSE - @m42a_lib.M42A
PBUS_SMC_VSENSE_EN - @m42a_lib.M42A
PBUS_SMC_VSENSE_EN_L @m42a_lib.M42A
PCIE_A_D2R_C_N - @m42a_lib.M42A
PCIE_A_D2R_C_P - @m42a_lib.M42A
PCIE_A_D2R_N - @m42a_lib.M42A
PCIE_A_D2R_P - @m42a_lib.M42A
PCIE_A_R2D_C_N - @m42a_lib.M42A
PCIE_A_R2D_C_P - @m42a_lib.M42A
PCIE_A_R2D_N - @m42a_lib.M42A
PCIE_A_R2D_P - @m42a_lib.M42A
PCIE_B_D2R_N - @m42a_lib.M42A
PCIE_B_D2R_P - @m42a_lib.M42A
PCIE_B_R2D_C_N - @m42a_lib.M42A
PCIE_B_R2D_C_P - @m42a_lib.M42A
PCIE_B_R2D_N - @m42a_lib.M42A
PCIE_B_R2D_P - @m42a_lib.M42A
PCIE_C_D2R_N - @m42a_lib.M42A
PCIE_C_D2R_N_SPN - @m42a_lib.M42A
PCIE_C_D2R_P - @m42a_lib.M42A
PCIE_C_D2R_P_SPN - @m42a_lib.M42A
PCIE_C_R2D_C_N - @m42a_lib.M42A
PCIE_C_R2D_C_N_SPN - @m42a_lib.M42A
PCIE_C_R2D_C_P - @m42a_lib.M42A
PCIE_C_R2D_C_P_SPN - @m42a_lib.M42A
PCIE_D_D2R_N - @m42a_lib.M42A
PCIE_D_D2R_N_SPN - @m42a_lib.M42A
PCIE_D_D2R_P - @m42a_lib.M42A
PCIE_D_D2R_P_SPN - @m42a_lib.M42A
PCIE_D_R2D_C_N - @m42a_lib.M42A
PCIE_D_R2D_C_N_SPN - @m42a_lib.M42A
PCIE_D_R2D_C_P - @m42a_lib.M42A
PCIE_D_R2D_C_P_SPN - @m42a_lib.M42A
PCIE_E_D2R_N - @m42a_lib.M42A
PCIE_E_D2R_N_SPN - @m42a_lib.M42A
PCIE_E_D2R_P - @m42a_lib.M42A
PCIE_E_D2R_P_SPN - @m42a_lib.M42A
PCIE_E_R2D_C_N - @m42a_lib.M42A
PCIE_E_R2D_C_N_SPN - @m42a_lib.M42A
PCIE_E_R2D_C_P - @m42a_lib.M42A
PCIE_E_R2D_C_P_SPN - @m42a_lib.M42A
PCIE_F_D2R_N - @m42a_lib.M42A
PCIE_F_D2R_N_SPN - @m42a_lib.M42A
PCIE_F_D2R_P - @m42a_lib.M42A
PCIE_F_D2R_P_SPN - @m42a_lib.M42A
PCIE_F_R2D_C_N - @m42a_lib.M42A

6D4 14C6
6D3
6D4 14C6
6D3
6D4 14C6
6D3
6D4 14C6
6D3
6D4 14C6
6D3
6D4 14C6
6D3
14C6 20C5
6D4 14C6
6D3
14C6 20B5
14C6 20B5
14B6 20A5
14C4 33B2 33C4
14C4 33C2 33C4
14C4 33B3 33C2
14C4 33B3 33C2
14C4 33A4 33C2
14B4 33A3 33C2
12C4
12A6
12A6
12A6
12A6
12A6
12A6
62A6
62A7
62A7
62A6
62A6
6A8
14B6
14B6 22A6
14D6
14C6
16B4
16B4
16B8
16B8
17A4
17A4
17B4
34C7
34C6
34C5
65C5
65C7
65C5
65C6
65B7
65C8
65C7
65C6

PCIE_F_R2D_C_P
PCIE_WAKE_L
PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>
PCI_CLK_FW
PCI_CLK_PORT80_LPC
PCI_CLK_SB
PCI_CLK_SMC
PCI_CLK_TPM
PCI_C_BE_L<0>
PCI_C_BE_L<1>
PCI_C_BE_L<2>
PCI_C_BE_L<3>
PCI_DEVSEL_L
PCI_FRAME_L
PCI_GNT3_L
PCI_IRDY_L
PCI_LOCK_L
PCI_PAR
PCI_PERR_L
PCI_PME_FW_L
PCI_REQ0_L
PCI_REQ1_L
PCI_REQ2_L
PCI_REQ3_L
PCI_RST_L
PCI_SERR_L
PCI_STOP_L
PCI_TRDY_L
PEG_COMP
PEG_D2R_N<0>
PEG_D2R_N<1>
PEG_D2R_N<2>
PEG_D2R_N<3>

46D3
63A5
63B5
63C5
63D2
5D7 63D2
63C5
63D5
23B3 23C3
48C6
48C8
48C7

PEG_D2R_N<4>
PEG_D2R_N<5>
PEG_D2R_N<6>
PEG_D2R_N<7>
PEG_D2R_N<8>
PEG_D2R_N<9>

36D6
36D6
22D4 36D5
22D4 36D5
22D4 36C5
22D4 36C5
36C6
36C6
22D4 43C7
22D4 43C7
22D4 43B7
22D4 43B7
43B6
43B6
6C4 22D4
6C3
6C4 22D4
6C3
6C4 22D4
6C3
6C4 22D4
6C3
6C4 22D4
6C3
6C4 22D4
6C3
6C4 22D4
6C3
6C4 22D4
6C3
6C4 22C4
6C3
6C4 22C4
6C3
6C4 22C4
6C3
6C4 22C4
6C3
6C4 22C4
6C3
6C4 22C4
6C3
6C4 22C4

PEG_D2R_N<10>
PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>

PCIE_F_R2D_C_N_SPN - @m42a_lib.M42A
PCIE_F_R2D_C_P - @m42a_lib.M42A
PCIE_F_R2D_C_P_SPN - @m42a_lib.M42A
PCIE_WAKE_L - @m42a_lib.M42A
PCI_AD<0> - @m42a_lib.M42A
PCI_AD<1> - @m42a_lib.M42A
PCI_AD<2> - @m42a_lib.M42A
PCI_AD<3> - @m42a_lib.M42A
PCI_AD<4> - @m42a_lib.M42A
PCI_AD<5> - @m42a_lib.M42A
PCI_AD<6> - @m42a_lib.M42A
PCI_AD<7> - @m42a_lib.M42A
PCI_AD<8> - @m42a_lib.M42A
PCI_AD<9> - @m42a_lib.M42A
PCI_AD<10> - @m42a_lib.M42A
PCI_AD<11> - @m42a_lib.M42A
PCI_AD<12> - @m42a_lib.M42A
PCI_AD<13> - @m42a_lib.M42A
PCI_AD<14> - @m42a_lib.M42A
PCI_AD<15> - @m42a_lib.M42A
PCI_AD<16> - @m42a_lib.M42A
PCI_AD<17> - @m42a_lib.M42A
PCI_AD<18> - @m42a_lib.M42A
PCI_AD<19> - @m42a_lib.M42A
PCI_AD<20> - @m42a_lib.M42A
PCI_AD<21> - @m42a_lib.M42A
PCI_AD<22> - @m42a_lib.M42A
PCI_AD<23> - @m42a_lib.M42A
PCI_AD<24> - @m42a_lib.M42A
PCI_AD<25> - @m42a_lib.M42A
PCI_AD<26> - @m42a_lib.M42A
PCI_AD<27> - @m42a_lib.M42A
PCI_AD<28> - @m42a_lib.M42A
PCI_AD<29> - @m42a_lib.M42A
PCI_AD<30> - @m42a_lib.M42A
PCI_AD<31> - @m42a_lib.M42A
PCI_CLK_FW - @m42a_lib.M42A
PCI_CLK_PORT80_LPC - @m42a_lib.M42A
PCI_CLK_SB - @m42a_lib.M42A
PCI_CLK_SMC - @m42a_lib.M42A
PCI_CLK_TPM - @m42a_lib.M42A
PCI_C_BE_L<0> - @m42a_lib.M42A
PCI_C_BE_L<1> - @m42a_lib.M42A
PCI_C_BE_L<2> - @m42a_lib.M42A
PCI_C_BE_L<3> - @m42a_lib.M42A
PCI_DEVSEL_L - @m42a_lib.M42A
PCI_FRAME_L - @m42a_lib.M42A
PCI_GNT3_L - @m42a_lib.M42A
PCI_IRDY_L - @m42a_lib.M42A
PCI_LOCK_L - @m42a_lib.M42A
PCI_PAR - @m42a_lib.M42A
PCI_PERR_L - @m42a_lib.M42A
PCI_PME_FW_L - @m42a_lib.M42A
PCI_REQ0_L - @m42a_lib.M42A
PCI_REQ1_L - @m42a_lib.M42A
PCI_REQ2_L - @m42a_lib.M42A
PCI_REQ3_L - @m42a_lib.M42A
PCI_RST_L - @m42a_lib.M42A
PCI_SERR_L - @m42a_lib.M42A
PCI_STOP_L - @m42a_lib.M42A
PCI_TRDY_L - @m42a_lib.M42A
PEG_COMP - @m42a_lib.M42A
PEG_D2R_N<0> - @m42a_lib.M42A
PEG_D2R_N0_SPN - @m42a_lib.M42A
PEG_D2R_N<1> - @m42a_lib.M42A
PEG_D2R_N<2> - @m42a_lib.M42A
PEG_D2R_N2_SPN - @m42a_lib.M42A
PEG_D2R_N<3> - @m42a_lib.M42A
PEG_D2R_N3_SPN - @m42a_lib.M42A
PEG_D2R_N<4> - @m42a_lib.M42A
PEG_D2R_N4_SPN - @m42a_lib.M42A
PEG_D2R_N<5> - @m42a_lib.M42A
PEG_D2R_N5_SPN - @m42a_lib.M42A
PEG_D2R_N<6> - @m42a_lib.M42A
PEG_D2R_N6_SPN - @m42a_lib.M42A
PEG_D2R_N<7> - @m42a_lib.M42A
PEG_D2R_N7_SPN - @m42a_lib.M42A
PEG_D2R_N<8> - @m42a_lib.M42A
PEG_D2R_N8_SPN - @m42a_lib.M42A
PEG_D2R_N<9> - @m42a_lib.M42A
PEG_D2R_N9_SPN - @m42a_lib.M42A
PEG_D2R_N<10> - @m42a_lib.M42A
PEG_D2R_N10_SPN - @m42a_lib.M42A
PEG_D2R_N<11> - @m42a_lib.M42A
PEG_D2R_N11_SPN - @m42a_lib.M42A
PEG_D2R_N<12> - @m42a_lib.M42A
PEG_D2R_N12_SPN - @m42a_lib.M42A
PEG_D2R_N<13> - @m42a_lib.M42A
PEG_D2R_N13_SPN - @m42a_lib.M42A
PEG_D2R_N<14> - @m42a_lib.M42A
PEG_D2R_N14_SPN - @m42a_lib.M42A
PEG_D2R_N<15> - @m42a_lib.M42A
PEG_D2R_N15_SPN - @m42a_lib.M42A
PEG_D2R_P<0> - @m42a_lib.M42A
PEG_D2R_P0_SPN - @m42a_lib.M42A
PEG_D2R_P<1> - @m42a_lib.M42A
PEG_D2R_P<2> - @m42a_lib.M42A
PEG_D2R_P2_SPN - @m42a_lib.M42A
PEG_D2R_P<3> - @m42a_lib.M42A
PEG_D2R_P3_SPN - @m42a_lib.M42A
PEG_D2R_P<4> - @m42a_lib.M42A
PEG_D2R_P4_SPN - @m42a_lib.M42A
PEG_D2R_P<5> - @m42a_lib.M42A
PEG_D2R_P5_SPN - @m42a_lib.M42A
PEG_D2R_P<6> - @m42a_lib.M42A
PEG_D2R_P6_SPN - @m42a_lib.M42A
PEG_D2R_P<7> - @m42a_lib.M42A
PEG_D2R_P7_SPN - @m42a_lib.M42A
PEG_D2R_P<8> - @m42a_lib.M42A
PEG_D2R_P8_SPN - @m42a_lib.M42A
PEG_D2R_P<9> - @m42a_lib.M42A
PEG_D2R_P9_SPN - @m42a_lib.M42A
PEG_D2R_P<10> - @m42a_lib.M42A
PEG_D2R_P10_SPN - @m42a_lib.M42A
PEG_D2R_P<11> - @m42a_lib.M42A
PEG_D2R_P11_SPN - @m42a_lib.M42A
PEG_D2R_P<12> - @m42a_lib.M42A
PEG_D2R_P12_SPN - @m42a_lib.M42A
PEG_D2R_P<13> - @m42a_lib.M42A
PEG_D2R_P13_SPN - @m42a_lib.M42A
PEG_D2R_P<14> - @m42a_lib.M42A
PEG_D2R_P14_SPN - @m42a_lib.M42A
PEG_D2R_P<15> - @m42a_lib.M42A
PEG_D2R_P15_SPN - @m42a_lib.M42A

PEG_D2R_N<15>
PEG_D2R_P<0>
PEG_D2R_P<1>
PEG_D2R_P<2>
PEG_D2R_P<3>
PEG_D2R_P<4>
PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_P<7>
PEG_D2R_P<8>
PEG_D2R_P<9>

PEG_D2R_P<10>
PEG_D2R_P<11>
PEG_D2R_P<12>
PEG_D2R_P<13>
PEG_D2R_P<14>
PEG_D2R_P<15>

PEG_R2D_C_N<0>
PEG_R2D_C_N<1>
PEG_R2D_C_N<2>
PEG_R2D_C_N<3>
PEG_R2D_C_N<4>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>
PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>
PEG_R2D_C_P<0>
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
PEG_R2D_C_P<3>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>
PEG_R2D_C_P<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>
PLT_RST_BUF_L
PLT_RST_GATED_L
PLT_RST_L

PEG_R2D_C_N<0> - @m42a_lib.M42A
PEG_R2D_C_N<1> - @m42a_lib.M42A
PEG_R2D_C_N<2> - @m42a_lib.M42A
PEG_R2D_C_N<3> - @m42a_lib.M42A
PEG_R2D_C_N<4> - @m42a_lib.M42A
PEG_R2D_C_N4_SPN - @m42a_lib.M42A
PEG_R2D_C_N<5> - @m42a_lib.M42A
PEG_R2D_C_N5_SPN - @m42a_lib.M42A
PEG_R2D_C_N<6> - @m42a_lib.M42A
PEG_R2D_C_N6_SPN - @m42a_lib.M42A
PEG_R2D_C_N<7> - @m42a_lib.M42A
PEG_R2D_C_N7_SPN - @m42a_lib.M42A
PEG_R2D_C_N<8> - @m42a_lib.M42A
PEG_R2D_C_N8_SPN - @m42a_lib.M42A
PEG_R2D_C_N<9> - @m42a_lib.M42A
PEG_R2D_C_N9_SPN - @m42a_lib.M42A
PEG_R2D_C_N<10> - @m42a_lib.M42A
PEG_R2D_C_N10_SPN - @m42a_lib.M42A
PEG_R2D_C_N<11> - @m42a_lib.M42A
PEG_R2D_C_N11_SPN - @m42a_lib.M42A
PEG_R2D_C_N<12> - @m42a_lib.M42A
PEG_R2D_C_N12_SPN - @m42a_lib.M42A
PEG_R2D_C_N<13> - @m42a_lib.M42A
PEG_R2D_C_N13_SPN - @m42a_lib.M42A
PEG_R2D_C_N<14> - @m42a_lib.M42A
PEG_R2D_C_N14_SPN - @m42a_lib.M42A
PEG_R2D_C_N<15> - @m42a_lib.M42A
PEG_R2D_C_N15_SPN - @m42a_lib.M42A
PEG_R2D_C_P<0> - @m42a_lib.M42A
PEG_R2D_C_P<1> - @m42a_lib.M42A
PEG_R2D_C_P<2> - @m42a_lib.M42A
PEG_R2D_C_P<3> - @m42a_lib.M42A
PEG_R2D_C_P<4> - @m42a_lib.M42A
PEG_R2D_C_P4_SPN - @m42a_lib.M42A
PEG_R2D_C_P<5> - @m42a_lib.M42A
PEG_R2D_C_P5_SPN - @m42a_lib.M42A
PEG_R2D_C_P<6> - @m42a_lib.M42A
PEG_R2D_C_P6_SPN - @m42a_lib.M42A
PEG_R2D_C_P<7> - @m42a_lib.M42A
PEG_R2D_C_P7_SPN - @m42a_lib.M42A
PEG_R2D_C_P<8> - @m42a_lib.M42A
PEG_R2D_C_P8_SPN - @m42a_lib.M42A
PEG_R2D_C_P<9> - @m42a_lib.M42A
PEG_R2D_C_P9_SPN - @m42a_lib.M42A
PEG_R2D_C_P<10> - @m42a_lib.M42A
PEG_R2D_C_P10_SPN - @m42a_lib.M42A
PEG_R2D_C_P<11> - @m42a_lib.M42A
PEG_R2D_C_P11_SPN - @m42a_lib.M42A
PEG_R2D_C_P<12> - @m42a_lib.M42A
PEG_R2D_C_P12_SPN - @m42a_lib.M42A
PEG_R2D_C_P<13> - @m42a_lib.M42A
PEG_R2D_C_P13_SPN - @m42a_lib.M42A
PEG_R2D_C_P<14> - @m42a_lib.M42A
PEG_R2D_C_P14_SPN - @m42a_lib.M42A
PEG_R2D_C_P<15> - @m42a_lib.M42A
PEG_R2D_C_P15_SPN - @m42a_lib.M42A
PLT_RST_BUF_L - @m42a_lib.M42A
PLT_RST_GATED_L - @m42a_lib.M42A
PLT_RST_L - @m42a_lib.M42A
NB_RST_IN_L - @m42a_lib.M42A
PM_BATLOW_L - @m42a_lib.M42A
PM_BMBUSY_L - @m42a_lib.M42A
PM_CLKRUN_L - @m42a_lib.M42A

13C3 68C6
13C3 68C6
13C3 68B6
13B3 68B6
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
13B3 68C6
13B3 68C6
13B3 68B6
13B3 68B6
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13B3
6B5
6B6 13A3
6B5
6B6 13A3
6B5
6B6 13A3
6B5
6B6 13A3
6B5
26B3
26A3
22A6 26C3
14B7 26C1
23C1 45B8
14B6 23C5
5C2 23C8 38A5 45D5 47C6
53C6
PM_DPRSLPVR - @m42a_lib.M42A
14B7 23C3 58D8
PM_DPRSLPVR_R - @m42a_lib.M42A
14B6
PM_EXTTS_L<0> - @m42a_lib.M42A
6B2 14B7 45B8
DIMM_OVERTEMP_L - @m42a_lib.M42A
6B1 28C4 29C4
PM_LAN_ENABLE - @m42a_lib.M42A
23C3 45D8
PM_PWRBTN_L - @m42a_lib.M42A
23C3 45D8
PM_RI_L - @m42a_lib.M42A
23D5
PM_RSMRST_L - @m42a_lib.M42A
23C1 45D8
PM_SB_PWROK - @m42a_lib.M42A
23C3 26A6
PM_SLP_S3 - @m42a_lib.M42A
48C8 63B7
PM_SLP_S3BATT - @m42a_lib.M42A
60C7
PM_SLP_S3_L - @m42a_lib.M42A
23C3 45C5 63A7 63A7 63B8
PM_SLP_S3_LS12V6 - @m42a_lib.M42A
63B7
PM_SLP_S4_L - @m42a_lib.M42A
23C3 45C5 60C8 61B8 63D6
PM_SLP_S5_L - @m42a_lib.M42A
23C3 45C5 46D3
PM_STPCPU_L - @m42a_lib.M42A
23C8 32C4
PM_STPPCI_L - @m42a_lib.M42A
23C8 32C4
PM_SUS_STAT_L - @m42a_lib.M42A
5C2 23C5 45D5 46D3 47C5
53C6
PM_SYSRST_L - @m42a_lib.M42A
23C5 26C5 45C8
XDP_DBRESET_L_R - @m42a_lib.M42A
26C6
PM_THRMTRIP_L - @m42a_lib.M42A
7C6 14B6 21C2 46B3
PM_THRM_L - @m42a_lib.M42A
23C8 45B8
PP0V9_S0 - @m42a_lib.M42A
5A2 64D7
=PP0V9_S0_MEM_TERM - @m42a_lib.M42A 30D4 64D6
=PP0V9_S0_MEM_REG - @m42a_lib.M42A 31B3 63B2 64D8
=PP0V9_S0_MEM_TERM - @m42a_lib.M42A 30D4 64D6
=PP0V9_S0_MEM_REG - @m42a_lib.M42A 31B3 63B2 64D8
PP1V2_S0 - @m42a_lib.M42A
63B4
PP1V2_S3 - @m42a_lib.M42A
5A2 64C4
=PP1V2_S3_REG - @m42a_lib.M42A
60B2 63B5 64C6
=PP1V2_S3_ENET - @m42a_lib.M42A
36A8 36D7 64C3
=PP1V2_S3_REG - @m42a_lib.M42A
60B2 63B5 64C6
=PP1V2_S3_ENET - @m42a_lib.M42A
36A8 36D7 64C3
PP1V5_S0_DPLL - @m42a_lib.M42A
19D5
PP1V5_S0_NB_3GPLL_F 19A4
@m42a_lib.M42A
PP1V5_S0_NB_QTVDAC - @m42a_lib.M42A 19A7
PP1V5_S0_NB_VCC3G - @m42a_lib.M42A 17D6 19B2
PP1V5_S0_NB_VCCA_3GPLL 17D6 19A2
@m42a_lib.M42A
PP1V5_S0_NB_VCCA_DPLLA 17C6 19D4
@m42a_lib.M42A
PP1V5_S0_NB_VCCA_DPLLB 17C6 19D4
@m42a_lib.M42A
PP1V5_S0_NB_VCCA_HPLL 17C6 19C4
@m42a_lib.M42A
PP1V5_S0_NB_VCCA_MPLL 17C6 19C4
@m42a_lib.M42A
PP1V5_S0_NB_VCCD_QTVDAC 17B6 19A5
@m42a_lib.M42A
PP1V5_S0_NB_VCCD_TVDAC 17C6 19A5
@m42a_lib.M42A
PP1V5_S0_REG_P - @m42a_lib.M42A
62B8
PP1V5_S0_SB_VCC1_5_B 22C1 24D5 25B6
@m42a_lib.M42A
PP1V5_S0_SB_VCCDMIPLL 24B5 25A5
@m42a_lib.M42A
PP1V5_S0_SB_VCCDMIPLL_F 25A7
@m42a_lib.M42A

PM_DPRSLPVR
PM_DPRSLPVR_R
PM_EXTTS_L<0>

PM_LAN_ENABLE
PM_PWRBTN_L
PM_RI_L
PM_RSMRST_L
PM_SB_PWROK
PM_SLP_S3
PM_SLP_S3BATT
PM_SLP_S3_L
PM_SLP_S3_LS12V6
PM_SLP_S4_L
PM_SLP_S5_L
PM_STPCPU_L
PM_STPPCI_L
PM_SUS_STAT_L
PM_SYSRST_L

PM_THRMTRIP_L
PM_THRM_L
PP0V9_S0

PP1V2_S0
PP1V2_S3

PP1V5_S0_DPLL
PP1V5_S0_NB_3GPLL_F
PP1V5_S0_NB_QTVDAC
PP1V5_S0_NB_VCC3G
PP1V5_S0_NB_VCCA_3GP
LL
PP1V5_S0_NB_VCCA_DPL
LA
PP1V5_S0_NB_VCCA_DPL
LB
PP1V5_S0_NB_VCCA_HPL
L
PP1V5_S0_NB_VCCA_MPL
L
PP1V5_S0_NB_VCCD_QTV
DAC
PP1V5_S0_NB_VCCD_TVD
AC
PP1V5_S0_REG_P
PP1V5_S0_SB_VCC1_5_B
PP1V5_S0_SB_VCCDMIPL
L
PP1V5_S0_SB_VCCDMIPL
L_F

PP1V8_S0

PP1V8_S0 - @m42a_lib.M42A
=PP1V8_S0_TMDS - @m42a_lib.M42A
=PP1V8_S0_FET - @m42a_lib.M42A
=PP1V8_S0_TMDS - @m42a_lib.M42A
=PP1V8_S0_FET - @m42a_lib.M42A
PP1V8_S0_ANALOG_SDVO PP1V8_S0_ANALOG_SDVO_F _F
@m42a_lib.M42A
PP1V8_S0_TMDS_F
PP1V8_S0_TMDS_F - @m42a_lib.M42A
PP1V8_S3
PP1V8_S3 - @m42a_lib.M42A
=PP1V8_S3_1V2S3 - @m42a_lib.M42A
=PP1V8_S3_MEM_NB_SENSE @m42a_lib.M42A
=PP1V8_S3_MEMVTT - @m42a_lib.M42A
=PP1V8_S3_P1V8S0 - @m42a_lib.M42A
=PP1V8_S3_REG - @m42a_lib.M42A
=PP1V8_S3_MEM - @m42a_lib.M42A

5B2 64C7
64B6 68D6 68D6
63B3 64B8
64B6 68D6 68D6
63B3 64B8
68C4 68D3
68B4 68D3
5A2 64C4
60B5 64C3
61C4 64C3
31C6
63A5
61B1
19C7
29B2
61B1
63A5
61C4

64C3
64C3
64C6
19C8 28B2 28D4 28D6
29D4 29D6 64C3
64C6
64C3
64C3

31C6
19C7
29B2
60B5
31C5

64C3
19C8 28B2 28D4 28D6
29D4 29D6 64C3
64C3

y
r

=PP1V8_S3_REG - @m42a_lib.M42A
=PP1V8_S3_P1V8S0 - @m42a_lib.M42A
=PP1V8_S3_MEM_NB_SENSE @m42a_lib.M42A
=PP1V8_S3_MEMVTT - @m42a_lib.M42A
=PP1V8_S3_MEM - @m42a_lib.M42A

=PP1V8_S3_1V2S3 - @m42a_lib.M42A
PP1V8_S3_MEMVTT_VDDQ PP1V8_S3_MEMVTT_VDDQ @m42a_lib.M42A
PP1V8_S3_R
PP1V8_S3_R - @m42a_lib.M42A
PP2V5_S0_NB_CRTDAC_F PP2V5_S0_NB_CRTDAC_F @m42a_lib.M42A
PP2V5_S0_NB_CRTDAC_F PP2V5_S0_NB_CRTDAC_FOLLOW OLLOW
@m42a_lib.M42A
PP2V5_S0_NB_VCCA_CRT PP2V5_S0_NB_VCCA_CRTDAC DAC
@m42a_lib.M42A
PP2V5_S3
PP2V5_S3 - @m42a_lib.M42A
=PP2V5_S3_REG - @m42a_lib.M42A
=PP2V5_S3_ENET - @m42a_lib.M42A
=PP2V5_S3_REG - @m42a_lib.M42A
=PP2V5_S3_ENET - @m42a_lib.M42A
PP2V5_S3_ENET_AVDD
PP2V5_S3_ENET_AVDD - @m42a_lib.M42A
PP2V5_S3_ENET_AVDD_F PP2V5_S3_ENET_AVDD_F @m42a_lib.M42A
PP3V3_AUDIO_CODEC
PP3V3_AUDIO_CODEC - @m42a_lib.M42A
PP3V3_AVREF_SMC
PP3V3_AVREF_SMC - @m42a_lib.M42A
PP3V3_G3C_SB_RTC_D
PP3V3_G3C_SB_RTC_D - @m42a_lib.M42A
PP3V3_S5_SB_RTC - @m42a_lib.M42A
PP3V3_LCDVDD_SW
PP3V3_LCDVDD_SW - @m42a_lib.M42A
PP3V3_LCDVDD_SW_F
PP3V3_LCDVDD_SW_F - @m42a_lib.M42A
PP3V3_S0_ANALOG_SDVO PP3V3_S0_ANALOG_SDVO_F _F
@m42a_lib.M42A
PP3V3_S0_ANALOG_TMDS PP3V3_S0_ANALOG_TMDS_F _F
@m42a_lib.M42A
PP3V3_S0_AUDIO_F
PP3V3_S0_AUDIO_F - @m42a_lib.M42A
PP3V3_S0_AUDIO_SPDIF PP3V3_S0_AUDIO_SPDIF @m42a_lib.M42A
PP3V3_S0_CK410_VDD48 PP3V3_S0_CK410_VDD48 @m42a_lib.M42A
PP3V3_S0_CK410_VDDA PP3V3_S0_CK410_VDDA @m42a_lib.M42A
PP3V3_S0_CK410_VDD_C PP3V3_S0_CK410_VDD_CPU_SRC PU_SRC
@m42a_lib.M42A
PP3V3_S0_CK410_VDD_P PP3V3_S0_CK410_VDD_PCI CI
@m42a_lib.M42A
PP3V3_S0_CK410_VDD_R PP3V3_S0_CK410_VDD_REF EF
@m42a_lib.M42A
PP3V3_S0_IMVP6_3V3
PP3V3_S0_IMVP6_3V3 - @m42a_lib.M42A
PP3V3_S0_LCD_F
PP3V3_S0_LCD_F - @m42a_lib.M42A
PP3V3_S0_NB_TVDAC
PP3V3_S0_NB_TVDAC - @m42a_lib.M42A
PP3V3_S0_NB_TVDAC_F PP3V3_S0_NB_TVDAC_F @m42a_lib.M42A
PP3V3_S0_NB_TVDAC_FO PP3V3_S0_NB_TVDAC_FOLLOW LLOW
@m42a_lib.M42A
PP3V3_S0_NB_VCCA_TVB PP3V3_S0_NB_VCCA_TVBG G
@m42a_lib.M42A
PP3V3_S0_NB_VCCA_TVD PP3V3_S0_NB_VCCA_TVDACA ACA
@m42a_lib.M42A
PP3V3_S0_NB_VCCA_TVD PP3V3_S0_NB_VCCA_TVDACB ACB
@m42a_lib.M42A
PP3V3_S0_NB_VCCA_TVD PP3V3_S0_NB_VCCA_TVDACC ACC
@m42a_lib.M42A
PP3V3_S0_PVCC1_TMDS_ PP3V3_S0_PVCC1_TMDS_F F
@m42a_lib.M42A
PP3V3_S0_PVCC2_TMDS_ PP3V3_S0_PVCC2_TMDS_F F
@m42a_lib.M42A
PP3V3_S0_TPM_3VSB
PP3V3_S0_TPM_3VSB - @m42a_lib.M42A
PP3V3_S3
PP3V3_S3 - @m42a_lib.M42A
=PP3V3_S3_PDCISENS - @m42a_lib.M42A
=PP3V3_S3_FW - @m42a_lib.M42A
=PP3V3_S3_AIRPORT_AUX @m42a_lib.M42A
=PP3V3_S3_RSTGATE - @m42a_lib.M42A
=PP3V3_S3_PCI - @m42a_lib.M42A
=PP3V3_S3_SMS - @m42a_lib.M42A
=PP3V3_S3_TPM - @m42a_lib.M42A
=PP3V3_S3_2V5S3 - @m42a_lib.M42A
=PP3V3_S3_ENET - @m42a_lib.M42A

a
n
i

m
il
PM_BATLOW_L
PM_BMBUSY_L
PM_CLKRUN_L

e
r

PEG_D2R_N<14>

6C3
6B4 22C4
6B3
23C8 36C6 43C6
22B7 38C5
22B7 38C5
22B7 38C5
22B7 38C5
22B7 38C5
22B7 38C5
22B7 38C5
22B7 38C5
22B7 38C5
22B7 38C5
22B7 38C5
22B7 38C5
22B7 38B5
22B7 38B5
22B7 38B5
22B7 38B5
22B7 38B5
22B7 38B5
22B7 38B5
22A7 38B6
22A7 38B5
22A7 38B5
22A7 38B5
22A7 38B5
22A7 38B5
22A7 38B5
22A7 38B5
22A7 38B5
22A7 38B5
22A7 38B5
22A7 38B5
22A7 38B5
33D6 38A5
5C2 33D6 47C5
22A6 33D6
33D6 45C8
33D6 53C6
22B6 38B5
22B6 38B5
22B6 38B5
22B6 38B5
22A6 26D3 38A5
22A7 26D3 38A5
22B6 38A5
22A6 26D3 38A5
22A6 26D3
22A6 38B5
22A6 26D3 38A5
22B5 38A5
22B6 26C3
22B6 26C3
22B6 26C3
22B6 26C3 38A5
22A6 38A6
22A6 26D3 38A5
22A6 26D3 38A5
22A6 26D3 38A5
13D3
6D6 13D3
6D5
13D3 68B6
6D6 13D3
6D5
6C6 13D3
6C5
6C6 13D3
6C5
6C6 13D3
6C5
6C6 13D3
6C5
6C6 13D3
6C5
6C6 13D3
6C5
6C6 13D3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
13C3 68B6
6C6 13C3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
6C6 13C3
6C5
6B6 13C3
6B5
6B6 13C3
6B5

=PP3V3_S3_BT - @m42a_lib.M42A
=PP3V3_S3_FET - @m42a_lib.M42A
=PP3V3_S3_SMBUS_SMC_RMT @m42a_lib.M42A
=PP3V3_S3_TPM - @m42a_lib.M42A
=PP3V3_S3_SMS - @m42a_lib.M42A
=PP3V3_S3_SMBUS_SMC_RMT @m42a_lib.M42A
=PP3V3_S3_RSTGATE - @m42a_lib.M42A
=PP3V3_S3_PDCISENS - @m42a_lib.M42A
=PP3V3_S3_PCI - @m42a_lib.M42A
=PP3V3_S3_FW - @m42a_lib.M42A
=PP3V3_S3_FET - @m42a_lib.M42A
=PP3V3_S3_ENET - @m42a_lib.M42A
=PP3V3_S3_BT - @m42a_lib.M42A
=PP3V3_S3_AIRPORT_AUX @m42a_lib.M42A
=PP3V3_S3_2V5S3 - @m42a_lib.M42A
PP3V3_S3_AIRPORT_AUX PP3V3_S3_AIRPORT_AUX_CONN _CONN
@m42a_lib.M42A
PP3V3_S3_BT_F
PP3V3_S3_BT_F - @m42a_lib.M42A
PP3V3_S3_FW_AVDD
PP3V3_S3_FW_AVDD - @m42a_lib.M42A
PP3V3_S3_ST_ACCEL
PP3V3_S3_ST_ACCEL - @m42a_lib.M42A
PP3V3_S5
PP3V3_S5 - @m42a_lib.M42A
=PP3V3_S5_LCD - @m42a_lib.M42A
=PP3V3_S5_FWLATEVG - @m42a_lib.M42A

61B2
19D3
19D3

17D6 19D1
5A2 64C4
60C2 64C6
36D3 64C3
60C2 64C6
36D3 64C3
36D5 37D8
37D7

54D6
45D2 46C6
26D4
21D6 24B3 25A4 26D3
67C5
67B2
68C4 68D6

68B1 68B4 68D6


57B3 57C8 57C8 57D8
56B8 56D8
32D5
32C7
32D6
32D5
32C5
58D7
67B3
19C3
19C2
19C3
17C6 19B1
17C6 19C1
17C6 19B1

17C6 19B1
68C4 68C6
68C4 68C7
53C4
5A2 64B4
61C1 64B3
38D5 64B3
43C3 64B3
26B3
38C5
46D5
46D5
60C4
36A5
36D8
44C6
63D3
27D3

64B3
64B3
52C7
53C2
60D6
36B4
64B3
64B3
64B6
64B3

64B3
64B3
64B3
36B5 36C8 36D6

46D5 53C2 64B3


46D5 52C7 64B3
27D3 64B3
26B3
61C1
38C5
38D5
63D3
36A5
36D8
44C6
43C3

64B3
64B3
64B3
64B3
64B6
36B4 36B5 36C8 36D6
64B3
64B3
64B3

60C4 60D6 64B3


43C4
44C4
38D3
52B6
5A2 64A4
64A3 67C7
39A8 64A3
102

8
=PP3V3_S5_P3V3S3 - @m42a_lib.M42A
=PP3V3_S5_P3V3S0 - @m42a_lib.M42A
=PP3V3_S5_ROM - @m42a_lib.M42A
=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA @m42a_lib.M42A
=PP3V3_S5_SB_IO - @m42a_lib.M42A
=PP3V3_S5_SB_VCCSUS3_3_USB @m42a_lib.M42A
=PP3V3_S5_SB_PM - @m42a_lib.M42A
=PP3V3_S5_SB_VCCSUS3_3 @m42a_lib.M42A
=PP3V3_S5_REG - @m42a_lib.M42A
=PP3V3_S5_SB - @m42a_lib.M42A

=PP3V3_S5_SB_USB - @m42a_lib.M42A
=PP3V3_S5_SB_VCCSUS3_3_USB @m42a_lib.M42A
=PP3V3_S5_SB_VCCSUS3_3 @m42a_lib.M42A
=PP3V3_S5_SB_USB - @m42a_lib.M42A
=PP3V3_S5_SB_PM - @m42a_lib.M42A
=PP3V3_S5_SB_IO - @m42a_lib.M42A
=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA @m42a_lib.M42A
=PP3V3_S5_SB - @m42a_lib.M42A

PP3V3_S5_FWLATEVG
PP3V3_S5_FWLATEVG_F
PP3V3_S5_REG_P
PP3V42G3H_SW
PP3V42_G3H_LIDSWITCH
_F
PP3V42_G3H_SMC_CLK_F

PP3V42_ONEWIRE
PP4V5_AUDIO_ANALOG
PP5V_INV
PP5V_INV_F
PP5V_S0_AUDIO
PP5V_S0_AUDIO_F
PP5V_S0_AUDIO_PWR
PP5V_S0_DVIPORT
PP5V_S0_DVIPORT_D
PP5V_S0_IMVP6_VDD
PP5V_S0_SB_V5REF
PP5V_S0_TMDS_FUSE
PP5V_S3

PP5V_S3_CAMERA_F
PP5V_S3_GEYSER_F
PP5V_S3_SYSLED_F
PP5V_S3_USB2_EXTA
PP5V_S3_USB2_EXTA_F
PP5V_S3_USB2_EXTB
PP5V_S3_USB2_EXTB_F
PP5V_S5

PP5V_S5_1V51V05S0_IN
TVCC
PP5V_S5_5V3V3S5_INTV
CC
PP5V_S5_REG_P
PP5V_S5_SB_V5REF_SUS
PP18V5_DCIN
PP18V5_DCIN_F
PP18V5_DCIN_ONEWIRE
PP18V5_G3H

PP18V5_S5_CHGR_SW_R
PPBUSA_G3H
PPBUSB_G3H

=PP3V3_S5_ROM - @m42a_lib.M42A
=PP3V3_S5_REG - @m42a_lib.M42A
=PP3V3_S5_P3V3S3 - @m42a_lib.M42A
=PP3V3_S5_P3V3S0 - @m42a_lib.M42A
=PP3V3_S5_LCD - @m42a_lib.M42A
=PP3V3_S5_FWLATEVG - @m42a_lib.M42A
PP3V3_S5_FWLATEVG - @m42a_lib.M42A
PP3V3_S5_FWLATEVG_F @m42a_lib.M42A
PP3V3_S5_REG_P - @m42a_lib.M42A
PP3V42G3H_SW - @m42a_lib.M42A
PP3V42_G3H_LIDSWITCH_F @m42a_lib.M42A
PP3V42_G3H_SMC_CLK_F @m42a_lib.M42A
PP3V42_ONEWIRE - @m42a_lib.M42A
PP4V5_AUDIO_ANALOG - @m42a_lib.M42A
PP5V_INV - @m42a_lib.M42A
PP5V_INV_F - @m42a_lib.M42A
PP5V_S0_AUDIO - @m42a_lib.M42A
PP5V_S0_AUDIO_F - @m42a_lib.M42A
PP5V_S0_AUDIO_PWR - @m42a_lib.M42A
PP5V_S0_DVIPORT - @m42a_lib.M42A
PP5V_S0_DVIPORT_D - @m42a_lib.M42A
PP5V_S0_IMVP6_VDD - @m42a_lib.M42A
PP5V_S0_SB_V5REF - @m42a_lib.M42A
PP5V_S0_TMDS_FUSE - @m42a_lib.M42A
PP5V_S3 - @m42a_lib.M42A
=PP5V_S3_IR - @m42a_lib.M42A
=PP5V_S3_GEYSER - @m42a_lib.M42A
=PP5V_S3_CAMERA - @m42a_lib.M42A
=PP5V_S3_FET - @m42a_lib.M42A
=PP5V_S3_SYSLED - @m42a_lib.M42A
=PP5V_S3_IR - @m42a_lib.M42A
=PP5V_S3_GEYSER - @m42a_lib.M42A
=PP5V_S3_FET - @m42a_lib.M42A
=PP5V_S3_CAMERA - @m42a_lib.M42A
PP5V_S3_CAMERA_F - @m42a_lib.M42A
PP5V_S3_GEYSER_F - @m42a_lib.M42A
PP5V_S3_SYSLED_F - @m42a_lib.M42A
PP5V_S3_USB2_EXTA - @m42a_lib.M42A
PP5V_S3_USB2_EXTA_F @m42a_lib.M42A
PP5V_S3_USB2_EXTB - @m42a_lib.M42A
PP5V_S3_USB2_EXTB_F @m42a_lib.M42A
PP5V_S5 - @m42a_lib.M42A
=PP5V_S5_1V8S3 - @m42a_lib.M42A
=PP5V_S5_PATA - @m42a_lib.M42A
=PP5V_S5_USB - @m42a_lib.M42A
=PP5V_S5_P5VS0 - @m42a_lib.M42A
=PP5V_S5_PWRCTL - @m42a_lib.M42A
=PP5V_S5_REG - @m42a_lib.M42A
=PP5V_S5_P5VS3 - @m42a_lib.M42A
=PP5V_S5_SB - @m42a_lib.M42A
=PP5V_S5_USB - @m42a_lib.M42A
=PP5V_S5_SB - @m42a_lib.M42A
=PP5V_S5_REG - @m42a_lib.M42A
=PP5V_S5_PWRCTL - @m42a_lib.M42A
=PP5V_S5_PATA - @m42a_lib.M42A
=PP5V_S5_P5VS3 - @m42a_lib.M42A
=PP5V_S5_P5VS0 - @m42a_lib.M42A
=PP5V_S5_1V8S3 - @m42a_lib.M42A
PP5V_S5_1V51V05S0_INTVCC @m42a_lib.M42A
PP5V_S5_5V3V3S5_INTVCC @m42a_lib.M42A
PP5V_S5_REG_P - @m42a_lib.M42A
PP5V_S5_SB_V5REF_SUS @m42a_lib.M42A
PP18V5_DCIN - @m42a_lib.M42A
PP18V5_DCIN_F - @m42a_lib.M42A
PP18V5_DCIN_ONEWIRE @m42a_lib.M42A
PP18V5_G3H - @m42a_lib.M42A
=PP18V5_G3H_INRUSH - @m42a_lib.M42A
=PP18V5_G3H_CHGR - @m42a_lib.M42A
=PP18V5_G3H_INRUSH - @m42a_lib.M42A
=PP18V5_G3H_CHGR - @m42a_lib.M42A
PP18V5_S5_CHGR_SW_R @m42a_lib.M42A
PPBUSA_G3H - @m42a_lib.M42A
PPBUSB_G3H - @m42a_lib.M42A
=PPBUS_S5_YUKON_CTRL @m42a_lib.M42A
=PPVIN_S5_IMVP6 - @m42a_lib.M42A
=PPVIN_S5_1V51V05S0 @m42a_lib.M42A
=PPBUSB_G3H - @m42a_lib.M42A
=PPBUS_S5_INV - @m42a_lib.M42A
=PPBUS_S5_FWPWRSW - @m42a_lib.M42A
=PPVIN_S5_5V3V3S5 - @m42a_lib.M42A
=PPVIN_S5_1V8S3 - @m42a_lib.M42A
=PPVIN_S5_IMVP6 - @m42a_lib.M42A
=PPVIN_S5_5V3V3S5 - @m42a_lib.M42A
=PPVIN_S5_1V8S3 - @m42a_lib.M42A
=PPVIN_S5_1V51V05S0 @m42a_lib.M42A

63D5
63C5
50D4
24C3

64A3
64A3
64A3
64A3

22C6 64A3
24B3 25D2 64A3
11B5 23D1 26C5 64A3
24A5 24B3 25B6 25D2 64A3
59B8
23A7
64A3
22D8
24B3

64A6
23B7 23D4 23D8 25C8
64A3
25D2 64A3

PPBUS_ALL_INV_CONN
PPBUS_S5_FWPWRSW_F
PPDCIN_G3H_R
PPFW_PORT0_VP
PPFW_PORT0_VP_F
PPFW_SWITCH
PPVBATT_G3C_RTC
PPVBATT_G3C_RTC_R
PPVBATT_G3H_PRE
PPVBATT_G3H_R
PPVBAT_G3H_CHGR_OUT

24A5 24B3 25B6 25D2 64A3


PPVBAT_G3H_CHGR_REG
22D8
11B5
22C6
24C3
23A7
64A3
50D4
59B8
63D5
63C5
64A3
39A8
39A6
39A7

64A3
23D1 26C5 64A3
64A3
64A3
23B7 23D4 23D8 25C8
64A3
64A6
64A3
64A3
67C7
64A3
39B5

59B8
63D2
65A7
46A7
65C7
54A3 54D2
67D5
5B1 67D3
5D1
55B8 55B8
5D1
68A6 69B4
68A8 69C5
58D7
24D5 25D7
69C5
5A2 64B4
41D6 64B3
40D6 64B3
64B3 67A5
63D3 64B6
35B6 46B4
41D6 64B3
40D6 64B3
63D3 64B6
64B3 67A5
67A3
40D5
35B8
42C7
42D2 42D3

57C3 57C5

55C4
69C3

64B3

42C7
42B2 42C3
5A2 64A4
61C7 64A3
34D6 64A3
42C8 64A3
63C5 64A3
63A7 63D6 64A3
59B1 64A6
63D5 64A3
25C8 64A3
42C8 64A3
25C8 64A3
59B1 64A6
63A7 63D6 64A3
34D6 64A3
63D5 64A3
63C5 64A3
61C7 64A3
62A2 62C3 62C6
59A2 59C3 59C6
59A6 59B1
24D5 25C7
65D4
65D7
65C6
5A2 64C1
64C3 65D1
64C1 66D8
64C3 65D1
64C1 66D8
66C4
5A2
5A2 64C1
60C8 64C1
48C7 58C2 58D5 58D8 64C1
62D8 64C1
64C3
64C1
39D6
59D8
61C7
48C7
59D8
61C7
62D8

66C2
67D4
64C1
63B7 64C1
64C1
58C2 58D5 58D8 64C1
63B7 64C1
64C1
64C1

PPVCORE_CPU_S0

=PPBUS_S5_YUKON_CTRL @m42a_lib.M42A
=PPBUS_S5_INV - @m42a_lib.M42A
=PPBUS_S5_FWPWRSW - @m42a_lib.M42A
=PPBUSB_G3H - @m42a_lib.M42A
=PPBUSA_G3H - @m42a_lib.M42A
PPBUS_ALL_INV_CONN - @m42a_lib.M42A
PPBUS_S5_FWPWRSW_F - @m42a_lib.M42A
PPDCIN_G3H_R - @m42a_lib.M42A
PPFW_PORT0_VP - @m42a_lib.M42A
PPFW_PORT0_VP_F - @m42a_lib.M42A
PPFW_SWITCH - @m42a_lib.M42A
PPVBATT_G3C_RTC - @m42a_lib.M42A
PPVBATT_G3C_RTC_R - @m42a_lib.M42A
PPVBATT_G3H_PRE - @m42a_lib.M42A
PPVBATT_G3H_R - @m42a_lib.M42A
PPVBAT_G3H_CHGR_OUT @m42a_lib.M42A
PPVBAT_G3H_CHGR_REG @m42a_lib.M42A
PPVCORE_CPU_S0 - @m42a_lib.M42A
=PPVCORE_S0_CPU - @m42a_lib.M42A
=PPVOUT_S0_IMVP6_REG @m42a_lib.M42A
=PPVCORE_S0_CPU - @m42a_lib.M42A

PPVDCIN_G3H_PRE
PPVDCIN_G3H_PRE - @m42a_lib.M42A
PPVIN_S5_1V51V05S0_R PPVIN_S5_1V51V05S0_R @m42a_lib.M42A
PPVIN_S5_5V3V3S5_R
PPVIN_S5_5V3V3S5_R - @m42a_lib.M42A
PPVIN_S5_IMVP6_VIN
PPVIN_S5_IMVP6_VIN - @m42a_lib.M42A
RSMRST_PWRGD
RSMRST_PWRGD - @m42a_lib.M42A
5V3V3S5_PGOOD - @m42a_lib.M42A
S0PWRGD_0V9_DIV
S0PWRGD_0V9_DIV - @m42a_lib.M42A
S0PWRGD_1V2_DIV
S0PWRGD_1V2_DIV - @m42a_lib.M42A
S0PWRGD_OK
S0PWRGD_OK - @m42a_lib.M42A
SATA_A_D2R_N
SATA_A_D2R_N - @m42a_lib.M42A
SATA_A_D2R_N_SPN - @m42a_lib.M42A
SATA_A_D2R_P
SATA_A_D2R_P - @m42a_lib.M42A
SATA_A_D2R_P_SPN - @m42a_lib.M42A
SATA_A_R2D_C_N
SATA_A_R2D_C_N - @m42a_lib.M42A
SATA_A_R2D_C_N_SPN - @m42a_lib.M42A
SATA_A_R2D_C_P
SATA_A_R2D_C_P - @m42a_lib.M42A
SATA_A_R2D_C_P_SPN - @m42a_lib.M42A
SATA_C_D2R_C_N
SATA_C_D2R_C_N - @m42a_lib.M42A
SATA_C_D2R_C_P
SATA_C_D2R_C_P - @m42a_lib.M42A
SATA_C_D2R_F_N
SATA_C_D2R_F_N - @m42a_lib.M42A
SATA_C_D2R_F_P
SATA_C_D2R_F_P - @m42a_lib.M42A
SATA_C_D2R_N
SATA_C_D2R_N - @m42a_lib.M42A
SATA_C_D2R_P
SATA_C_D2R_P - @m42a_lib.M42A
SATA_C_DET_L
SATA_C_DET_L - @m42a_lib.M42A
SATA_C_PWR_EN_L
SATA_C_PWR_EN_L - @m42a_lib.M42A
SATA_C_R2D_C_N
SATA_C_R2D_C_N - @m42a_lib.M42A
SATA_C_R2D_C_P
SATA_C_R2D_C_P - @m42a_lib.M42A
SATA_C_R2D_F_N
SATA_C_R2D_F_N - @m42a_lib.M42A
SATA_C_R2D_F_P
SATA_C_R2D_F_P - @m42a_lib.M42A
SATA_C_R2D_N
SATA_C_R2D_N - @m42a_lib.M42A
SATA_C_R2D_P
SATA_C_R2D_P - @m42a_lib.M42A
SATA_RBIAS_N
SATA_RBIAS_N - @m42a_lib.M42A
SATA_RBIAS_P - @m42a_lib.M42A
SATA_RBIAS_PN - @m42a_lib.M42A
SATA_RBIAS_P - @m42a_lib.M42A
SB_A20GATE
SB_A20GATE - @m42a_lib.M42A
SB_ACZ_BITCLK
SB_ACZ_BITCLK - @m42a_lib.M42A
SB_ACZ_RST_L
SB_ACZ_RST_L - @m42a_lib.M42A
SB_ACZ_SDATAOUT
SB_ACZ_SDATAOUT - @m42a_lib.M42A
SB_ACZ_SYNC
SB_ACZ_SYNC - @m42a_lib.M42A
SB_CLK14P3M_TIMER
SB_CLK14P3M_TIMER - @m42a_lib.M42A
SB_CLK48M_USBCTLR
SB_CLK48M_USBCTLR - @m42a_lib.M42A
SB_CLK100M_DMI_N
SB_CLK100M_DMI_N - @m42a_lib.M42A
SB_CLK100M_DMI_P
SB_CLK100M_DMI_P - @m42a_lib.M42A
SB_CLK100M_SATA_N
SB_CLK100M_SATA_N - @m42a_lib.M42A
SB_CLK100M_SATA_OE_L SB_CLK100M_SATA_OE_L @m42a_lib.M42A
SB_CLK100M_SATA_P
SB_CLK100M_SATA_P - @m42a_lib.M42A
SB_GPIO2
SB_GPIO2 - @m42a_lib.M42A
SB_GPIO3
SB_GPIO3 - @m42a_lib.M42A
SB_GPIO4
SB_GPIO4 - @m42a_lib.M42A
SB_GPIO5
SB_GPIO5 - @m42a_lib.M42A
ODD_PWR_EN_L - @m42a_lib.M42A
SB_GPIO14
SB_GPIO14 - @m42a_lib.M42A
SB_GPIO19
SB_GPIO19 - @m42a_lib.M42A
SB_GPIO21
SB_GPIO21 - @m42a_lib.M42A
SB_GPIO26
SB_GPIO26 - @m42a_lib.M42A
SB_GPIO29
SB_GPIO29 - @m42a_lib.M42A
SB_GPIO30
SB_GPIO30 - @m42a_lib.M42A
SB_GPIO31
SB_GPIO31 - @m42a_lib.M42A
SB_GPIO37
SB_GPIO37 - @m42a_lib.M42A
SB_INTVRMEN
SB_INTVRMEN - @m42a_lib.M42A
SB_RTC_RST_L
SB_RTC_RST_L - @m42a_lib.M42A
SB_RTC_X1
SB_RTC_X1 - @m42a_lib.M42A
SB_RTC_X1_R
SB_RTC_X1_R - @m42a_lib.M42A
SB_RTC_X2
SB_RTC_X2 - @m42a_lib.M42A
SB_RUNTIME_SCI_L
SB_RUNTIME_SCI_L - @m42a_lib.M42A
SB_SM_INTRUDER_L
SB_SM_INTRUDER_L - @m42a_lib.M42A
SB_SPKR
SB_SPKR - @m42a_lib.M42A
SC_RX_L
SC_RX_L - @m42a_lib.M42A
SC_TX_L
SC_TX_L - @m42a_lib.M42A
SDATAIN
SDATAIN - @m42a_lib.M42A
SDVO_CTRLCLK
SDVO_CTRLCLK - @m42a_lib.M42A
SDVO_CTRLDATA
SDVO_CTRLDATA - @m42a_lib.M42A
SMBUS_BATT_SCL_F
SMBUS_BATT_SCL_F - @m42a_lib.M42A
SMBUS_BATT_SDA_F
SMBUS_BATT_SDA_F - @m42a_lib.M42A
SMB_0_CLK
SMB_0_CLK - @m42a_lib.M42A
SMBUS_SMC_0_SCL - @m42a_lib.M42A
THRM_DIMM1_SMB_CLK - @m42a_lib.M42A
SMBUS_SMC_0_SCL - @m42a_lib.M42A
SMB_0_DATA
SMB_0_DATA - @m42a_lib.M42A
SMBUS_SMC_0_SDA - @m42a_lib.M42A
THRM_DIMM1_SMB_DATA @m42a_lib.M42A
SMBUS_SMC_0_SDA - @m42a_lib.M42A
SMB_AIRPORT_CONN_CLK SMB_AIRPORT_CONN_CLK @m42a_lib.M42A
SMB_AIRPORT_CONN_DAT SMB_AIRPORT_CONN_DATA A
@m42a_lib.M42A
SMB_ALERT_L
SMB_ALERT_L - @m42a_lib.M42A
SMB_BSA_CLK
SMB_BSA_CLK - @m42a_lib.M42A
SMBUS_SMC_BSA_SCL - @m42a_lib.M42A
=SMBUS_BATT_SCL - @m42a_lib.M42A
SMBUS_SMC_BSA_SCL - @m42a_lib.M42A
=SMBUS_BATT_SCL - @m42a_lib.M42A
SMB_BSA_DATA
SMB_BSA_DATA - @m42a_lib.M42A

60C8 64C1

SMBUS_SMC_BSA_SDA - @m42a_lib.M42A
=SMBUS_BATT_SDA - @m42a_lib.M42A
SMBUS_SMC_BSA_SDA - @m42a_lib.M42A
=SMBUS_BATT_SDA - @m42a_lib.M42A
SMB_BSB_CLK
SMB_BSB_CLK - @m42a_lib.M42A
SMB_BSB_DATA
SMB_BSB_DATA - @m42a_lib.M42A
SMB_LINK_ALERT_L
SMB_LINK_ALERT_L - @m42a_lib.M42A
SMB_MLB_CLK
SMB_MLB_CLK - @m42a_lib.M42A
THRM_DIMM0_SMB_CLK - @m42a_lib.M42A
SMBUS_SMC_MLB_SCL - @m42a_lib.M42A
SMB_THRM_CLK - @m42a_lib.M42A
THRM_DIMM0_SMB_CLK - @m42a_lib.M42A
SMB_THRM_CLK - @m42a_lib.M42A
SMBUS_SMC_MLB_SCL - @m42a_lib.M42A
SMB_MLB_DATA
SMB_MLB_DATA - @m42a_lib.M42A
THRM_DIMM0_SMB_DATA @m42a_lib.M42A
SMBUS_SMC_MLB_SDA - @m42a_lib.M42A
SMB_THRM_DATA - @m42a_lib.M42A
THRM_DIMM0_SMB_DATA @m42a_lib.M42A
SMB_THRM_DATA - @m42a_lib.M42A
SMBUS_SMC_MLB_SDA - @m42a_lib.M42A
SMC_AVCC_RC
SMC_AVCC_RC - @m42a_lib.M42A
SMC_BATT_CHG_EN
SMC_BATT_CHG_EN - @m42a_lib.M42A
SMC_BATT_ISENSE
SMC_BATT_ISENSE - @m42a_lib.M42A
SMC_BATT_ISET
SMC_BATT_ISET - @m42a_lib.M42A
SMC_BATT_TRICKLE_EN_ SMC_BATT_TRICKLE_EN_L L
@m42a_lib.M42A
SMC_BATT_VSET
SMC_BATT_VSET - @m42a_lib.M42A
SMC_BC_ACOK
SMC_BC_ACOK - @m42a_lib.M42A

64C1 67D4
39D6 64C1
64C3 66C2
64C3 66C2
5B1 67D3
39D6
65D4
39C2
39C3
5B2 39D4
26D6
26D5
66B3
66B2
5C1 66B5 66C2
66C4
5B2 64D7
8B5 8D7 9B8 48A5 48B3
64D6
58D1 64D8
8B5 8D7 9B8 48A5 48B3
64D6
66D4
62C5
59C5
58D7
45D8 46D6
59A2
63B2
63A2
63B2
6C4 21B6
6C3
6C4 21B6
6C3
6C4 21B6
6C3
6C4 21B6
6C3
35D7
35C7
35D5
35C5
21B6 35D4
21B6 35C4
23D2 35D2
23A3 23B3
21B6 35D4
21B6 35D4
35D6
35D6
35D7
35D7
21B6 35D2
21B6 35D2
35D3
21B6 35D2
21C4
21C6
21C6
21C6
21C6
23D3 33A6
23D3 33C7
22C2 33B2
22C2 33B2
21B6 33B2
23C3 32B4

59A1

SMC_BKLIGHT_ENABLE
SMC_BS_ALRT_L
SMC_BS_ALRT_L_F
SMC_CASE_OPEN
SMC_CPU_ISENSE
SMC_CPU_RESET_3_3_L
SMC_CPU_VSENSE
SMC_DCIN_ISENSE
SMC_DISPLAY_ENABLE
SMC_DISP_BKLT_A
SMC_DISP_BKLT_B
SMC_EXCARD_CP
SMC_EXCARD_PWR_EN
SMC_EXCARD_PWR_OC_L

33C3
33C3
33B3

SMC_EXTAL
SMC_EXTSMI_L
SMC_FAN_0_CTL
SMC_FAN_0_TACH
SMC_FAN_1_CTL
SMC_FAN_1_TACH
SMC_FAN_2_CTL
SMC_FAN_2_TACH
SMC_FAN_3_CTL
SMC_FAN_3_TACH
SMC_FWE
SMC_FWIRE_ISENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_LID
SMC_LID_F
SMC_LRESET_L
SMC_MANUAL_RST_L
SMC_MD1
SMC_MEM_ISENSE
SMC_NB_ISENSE
SMC_NMI
SMC_ODD_DETECT
SMC_ONOFF_L

33B3
26C3
34C8

36D8

27D5
43B5
43B5
23C5
27C3
27C2
27C1
27C2
27C1
27C3

45B5
65A2
65A2
45B5

27C2
27C1 65A2
27C2
27C1 65A2
27B3 45C5
27B3 45C8
23D5
27C6 45B5
27B3 49C4
5B2 27C5
10B3 27C3
27B3 49C4
10B3 27C3
5B2 27C5
27B6 45B5
27B3 49C4
5B2 27B5
10B3 27B3
27B3 49C4
10B3 27B3
5B2 27B5
45D3
5C1 45D8 46B6 66A4
45D5 66B1
5C1 45B5 66B7
5C1 45D8 46B6 66A3

45B5 46C3
5C1 45C5 46B6 65C3 65C7
66A5
SMC_BKLIGHT_ENABLE - @m42a_lib.M42A 45C8
SMC_BS_ALRT_L - @m42a_lib.M42A
5D1 45C5 46C6 65A2
SMC_BS_ALRT_L_F - @m42a_lib.M42A
65A6
SMC_CASE_OPEN - @m42a_lib.M42A
45C5 46B3
SMC_CPU_ISENSE - @m42a_lib.M42A
45D5 48C1
SMC_CPU_RESET_3_3_L 45B5 46C1
@m42a_lib.M42A
SMC_CPU_VSENSE - @m42a_lib.M42A
5B2 45D5 48B1
SMC_DCIN_ISENSE - @m42a_lib.M42A
45D5 66C2
SMC_DISPLAY_ENABLE - @m42a_lib.M42A 45C8
SMC_DISP_BKLT_A - @m42a_lib.M42A
45B5
SMC_DISP_BKLT_B - @m42a_lib.M42A
45B5 46C3
SMC_EXCARD_CP - @m42a_lib.M42A
45B8 46C3
SMC_EXCARD_PWR_EN - @m42a_lib.M42A 45B8 46C3
SMC_EXCARD_PWR_OC_L 45B8 46D3
@m42a_lib.M42A
SMC_EXTAL - @m42a_lib.M42A
45C4 46C7
SMC_EXTSMI_L - @m42a_lib.M42A
23B8 45B8
SMC_FAN_0_CTL - @m42a_lib.M42A
45B8 46C3
SMC_FAN_0_TACH - @m42a_lib.M42A
45B8 46C3
SMC_FAN_1_CTL - @m42a_lib.M42A
5D2 45B8 51B4
SMC_FAN_1_TACH - @m42a_lib.M42A
5D2 45B8 51C4
SMC_FAN_2_CTL - @m42a_lib.M42A
45B8 46C3
SMC_FAN_2_TACH - @m42a_lib.M42A
45B8 46C3
SMC_FAN_3_CTL - @m42a_lib.M42A
45B8 46C3
SMC_FAN_3_TACH - @m42a_lib.M42A
5A7 45B8 46C3
SMC_FWE - @m42a_lib.M42A
45B5 46C6
SMC_FWIRE_ISENSE - @m42a_lib.M42A
45D5 46B3
SMC_GPU_ISENSE - @m42a_lib.M42A
45D5 46C6
SMC_GPU_VSENSE - @m42a_lib.M42A
45D5 46C6
SMC_LID - @m42a_lib.M42A
5B2 40C4 45B5 46C6 65A8
SMC_LID_F - @m42a_lib.M42A
65A7
SMC_LRESET_L - @m42a_lib.M42A
26B1 45C8
SMC_MANUAL_RST_L - @m42a_lib.M42A
5B2 46D8
SMC_MD1 - @m42a_lib.M42A
5C2 45C2 47B6
SMC_MEM_ISENSE - @m42a_lib.M42A
45A8 46B3 61C1
SMC_NB_ISENSE - @m42a_lib.M42A
45B8 46B3 62A5
SMC_NMI - @m42a_lib.M42A
5C2 45C1 47B5
SMC_ODD_DETECT - @m42a_lib.M42A
34B3 45B8
SMC_ONOFF_L - @m42a_lib.M42A
40C8 45C5 46C8 46D6 48C8
CONN_GEYSER_ONOFF_L 40C7
@m42a_lib.M42A
SMC_P20 - @m42a_lib.M42A
45D8 46C6
SMC_P21 - @m42a_lib.M42A
45D8 46C6
SMC_P22 - @m42a_lib.M42A
45D8 46C6
SMC_P23 - @m42a_lib.M42A
45D8 46C6
SMC_P26 - @m42a_lib.M42A
45D8 46C6
SMC_P27 - @m42a_lib.M42A
45D8 46C6
SMC_P44 - @m42a_lib.M42A
45C8 46C6
SMC_P46 - @m42a_lib.M42A
45C8 46C6
SMC_PB7 - @m42a_lib.M42A
45B8 46C6
SMC_PBUS_VSENSE - @m42a_lib.M42A
45D5 48C5
SMC_PD3 - @m42a_lib.M42A
45B8 46C3
SMC_PG1 - @m42a_lib.M42A
45B5 46C6
SMC_PM_G2_EN - @m42a_lib.M42A
45D5 63C8
SMC_PM_G2_EN_L - @m42a_lib.M42A
63C7
SMC_PROCHOT - @m42a_lib.M42A
45B5 46B6
SMC_PROCHOT_3_3_L - @m42a_lib.M42A 45D5 46C1
SMC_PS_ON - @m42a_lib.M42A
5C1 39C6 45D5 46B3 65C3
SMC_RCIN_L - @m42a_lib.M42A
21C3 45C8
SMC_RSTGATE_L - @m42a_lib.M42A
26A3 45D8
SMC_RST_L - @m42a_lib.M42A
5C2 45C3 46D7 47C5
SMC_RUNTIME_SCI_L - @m42a_lib.M42A 23C8 45B8
SMC_RX_L - @m42a_lib.M42A
5C2 45C8 46B2 46D6 47B5
SMC_SB_NMI - @m42a_lib.M42A
23C3 45D8
SMC_SUS_CLK - @m42a_lib.M42A
45C5 46A6
SMC_SUS_CLK_R - @m42a_lib.M42A
46A7
SMC_SYS_ISET - @m42a_lib.M42A
45B5 66D7
SMC_SYS_KBDLED - @m42a_lib.M42A
45C8 46C6
SMC_SYS_LED_16B - @m42a_lib.M42A
45C8 46A4
SMC_SYS_VSET - @m42a_lib.M42A
45B5 46C3
SMC_TCK - @m42a_lib.M42A
5C2 45C5 46C6 47C5
SMC_TDI - @m42a_lib.M42A
5C2 45C5 46C6 47C5
SMC_TDO - @m42a_lib.M42A
5C2 45C5 46C6 47B6
SMC_THRMTRIP - @m42a_lib.M42A
45B5 46B5
SMC_TMS - @m42a_lib.M42A
5C2 45B5 46C6 47C6
SMC_TPM_GPIO - @m42a_lib.M42A
45D5 46B2
SMC_TPM_PP - @m42a_lib.M42A
45C8 53C7
SMC_TPM_PP_R - @m42a_lib.M42A
53C6
SMC_TPM_RESET_L - @m42a_lib.M42A
45C8 46D6 53B7
SMC_TRST_L - @m42a_lib.M42A
5C2 45C1 47C6
SMC_TX_L - @m42a_lib.M42A
5C2 45C8 46B2 46D6 47B6
SMC_VCL - @m42a_lib.M42A
45D3
SMC_WAKE_SCI_L - @m42a_lib.M42A
23C1 45D5
SMC_XTAL - @m42a_lib.M42A
45C4 46C7
SMLINK<0> - @m42a_lib.M42A
23D5
SMLINK<1> - @m42a_lib.M42A
23D5
SMS_ACC_SELFTEST - @m42a_lib.M42A
52B6
SMS_INT_L - @m42a_lib.M42A
23C3 45B5 46D6
SMS_ONOFF_L - @m42a_lib.M42A
45B5 52C7
SMS_X_AXIS - @m42a_lib.M42A
45B8 52C2
SMS_Y_AXIS - @m42a_lib.M42A
45B8 52C2

SMS_Z_AXIS
SPI_ARB
SPI_CE_L
SPI_HOLD_L
SPI_SCLK
SPI_SCLK_R
SPI_SI
SPI_SI_R
SPI_SO
SPI_SO_R
SPI_WP_L
SPKRAMP_L_N_OUT
SPKRAMP_L_P_OUT
SPKRAMP_R_N_OUT
SPKRAMP_R_P_OUT
SPKRAMP_SUB_N_OUT
SPKRAMP_SUB_P_OUT
SPKRAMP_SYNC1
SPKRAMP_SYNC2
SPKRAMP_THERMPLANE
SPKRCONN_L_N_OUT
SPKRCONN_L_P_OUT
SPKRCONN_R_N_OUT
SPKRCONN_R_P_OUT
SPKRCONN_SUB_N_OUT
SPKRCONN_SUB_P_OUT
SPKR_SHIELD
ST_ACCEL_ON_L
SUS_CLK_SB

SMS_Z_AXIS - @m42a_lib.M42A
SPI_ARB - @m42a_lib.M42A
SPI_CE_L - @m42a_lib.M42A
SPI_HOLD_L - @m42a_lib.M42A
SPI_SCLK - @m42a_lib.M42A
SPI_SCLK_R - @m42a_lib.M42A
SPI_SI - @m42a_lib.M42A
SPI_SI_R - @m42a_lib.M42A
SPI_SO - @m42a_lib.M42A
SPI_SO_R - @m42a_lib.M42A
SPI_WP_L - @m42a_lib.M42A
SPKRAMP_L_N_OUT - @m42a_lib.M42A
SPKRAMP_L_P_OUT - @m42a_lib.M42A
SPKRAMP_R_N_OUT - @m42a_lib.M42A
SPKRAMP_R_P_OUT - @m42a_lib.M42A
SPKRAMP_SUB_N_OUT - @m42a_lib.M42A
SPKRAMP_SUB_P_OUT - @m42a_lib.M42A
SPKRAMP_SYNC1 - @m42a_lib.M42A
SPKRAMP_SYNC2 - @m42a_lib.M42A
SPKRAMP_THERMPLANE - @m42a_lib.M42A
SPKRCONN_L_N_OUT - @m42a_lib.M42A
SPKRCONN_L_P_OUT - @m42a_lib.M42A
SPKRCONN_R_N_OUT - @m42a_lib.M42A
SPKRCONN_R_P_OUT - @m42a_lib.M42A
SPKRCONN_SUB_N_OUT - @m42a_lib.M42A
SPKRCONN_SUB_P_OUT - @m42a_lib.M42A
SPKR_SHIELD - @m42a_lib.M42A
ST_ACCEL_ON_L - @m42a_lib.M42A
SUS_CLK_SB - @m42a_lib.M42A
SUS_CLK_SB_SPN - @m42a_lib.M42A
SV_SET_UP
SV_SET_UP - @m42a_lib.M42A
SYS_LED_ANODE
SYS_LED_ANODE - @m42a_lib.M42A
SYS_LED_ANODE_L
SYS_LED_ANODE_L - @m42a_lib.M42A
SYS_LED_ILIM
SYS_LED_ILIM - @m42a_lib.M42A
SYS_LED_L
SYS_LED_L - @m42a_lib.M42A
SYS_LED_L_VDIV
SYS_LED_L_VDIV - @m42a_lib.M42A
SYS_ONEWIRE
SYS_ONEWIRE - @m42a_lib.M42A
THRM_ALERT
THRM_ALERT - @m42a_lib.M42A
THRM_ALERT_L
THRM_ALERT_L - @m42a_lib.M42A
THRM_CPU_DX_N
THRM_CPU_DX_N - @m42a_lib.M42A
THRM_CPU_DX_P
THRM_CPU_DX_P - @m42a_lib.M42A
THRM_DIMM0_3V3_UNFIL THRM_DIMM0_3V3_UNFILTERED TERED
@m42a_lib.M42A
THRM_DIMM0_DXN
THRM_DIMM0_DXN - @m42a_lib.M42A
THRM_DIMM0_DXP1
THRM_DIMM0_DXP1 - @m42a_lib.M42A
THRM_DIMM0_DXP2
THRM_DIMM0_DXP2 - @m42a_lib.M42A
THRM_DIMM1_3V3_UNFIL THRM_DIMM1_3V3_UNFILTERED TERED
@m42a_lib.M42A
THRM_DIMM1_DXN
THRM_DIMM1_DXN - @m42a_lib.M42A
THRM_DIMM1_DXP1
THRM_DIMM1_DXP1 - @m42a_lib.M42A
THRM_DIMM1_DXP2
THRM_DIMM1_DXP2 - @m42a_lib.M42A
TMDS_EXT_RES
TMDS_EXT_RES - @m42a_lib.M42A
TMDS_EXT_SWING
TMDS_EXT_SWING - @m42a_lib.M42A
TMDS_HTPLG
TMDS_HTPLG - @m42a_lib.M42A
TMDS_HTPLG_R
TMDS_HTPLG_R - @m42a_lib.M42A
TMDS_I2C_SCL
TMDS_I2C_SCL - @m42a_lib.M42A
TMDS_I2C_SDA
TMDS_I2C_SDA - @m42a_lib.M42A
TMDS_INT_N
TMDS_INT_N - @m42a_lib.M42A
TMDS_INT_P
TMDS_INT_P - @m42a_lib.M42A
TMDS_RST_L
TMDS_RST_L - @m42a_lib.M42A
TMDS_SDB_N
TMDS_SDB_N - @m42a_lib.M42A
TMDS_SDB_P
TMDS_SDB_P - @m42a_lib.M42A
TMDS_SDC_N
TMDS_SDC_N - @m42a_lib.M42A
TMDS_SDC_P
TMDS_SDC_P - @m42a_lib.M42A
TMDS_SDG_N
TMDS_SDG_N - @m42a_lib.M42A
TMDS_SDG_P
TMDS_SDG_P - @m42a_lib.M42A
TMDS_SDR_N
TMDS_SDR_N - @m42a_lib.M42A
TMDS_SDR_P
TMDS_SDR_P - @m42a_lib.M42A
TMDS_TX<0>
TMDS_TX<0> - @m42a_lib.M42A
TMDS_TX<1>
TMDS_TX<1> - @m42a_lib.M42A
TMDS_TX<2>
TMDS_TX<2> - @m42a_lib.M42A
TMDS_TX_CLK
TMDS_TX_CLK - @m42a_lib.M42A
TMDS_TX_CLK_N
TMDS_TX_CLK_N - @m42a_lib.M42A
TMDS_TX_CLK_P
TMDS_TX_CLK_P - @m42a_lib.M42A
TMDS_TX_CONN_CLK_N
TMDS_TX_CONN_CLK_N - @m42a_lib.M42A
TMDS_TX_CONN_CLK_P
TMDS_TX_CONN_CLK_P - @m42a_lib.M42A
TMDS_TX_CONN_N<0>
TMDS_TX_CONN_N<0> - @m42a_lib.M42A
TMDS_TX_CONN_N<1>
TMDS_TX_CONN_N<1> - @m42a_lib.M42A
TMDS_TX_CONN_N<2>
TMDS_TX_CONN_N<2> - @m42a_lib.M42A
TMDS_TX_CONN_P<0>
TMDS_TX_CONN_P<0> - @m42a_lib.M42A
TMDS_TX_CONN_P<1>
TMDS_TX_CONN_P<1> - @m42a_lib.M42A
TMDS_TX_CONN_P<2>
TMDS_TX_CONN_P<2> - @m42a_lib.M42A
TMDS_TX_N<0>
TMDS_TX_N<0> - @m42a_lib.M42A
TMDS_TX_N<1>
TMDS_TX_N<1> - @m42a_lib.M42A
TMDS_TX_N<2>
TMDS_TX_N<2> - @m42a_lib.M42A
TMDS_TX_P<0>
TMDS_TX_P<0> - @m42a_lib.M42A
TMDS_TX_P<1>
TMDS_TX_P<1> - @m42a_lib.M42A
TMDS_TX_P<2>
TMDS_TX_P<2> - @m42a_lib.M42A
TPM_BADD
TPM_BADD - @m42a_lib.M42A
TPM_GPIO1
TPM_GPIO1 - @m42a_lib.M42A
TPM_GPIO2
TPM_GPIO2 - @m42a_lib.M42A
TPM_LRESET_L
TPM_LRESET_L - @m42a_lib.M42A
TPM_RST_L
TPM_RST_L - @m42a_lib.M42A
TPM_XTALI
TPM_XTALI - @m42a_lib.M42A
TPM_XTALO
TPM_XTALO - @m42a_lib.M42A
TPS73115_NR
TPS73115_NR - @m42a_lib.M42A
TP_AZ_DOCK_EN_L
TP_AZ_DOCK_EN_L - @m42a_lib.M42A
TP_AZ_DOCK_RST_L
TP_AZ_DOCK_RST_L - @m42a_lib.M42A
TP_CPU_A32_L
TP_CPU_A32_L - @m42a_lib.M42A
TP_CPU_A33_L
TP_CPU_A33_L - @m42a_lib.M42A
TP_CPU_A34_L
TP_CPU_A34_L - @m42a_lib.M42A
TP_CPU_A35_L
TP_CPU_A35_L - @m42a_lib.M42A
TP_CPU_A36_L
TP_CPU_A36_L - @m42a_lib.M42A
TP_CPU_A37_L
TP_CPU_A37_L - @m42a_lib.M42A
TP_CPU_A38_L
TP_CPU_A38_L - @m42a_lib.M42A
TP_CPU_A39_L
TP_CPU_A39_L - @m42a_lib.M42A
TP_CPU_APM0_L
TP_CPU_APM0_L - @m42a_lib.M42A
TP_CPU_APM1_L
TP_CPU_APM1_L - @m42a_lib.M42A
TP_CPU_CPUSLP_L
TP_CPU_CPUSLP_L - @m42a_lib.M42A
TP_CPU_EXTBREF
TP_CPU_EXTBREF - @m42a_lib.M42A
TP_CPU_HFPLL
TP_CPU_HFPLL - @m42a_lib.M42A
TP_CPU_SPARE0
TP_CPU_SPARE0 - @m42a_lib.M42A
TP_CPU_SPARE1
TP_CPU_SPARE1 - @m42a_lib.M42A
TP_CPU_SPARE2
TP_CPU_SPARE2 - @m42a_lib.M42A
TP_CPU_SPARE3
TP_CPU_SPARE3 - @m42a_lib.M42A
TP_CPU_SPARE4
TP_CPU_SPARE4 - @m42a_lib.M42A
TP_CPU_SPARE5
TP_CPU_SPARE5 - @m42a_lib.M42A
TP_CPU_SPARE6
TP_CPU_SPARE6 - @m42a_lib.M42A
TP_CPU_SPARE7
TP_CPU_SPARE7 - @m42a_lib.M42A
TP_LVDS_VBG
TP_LVDS_VBG - @m42a_lib.M42A
TP_NB_TESTIN_L
TP_NB_TESTIN_L - @m42a_lib.M42A
TP_NB_XOR_FSB2_H7
TP_NB_XOR_FSB2_H7 - @m42a_lib.M42A
TP_NB_XOR_LVDS_A34
TP_NB_XOR_LVDS_A34 - @m42a_lib.M42A
TP_NB_XOR_LVDS_A35
TP_NB_XOR_LVDS_A35 - @m42a_lib.M42A

45B8 52C2
22C6 45D5
22C6 45B5 50C7
50C4
22C6 45D5 50C7
50C4
22C6 45D5 50C1
50C3
22C6 45D5 50C1
50C3
50C4
55B4 55C3
55B4 55C3
55C3 55C4
55C4 55D3
55A4 55B3
55A4 55B3
55A4 55C4
55A4 55B4
55A4 55A4 55B4 55C4
55C1 56D2
55C1 56D2
55C1 56C2
55D1 56C2
55B1 56C2
55B1 56C2
56C2
52B6
6B4 23C3
6B3
5C2 23B6 23C3 47B5
5B2 35C5 46A3
35C7
46A3
46A3
46A3
5C1 45B8 46D6 65C8
10B4
10C4
10B5
10B5
49D4

y
r

a
n
i

m
il

e
r
21B6 33B2
22A6 26C3
22A6 23A4
22A6 26C3
22A6 26C3
34C8
23A4 23C3
23D3
23D3
23C8
22C4 22D8
22C4 22D8
22C4 22D8
23D3
21D6
21D6 26D4
21D6 26C8
26C7
21D6 26C8
23C5
21D6 26D4
23C5
45C5 46B1
45C5 46B1
54C6
14B6 68A6
14B6 68A6
5D1 65B6
5D1 65A6
27D6 45C8
27D5
27D3 49B4
27D5
27D6 45C5
27D5
27C3 49B4

SMC_P20
SMC_P21
SMC_P22
SMC_P23
SMC_P26
SMC_P27
SMC_P44
SMC_P46
SMC_PB7
SMC_PBUS_VSENSE
SMC_PD3
SMC_PG1
SMC_PM_G2_EN
SMC_PM_G2_EN_L
SMC_PROCHOT
SMC_PROCHOT_3_3_L
SMC_PS_ON
SMC_RCIN_L
SMC_RSTGATE_L
SMC_RST_L
SMC_RUNTIME_SCI_L
SMC_RX_L
SMC_SB_NMI
SMC_SUS_CLK
SMC_SUS_CLK_R
SMC_SYS_ISET
SMC_SYS_KBDLED
SMC_SYS_LED_16B
SMC_SYS_VSET
SMC_TCK
SMC_TDI
SMC_TDO
SMC_THRMTRIP
SMC_TMS
SMC_TPM_GPIO
SMC_TPM_PP
SMC_TPM_PP_R
SMC_TPM_RESET_L
SMC_TRST_L
SMC_TX_L
SMC_VCL
SMC_WAKE_SCI_L
SMC_XTAL
SMLINK<0>
SMLINK<1>
SMS_ACC_SELFTEST
SMS_INT_L
SMS_ONOFF_L
SMS_X_AXIS
SMS_Y_AXIS

40C5 49C6
40C4 49D6
49C6
49B4
49B5
49B5
49A5
68B4
68B3
68A7
68A7
68B2
68B2
68B5
68B5
26B1
68B4
68B4
68B4
68B4
68B4
68B4
68B4
68B4
68D2
68D2
68C2
68C2
68B2
68B2
69B3
69B3
69B3
69B3
69B3
69B3
69B3
69B3
68B2
68B2
68B2
68B2
68B2
68B2
53C3
46B1
46B1
26B1
53B6
53C6
53C6
19D5
23C5
23C5
7C8
7B8
7B8
7B8
7B8
7B8
7B8
7B8
7B8
7B8
21C4
7B6
7B8
7B6
7B6
7B6
7B6
7B6
7B6
7B6
7B6
13D5
14D6
14D6
14C6
14C6

69C6

68B5

68C1 69A2
68C3 69A2

B
68D1
68D1
68C1
68D3
68D3
68C3

69B2
69B2
69B2
69B2
69B2
69B2

53C6
53C6
53B7

103

8
TP_NB_XOR_LVDS_D27
TP_NB_XOR_LVDS_D28
TP_PCI_GNT0_L
TP_PCI_GNT1_L
TP_PCI_GNT2_L
TP_PCI_PME_L
TP_SB_ACZ_SDIN1
TP_SB_ACZ_SDIN2
TP_SB_DRQ0_L
TP_SB_GPIO6
TP_SB_GPIO22

TP_NB_XOR_LVDS_D27 - @m42a_lib.M42A
TP_NB_XOR_LVDS_D28 - @m42a_lib.M42A
TP_PCI_GNT0_L - @m42a_lib.M42A
TP_PCI_GNT1_L - @m42a_lib.M42A
TP_PCI_GNT2_L - @m42a_lib.M42A
TP_PCI_PME_L - @m42a_lib.M42A
TP_SB_ACZ_SDIN1 - @m42a_lib.M42A
TP_SB_ACZ_SDIN2 - @m42a_lib.M42A
TP_SB_DRQ0_L - @m42a_lib.M42A
TP_SB_GPIO6 - @m42a_lib.M42A
TP_SB_GPIO22 - @m42a_lib.M42A
=SB_GPIO22 - @m42a_lib.M42A
SB_GPIO22 - @m42a_lib.M42A
=SB_GPIO22 - @m42a_lib.M42A
TP_SB_GPIO23
TP_SB_GPIO23 - @m42a_lib.M42A
TP_SB_GPIO25_DO_NOT_ TP_SB_GPIO25_DO_NOT_USE USE
@m42a_lib.M42A
TP_SB_GPIO38
TP_SB_GPIO38 - @m42a_lib.M42A
TP_SB_RCVENIN_L
TP_SB_RCVENIN_L - @m42a_lib.M42A
TP_SB_RSVD9
TP_SB_RSVD9 - @m42a_lib.M42A
TP_SB_SATALED_L
TP_SB_SATALED_L - @m42a_lib.M42A
TP_SB_XOR-AD5
TP_SB_XOR-AD5 - @m42a_lib.M42A
TP_SB_XOR-AD9
TP_SB_XOR-AD9 - @m42a_lib.M42A
TP_SB_XOR-AE5
TP_SB_XOR-AE5 - @m42a_lib.M42A
TP_SB_XOR-AG4
TP_SB_XOR-AG4 - @m42a_lib.M42A
TP_SB_XOR-AH4
TP_SB_XOR-AH4 - @m42a_lib.M42A
TP_SB_XOR-U3
TP_SB_XOR-U3 - @m42a_lib.M42A
TP_SB_XOR-U7
TP_SB_XOR-U7 - @m42a_lib.M42A
TP_SB_XOR-V6
TP_SB_XOR-V6 - @m42a_lib.M42A
TP_SB_XOR-V7
TP_SB_XOR-V7 - @m42a_lib.M42A
TP_SB_XOR-Y1
TP_SB_XOR-Y1 - @m42a_lib.M42A
TP_SB_XOR-Y2
TP_SB_XOR-Y2 - @m42a_lib.M42A
TP_SB_XOR_AE9
TP_SB_XOR_AE9 - @m42a_lib.M42A
TP_SB_XOR_AG8
TP_SB_XOR_AG8 - @m42a_lib.M42A
TP_SB_XOR_AH8
TP_SB_XOR_AH8 - @m42a_lib.M42A
TP_SB_XOR_W1
TP_SB_XOR_W1 - @m42a_lib.M42A
TP_USBN_F
TP_USBN_F - @m42a_lib.M42A
TP_USBP_F
TP_USBP_F - @m42a_lib.M42A
TV_DACA_OUT
TV_DACA_OUT - @m42a_lib.M42A
TV_DACB_OUT
TV_DACB_OUT - @m42a_lib.M42A
TV_DACC_OUT
TV_DACC_OUT - @m42a_lib.M42A
TV_IREF
TV_IREF - @m42a_lib.M42A
USB2_BT_F_N
USB2_BT_F_N - @m42a_lib.M42A
USB2_BT_F_P
USB2_BT_F_P - @m42a_lib.M42A
USB2_CAMERA_CONN_N
USB2_CAMERA_CONN_N - @m42a_lib.M42A
USB2_CAMERA_CONN_P
USB2_CAMERA_CONN_P - @m42a_lib.M42A
USB2_EXTA_F_N
USB2_EXTA_F_N - @m42a_lib.M42A
USB2_EXTA_F_P
USB2_EXTA_F_P - @m42a_lib.M42A
USB2_EXTB_F_N
USB2_EXTB_F_N - @m42a_lib.M42A
USB2_EXTB_F_P
USB2_EXTB_F_P - @m42a_lib.M42A
USB2_GND_EXTA_F
USB2_GND_EXTA_F - @m42a_lib.M42A
USB2_GND_EXTB_F
USB2_GND_EXTB_F - @m42a_lib.M42A
USB_A_N
USB_A_N - @m42a_lib.M42A
=USB2_EXTA_N - @m42a_lib.M42A
USB2_EXTA_N - @m42a_lib.M42A
=USB2_EXTA_N - @m42a_lib.M42A
USB_A_OC_L
USB_A_OC_L - @m42a_lib.M42A
=EXTAUSB_OC_L - @m42a_lib.M42A
EXTAUSB_OC_L - @m42a_lib.M42A
=EXTAUSB_OC_L - @m42a_lib.M42A
USB_A_P
USB_A_P - @m42a_lib.M42A
=USB2_EXTA_P - @m42a_lib.M42A
USB2_EXTA_P - @m42a_lib.M42A
=USB2_EXTA_P - @m42a_lib.M42A
USB_B_N
USB_B_N - @m42a_lib.M42A
=USB2_GEYSER_N - @m42a_lib.M42A
USB2_GEYSER_N - @m42a_lib.M42A
=USB2_GEYSER_N - @m42a_lib.M42A
USB_B_OC_L
USB_B_OC_L - @m42a_lib.M42A
USB_B_P
USB_B_P - @m42a_lib.M42A
=USB2_GEYSER_P - @m42a_lib.M42A
USB2_GEYSER_P - @m42a_lib.M42A
=USB2_GEYSER_P - @m42a_lib.M42A
USB_C_N
USB_C_N - @m42a_lib.M42A
=USB2_EXTB_N - @m42a_lib.M42A
USB2_EXTB_N - @m42a_lib.M42A
=USB2_EXTB_N - @m42a_lib.M42A
USB_C_P
USB_C_P - @m42a_lib.M42A
=USB2_EXTB_P - @m42a_lib.M42A
USB2_EXTB_P - @m42a_lib.M42A
=USB2_EXTB_P - @m42a_lib.M42A
USB_D_OC_L
USB_D_OC_L - @m42a_lib.M42A
USB_E_N
USB_E_N - @m42a_lib.M42A
TP_USBN_E - @m42a_lib.M42A
USB_E_OC_L
USB_E_OC_L - @m42a_lib.M42A
USB_E_P
USB_E_P - @m42a_lib.M42A
TP_USBP_E - @m42a_lib.M42A
USB_F_N
USB_F_N - @m42a_lib.M42A
=USB2_IR_N - @m42a_lib.M42A
USB_IR_N - @m42a_lib.M42A
=USB2_IR_N - @m42a_lib.M42A
USB_F_P
USB_F_P - @m42a_lib.M42A
=USB2_IR_P - @m42a_lib.M42A
USB_IR_P - @m42a_lib.M42A
=USB2_IR_P - @m42a_lib.M42A
USB_G_N
USB_G_N - @m42a_lib.M42A
=USB2_BT_N - @m42a_lib.M42A
USB_BT_N - @m42a_lib.M42A
=USB2_BT_N - @m42a_lib.M42A
USB_G_P
USB_G_P - @m42a_lib.M42A
=USB2_BT_P - @m42a_lib.M42A
USB_BT_P - @m42a_lib.M42A
=USB2_BT_P - @m42a_lib.M42A
USB_RBIAS_PN
USB_RBIAS_PN - @m42a_lib.M42A
VGA_B
VGA_B - @m42a_lib.M42A
VGA_G
VGA_G - @m42a_lib.M42A
VGA_HSYNC
VGA_HSYNC - @m42a_lib.M42A
VGA_R
VGA_R - @m42a_lib.M42A
VGA_VSYNC
VGA_VSYNC - @m42a_lib.M42A
VOL_DOWN
VOL_DOWN - @m42a_lib.M42A
VOL_UP
VOL_UP - @m42a_lib.M42A
VREG_FB
VREG_FB - @m42a_lib.M42A
VR_PWRGD_CK410
VR_PWRGD_CK410 - @m42a_lib.M42A
VR_PWRGOOD_DELAY
VR_PWRGOOD_DELAY - @m42a_lib.M42A
XDP_BPM_L<0>
XDP_BPM_L<0> - @m42a_lib.M42A
XDP_BPM_L<1>
XDP_BPM_L<1> - @m42a_lib.M42A
XDP_BPM_L<2>
XDP_BPM_L<2> - @m42a_lib.M42A
XDP_BPM_L<3>
XDP_BPM_L<3> - @m42a_lib.M42A
XDP_BPM_L<4>
XDP_BPM_L<4> - @m42a_lib.M42A
XDP_BPM_L<5>
XDP_BPM_L<5> - @m42a_lib.M42A
XDP_DBRESET_L
XDP_DBRESET_L - @m42a_lib.M42A
XDP_TCK
XDP_TCK - @m42a_lib.M42A
XDP_TDI
XDP_TDI - @m42a_lib.M42A
XDP_TDO
XDP_TDO - @m42a_lib.M42A

7
14C6
14C6
22B6
22B6
22B6
22A6
21C6
21C6
21D4
23C5
6B1 22B6
6B2 69A6
6B2
6B2 69A6
21D5
23C3

XDP_TMS
XDP_TRST_L

XDP_TMS - @m42a_lib.M42A
XDP_TRST_L - @m42a_lib.M42A

7B8 7C6 11B2


7C6 11B3

23C3
15B2
22A6
21C6
22A7
22A7
22A7
22A7
22A7
21C6
21C6
21C6
21C6
21C6
21C6
22A6
22A6
22A6
21C6
5C1
5C1
13C5 69B8
13C5 69A8
13C5 69A8
13C5 69C8
44C4
44B4
67A2
67B2
42C2
42C2
42B2
42B2
42C2
42B2
6C1 22C2
6C2 42C5
6C2
6C2 42C5
6C1 22C4 22D8
6C2 42C8
6C2
6C2 42C8
6C1 22C2
6C2 42C5
6C2
6C2 42C5
6C1 22C2
6C2 40C7
6C2
6C2 40C7
22C4 22D8
6C1 22C2
6C2 40C7
6C2
6C2 40C7
6C1 22C2
6C2 42B5
6C2
6C2 42B5
6C1 22C2
6C2 42B5
6C2
6C2 42B5
22C4 22D8
6C1 22C2
5C1 6C2
22C4 22D8
6C1 22C2
5C1 6C2
6C1 22C2
6C2 41C6
6C2
6C2 41C6
6C1 22C2
6C2 41C6
6C2
6C2 41C6
6B1 22C2
6B2 44C6
6B2
6B2 44C6
6B1 22C2
6C2 44C6
6C2
6C2 44C6
22C2
69B4
69B4
69B4 69C1
69A4
69B4 69C1
54B7 54C7
54B7 54C7
54A4
23C5 26A8
14B6 26B5 58C7
7C6 11B2
7C6 11B2
7C6 11B2
7C6 11B3
7C6 11B2
7C6 11B2
7C6 11B4 26C6
7A8 7C6 11B2 11B3
7B8 7C6 11B3
7C6 11B5

y
r

a
n
i

m
il

e
r

104

8
Title:
Design:
Date:

C0607
C0608
C0610
C0611
C0612
C0613
C0614
C0615
C0616
C0617
C0618
C0619
C0630
C0900
C0901
C0902
C0904
C0907
C0908
C0909
C0910
C0911
C0912
C0913
C0918
C0920
C0923
C0924
C0926
C0928
C0929
C0930
C0931
C0934
C0935
C0936
C0937
C0938
C0939
C0940
C0941
C0942
C0943
C0944
C0946
C0950
C0951
C1001
C1002
C1100
C1211
C1226
C1236
C1415
C1416
C1610
C1611
C1612
C1613
C1614
C1615
C1620
C1621
C1711
C1712
C1713
C1900
C1902
C1903
C1904
C1905
C1906
C1907
C1910
C1911
C1912
C1913
C1914
C1915
C1916
C1917
C1918
C1920
C1921
C1922
C1923
C1934
C1935
C1936
C1937
C1940
C1941
C1942
C1950
C1951
C1952
C1953
C1954
C1965
C1966
C1967
C1970
C1971
C1972
C1975
C1976
C1980
C1981
C1985
C1986
C1990
C1991
C1992
C1993
C1994
C1995
C1996
C1997
C1998

Cref Part Report


m42a
Aug 5 16:01:17 2006

CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_805
CAP_805
CAP_805
CAP_805
CAP_805
CAP_805
CAP_805
CAP_805
CAP_805
CAP_805
CAP_805
CAP_805
CAP_805
CAP_805
CAP_805
CAP_402
CAP_805
CAP_805
CAP_805
CAP_805
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_805
CAP_P_3P_D2T
CAP_P_3P_D2T
CAP_P_3P_D2T
CAP_P_3P_D2T
CAP_P_3P_D2T
CAP_P_3P_D2T
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_603
CAP_402
CAP_402
CAP_402
CAP_P_3P_D2T
CAP_603
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_603
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
FILTER_3P_A_NFM18
CAP_402
FILTER_3P_A_NFM18
CAP_805
CAP_402
CAP_805
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_603
CAP_603
CAP_402
CAP_P_SMB2
CAP_603
CAP_603
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
FILTER_3P_A_NFM18
CAP_603
CAP_402
FILTER_3P_A_NFM18
CAP_402
FILTER_3P_A_NFM18
CAP_402
FILTER_3P_A_NFM18
CAP_402
FILTER_3P_A_NFM18

7
C2500
C2501
C2502
C2503
C2504
C2505
C2506
C2507
C2508
C2509
C2510
C2511
C2512
C2513
C2514
C2515
C2516
C2517
C2518
C2519
C2520
C2521
C2522
C2523
C2524
C2525
C2526
C2527
C2528
C2529
C2530
C2531
C2532
C2533
C2534
C2605
C2607
C2608
C2609
C2610
C2611
C2680
C2800
C2809
C2810
C2811
C2812
C2813
C2814
C2815
C2816
C2817
C2820
C2821
C2822
C2830
C2831
C2832
C2900
C2909
C2910
C2911
C2912
C2913
C2914
C2915
C2916
C2917
C2920
C2921
C2922
C2930
C2931
C2932
C3000
C3001
C3002
C3003
C3004
C3005
C3006
C3007
C3008
C3009
C3010
C3011
C3012
C3013
C3014
C3015
C3016
C3017
C3018
C3019
C3020
C3021
C3022
C3023
C3024
C3025
C3100
C3101
C3102
C3103
C3104
C3105
C3301
C3302
C3303
C3304
C3305
C3306
C3307
C3308
C3309
C3310
C3311
C3312
C3314
C3315
C3316
C3317
C3389
C3390

m42a[6C7]
m42a[6C7]
m42a[6C7]
m42a[6C7]
m42a[6A8]
m42a[6A8]
m42a[6B7]
m42a[6B7]
m42a[6B7]
m42a[6B7]
m42a[6A8]
m42a[6A7]
m42a[6C7]
m42a[9B5]
m42a[9B6]
m42a[9A5]
m42a[9A6]
m42a[9B4]
m42a[9B6]
m42a[9B5]
m42a[9B7]
m42a[9B7]
m42a[9A6]
m42a[9A7]
m42a[9A7]
m42a[9A4]
m42a[9B7]
m42a[9A7]
m42a[9B7]
m42a[9B5]
m42a[9B4]
m42a[9A5]
m42a[9A5]
m42a[9B7]
m42a[9B7]
m42a[9B6]
m42a[9B6]
m42a[9B5]
m42a[9A4]
m42a[9B5]
m42a[9A7]
m42a[9A7]
m42a[9A6]
m42a[9A6]
m42a[9A5]
m42a[9D7]
m42a[9D7]
m42a[10B5]
m42a[10C4]
m42a[11B3]
m42a[12C3]
m42a[12B6]
m42a[12A6]
m42a[14C3]
m42a[14C2]
m42a[16B5]
m42a[16B4]
m42a[16B4]
m42a[16B8]
m42a[16B8]
m42a[16B6]
m42a[16B5]
m42a[16B5]
m42a[17A3]
m42a[17A3]
m42a[17B3]
m42a[19B8]
m42a[19B7]
m42a[19B7]
m42a[19B6]
m42a[19B6]
m42a[19B6]
m42a[19B5]
m42a[19B8]
m42a[19B7]
m42a[19B8]
m42a[19B7]
m42a[19B6]
m42a[19B6]
m42a[19B6]
m42a[19B5]
m42a[19B5]
m42a[19A6]
m42a[19A6]
m42a[19A6]
m42a[19A6]
m42a[19C5]
m42a[19C5]
m42a[19C5]
m42a[19C5]
m42a[19C4]
m42a[19C3]
m42a[19C3]
m42a[19D6]
m42a[19D5]
m42a[19D5]
m42a[19D4]
m42a[19C4]
m42a[19B4]
m42a[19B4]
m42a[19B4]
m42a[19A4]
m42a[19A3]
m42a[19A3]
m42a[19A3]
m42a[19A3]
m42a[19D2]
m42a[19D2]
m42a[19C2]
m42a[19D2]
m42a[19C2]
m42a[19C2]
m42a[19C2]
m42a[19B2]
m42a[19B2]
m42a[19B2]
m42a[19B2]
m42a[19A2]
m42a[19A2]

CAP_P_SMB2
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_P_CASE-C2
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_603
CAP_402
CAP_603
CAP_P_SMC-LF
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_603
CAP_603
CAP_402
CAP_402

m42a[25B8]
m42a[25A6]
m42a[25D4]
m42a[25D8]
m42a[25C8]
m42a[25B7]
m42a[25B7]
m42a[25B7]
m42a[25A6]
m42a[25B8]
m42a[25C1]
m42a[25D6]
m42a[25B1]
m42a[25C6]
m42a[25C6]
m42a[25B6]
m42a[25D3]
m42a[25D6]
m42a[25D4]
m42a[25D3]
m42a[25B6]
m42a[25C3]
m42a[25B3]
m42a[25B4]
m42a[25B3]
m42a[25B3]
m42a[25A4]
m42a[25A3]
m42a[25A3]
m42a[25A3]
m42a[25A3]
m42a[25D1]
m42a[25C1]
m42a[25C1]
m42a[25D1]
m42a[26D4]
m42a[26B5]
m42a[26C7]
m42a[26C7]
m42a[26D4]
m42a[26B8]
m42a[26B3]
m42a[28D7]
m42a[28B2]
m42a[28B2]
m42a[28B2]
m42a[28B1]
m42a[28B1]
m42a[28B2]
m42a[28B2]
m42a[28B1]
m42a[28B1]
m42a[28D7]
m42a[28A7]
m42a[28A7]
m42a[28B2]
m42a[28B2]
m42a[28B1]
m42a[29D7]
m42a[29B2]
m42a[29B2]
m42a[29B2]
m42a[29B1]
m42a[29B1]
m42a[29B2]
m42a[29B2]
m42a[29B1]
m42a[29B1]
m42a[29D7]
m42a[29A7]
m42a[29A7]
m42a[29B2]
m42a[29B2]
m42a[29B1]
m42a[30D4]
m42a[30D3]
m42a[30D4]
m42a[30D3]
m42a[30D4]
m42a[30D3]
m42a[30C4]
m42a[30C3]
m42a[30C4]
m42a[30C3]
m42a[30C4]
m42a[30C3]
m42a[30B4]
m42a[30B3]
m42a[30B4]
m42a[30B3]
m42a[30B4]
m42a[30B3]
m42a[30B4]
m42a[30B3]
m42a[30A4]
m42a[30A3]
m42a[30A4]
m42a[30A3]
m42a[30A4]
m42a[30A3]
m42a[31C4]
m42a[31B5]
m42a[31B3]
m42a[31B5]
m42a[31C4]
m42a[31B4]
m42a[32D6]
m42a[32D6]
m42a[32D6]
m42a[32D6]
m42a[32D4]
m42a[32D4]
m42a[32C4]
m42a[32D4]
m42a[32D4]
m42a[32D3]
m42a[32C6]
m42a[32C6]
m42a[32D8]
m42a[32D7]
m42a[32D7]
m42a[32D4]
m42a[32C7]
m42a[32C7]

C3804
C3805
C3806
C3875
C3876
C3900
C3901
C3902
C3903
C3920
C3921
C3922
C3923
C3950
C4100
C4101
C4102
C4103
C4104
C4105
C4106
C4107
C4110
C4111
C4112
C4113
C4115
C4116
C4117
C4118
C4126
C4127
C4128
C4129
C4130
C4131
C4132
C4133
C4134
C4135
C4136
C4137
C4138
C4139
C4140
C4150
C4151
C4200
C4201
C4202
C4203
C4204
C4205
C4206
C4207
C4210
C4211
C4212
C4411
C4412
C4416
C4417
C4418
C4420
C4422
C4424
C4425
C4426
C4428
C4429
C4430
C4432
C4500
C4501
C4510
C4520
C4521
C4522
C4523
C4524
C4525
C4551
C4552
C4590
C4900
C4910
C5100
C5101
C5102
C5202
C5203
C5206
C5207
C5208
C5209
C5210
C5211
C5212
C5213
C5250
C5251
C5300
C5301
C5304
C5305
C5306
C5307
C5308
C5309
C5310
C5498
C5499
C5802
C5803
C5804
C5805
C5806
C5807
C5820
C5900
C5901
C5910
C5911
C5920

m42a[34B5]
m42a[34B3]
m42a[34B3]
m42a[34C7]
m42a[34C5]
m42a[35D6]
m42a[35D5]
m42a[35C6]
m42a[35D5]
m42a[35C7]
m42a[35C6]
m42a[35C5]
m42a[35C6]
m42a[35B8]
m42a[36D6]
m42a[36D6]
m42a[36D5]
m42a[36D5]
m42a[36D5]
m42a[36D5]
m42a[36D4]
m42a[36D4]
m42a[36D5]
m42a[36D5]
m42a[36C5]
m42a[36C5]
m42a[36B4]
m42a[36B4]
m42a[36B3]
m42a[36B3]
m42a[36A8]
m42a[36A8]
m42a[36A7]
m42a[36A7]
m42a[36A7]
m42a[36A6]
m42a[36A6]
m42a[36A6]
m42a[36A6]
m42a[36A5]
m42a[36A5]
m42a[36A4]
m42a[36A4]
m42a[36A4]
m42a[36B3]
m42a[36B6]
m42a[36B6]
m42a[37C7]
m42a[37C6]
m42a[37C6]
m42a[37C6]
m42a[37C7]
m42a[37C6]
m42a[37C6]
m42a[37C6]
m42a[37A6]
m42a[37A6]
m42a[37A5]
m42a[38C2]
m42a[38C2]
m42a[38D4]
m42a[38D4]
m42a[38D4]
m42a[38C3]
m42a[38D4]
m42a[38D5]
m42a[38D3]
m42a[38D4]
m42a[38D3]
m42a[38D3]
m42a[38D3]
m42a[38D3]
m42a[39B5]
m42a[39A5]
m42a[39C3]
m42a[39B4]
m42a[39B3]
m42a[39A4]
m42a[39A3]
m42a[39A2]
m42a[39A2]
m42a[39A7]
m42a[39A7]
m42a[39C5]
m42a[40C4]
m42a[40C6]
m42a[41D6]
m42a[41D6]
m42a[41B5]
m42a[42C2]
m42a[42C2]
m42a[42B2]
m42a[42B2]
m42a[42C6]
m42a[42B6]
m42a[42C6]
m42a[42B6]
m42a[42C8]
m42a[42C8]
m42a[42C8]
m42a[42B8]
m42a[43B6]
m42a[43B6]
m42a[43D4]
m42a[43D4]
m42a[43D4]
m42a[43C4]
m42a[43C4]
m42a[43C3]
m42a[43C3]
m42a[44C5]
m42a[44C5]
m42a[45D3]
m42a[45D2]
m42a[45D2]
m42a[45D2]
m42a[45D1]
m42a[45D2]
m42a[45C3]
m42a[46D8]
m42a[46D8]
m42a[46A7]
m42a[46A7]
m42a[46C6]

C5921
C5951
C5965
C5966
C5967
C5977
C6100
C6101
C6102
C6103
C6104
C6105
C6112
C6150
C6200
C6201
C6202
C6250
C6251
C6252
C6301
C6308
C6309
C6311
C6312
C6604
C6605
C6606
C6620
C6700
C6701
C6702
C6703
C6795
C6796
C6800
C6801
C6802
C6803
C6804
C6805
C6806
C6807
C6810
C6812
C6813
C6821
C6822
C6823
C6825
C6830
C6833
C6835
C6836
C6853
C7200
C7201
C7202
C7203
C7204
C7205
C7206
C7207
C7208
C7209
C7210
C7211
C7220
C7221
C7230
C7231
C7260
C7261
C7270
C7271
C7280
C7281
C7300
C7301
C7302
C7303
C7304
C7305
C7306
C7307
C7308
C7350
C7351
C7352
C7353
C7354
C7355
C7356
C7357
C7370
C7371
C7372
C7400
C7401
C7402
C7404
C7411
C7412
C7414
C7430
C7431
C7432
C7433
C7435
C7440
C7441
C7445
C7446
C7447
C7450
C7451
C7452
C7500
C7501
C7502
C7503
C7504
C7505
C7506

CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_P_CASE-B3-LF
CAP_P_CASE-B3-LF
CAP_P_SMA-LF
CAP_603
CAP_603
CAP_P_SMA-LF
CAP_P_SMA-LF
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_P_SMC-LF
CAP_P_CASE-B3-LF
CAP_603
CAP_P_CASE-B3-LF
CAP_603
CAP_P_CASE-B2
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_P_B2
CAP_P_B2
CAP_805-1
CAP_805-1
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_P_CASED2E-SM
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402

m42a[46C6]
m42a[46A4]
m42a[46B8]
m42a[46B7]
m42a[46B7]
m42a[46C2]
m42a[48D3]
m42a[48C3]
m42a[48C2]
m42a[48C3]
m42a[48D4]
m42a[48C4]
m42a[48B2]
m42a[48C6]
m42a[49C5]
m42a[49C5]
m42a[49D4]
m42a[49B5]
m42a[49A5]
m42a[49B4]
m42a[50C2]
m42a[50C5]
m42a[50C6]
m42a[50C2]
m42a[50D3]
m42a[52B4]
m42a[52B4]
m42a[52B4]
m42a[52C4]
m42a[53C4]
m42a[53C4]
m42a[53C3]
m42a[53C3]
m42a[53C6]
m42a[53B6]
m42a[54D6]
m42a[54D6]
m42a[54D4]
m42a[54D3]
m42a[54B4]
m42a[54B4]
m42a[54B3]
m42a[54B3]
m42a[54B2]
m42a[54B4]
m42a[54B3]
m42a[54C6]
m42a[54A5]
m42a[54A5]
m42a[54A4]
m42a[54D4]
m42a[54B2]
m42a[54D6]
m42a[54D3]
m42a[54B4]
m42a[55D6]
m42a[55C4]
m42a[55C4]
m42a[55B4]
m42a[55B4]
m42a[55B4]
m42a[55B4]
m42a[55C5]
m42a[55B5]
m42a[55A5]
m42a[55C6]
m42a[55C5]
m42a[55B6]
m42a[55B5]
m42a[55A6]
m42a[55A5]
m42a[55D2]
m42a[55C2]
m42a[55C2]
m42a[55B2]
m42a[55B2]
m42a[55B2]
m42a[56C7]
m42a[56C5]
m42a[56C5]
m42a[56C5]
m42a[56C5]
m42a[56C5]
m42a[56C8]
m42a[56C6]
m42a[56C6]
m42a[56A7]
m42a[56A7]
m42a[56A5]
m42a[56A5]
m42a[56A5]
m42a[56A5]
m42a[56A5]
m42a[56A8]
m42a[56A2]
m42a[56A2]
m42a[56A1]
m42a[57B4]
m42a[57D7]
m42a[57C7]
m42a[57C4]
m42a[57B7]
m42a[57B6]
m42a[57C4]
m42a[57D2]
m42a[57C2]
m42a[57B2]
m42a[57A2]
m42a[57B1]
m42a[57A4]
m42a[57A4]
m42a[57A3]
m42a[57A3]
m42a[57A3]
m42a[57A6]
m42a[57A7]
m42a[57A6]
m42a[58C4]
m42a[58C3]
m42a[58B4]
m42a[58C2]
m42a[58B2]
m42a[58C8]
m42a[58B8]

y
r

a
n
i

m
il

e
r

CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_1808
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603-1
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_P_B2
CAP_P_B2
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_603
CAP_805
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402

105

C7507
C7508
C7509
C7510
C7511
C7512
C7513
C7514
C7515
C7516
C7517
C7518
C7521
C7526
C7527
C7528
C7529
C7530
C7531
C7532
C7533
C7534
C7535
C7590
C7592
C7596
C7599
C7600
C7601
C7602
C7604
C7605
C7607
C7608
C7609
C7621
C7622
C7624
C7625
C7626
C7628
C7629
C7630
C7631
C7632
C7640
C7641
C7650
C7651
C7652
C7661
C7662
C7664
C7665
C7666
C7668
C7669
C7670
C7680
C7681
C7689
C7690
C7691
C7692
C7700
C7701
C7702
C7703
C7704
C7705
C7720
C7721
C7750
C7800
C7801
C7802
C7803
C7804
C7805
C7806
C7807
C7808
C7809
C7810
C7830
C7831
C7840
C7841
C7842
C7843
C7864
C7900
C7901
C7902
C7903
C7904
C7905
C7906
C7907
C7908
C7909
C7921
C7922
C7924
C7925
C7926
C7928
C7929
C7930
C7931
C7932
C7940
C7941
C7950
C7952
C7961
C7962
C7964
C7965
C7966
C7968
C7969
C7970
C7980

CAP_402
CAP_P_CASED2E-SM
CAP_P_CASED2E-SM
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_P_CASED2E-SM
CAP_603
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_603
CAP_603
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_P_CASED2E-SM
CAP_603
CAP_805
CAP_805
CAP_P_SMC-LF
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_P_CASED2E-SM
CAP_603
CAP_402
CAP_805
CAP_805
CAP_P_SMC-LF
CAP_603
CAP_402
CAP_603
CAP_603
CAP_402
CAP_603
CAP_402
CAP_603
CAP_402
CAP_603
CAP_603
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_P_CASED2E-SM
CAP_603
CAP_805
CAP_805
CAP_P_CASE-D2E-LF
CAP_P_CASE-D2E-LF
CAP_402
CAP_603
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_P_CASED2E-SM
CAP_603
CAP_805
CAP_P_CASE-D2E-LF
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_P_CASED2E-SM

7
m42a[58B7]
m42a[58C3]
m42a[58D3]
m42a[58C8]
m42a[58B3]
m42a[58C3]
m42a[58B7]
m42a[58B8]
m42a[58C5]
m42a[58B4]
m42a[58D3]
m42a[58D2]
m42a[58A6]
m42a[58D7]
m42a[58C5]
m42a[58B5]
m42a[58B5]
m42a[58C7]
m42a[58B5]
m42a[58B6]
m42a[58B6]
m42a[58B5]
m42a[58D6]
m42a[58C3]
m42a[58B3]
m42a[58D7]
m42a[58C2]
m42a[59C4]
m42a[59A4]
m42a[59A4]
m42a[59A2]
m42a[59A5]
m42a[59A3]
m42a[59D2]
m42a[59D7]
m42a[59B6]
m42a[59C5]
m42a[59C6]
m42a[59B6]
m42a[59B6]
m42a[59B7]
m42a[59B7]
m42a[59B5]
m42a[59C7]
m42a[59C2]
m42a[59D6]
m42a[59D6]
m42a[59B7]
m42a[59B8]
m42a[59B8]
m42a[59B3]
m42a[59C4]
m42a[59C3]
m42a[59B4]
m42a[59B3]
m42a[59B2]
m42a[59B2]
m42a[59B4]
m42a[59D3]
m42a[59D4]
m42a[59B4]
m42a[59B2]
m42a[59B1]
m42a[59B1]
m42a[60C4]
m42a[60C3]
m42a[60C3]
m42a[60C4]
m42a[60C3]
m42a[60C3]
m42a[60B4]
m42a[60B3]
m42a[60C6]
m42a[61C5]
m42a[61C6]
m42a[61C5]
m42a[61B2]
m42a[61C2]
m42a[61C2]
m42a[61B7]
m42a[61B6]
m42a[61B6]
m42a[61C4]
m42a[61B4]
m42a[61C4]
m42a[61C4]
m42a[61B3]
m42a[61B3]
m42a[61B3]
m42a[61B2]
m42a[61C2]
m42a[62C4]
m42a[62A4]
m42a[62A4]
m42a[62A6]
m42a[62A2]
m42a[62A5]
m42a[62A6]
m42a[62A3]
m42a[62D2]
m42a[62C7]
m42a[62B6]
m42a[62C5]
m42a[62C6]
m42a[62B6]
m42a[62B6]
m42a[62B7]
m42a[62B7]
m42a[62B5]
m42a[62C7]
m42a[62C2]
m42a[62C6]
m42a[62C6]
m42a[62B8]
m42a[62B8]
m42a[62B3]
m42a[62C4]
m42a[62C3]
m42a[62B3]
m42a[62B3]
m42a[62B2]
m42a[62B2]
m42a[62B4]
m42a[62C4]

C7981
C7989
C7990
C7991
C7992
C7999
C8000
C8005
C8010
C8015
C8025
C8060
C8061
C8062
C8090
C8091
C8092
C8093
C8202
C8203
C8205
C8206
C8209
C8211
C8215
C8217
C8218
C8220
C8221
C8230
C8300
C8301
C8302
C8303
C8304
C8305
C8306
C8307
C8308
C8309
C8310
C8311
C8312
C8313
C8316
C8317
C8318
C8320
C8321
C8322
C8323
C8324
C8325
C8326
C8327
C8328
C8340
C8341
C8370
C8371
C8372
C8375
C8381
C9400
C9401
C9402
C9403
C9408
C9409
C9410
C9411
C9412
C9413
C9414
C9415
C9416
C9459
C9500
C9501
C9502
C9503
C9504
C9505
C9506
C9507
C9508
C9509
C9510
C9511
C9512
C9513
C9514
C9519
C9520
C9521
C9522
C9523
C9524
C9525
C9526
C9527
C9530
C9531
C9532
C9533
C9534
C9535
C9536
C9537
C9538
C9539
C9540
C9541
C9542
C9543
C9544
C9545
C9546
C9547
C9548
C9804
C9808
C9809
C9812

CAP_603
CAP_402
CAP_805
CAP_805
CAP_P_CASE-D2E-LF
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_1206-1
CAP_402
CAP_402
CAP_805
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_1206-1
CAP_1206-1
CAP_1206-1
CAP_P_CASED2E-SM
CAP_P_6.3X5.5SM1
CAP_P_CASED2E-SM
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_603
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402

m42a[62C4]
m42a[62B4]
m42a[62A7]
m42a[62A7]
m42a[62B1]
m42a[62A6]
m42a[63D4]
m42a[63C4]
m42a[63C4]
m42a[63B4]
m42a[63A4]
m42a[63B3]
m42a[63B2]
m42a[63B2]
m42a[63C3]
m42a[63D2]
m42a[63D1]
m42a[63D1]
m42a[65D7]
m42a[65C7]
m42a[65A5]
m42a[65A4]
m42a[65A5]
m42a[65A5]
m42a[65A4]
m42a[65C2]
m42a[65C4]
m42a[65A7]
m42a[65A7]
m42a[65C6]
m42a[66C7]
m42a[66C7]
m42a[66C7]
m42a[66C4]
m42a[66C5]
m42a[66C4]
m42a[66C3]
m42a[66C3]
m42a[66B4]
m42a[66B3]
m42a[66B3]
m42a[66C7]
m42a[66C5]
m42a[66C6]
m42a[66B4]
m42a[66B5]
m42a[66B4]
m42a[66B5]
m42a[66B5]
m42a[66B4]
m42a[66A5]
m42a[66A4]
m42a[66C7]
m42a[66C7]
m42a[66D7]
m42a[66B6]
m42a[66C7]
m42a[66B8]
m42a[66C3]
m42a[66C2]
m42a[66B1]
m42a[66B3]
m42a[66B3]
m42a[67C3]
m42a[67C3]
m42a[67C3]
m42a[67C3]
m42a[67A3]
m42a[67B2]
m42a[67A3]
m42a[67B5]
m42a[67B5]
m42a[67B6]
m42a[67D5]
m42a[67A3]
m42a[67A4]
m42a[67C5]
m42a[68D5]
m42a[68D4]
m42a[68D4]
m42a[68D4]
m42a[68D4]
m42a[68B2]
m42a[68C7]
m42a[68D5]
m42a[68D5]
m42a[68D4]
m42a[68D4]
m42a[68D4]
m42a[68D3]
m42a[68D3]
m42a[68D7]
m42a[68B6]
m42a[68B6]
m42a[68B3]
m42a[68D2]
m42a[68D2]
m42a[68C2]
m42a[68C2]
m42a[68C3]
m42a[68C1]
m42a[68D7]
m42a[68D7]
m42a[68C7]
m42a[68C7]
m42a[68C7]
m42a[68C7]
m42a[68D7]
m42a[68D7]
m42a[68D7]
m42a[68D7]
m42a[68D6]
m42a[68B5]
m42a[68B5]
m42a[68B5]
m42a[68B5]
m42a[68B5]
m42a[68B4]
m42a[68B4]
m42a[68B4]
m42a[69C4]
m42a[69C5]
m42a[69B5]
m42a[69B5]

C9820
C9821
C9824
C9834
C9839
C9842
C9843
C9860
D1986
D2502
D2600
D4520
D4521
D4550
D4590
D4591
D4900
D5200
D5201
D7500
D7501
D7624
D7664
D7820
D7921
D7924
D7961
D7964
D8200
D8201
D8201
D8300
D8322
D9500
DZ7300
DZ7301
DZ7350
DZ7351
F8200
F8300
F9804
FL4520
FL4521
FL4590
FL9800

m42a[69A4]
m42a[69A3]
m42a[69B5]
m42a[69A4]
m42a[69B7]
m42a[69C1]
m42a[69C1]
m42a[69C2]
m42a[19C2 19D2]
m42a[25C8 25D8]
m42a[26D5 26D5]
m42a[39B4 39B3]
m42a[39A4 39A3]
m42a[39A6]
m42a[39D4]
m42a[39C5 39C5 39C5]
m42a[40C6]
m42a[42C3]
m42a[42A3]
m42a[58C3]
m42a[58B3]
m42a[59C6]
m42a[59C3]
m42a[61B4]
m42a[62B7]
m42a[62C6]
m42a[62B2]
m42a[62C3]
m42a[65C7]

m42a[56C6]
m42a[56C6]
m42a[56A6]
m42a[56A6]
m42a[65D6]
m42a[66C3]
m42a[69C5]
m42a[39B3]
m42a[39B3]
m42a[39D5]
m42a[69B5]

FL9802
GV3901
GV3902
GV3903
GV3904
GV3905
GV3906
GV3907
GV3908
J1102
J2600
J2801
J2901
J3801
J3901
J4200
J4500
J4900
J5200
J5201
J5300
J5400
J6000
J6250
J6251
J6501
J7300
J7301
J7302
J7303
J7350
J8200
J8250
J9400
J9401
J9801

m42a[69A5]
m42a[69A5]
m42a[35C2]
m42a[35C2]
m42a[35C2]
m42a[35C2]
m42a[35B2]
m42a[35B2]
m42a[35B2]
m42a[35B2]
m42a[11B2]
m42a[26D6]
m42a[28D6]
m42a[29D5]
m42a[34C4]
m42a[35D8]
m42a[37C2]
m42a[39B2]
m42a[40C4]
m42a[42D1]
m42a[42B1]
m42a[43C5]
m42a[44C4]
m42a[47C6]
m42a[49C6]

L1922
L1934
L1936
L1970
L1975
L1985
L1990
L2500
L2507
L3301
L3302
L3901
L3902
L3912
L4100
L4250
L4400
L4510
L4550
L4900
L4901
L4902
L5200
L5201
L5202
L5203
L5204
L5205
L5400
L5410
L5411
L5910
L6800
L6801
L7200
L7210
L7211
L7220
L7230
L7300
L7301
L7302
L7303
L7304
L7305
L7306
L7307
L7350
L7351
L7352
L7353
L7354
L7355
L7356
L7357
L7370
L7371
L7372
L7373
L7374
L7375
L7390
L7400
L7500
L7501
L7620
L7680
L7820
L7920
L7960
L8090
L8201
L8202
L8203
L8204
L8205
L8207
L8208
L8209
L8300
L9400
L9401
L9402
L9403
L9404
L9405
L9407
L9408
L9500
L9501
L9503
L9504
L9505
L9506
L9804
L9805
L9806
L9807
L9844
Q2680

IND_0603
IND_0603
IND_0603
IND_1210
IND_0805
IND_0603
IND_0603
IND_SM-3
IND_1206
IND_0402-LF
IND_0402-LF
FILTER_4P_2012H
FILTER_4P_2012H
IND_0402
IND_0402-LF
IND_0402-LF
IND_0402
IND_SM
IND_SM-1
IND_0402
FILTER_4P_SM
IND_0402
FILTER_4P_SM
FILTER_4P_SM
IND_0402-LF
IND_0402-LF
IND_0402-LF
IND_0402-LF
FILTER_4P_SM
IND_0402-LF
IND_0402-LF
IND_0603
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402-LF
IND_0402-LF
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_0402
IND_SM
IND_SM
IND_L812HW
IND_SM
IND_3P_SM
IND_SM
IND_3P_SM
IND_CDPH4D19F-SM
IND_SM-LF
IND_0402-LF
IND_0402-LF
IND_0402-LF
IND_SM-LF
IND_0402
IND_0402
IND_0402
IND_3P_SM
IND_0402-LF
IND_0402-LF
IND_0402-LF
IND_0402-LF
IND_0402-LF
IND_0402-LF
FILTER_4P_SM
IND_0402-LF
IND_0402-LF
IND_0402-LF
IND_0402-LF
IND_0402-LF
IND_0402-LF
IND_0402-LF
FILTER_4P_SM1
FILTER_4P_2012H
FILTER_4P_2012H
FILTER_4P_2012H
IND_SM-1
TRA_SINGLE_MOSFET_NC
HN_SOT23
TRA_FDC638P_SM-LF
TRA_2N7002DW_SOT-363
TRA_FDC638P_SM-LF
TRA_2N7002_SOT23-LF
TRA_2N7002DW_SOT-363
TRA_2N3906_SOT23-LF
TRA_2N7002_SOT23-LF
TRA_SI3446DV_TSOP-LF
TRA_2N7002DW_SOT-363
TRA_TP0610_S0T23-3
TRA_2N7002_SOT23-LF
TRA_TP0610_S0T23-3
TRA_TP0610_S0T23-3
TRA_BC846BM3T5G_NPN_
SOT732-3
TRA_2N7002_SOT23-LF
TRA_2N7002_SOT23-LF
TRA_TP0610_S0T23-3
TRA_2N7002DW_SOT-363
TRA_2N7002DW_SOT-363
TRA_2N7002DW_SOT-363
TRA_HAT2168H_LFPAK
TRA_HAT2165H_LFPAK

m42a[49A6]
Q3810
Q3875
Q4590
Q4591
Q5901
Q5950
Q5952
Q6100
Q6101
Q6150
Q6151
Q6152
Q6153
Q6200

m42a[51C3]
m42a[56C8]
m42a[56D1]
m42a[56D1]
m42a[56C1]
m42a[56B8]
m42a[65D7]
m42a[65B6]

Q6560
Q6650
Q6651
Q7400
Q7401
Q7402
Q7500
Q7501

m42a[67D2]
m42a[67B1]
m42a[69B4]

m42a[19A7]
m42a[19C5]
m42a[19C5]
m42a[19B4]
m42a[19A4]
m42a[19D3]
m42a[19C3]
m42a[25B8]
m42a[25A7]
m42a[32D7]
m42a[32D3]
m42a[35D6]
m42a[35D5]
m42a[35C6]
m42a[36D3]
m42a[37D7]
m42a[38D4]
m42a[39C3]
m42a[39A7]
m42a[40D5]
m42a[40C6]
m42a[40C5]
m42a[42C4]
m42a[42B4]
m42a[42D4]
m42a[42C4]
m42a[42C3]
m42a[42A3]
m42a[44B5]
m42a[44C5]
m42a[44B5]
m42a[46A7]
m42a[54A5]
m42a[54D6]
m42a[55C7]
m42a[55C7]
m42a[55A7]
m42a[55B7]
m42a[55A7]
m42a[56D6]
m42a[56D4]
m42a[56D6]
m42a[56C6]
m42a[56C4]
m42a[56C6]
m42a[56C4]
m42a[56C6]
m42a[56B6]
m42a[56B4]
m42a[56B6]
m42a[56B6]
m42a[56B4]
m42a[56B6]
m42a[56B4]
m42a[56A6]
m42a[56B2]
m42a[56B1]
m42a[56B2]
m42a[56B1]
m42a[56B2]
m42a[56B1]
m42a[56D8]
m42a[57B4]
m42a[58D2]
m42a[58B2]
m42a[59B7]
m42a[59B2]
m42a[61B3]
m42a[62B7]
m42a[62B2]
m42a[63D1]
m42a[65A3]
m42a[65A3]
m42a[65A3]
m42a[65A3]
m42a[65A3]
m42a[65A7]
m42a[65A7]
m42a[65A7]
m42a[66C4]
m42a[67D4]
m42a[67C4]
m42a[67D4]
m42a[67D4]
m42a[67B4]
m42a[67A4]
m42a[67A4]
m42a[67B4]
m42a[68D5]
m42a[68D5]
m42a[68D8]
m42a[68C8]
m42a[68C8]
m42a[68D8]
m42a[69A2]
m42a[69B2]
m42a[69B2]
m42a[69B2]
m42a[69C4]
m42a[26A3]

y
r

a
n
i

m42a[65D4]
m42a[66B3]
m42a[66C5]
m42a[66C8 66A5 66A6]
m42a[68A7 68B7]

m
il
FL9801

e
r

CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
CAP_402
DIODE_SCHOT_6PB_SOT363
DIODE_SCHOT_6PB_SOT363
DIODE_SCHOT_6PB_SOT363
DIODE_DUAL_6P_SOT-36
3
DIODE_DUAL_6P_SOT-36
3
ZENER_SOT23
DIODE_SCHOT_SMB
DPAK3P_SOT-363
DIODE_SCHOT_3P_A_SC75
DIODE_SCHOT_3P_A_SC75
DIODE_SCHOT_3P_A_SC75
DIODE_SCHOT_SMB
DIODE_SCHOT_SMB
DIODE_SCHOT_SOD-323
DIODE_SCHOT_SOD-323
DIODE_SCHOT_SMB
DIODE_SMB
DIODE_SCHOT_SOD-323
DIODE_SMB
DIODE_SCHOT_SOD-323
DIODE_SCHOT_3P_A_SC75
DPAK3P_SOT-363
DPAK3P_SOT-363
DIODE_SCHOT_SOD-123
DPAK3P_SOT-363
DIODE_DUAL_6P_SOT-36
3
SUPPR_TRANSIENT_4P1_
0405
SUPPR_TRANSIENT_4P1_
0405
SUPPR_TRANSIENT_4P1_
0405
SUPPR_TRANSIENT_4P1_
0405
FUSE_1206
FUSE_1206
FUSE_SM-LF
FILTER_4P_2012
FILTER_4P_2012
FUSE_MINISMDC
FILTER_LC_SM-220MHZLF
FILTER_LC_SM-220MHZLF
FILTER_LC_SM-220MHZLF
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
HOLE_VIA
CON_F30STSM_5047_SM1
CON_F2RT_S2MT_SM_F-R
T-SM
CON_F200RT_DDR2DIMM_
TH1_F-RT-TH2
CON_F200RT_DDR2DIMM_
TH1_F-RT-TH2
CON_M50ST_D2MT_SM_MST-SM
CON_F19ST_S2MT_SM_FST-SM
CON_RJ45_8RT_S2MT_SM
_F-RT-SM
CON_F6RT_S2MT_TH_F-R
T-TH1
CON_F10ST_D_SMA_F-ST
-SM
CON_F4RT_USB_S2MT_TH
_F-RT-TH-M42
CON_F4RT_USB_S2MT_TH
_F-RT-TH-M42
CON_F52RT_D2MT_SM_FST-SM
CON_F4ST_S2MT_SM_F-S
T-SM
CON_F30STSM_5047_SM1
CON_F2ST_S2MT_SM_F-S
T-SM
CON_F2ST_S2MT_SM_F-S
T-SM
CON_F4ST_S2MT_SM_F-S
T-SM
CON_F8RT_2MT_AUDIOOU
T_TH_F-RT-TH
CON_M3RT_S2MT_SM_M-R
T-SM1
CON_F2ST_S2MT_SM_F-S
T-SM
CON_F4ST_S2MT_SM_F-S
T-SM
CON_F8RT_2MT_AUDIOIN
_TH_F-RT-TH
CON_M5RT_S_SM_M-RT-S
M
CON_F20ST_D_SM_F-STSM1
CON_F4ST_S2MT_SM_F-S
T-SM
CON_F22RT_S4MT_SM_FRT-SM
CON_DVI_30RT_Q4MT_TH
1_RT-TH

m42a[34C5]
m42a[34C6 34C7]
m42a[39D5]
m42a[39C5]
m42a[46B4 46B5]
m42a[46A3]
m42a[46A3]
m42a[48A5]
m42a[48A6 48A7]
m42a[48C6]
m42a[48C7]
m42a[48C7]
m42a[48C8]
m42a[49B6]

m42a[51B3]
m42a[52B6]
m42a[52B6]
m42a[57C7 57D7]
m42a[57D5 57D6]
m42a[57B7 57C5]
m42a[58D3]
m42a[58D4]
106

8
Q7502
Q7503
Q7504
Q7505
Q7620
Q7621
Q7660
Q7661

Q7750
Q7820
Q7821
Q7920
Q7921
Q7960
Q7961
Q8000
Q8005
Q8010
Q8015

Q8025
Q8030
Q8031
Q8059
Q8060
Q8061
Q8062
Q8063
Q8210
Q8220
Q8240
Q8250
Q8298
Q8299
Q8300
Q8301
Q8302
Q8320
Q8321
Q8322
Q8324
Q8340
Q8350
Q9403
Q9404
Q9405
Q9406
Q9801
R0610
R0611
R0612
R0621
R0702
R0703
R0704
R0705
R0706
R0707
R0712
R0716
R0717
R0718
R0719
R0720
R0721
R0722
R0730
R0802
R0803
R0921
R0922
R0923
R0924
R0925
R0926
R0927
R1001
R1002
R1005
R1006
R1100
R1101
R1102
R1103
R1104
R1106
R1210
R1211
R1220
R1221
R1225
R1226
R1230
R1231
R1235
R1236
R1310
R1410
R1411
R1420
R1421
R1422
R1430
R1440
R1441
R1950
R1951
R1975
R1985
R1986
R1987
R1988
R1989
R1990
R2058
R2059
R2060
R2075
R2077

TRA_HAT2168H_LFPAK
TRA_HAT2165H_LFPAK
TRA_HAT2165H_LFPAK
TRA_HAT2165H_LFPAK
TRA_STL8NH3LL_COMBO_
PWRFLT-3P3X3P3
TRA_STL8NH3LL_COMBO_
PWRFLT-3P3X3P3
TRA_STL8NH3LL_COMBO_
PWRFLT-3P3X3P3
TRA_STL8NH3LL_COMBO_
PWRFLT-3P3X3P3
TRA_2N7002DW_SOT-363
TRA_IRF7821_SO-8
TRA_IRF7832_SO-8
TRA_IRF7821_SO-8
TRA_IRF7832_SO-8
TRA_IRF7821_SO-8
TRA_IRF7832_SO-8
TRA_FDC638P_SM-LF
TRA_STL8NH3LL_COMBO_
PWRFLT-3P3X3P3
TRA_FDC638P_SM-LF
TRA_STL8NH3LL_COMBO_
PWRFLT-3P3X3P3
TRA_SI3447BDV_SOT-6
TRA_2N7002DW_SOT-363
TRA_2N7002DW_SOT-363
TRA_2N7002DW_SOT-363
TRA_2N7002_SOT23-LF
TRA_2N7002DW_SOT-363
TRA_2N7002_SOT23-LF
TRA_2N7002_SOT23-LF
TRA_2N7002DW_SOT-363
TRA_2N7002DW_SOT-363
TRA_TP0610_S0T23-3
TRA_SI4405DY_SO-8
TRA_TP0610_S0T23-3
TRA_2N7002_SOT23-LF
TRA_SI4405DY_SO-8
TRA_HAT2168H_LFPAK
TRA_HAT2165H_LFPAK
TRA_SI4405DY_SO-8
TRA_SI4405DY_SO-8
TRA_2N7002DW_SOT-363
TRA_2N7002DW_SOT-363
TRA_IRLML5203_SM
TRA_2N7002_SOT23-LF
TRA_FDC638P_SM-LF
TRA_2N7002_SOT23-LF
TRA_TP0610_S0T23-3
TRA_2N7002_SOT23-LF
TRA_2N7002DW_SOT-363
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402

7
m42a[58C3]
m42a[58B4]
m42a[58D3]
m42a[58B3]
m42a[59C7]

R2079
R2085
R2100
R2101
R2105
R2107
R2108
R2110
R2194
R2195
R2196
R2197
R2198
R2199
R2200
R2203
R2204
R2205
R2206
R2207
R2208
R2211
R2223
R2225
R2226
R2250
R2251
R2255
R2299
R2300
R2302
R2303
R2305
R2306
R2307
R2308
R2309
R2310
R2311
R2312
R2313
R2314
R2315
R2316
R2317
R2318
R2319
R2320
R2323
R2326
R2327
R2343
R2388
R2389
R2390
R2395
R2396
R2397
R2398
R2399
R2500
R2501
R2502
R2600
R2606
R2607
R2609
R2610
R2611
R2612
R2622
R2636
R2637
R2638
R2639
R2640
R2641
R2642
R2643
R2680
R2681
R2682
R2683
R2684
R2685
R2687
R2688
R2689
R2696
R2697
R2698
R2700
R2701
R2750
R2751
R2760
R2761
R2770
R2771
R2780
R2781
R2782
R2783
R2800
R2801
R2900
R2901
R2902
R3001
R3009
R3011
R3025
R3035
R3100
R3104
R3300
R3301
R3302
R3303
R3304
R3400
R3401
R3402
R3403

m42a[59B7]
m42a[59C3]
m42a[59B3]
m42a[60C6 60C7]
m42a[61C4]
m42a[61B4]
m42a[62C6]
m42a[62B6]
m42a[62C3]
m42a[62B3]
m42a[63D4]
m42a[63C4]
m42a[63D4]
m42a[63C4]
m42a[63A4]
m42a[63A6 63B6]
m42a[63D6 63A6]
m42a[63C7 63C7]
m42a[63C8]
m42a[63B7 63B7]
m42a[63B8]
m42a[63B4]
m42a[65C6 65C3]
m42a[65C7 65C6]
m42a[65C5]
m42a[65D2]
m42a[65C7]
m42a[65C7]
m42a[66D5]
m42a[66C4]
m42a[66B4]
m42a[66B3]
m42a[66B3]
m42a[66A4 66A4]
m42a[66A3 66A4]
m42a[66C8]
m42a[66A6]
m42a[67B6]
m42a[67B7]
m42a[67D5]
m42a[67D6]
m42a[69D6 69D6]
m42a[6A7]
m42a[6A8]
m42a[6A8]
m42a[6A7]
m42a[7D5]
m42a[7C5]
m42a[7C5]
m42a[7B4]
m42a[7B4]
m42a[7A4]
m42a[7A4]
m42a[7B2]
m42a[7B2]
m42a[7B2]
m42a[7B2]
m42a[7B7]
m42a[7B7]
m42a[7A7]
m42a[7A4]
m42a[8B6]
m42a[8A7]
m42a[9D2]
m42a[9D2]
m42a[9C2]
m42a[9C2]
m42a[9C2]
m42a[9C2]
m42a[9C2]
m42a[10B6]
m42a[10B6]
m42a[10C4]
m42a[10C3]
m42a[11B5]
m42a[11C5]
m42a[11B4]
m42a[11C5]
m42a[11B5]
m42a[11A3]
m42a[12C3]
m42a[12C3]
m42a[12B7]
m42a[12B7]
m42a[12B7]
m42a[12B7]
m42a[12A7]
m42a[12A7]
m42a[12A7]
m42a[12A7]
m42a[13D3]
m42a[14C2]
m42a[14C2]
m42a[14C6]
m42a[14C6]
m42a[14B6]
m42a[14B6]
m42a[14D6]
m42a[14D6]
m42a[19D5]
m42a[19D5]
m42a[19A4]
m42a[19D3]
m42a[19C6]
m42a[19C6]
m42a[19C7]
m42a[19C7]
m42a[19C3]
m42a[20B4]
m42a[20B4]
m42a[20A4]
m42a[20C7]
m42a[20B7]

RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_603
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402

m42a[20B7]
m42a[20C4]
m42a[21C3]
m42a[21C4]
m42a[21D6]
m42a[21C2]
m42a[21C2]
m42a[21C2]
m42a[21D4]
m42a[21C6]
m42a[21C6]
m42a[21C6]
m42a[21C6]
m42a[21C3]
m42a[22D7]
m42a[22C2]
m42a[22C2]
m42a[22C6]
m42a[22C5]
m42a[22C5]
m42a[22D5]
m42a[22B3]
m42a[22D6]
m42a[22D7]
m42a[22D5]
m42a[22D7]
m42a[22D6]
m42a[22D7]
m42a[22B5]
m42a[23C7]
m42a[23D3]
m42a[23D3]
m42a[23D3]
m42a[23B7]
m42a[23A7]
m42a[23B7]
m42a[23A7]
m42a[23A7]
m42a[23A7]
m42a[23A3]
m42a[23A7]
m42a[23A7]
m42a[23A3]
m42a[23D7]
m42a[23D7]
m42a[23D7]
m42a[23D2]
m42a[23D7]
m42a[23D5]
m42a[23D6]
m42a[23D6]
m42a[23D1]
m42a[23B2]
m42a[23A4]
m42a[23B3]
m42a[23D7]
m42a[23D6]
m42a[23D6]
m42a[23D8]
m42a[23C1]
m42a[25A8]
m42a[25C8]
m42a[25D8]
m42a[26D4]
m42a[26D5]
m42a[26D5]
m42a[26C7]
m42a[26C7]
m42a[26B5]
m42a[26A5]
m42a[26A5]
m42a[26C2]
m42a[26C2]
m42a[26C2]
m42a[26C2]
m42a[26C2]
m42a[26C2]
m42a[26C2]
m42a[26C2]
m42a[26B3]
m42a[26B2]
m42a[26A2]
m42a[26B2]
m42a[26B2]
m42a[26B2]
m42a[26B2]
m42a[26A3]
m42a[26A2]
m42a[26C6]
m42a[26C5]
m42a[26C5]
m42a[27D7]
m42a[27D7]
m42a[27D4]
m42a[27D4]
m42a[27C4]
m42a[27C4]
m42a[27D2]
m42a[27D2]
m42a[27C2]
m42a[27C2]
m42a[27B2]
m42a[27B2]
m42a[28D2]
m42a[28D2]
m42a[29A4]
m42a[29D2]
m42a[29D2]
m42a[30D4]
m42a[30D4]
m42a[30C4]
m42a[30C4]
m42a[30B4]
m42a[31C5]
m42a[31C5]
m42a[32B6]
m42a[32B7]
m42a[32D4]
m42a[32C4]
m42a[32C7]
m42a[33C1]
m42a[33C7]
m42a[33C1]
m42a[33C1]

R3404
R3405
R3406
R3407
R3408
R3409
R3410
R3411
R3412
R3413
R3414
R3415
R3416
R3417
R3418
R3419
R3420
R3421
R3422
R3423
R3426
R3427
R3428
R3429
R3430
R3431
R3432
R3433
R3434
R3435
R3436
R3437
R3438
R3439
R3440
R3441
R3442
R3450
R3451
R3452
R3453
R3454
R3463
R3465
R3466
R3467
R3468
R3469
R3470
R3471
R3472
R3473
R3474
R3475
R3476
R3477
R3478
R3480
R3481
R3482
R3490
R3824
R3825
R3851
R3853
R3858
R3859
R3865
R3876
R3877
R3900
R3901
R3950
R4101
R4102
R4103
R4104
R4105
R4106
R4107
R4117
R4118
R4119
R4120
R4122
R4123
R4124
R4130
R4131
R4200
R4201
R4202
R4203
R4400
R4420
R4431
R4432
R4452
R4500
R4501
R4502
R4503
R4504
R4550
R4590
R4591
R4593
R4594
R4595
R4910
R5100
R5250
R5251
R5301
R5302
R5303
R5801
R5802
R5803
R5809
R5898
R5899
R5900
R5901

m42a[33D1]
m42a[33C1]
m42a[33B1]
m42a[33B1]
m42a[33C1]
m42a[33C1]
m42a[33C1]
m42a[33D4]
m42a[33D4]
m42a[33D4]
m42a[33D4]
m42a[33D4]
m42a[33D4]
m42a[33C7]
m42a[33B4]
m42a[33B4]
m42a[33A4]
m42a[33A4]
m42a[33C4]
m42a[33C4]
m42a[33C4]
m42a[33C4]
m42a[33C4]
m42a[33D8]
m42a[33D7]
m42a[33B1]
m42a[33D7]
m42a[33D8]
m42a[33D4]
m42a[33C4]
m42a[33B1]
m42a[33B1]
m42a[33D1]
m42a[33D1]
m42a[33D1]
m42a[33D1]
m42a[33C1]
m42a[33C7]
m42a[33B7]
m42a[33B7]
m42a[33B7]
m42a[33B7]
m42a[33D7]
m42a[33C4]
m42a[33A7]
m42a[33A7]
m42a[33C7]
m42a[33C7]
m42a[33C7]
m42a[33B7]
m42a[33B7]
m42a[33B7]
m42a[33B8]
m42a[33B7]
m42a[33A7]
m42a[33B4]
m42a[33B4]
m42a[33C7]
m42a[33B1]
m42a[33B1]
m42a[33A4]
m42a[34C4]
m42a[34C5]
m42a[34C4]
m42a[34C3]
m42a[34B5]
m42a[34B4]
m42a[34C6]
m42a[34C7]
m42a[34C6]
m42a[35D3]
m42a[35C3]
m42a[35B7]
m42a[36D8]
m42a[36C8]
m42a[36B4]
m42a[36B4]
m42a[36B4]
m42a[36B5]
m42a[36D8]
m42a[36B3]
m42a[36B3]
m42a[36B3]
m42a[36B4]
m42a[36A3]
m42a[36A2]
m42a[36A2]
m42a[36B6]
m42a[36B6]
m42a[37A6]
m42a[37A5]
m42a[37A5]
m42a[37A5]
m42a[38C3]
m42a[38C2]
m42a[38A6]
m42a[38A6]
m42a[38C3]
m42a[39B6]
m42a[39B6]
m42a[39B5]
m42a[39B5]
m42a[39A5]
m42a[39A7]
m42a[39C5]
m42a[39C5]
m42a[39C6]
m42a[39C6]
m42a[39C5]
m42a[40C6]
m42a[41C6]
m42a[42C8]
m42a[42C8]
m42a[43B4]
m42a[43B4]
m42a[43C4]
m42a[45D1]
m42a[45C1]
m42a[45C1]
m42a[45D2]
m42a[45C2]
m42a[45D3]
m42a[46D7]
m42a[46D8]

R5905
R5906
R5910
R5911
R5918
R5919
R5920
R5922
R5923
R5924
R5925
R5926
R5927
R5928
R5929
R5930
R5931
R5932
R5933
R5934
R5935
R5936
R5937
R5938
R5939
R5940
R5941
R5942
R5943
R5944
R5945
R5946
R5947
R5948
R5949
R5950
R5951
R5952
R5953
R5954
R5955
R5970
R5971
R5972
R5973
R5976
R5977
R5980
R5981
R5982
R5983
R5984
R5985
R5986
R5987
R5988
R5989
R5990
R5991
R5992
R5993
R5994
R5995
R5996
R5997
R5998
R5999
R6100
R6102
R6103
R6105
R6106
R6107
R6108
R6112
R6140
R6141
R6142
R6143
R6144
R6150
R6151
R6152
R6153
R6200
R6201
R6203
R6251
R6252
R6301
R6302
R6303
R6306
R6307
R6308
R6309
R6560
R6561
R6565
R6621
R6650
R6652
R6700
R6702
R6703
R6704
R6705
R6798
R6799
R6800
R6801
R6802
R6807
R6808
R6809
R6810
R6811
R6850
R6851
R6852
R6853
R6854
R7201
R7202

RES_402
RES_402
RES_603
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_1206
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_805
RES_805
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402

m42a[46D4]
m42a[46D4]
m42a[46C8]
m42a[46A6]
m42a[46C5]
m42a[46C5]
m42a[46C5]
m42a[46C5]
m42a[46C5]
m42a[46C4]
m42a[46C5]
m42a[46C4]
m42a[46C5]
m42a[46D4]
m42a[46C5]
m42a[46C5]
m42a[46C4]
m42a[46C4]
m42a[46C4]
m42a[46C5]
m42a[46C4]
m42a[46C5]
m42a[46C4]
m42a[46C5]
m42a[46C4]
m42a[46C5]
m42a[46C4]
m42a[46C5]
m42a[46B4]
m42a[46B4]
m42a[46C4]
m42a[46C4]
m42a[46B4]
m42a[46C5]
m42a[46C4]
m42a[46A3]
m42a[46A3]
m42a[46A3]
m42a[46D5]
m42a[46B5]
m42a[46B5]
m42a[46D3]
m42a[46D3]
m42a[46C7]
m42a[46C5]
m42a[46D1]
m42a[46C1]
m42a[46D5]
m42a[46D5]
m42a[46D5]
m42a[46C5]
m42a[46C5]
m42a[46C5]
m42a[46C5]
m42a[46C5]
m42a[46B5]
m42a[46D5]
m42a[46B2]
m42a[46B2]
m42a[46B2]
m42a[46B2]
m42a[46D5]
m42a[46D5]
m42a[46B4]
m42a[46B4]
m42a[46C4]
m42a[46C4]
m42a[48D3]
m42a[48C2]
m42a[48C3]
m42a[48D4]
m42a[48C4]
m42a[48D4]
m42a[48C4]
m42a[48B2]
m42a[48A7]
m42a[48A7]
m42a[48A6]
m42a[48A4]
m42a[48A6]
m42a[48C6]
m42a[48B6]
m42a[48C7]
m42a[48B7]
m42a[49C5]
m42a[49C5]
m42a[49D3]
m42a[49A5]
m42a[49B3]
m42a[50D4]
m42a[50D4]
m42a[50C3]
m42a[50C2]
m42a[50C5]
m42a[50D3]
m42a[50C5]
m42a[51C3]
m42a[51B4]
m42a[51C3]
m42a[52A5]
m42a[52B6]
m42a[52B7]
m42a[53C7]
m42a[53C4]
m42a[53C4]
m42a[53C2]
m42a[53C3]
m42a[53B6]
m42a[53B6]
m42a[54C6]
m42a[54B5]
m42a[54A5]
m42a[54D7]
m42a[54D3]
m42a[54C3]
m42a[54A4]
m42a[54A4]
m42a[54B7]
m42a[54B7]
m42a[54B7]
m42a[54A7]
m42a[54B4]
m42a[55C4]
m42a[55A4]

y
r

a
n
i

m
il

e
r

RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_603

107

R7210
R7260
R7261
R7270
R7271
R7280
R7281
R7300
R7301
R7320
R7321
R7322
R7349
R7350
R7351
R7380
R7382
R7391
R7401
R7402
R7403
R7404
R7405
R7406
R7411
R7412
R7413
R7414
R7415
R7430
R7431
R7432
R7433
R7434
R7435
R7436
R7437
R7438
R7439
R7440
R7450
R7451
R7452
R7453
R7454
R7460
R7461
R7500
R7501
R7502
R7503
R7504
R7505
R7506
R7507
R7508
R7509
R7510
R7511
R7512
R7513
R7514
R7515
R7516
R7517
R7518
R7519
R7520
R7521
R7522
R7523
R7524
R7525
R7526
R7527
R7530
R7531
R7543
R7545
R7600
R7603
R7604
R7606
R7607
R7621
R7624
R7625
R7626
R7627
R7628
R7629
R7630
R7661
R7664
R7665
R7666
R7667
R7668
R7669
R7670
R7720
R7721
R7750
R7751
R7752
R7753
R7800
R7801
R7802
R7803
R7804
R7805
R7806
R7807
R7808
R7810
R7821
R7822
R7860
R7861
R7863
R7900
R7901
R7902

RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_603
RES_603
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_805
RES_805
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
THERMISTER_402
RES_402
RES_402
THERMISTER_0603-LF
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_1206
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_603
RES_402
RES_402
RES_402
RES_402
RES_1206

7
m42a[55A7]
m42a[55D2]
m42a[55C2]
m42a[55C2]
m42a[55C2]
m42a[55B2]
m42a[55B2]
m42a[56C4]
m42a[56C4]
m42a[56B5]
m42a[56D7]
m42a[56B7]
m42a[56B7]
m42a[56A4]
m42a[56A4]
m42a[56C2]
m42a[56B2]
m42a[56C7]
m42a[57D8]
m42a[57D7]
m42a[57C7]
m42a[57C4]
m42a[57D5]
m42a[57D6]
m42a[57C8]
m42a[57B7]
m42a[57C6]
m42a[57C4]
m42a[57C5]
m42a[57C3]
m42a[57B3]
m42a[57B3]
m42a[57A3]
m42a[57C2]
m42a[57C2]
m42a[57B2]
m42a[57B2]
m42a[57C2]
m42a[57B2]
m42a[57A5]
m42a[57A7]
m42a[57A7]
m42a[57A7]
m42a[57A7]
m42a[57A7]
m42a[57C6]
m42a[57C7]
m42a[58C2]
m42a[58C2]
m42a[58B3]
m42a[58D3]
m42a[58C1]
m42a[58B2]
m42a[58C7]
m42a[58B1]
m42a[58B8]
m42a[58B8]
m42a[58B6]
m42a[58B8]
m42a[58D7]
m42a[58B7]
m42a[58B8]
m42a[58B5]
m42a[58B4]
m42a[58B5]
m42a[58B5]
m42a[58C7]
m42a[58D7]
m42a[58D8]
m42a[58A5]
m42a[58A6]
m42a[58D5]
m42a[58C5]
m42a[58C7]
m42a[58C8]
m42a[58B4]
m42a[58B4]
m42a[58B2]
m42a[58C7]
m42a[59C5]
m42a[59A3]
m42a[59A3]
m42a[59A3]
m42a[59A3]
m42a[59C7]
m42a[59C6]
m42a[59B6]
m42a[59C7]
m42a[59B7]
m42a[59B7]
m42a[59C7]
m42a[59C5]
m42a[59C2]
m42a[59C3]
m42a[59B4]
m42a[59C2]
m42a[59B2]
m42a[59B2]
m42a[59C2]
m42a[59C4]
m42a[60B3]
m42a[60A3]
m42a[60C6]
m42a[60C7]
m42a[60C7]
m42a[60B7]
m42a[61C4]
m42a[61B2]
m42a[61C3]
m42a[61C2]
m42a[61C7]
m42a[61B7]
m42a[61B7]
m42a[61C5]
m42a[61B6]
m42a[61B4]
m42a[61B2]
m42a[61B2]
m42a[61C3]
m42a[61C2]
m42a[61C2]
m42a[62C5]
m42a[62B1]
m42a[62A7]

R7903
R7904
R7905
R7906
R7907
R7921
R7924
R7925
R7926
R7927
R7928
R7929
R7930
R7961
R7964
R7965
R7966
R7967
R7968
R7969
R7970
R7990
R7991
R7992
R8000
R8005
R8010
R8015
R8025
R8030
R8031
R8032
R8033
R8050
R8056
R8057
R8058
R8059
R8061
R8062
R8063
R8064
R8065
R8091
R8092
R8200
R8201
R8202
R8203
R8204
R8205
R8206
R8207
R8208
R8209
R8210
R8211
R8213
R8214
R8231
R8232
R8233
R8296
R8297
R8298
R8299
R8300
R8301
R8302
R8303
R8304
R8305
R8306
R8308
R8309
R8310
R8311
R8312
R8320
R8322
R8323
R8324
R8325
R8330
R8331
R8340
R8341
R8342
R8343
R8344
R8350
R8351
R8352
R8360
R8361
R8362
R8363
R8364
R8365
R8367
R8370
R8371
R8381
R8397
R9400
R9401
R9402
R9408
R9409
R9413
R9414
R9415
R9416
R9423
R9428
R9500
R9501
R9502
R9503
R9504
R9505
R9506
R9507
R9508

RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_603
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_805
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_805
RES_402
RES_402
RES_0612
RES_402
RES_402
RES_402
RES_402
RES_2525
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_603
RES_0612
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402

m42a[62A3]
m42a[62A3]
m42a[62A6]
m42a[62A3]
m42a[62A3]
m42a[62C7]
m42a[62C6]
m42a[62B6]
m42a[62C7]
m42a[62B8]
m42a[62B8]
m42a[62C7]
m42a[62C5]
m42a[62C2]
m42a[62C3]
m42a[62B3]
m42a[62C2]
m42a[62B2]
m42a[62B2]
m42a[62C2]
m42a[62C4]
m42a[62A6]
m42a[62A6]
m42a[62A7]
m42a[63D5]
m42a[63C5]
m42a[63C5]
m42a[63B5]
m42a[63A5]
m42a[63B6]
m42a[63B6]
m42a[63D6]
m42a[63D6]
m42a[63A6]
m42a[63C8]
m42a[63C8]
m42a[63B8]
m42a[63B8]
m42a[63B1]
m42a[63B1]
m42a[63A1]
m42a[63A1]
m42a[63B2]
m42a[63D1]
m42a[63C1]
m42a[65B7]
m42a[65C5]
m42a[65C5]
m42a[65C6]
m42a[65C6]
m42a[65D4]
m42a[65C4]
m42a[65C4]
m42a[65C4]
m42a[65C4]
m42a[65C4]
m42a[65C6]
m42a[65C2]
m42a[65C2]
m42a[65C5]
m42a[65C6]
m42a[65C5]
m42a[65B7]
m42a[65C3]
m42a[65C8]
m42a[65C7]
m42a[66C6]
m42a[66C7]
m42a[66C5]
m42a[66C5]
m42a[66B2]
m42a[66C5]
m42a[66C7]
m42a[66C3]
m42a[66B6]
m42a[66C5]
m42a[66B7]
m42a[66C7]
m42a[66B3]
m42a[66A3]
m42a[66A3]
m42a[66A4]
m42a[66A5]
m42a[66B4]
m42a[66A4]
m42a[66C8]
m42a[66B8]
m42a[66C8]
m42a[66B8]
m42a[66B8]
m42a[66B5]
m42a[66B6]
m42a[66B5]
m42a[66D7]
m42a[66C7]
m42a[66B7]
m42a[66B6]
m42a[66B6]
m42a[66B6]
m42a[66C6]
m42a[66C2]
m42a[66B2]
m42a[66B4]
m42a[66C4]
m42a[67D6]
m42a[67D6]
m42a[67C7]
m42a[67B5]
m42a[67B5]
m42a[67A6]
m42a[67B7]
m42a[67B7]
m42a[67B7]
m42a[67B6]
m42a[67C5]
m42a[68A7]
m42a[68B6]
m42a[68B6]
m42a[68A4]
m42a[68B2]
m42a[68B2]
m42a[68B1]
m42a[68D2]
m42a[68D2]

R9509
R9510
R9537
R9538
R9539
R9540
R9821
R9822
R9850
R9851
R9852
R9853
R9854
R9855
R9856
R9859
R9860
R9861
R9862
R9863
R9864
R9868
R9869
R9870
R9871
RP2300
RP2600
RP2601
RP2602
RP3000
RP3001
RP3002
RP3003
RP3004
RP3005
RP3006
RP3007
RP3008
RP3009
RP3010
RP3011
T4201
T4202
U0700
U0700
U1001
U1200
U1200
U1200
U1200
U1200
U1200
U1200
U1900

m42a[68C2]
m42a[68C2]
m42a[68D1]
m42a[68D1]
m42a[68C1]
m42a[68C1]
m42a[69D7]
m42a[69D6]
m42a[69B8]
m42a[69B8]
m42a[69A8]
m42a[69A8]
m42a[69A8]
m42a[69A8]
m42a[69B6]
m42a[69A6]
m42a[69C3]
m42a[69C3]
m42a[69C5]
m42a[69C5]
m42a[69A6]
m42a[69C8]
m42a[69C8]
m42a[69C1]
m42a[69C1]
m42a[23D5]
m42a[26D2]
m42a[26D2]
m42a[26C2]
m42a[30B4 30C4
m42a[30C4 30A4
m42a[30A4 30A4
m42a[30C4 30C4
m42a[30C4 30C4
m42a[30B4 30A4
m42a[30B4 30B4
m42a[30C4 30C4
m42a[30C4 30C4
m42a[30B4 30B4
m42a[30B4 30B4
m42a[30B4 30A4
m42a[37C6]

XW7300
XW7301
XW7302
XW7303
XW7304
XW7305
XW7400
XW7500
XW7600
XW7620
XW7660
XW7800
XW7900
XW7920
XW8101
XW8102
XW8300
Y2600
Y3301
Y4101

SHORT_SM
SHORT_SM
SHORT_SM
SHORT_SM
SHORT_SM
SHORT_SM
SHORT_SM
SHORT_SM
SHORT_SM
JUMPER_OPEN-SAWTOOTH
JUMPER_OPEN-SAWTOOTH
SHORT_SM
SHORT_SM
JUMPER_OPEN-SAWTOOTH
SHORT_SM
SHORT_SM
SHORT_SM
CRYSTAL_4PIN_SM-LF
CRYSTAL_5X3.2-SM
CRYSTAL_4PIN_SM-3.2X
2.5MM
CRYSTAL_4PIN_SM-3.2X
2.5MM
CRYSTAL_5X3.2-SM
CRYSTAL_4PIN_SM-LF
MTGHOLE
MTGHOLE
PCB_STANDOFF
PCB_STANDOFF
PCB_STANDOFF
MTGHOLE
MTGHOLE
MTGHOLE
MTGHOLE
MTGHOLE
MTGHOLE
PCB_STANDOFF
PCB_STANDOFF
PCB_STANDOFF
SPRING_CLIP_1P_EMI_C
LIP-SM-M42
CLIP_SM

Y5920
Y6795
Z0601
Z0602
Z0603
Z0604
Z0605
Z0606
Z0607
Z0608
Z0609
Z0610
Z0611
Z0612
Z0613
Z0621
ZS0620

a
n
i

m42a[37B6]
m42a[7C3 7D7]
m42a[8D8 8D4]
m42a[10C5]
m42a[12D5]
m42a[13D4]
m42a[14D5]
m42a[15D3 15D7]
m42a[16D2 16C8]
m42a[17D5]
m42a[18D4 18D7]
m42a[19D6]

m42a[56C4]
m42a[56B4]
m42a[56C2]
m42a[56C2]
m42a[56B2]
m42a[56B7]
m42a[57A7]
m42a[58A6]
m42a[59A5]
m42a[59B8]
m42a[59B1]
m42a[61B5]
m42a[62A5]
m42a[62B8]
m42a[64B2]
m42a[64B2]
m42a[66B4]
m42a[26C7]
m42a[32C7]
m42a[36B6]

y
r

Y4403

30D4 30D4]
30A4 30D4]
30A4 30D4]
30C4 30D4]
30D4]
30A4 30D4]
30A4 30D4]
30C4 30C4]
30C4 30C4]
30C4 30C4]
30B4 30B4]
30B4 30B4]

ZS0621

m42a[38C2]
m42a[46C7]
m42a[53B6]
m42a[6B8]
m42a[6C6]
m42a[6A8]
m42a[6A6]
m42a[6A8]
m42a[6D6]
m42a[6C6]
m42a[6C6]
m42a[6B7]
m42a[6B6]
m42a[6B7]
m42a[6A6]
m42a[6A5]
m42a[6A6]
m42a[6D7]
m42a[6D6]

m
il
U1901
U2100
U2100
U2100
U2100
U2601
U2603
U2680
U3100
U3301
U4101
U4102
U4400
U5100
U5200
U5800
U5900
U5910
U5977

e
r

RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RES_402
RPAK4P_SM-LF
RPAK4P_SM-LF
RPAK4P_SM-LF
RPAK4P_SM-LF
RPAK4P_SM-LF
RPAK4P_SM-LF
RPAK4P_SM-LF
RPAK4P_SM-LF
RPAK4P_SM-LF
RPAK4P_SM-LF
RPAK4P_SM-LF
RPAK4P_SM-LF
RPAK4P_SM-LF
RPAK4P_SM-LF
RPAK4P_SM-LF
RPAK4P_SM-LF
XFR_1000BT_82400275_
XFR-SM
XFR_1000BT_82400275_
XFR-SM
CPU_YONAH_BGA
CPU_YONAH_BGA
ADT7461_MSOP
NB_945GM_BGA
NB_945GM_BGA
NB_945GM_BGA
NB_945GM_BGA
NB_945GM_BGA
NB_945GM_BGA
NB_945GM_BGA
LREG_TPS73115_SOT235
MM157_SOT23-5-LF
SB_ICH7M_BGA
SB_ICH7M_BGA
SB_ICH7M_BGA
SB_ICH7M_BGA
MC74VHC1G08_SC70
MC74VHC1G00_SC70-5
MC74VHC1G08_SC70
LREG_BD3533FVM_MSOP8
CLK_SYN_SLG8LP436_QF
N
88E8053_QFN
EEPROM_M24C08_SO8
FW32306_BGA_BGA
CY8C24794_MLF
SWI_TPS2042B_MSOP
SMC_H8S2116_BGA
VDET_RN5VD_SOT23-5
OSC_12P_SG-3040LC-SM
COMPARATOR_LMC7211_S
M-LF
OPAMP_LMV2011_SOT235
MAX6695_UMAX
MAX6695_UMAX
FLASH_SST25VF016B_SO
I_SOI
KXM52_QFN
LIS3L02AL_LGA
TPM_TSSOP
AUDIO_STAC92204XR_LQ
FP
MAX9705_TDFN1
MAX9705_TDFN1
MAX9705_TDFN1
MAX9890_UCSP1
ISL6262_QFN
LTC3728L_QFN
MAX8887_SOT23-5
MAX8887_SOT23-5
LREG_MAX8516_SOP
ISL6269_QFN
AMP_INA326_MSOP
LTC3728L_QFN
AMP_INA326_MSOP
LTC2908_LLP
MC74VHC1G08_SC70
LT3470_TSOT23-8
COMPARATOR_LMC7211_S
M-LF
MC74VHC1G08_SC70
COMPARATOR_LM397_SOT
23-5
ISL6255_QFN
INA193_SOT23-5
INA193_SOT23-5
MC74VHC1G08_SC70
SIL1362_LQFP
VIDEO_TS3V330_SOP
SN74LVC2G125_US
VREF_ISL6000233_SOT2
3-3
LREG_TPS79501_SOT223
-6
SHORT_SM
SHORT_SM

U6100
U6200
U6250
U6301
U6620
U6650
U6700
U6800
U7210
U7220
U7230
U7400
U7500
U7600
U7700
U7701
U7720
U7800
U7801
U7900
U7901
U8070
U8080
U8090
U8200
U8250
U8290

U8300
U8370
U8375
U9453
U9500
U9801
U9804
VR5965
VR6800
XW5800
XW7200

m42a[19C4]
m42a[21D6]
m42a[22B7 22D3]
m42a[23D4]
m42a[24D4 24D7]
m42a[26A5]
m42a[26A7]
m42a[26B3]
m42a[31C4]
m42a[32C5]

m42a[36D6]
m42a[36A3]
m42a[38C5]
m42a[41C5]
m42a[42C7]
m42a[45A8 45C3 45C7 45D7]
m42a[46D7]
m42a[46A7]
m42a[46C2]

m42a[48C3]
m42a[49D4]
m42a[49B4]
m42a[50D3]
m42a[52C5]
m42a[52B5]
m42a[53C5]
m42a[54D5]
m42a[55C5]
m42a[55B5]
m42a[55A5]
m42a[57C2]
m42a[58C6]
m42a[59C5]
m42a[60D4]
m42a[60C4]
m42a[60B3]
m42a[61C5]
m42a[61C2]
m42a[62C5]
m42a[62A6]
m42a[63B2]
m42a[63B1]
m42a[63D3]
m42a[65C4]
m42a[65C3]
m42a[65C5]

m42a[66C6]
m42a[66C3]
m42a[66B2]
m42a[67C5]
m42a[68B4]
m42a[69B7]
m42a[69C2 69C2]
m42a[46C7]
m42a[54A5]
m42a[45C3]
m42a[55A5]
108

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