CAT28F020

Licensed Intel
2 Megabit CMOS Flash Memory second source

FEATURES
■ Commercial, industrial and automotive
■ Fast read access time: 90/120 ns temperature ranges
■ Low power CMOS dissipation: ■ Stop timer for program/erase
– Active: 30 mA max (CMOS/TTL levels)
■ On-chip address and data latches
– Standby: 1 mA max (TTL levels)
– Standby: 100 µA max (CMOS levels) ■ JEDEC standard pinouts:
– 32-pin DIP
■ High speed programming:
– 32-pin PLCC
– 10 µs per byte
– 32-pin TSOP (8 x 20)
– 4 seconds typical chip program
■ 100,000 program/erase cycles
■ 0.5 seconds typical chip-erase
■ 10 year data retention
■ 12.0V ± 5% programming and erase voltage
■ Electronic signature

DESCRIPTION
The CAT28F020 is a high speed 256K x 8-bit electrically using a two write cycle scheme. Address and Data are
erasable and reprogrammable Flash memory ideally latched to free the I/O bus and address bus during the
suited for applications requiring in-system or after-sale write operation.
code updates. Electrical erasure of the full memory
The CAT28F020 is manufactured using Catalyst’s
contents is achieved typically within 0.5 second.
advanced CMOS floating gate technology. It is designed
It is pin and Read timing compatible with standard to endure 100,000 program/erase cycles and has a data
EPROM and E2PROM devices. Programming and retention of 10 years. The device is available in JEDEC
Erase are performed through an operation and verify approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
algorithm. The instructions are input via the I/O bus, TSOP packages.

BLOCK DIAGRAM I/O0–I/O7

I/O BUFFERS
ERASE VOLTAGE
SWITCH

WE COMMAND DATA SENSE

PROGRAM VOLTAGE
REGISTER CE, OE LOGIC LATCH AMP
SWITCH

CE
OE
ADDRESS LATCH

Y-GATING
Y-DECODER

A0–A17 2,097,152 BIT

MEMORY
X-DECODER ARRAY

VOLTAGE VERIFY
5115 FHD F02
SWITCH

© 2009 SCILLC. All rights reserved. Doc. No. MD-1029, Rev. F

Characteristics subject to change without notice 1
CAT28F020

PIN CONFIGURATION PIN FUNCTIONS

DIP Package (L) PLCC Package (N, G) Pin Name Type Function

VCC
VPP
A12
A15
A16

A17
WE
VPP 1 32 VCC A0–A17 Input Address Inputs for
A16 2 31 WE memory addressing
A15 3 30 A17 4 3 2 1 32 31 30 I/O0–I/O7 I/O Data Input/Output
A12 4 29 A14 A7 5 29 A14
A7 5 28 A13 A6 6 28 A13 CE Input Chip Enable
A6 6 27 A8 A5 7 27 A8
OE Input Output Enable
A5 7 26 A9 A4 8 26 A9
A4 8 25 A11 A3 9 25 A11 WE Input Write Enable
A3 9 24 OE A2 10 24 OE
VCC Voltage Supply
A2 10 23 A10 A1 11 23 A10
A1 11 22 CE A0 12 22 CE VSS Ground
A0 12 21 I/O7 I/O0 13 21 I/O7
14 15 16 17 18 19 20 VPP Program/Erase
I/O0 13 20 I/O6
Voltage Supply
I/O1 14 19 I/O5
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
I/O2 15 18 I/O4
VSS 16 17 I/O3
5115 FHD F01

TSOP Package (Standard Pinout) (T, H)

A11 1 32 OE
A9 2 31 A10
A8 3 30 CE
A13 4 29 I/O7
A14 5 28 I/O6
A17 6 27 I/O5
WE 7 26 I/O4
VCC 8 25 I/O3
VPP 9 24 VSS
A16 10 23 I/O2
A15 11 22 I/O1
A12 12 21 I/O0
A7 13 20 A0
A6 14 19 A1
A5 15 18 A2
A4 16 17 A3

TSOP Package (Reverse Pinout) (TR, HR)

OE 1 32 A11
A10 2 31 A9
CE 3 30 A8
I/O7 4 29 A13
I/O6 5 28 A14
I/O5 6 27 A17
I/O4 7 26 WE
I/O3 8 25 VCC
VSS 9 24 VPP
I/O2 10 23 A16
I/O1 11 22 A15
I/O0 12 21 A12
A0 13 20 A7
A1 14 19 A6
A2 15 18 A5
A3 16 17 A4
5115 FHD F14

Doc. No. MD-1029, Rev. F © 2009 SCILLC. All rights reserved.

2 Characteristics subject to change without notice
 CAT28F020

ABSOLUTE MAXIMUM RATINGS* *COMMENT

Temperature Under Bias ................. –45°C to +130°C Stresses above those listed under “Absolute Maximum
Storage Temperature ....................... –65°C to +150°C Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
Voltage on Any Pin with the device at these or any other conditions outside of those
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V listed in the operational sections of this specification is not
Voltage on Pin A9 with implied. Exposure to any absolute maximum rating for
Respect to Ground(1) ................... –2.0V to +13.5V extended periods may affect device performance and
reliability.
VPP with Respect to Ground
during Program/Erase(1) .............. –2.0V to +14.0V
VCC with Respect to Ground(1) ............ –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA

RELIABILITY CHARACTERISTICS
Symbol Parameter Test Method Min Typ Max Units
NEND (3) Endurance MIL-STD-883, Test Method 1033 100K Cycles/Byte
TDR(3) Data Retention MIL-STD-883, Test Method 1008 10 Years
VZAP (3) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts
ILTH(3)(4) Latch-Up JEDEC Standard 17 100 mA

CAPACITANCE TA = 25°C, f = 1.0 MHz

Symbol Test Conditions Min Typ Max Units
CIN (3) Input Pin Capacitance VIN = 0V 6 pF
COUT(3) Output Pin Capacitance VOUT = 0V 10 pF
CVPP(3) VPP Supply Capacitance VPP = 0V 25 pF

Note:
1. The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

© 2009 SCILLC. All rights reserved. Doc. No. MD-1029, Rev. F

Characteristics subject to change without notice 3
CAT28F020

D.C. OPERATING CHARACTERISTICS

VCC = +5V ±10%, unless otherwise specified. (See Note 2)

Symbol Parameter Test Conditions Min Typ Max Unit

ILI Input Leakage Current VIN = VCC or VSS ±1 µA
VCC = 5.5V, OE = VIH
ILO Output Leakage Current VOUT = VCC or VSS, ±1 µA
VCC = 5.5V, OE = VIH
ISB1 VCC Standby Current CMOS CE = VCC ±0.5V, 100 µA
VCC = 5.5V
ISB2 VCC Standby Current TTL CE = VIH, VCC = 5.5V 1 mA
ICC1 VCC Active Read Current VCC = 5.5V, CE = VIL, 30 mA
IOUT = 0mA, f = 6 MHz
ICC2(1) VCC Programming Current VCC = 5.5V, 15 mA
Programming in Progress
ICC3(1) VCC Erase Current VCC = 5.5V, 15 mA
Erasure in Progress
ICC4(1) VCC Prog./Erase Verify Current VCC = 5.5V, Program or 15 mA
Erase Verify in Progress
IPPS VPP Standby Current VPP = VPPL ±10 µA
IPP1 VPP Read Current VPP = VPPH 200 µA
IPP2(1) VPP Programming Current VPP = VPPH, 30 mA
Programming in Progress
IPP3(1) VPP Erase Current VPP = VPPH, 30 mA
Erasure in Progress
IPP4(1) VPP Prog./Erase Verify Current VPP = VPPH, Program or 5 mA
Erase Verify in Progress
VIL Input Low Level TTL -0.5 0.8 V
VILC Input Low Level CMOS -0.5 0.8 V
VOL Output Low Level IOL = 5.8mA, VCC (2) = 4.5V 0.45 V
VIH Input High Level TTL 2 VCC+0.5 V
VIHC Input High Level CMOS VCC*0.7 VCC+0.5 V
VOH1 Output High Level TTL IOH = -2.5mA, VCC(2) = 4.5V 2.4 V
VOH2 Output High Level CMOS IOH = -400µA, VCC(2) = 4.5V VCC-0.4 V
VID A9 Signature Voltage A9 = VID 11.4 13 V
IID(1) A9 Signature Current A9 = VID 200 µA
VLO VCC Erase/Prog. Lockout Voltage 2.5 V
Note:
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. CAT28F020-90, VCCMIN = 4.75 V.

Doc. No. MD-1029, Rev. F © 2009 SCILLC. All rights reserved.

4 Characteristics subject to change without notice
 CAT28F020

SUPPLY CHARACTERISTICS
Symbol Parameter Min Typ Max Unit
28F020-90 4.75 5.5 V
VCC VCC Supply Voltage
28F020-12 4.5 5.5 V
VPPL VPP During Read Operations 0 6.5 V
VPPH VPP During Read/Erase/Program 11.4 12.6 V

A.C. CHARACTERISTICS, Read Operation

VCC = +5V ±10%, unless otherwise specified. (See Note 8)

JEDEC Standard 28F020-90(7) 28F020-12(7)

Symbol Symbol Parameter Min Typ Max Min Typ Max Unit
tAVAV tRC Read Cycle Time 90 120 ns
tELQV tCE CE Access Time 90 120 ns
tAVQV tACC Address Access Time 90 120 ns
tGLQV tOE OE Access Time 35 50 ns
tAXQX tOH Output Hold from Address OE/CE Change 0 0 ns
tGLQX tOLZ(1)(6) OE to Output in Low-Z 0 0 ns
tELQX tLZ(1)(6) CE to Output in Low-Z 0 0 ns
tGHQZ tDF(1)(2) OE High to Output High-Z 30 30 ns
tEHQZ tDF(1)(2) CE High to Output High-Z 40 40 ns
tWHGL(1) - Write Recovery Time Before Read 6 6 µs

Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)

2.4 V
2.0 V
INPUT PULSE LEVELS REFERENCE POINTS
0.8 V
0.45 V

Testing Load Circuit (example)

1.3V

1N914

3.3K
DEVICE
UNDER OUT
TEST
CL = 100 pF

L C INCLUDES JIG CAPACITANCE

Note:
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
3. Input Rise and Fall Times (10% to 90%) < 10 ns.
4. Input Pulse Levels = 0.45 V and 2.4 V. For High Speed Input Pulse Levels 0.0 V and 3.0 V.
5. Input and Output Timing Reference = 0.8 V and 2.0 V. For High Speed Input and Output Timing Reference = 1.5 V.
6. Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
7. For load and reference points, see Fig. 1.
8. CAT28F020-90, VCCMIN = 4.75 V.

© 2009 SCILLC. All rights reserved. Doc. No. MD-1029, Rev. F

Characteristics subject to change without notice 5
CAT28F020

A.C. CHARACTERISTICS, Program/Erase Operation

VCC = +5V ±10%, unless otherwise specified. (See Note 6)

JEDEC Standard 28F020-90 28F020-12

Symbol Symbol Parameter Min Typ Max Min Typ Max Unit
tAVAV tWC Write Cycle Time 90 120 ns
tAVWL tAS Address Setup Time 0 0 ns
tWLAX tAH Address Hold Time 40 40 ns
tDVWH tDS Data Setup Time 40 40 ns
tWHDX tDH Data Hold Time 10 10 ns
tELWL tCS CE Setup Time 0 0 ns
tWHEH tCH CE Hold Time 0 0 ns
tWLWH tWP WE Pulse Width 40 40 ns
tWHWL tWPH WE High Pulse Width 20 20 ns
tWHWH1 (2) - Program Pulse Width 10 10 µs
tWHWH2(2) - Erase Pulse Width 9.5 9.5 ms
tWHGL - Write Recovery Time Before Read 6 6 µs
tGHWL - Read Recovery Time Before Write 0 0 µs
tVPEL - VPP Setup Time to CE 100 100 ns

ERASE AND PROGRAMMING PERFORMANCE(1)

28F020-90 28F020-12
Parameter Min Typ Max Min Typ Max Unit
Chip Erase Time(3)(5) 0.5 10 0.5 10 sec
Chip Program Time(3)(4) 4 25 4 25 sec

Note:
1. Please refer to Supply characteristics for the value of VPPH and VPPL. The VPP supply can be either hardwired or switched. If VPP is switched,
VPPL can be ground, less than VCC + 2.0V or a no connect with a resistor tied to ground.
2. Program and Erase operations are controlled by internal stop timers.
3. ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V VPP.
4. Minimum byte programming time (excluding system overhead) is 16 µs (10 µs program + 6 µs write recovery), while maximum is 400 µs/
byte (16 µs x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since
most bytes program significantly faster than the worst case byte.
5. Excludes 00H Programming prior to Erasure.
6. CAT28F020-90, VCCMIN = 4.75 V

Doc. No. MD-1029, Rev. F © 2009 SCILLC. All rights reserved.

6 Characteristics subject to change without notice
 CAT28F020

FUNCTION TABLE(1)
Pins
Mode CE OE WE VPP I/O Notes
Read VIL VIL VIH VPPL DOUT
Output Disable VIL VIH VIH X High-Z
Standby VIH X X VPPL High-Z
Signature (MFG) VIL VIL VIH X 31H A0 = VIL, A9 = 12V
Signature (Device) VIL VIL VIH X BDH A0 = VIH, A9 = 12V
Program/Erase VIL VIH VIL VPPH DIN See Command Table
Write Cycle VIL VIH VIL VPPH DIN During Write Cycle
Read Cycle VIL VIL VIH VPPH DOUT During Write Cycle

WRITE COMMAND TABLE

Commands are written into the command register in one or two write cycles. The command register can be altered
only when VPP is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch
addresses and data required for programming and erase operations.
Pins
First Bus Cycle Second Bus Cycle
Mode Operation Address DIN Operation Address DIN DOUT
Set Read Write X 00H Read AIN DOUT
Read Sig. (MFG) Write X 90H Read 00 31H
Read Sig. (Device) Write X 90H Read 01 BDH
Erase Write X 20H Write X 20H
Erase Verify Write AIN A0H Read X DOUT
Program Write X 40H Write AIN DIN
Program Verify Write X C0H Read X DOUT
Reset Write X FFH Write X FFH
Note:
1. Logic Levels: X = Logic ‘Do not care’ (VIH, VIL, VPPL, VPPH)

© 2009 SCILLC. All rights reserved. Doc. No. MD-1029, Rev. F

Characteristics subject to change without notice 7
CAT28F020

READ OPERATIONS The conventional mode is entered as a regular READ

mode by driving the CE and OE pins low (with WE high),
Read Mode and applying the required high voltage on address pin A9
A Read operation is performed with both CE and OE low while all other address lines are held at VIL.
and with WE high. VPP can be either high or low,
A Read cycle from address 0000H retrieves the binary
however, if VPP is high, the Set READ command has to
code for the IC manufacturer on outputs I/O0 to I/O7:
be sent before reading data (see Write Operations). The
data retrieved from the I/O pins reflects the contents of CATALYST Code = 00110001 (31H)
the memory location corresponding to the state of the 18
address pins. The respective timing waveforms for the A Read cycle from address 0001H retrieves the binary
read operation are shown in Figure 3. Refer to the AC code for the device on outputs I/O0 to I/O7.
Read characteristics for specific timing parameters.
28F020 Code = 1011 1101 (BDH)
Signature Mode
Standby Mode
The signature mode allows the user to identify the IC
With CE at a logic-high level, the CAT28F020 is placed
manufacturer and the type of device while the device
in a standby mode where most of the device circuitry is
resides in the target system. This mode can be activated
disabled, thereby substantially reducing power con-
in either of two ways; through the conventional method
sumption. The outputs are placed in a high-impedance
of applying a high voltage (12V) to address pin A9 or by
state.
sending an instruction to the command register (see
Write Operations).

Figure 3. A.C. Timing for Read Operation

POWER UP STANDBY DEVICE AND OUPUTS DATA VALID STANDBY POWER DOWN
ADDRESS SELECTION ENABLED

ADDRESSES ADDRESS STABLE

tAVAV (tRC)

CE (E)
tEHQZ (tDF)

OE (G)
tWHGL tGHQZ (tDF)

WE (W) tGLQV (tOE)

tELQV (tCE)
tGLQX (tOLZ) tAXQX (tOH)
tELQX (tLZ)
HIGH-Z HIGH-Z
DATA (I/O) OUTPUT VALID

tAVQV (tACC)

28F020 F05

Doc. No. MD-1029, Rev. F © 2009 SCILLC. All rights reserved.

8 Characteristics subject to change without notice
 CAT28F020

WRITE OPERATIONS A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O7.
The following operations are initiated by observing the
sequence specified in the Write Command Table. 28F020 Code = 1011 1101 (BDH)

Read Mode Erase Mode

The device can be put into a standard READ mode by During the first Write cycle, the command 20H is written
initiating a write cycle with 00H on the data bus. The into the command register. In order to commence the
subsequent read cycles will be performed similar to a erase operation, the identical command of 20H has to be
standard EPROM or E2PROM Read. written again into the register. This two-step process
ensures against accidental erasure of the memory con-
Signature Mode tents. The final erase cycle will be stopped at the rising
An alternative method for reading device signature (see edge of WE, at which time the Erase Verify command
Read Operations Signature Mode), is initiated by writing (A0H) is sent to the command register. During this cycle,
the code 90H into the command register while keeping the address to be verified is sent to the address bus and
VPP high. A read cycle from address 0000H with CE and latched when WE goes low. An integrated stop timer
OE low (and WE high) will output the device signature. allows for automatic timing control over this operation,
eliminating the need for a maximum erase timing speci-
CATALYST Code = 00110001 (31H) fication. Refer to AC Characteristics (Program/Erase)
for specific timing parameters.

Figure 4. A.C. Timing for Erase Operation

VCC POWER-UP SETUP ERASE ERASE ERASING ERASE VERIFY ERASE VCC POWER-DOWN/
& STANDBY COMMAND COMMAND COMMAND VERIFICATION STANDBY

ADDRESSES
tWC tWC tWC tRC

tAS tAH

CE (E)
tCS tCH
tCH tEHQZ
tCH tCS

OE (G)
tGHWL
tWHWH2 tWHGL tDF
tWPH

WE (W)
tWP tWP tWP tOE
tDH tDH tDH tOH
tDS tDS tDS tOLZ
HIGH-Z
DATA (I/O) DATA IN DATA IN DATA IN
= 20H = 20H = A0H
tLZ VALID
DATA OUT
tCE

VCC 5.0V
0V tVPEL

VPP VPPH
VPPL
28F020 F11

© 2009 SCILLC. All rights reserved. Doc. No. MD-1029, Rev. F

Characteristics subject to change without notice 9
CAT28F020

Figure 5. Chip Erase Algorithm(1)

START ERASURE BUS

OPERATION COMMAND COMMENTS

APPLY VPPH VPP RAMPS TO VPPH

(OR VPP HARDWIRED)

ALL BYTES SHALL BE

PROGRAM ALL PROGRAMMED TO 00
BYTES TO 00H STANDBY
BEFORE AN ERASE
OPERATION

INITIALIZE
INITIALIZE ADDRESS
ADDRESS

INITIALIZE
PLSCNT = 0 PLSCNT = PULSE COUNT

ACTUAL ERASE
WRITE ERASE
WRITE ERASE NEEDS 10ms PULSE,
DATA=20H
SETUP COMMAND
DATA = 20H

DATA = 20H
WRITE ERASE
WRITE ERASE DATA = 20H
COMMAND

TIME OUT 10ms WAIT

ADDRESS = BYTE TO VERIFY

WRITE ERASE ERASE
WRITE A0H
DATA = 20H;
VERIFY COMMAND VERIFY
STOPS ERASE OPERATION

TIME OUT 6µs WAIT

INCREMENT
ADDRESS
READ DATA READ READ BYTE TO
FROM DEVICE VERIFY ERASURE
NO

DATA = NO INC PLSCNT COMPARE OUTPUT TO FF

STANDBY
FFH? ==1000
3000 ?? INCREMENT PULSE COUNT
YES YES

NO LAST
ADDRESS?

YES
DATA = 00H
WRITE READ
WRITE READ RESETS THE REGISTER
COMMAND
FOR READ OPERATION

VPP RAMPS TO VPPL

APPLY VPPL APPLY VPPL STANDBY
(OR VPP HARDWIRED)

ERASURE ERASE
COMPLETED ERROR

Note: 5108 FHD F10

(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.

Doc. No. MD-1029, Rev. F © 2009 SCILLC. All rights reserved.

10 Characteristics subject to change without notice
 CAT28F020

Erase-Verify Mode Program-Verify Mode

The Erase-verify operation is performed on every byte A Program-verify cycle is performed to ensure that all
after each erase pulse to verify that the bits have been bits have been correctly programmed following each
erased. byte programming operation. The specific address is
already latched from the write cycle just completed, and
Programming Mode stays latched until the verify is completed. The Program-
The programming operation is initiated using the pro- verify operation is initiated by writing C0H into the
gramming algorithm of Figure 7. During the first write command register. An internal reference generates the
cycle, the command 40H is written into the command necessary high voltages so that the user does not need
register. During the second write cycle, the address of to modify VCC. Refer to AC Characteristics (Program/
the memory location to be programmed is latched on the Erase) for specific timing parameters.
falling edge of WE, while the data is latched on the rising
edge of WE. The program operation terminates with the
next rising edge of WE. An integrated stop timer allows
for automatic timing control over this operation, eliminat-
ing the need for a maximum program timing specifica-
tion. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.

Figure 6. A.C. Timing for Programming Operation

VCC POWER-UP SETUP PROGRAM LATCH ADDRESS PROGRAM PROGRAM VCC POWER-DOWN/
& STANDBY COMMAND & DATA VERIFY VERIFICATION STANDBY
PROGRAMMING COMMAND

ADDRESSES
tWC tWC tRC

tAS tAH

CE (E)
tCS tCH
tCH tEHQZ
tCH tCS

OE (G)
tGHWL
tWHWH1 tWHGL tDF
tWPH

WE (W)
tWP tWP tWP tOE
tDH tDH tDH tOH
tDS tDS tDS tOLZ
HIGH-Z
DATA (I/O) DATA IN DATA IN DATA IN
= 40H = C0H
tLZ VALID
DATA OUT
tCE

5.0V
VCC
0V tVPEL

VPPH
VPP
VPPL
28F020 F07

© 2009 SCILLC. All rights reserved. Doc. No. MD-1029, Rev. F

Characteristics subject to change without notice 11
CAT28F020

Figure 7. Programming Algorithm(1)

START BUS
PROGRAMMING OPERATION COMMAND COMMENTS

APPLY VPPH STANDBY VPP RAMPS TO VPPH

(OR VPP HARDWIRED)

INITIALIZE
ADDRESS INITIALIZE ADDRESS

PLSCNT = 0 INITIALIZE PULSE COUNT

PLSCNT = PULSE COUNT

WRITE SETUP 1ST WRITE WRITE

PROG. COMMAND DATA = 40H
CYCLE SETUP

WRITE PROG. CMD 2ND WRITE

PROGRAM VALID ADDRESS AND DATA
ADDR AND DATA CYCLE

TIME OUT 10µs WAIT

WRITE PROGRAM 1ST WRITE PROGRAM

DATA = C0H
VERIFY COMMAND CYCLE VERIFY

TIME OUT 6µs WAIT

READ DATA READ

READ BYTE TO VERIFY
FROM DEVICE PROGRAMMING

NO

NO INC
VERIFY STANDBY
COMPARE DATA OUTPUT
PLSCNT
DATA ? TO DATA EXPECTED
= 25 ?
YES YES

INCREMENT NO LAST
ADDRESS ADDRESS?

YES
DATA = 00H
WRITE READ 1ST WRITE
READ SETS THE REGISTER FOR
COMMAND CYCLE READ OPERATION

APPLY VPPL APPLY VPPL STANDBY VPP RAMPS TO VPPL

(OR VPP HARDWIRED)

PROGRAMMING PROGRAM
COMPLETED ERROR
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
5108 FHD F06

Doc. No. MD-1029, Rev. F © 2009 SCILLC. All rights reserved.

12 Characteristics subject to change without notice
 CAT28F020

Abort/Reset POWER SUPPLY DECOUPLING

An Abort/Reset command is available to allow the user
To reduce the effect of transient power supply voltage
to safely abort an erase or program sequence. Two
spikes, it is good practice to use a 0.1µF ceramic
consecutive program cycles with FFH on the data bus
capacitor between VCC and VSS and VPP and VSS. These
will abort an erase or a program operation. The abort/
high-frequency capacitors should be placed as close as
reset operation can interrupt at any time in a program or
possible to the device for optimum decoupling.
erase operation and the device is reset to the Read
Mode.

POWER UP/DOWN PROTECTION

The CAT28F020 offers protection against inadvertent
programming during VPP and VCC power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, VPP and VCC
may power up in any order. Additionally VPP may be
hardwired to VPPH independent of the state of VCC and
any power up/down cycling. The internal command
register of the CAT28F020 is reset to the Read Mode on
power up.

Figure 8. Alternate A.C. Timing for Program Operation

VCC POWER-UP SETUP PROGRAM LATCH ADDRESS PROGRAM PROGRAM VCC POWER-DOWN/
& STANDBY COMMAND & DATA VERIFY VERIFICATION STANDBY
PROGRAMMING COMMAND

ADDRESSES
tWC tWC tRC

tAVEL tELAX

WE (W)
tWLEL tEHWH
tWLEL tEHWH tEHQZ
tEHWH tWLEL

OE (G)
tGHEL tEHEH tEHGL tDF
tEHEL

CE (E)
tELEH tELEH tOE
tEHDX tEHDX tEHDX tOH
tDVEH tDVEH tDVEH tOLZ
HIGH-Z
DATA (I/O) DATA IN DATA IN DATA IN
= 40H = C0H
tLZ VALID
DATA OUT
tCE

VCC 5.0V
0V tVPEL

VPP VPPH
VPPL
28F020 F09

28F020 F09
© 2009 SCILLC. All rights reserved. Doc. No. MD-1029, Rev. F
Characteristics subject to change without notice 13
CAT28F020

ALTERNATE CE
CE-CONTROLLED WRITES
JEDEC Standard 28F020-90 28F020-12
Symbol Symbol Parameter Min Typ Max Min Typ Max Unit
tAVAV tWC Write Cycle Time 90 120 ns
tAVEL tAS Address Setup Time 0 0 ns
tELAX tAH Address Hold Time 40 40 ns
tDVEH tDS Data Setup Time 40 40 ns
tEHDX tDH Data Hold Time 10 10 ns
tEHGL — Write Recovery Time Before Read 6 6 µs
tGHEL — Read Recovery Time Before Write 0 0 µs
tWLEL tWS WE Setup Time Before CE 0 0 ns
tEHWH — WE Hold Time After CE 0 0 ns
tELEH tCP Write Pulse Width 40 40 ns
tEHEL tCPH Write Pulse Width High 20 20 ns
tVPEL — VPP Setup Time to CE Low 100 100 ns

Doc. No. MD-1029, Rev. F © 2009 SCILLC. All rights reserved.

14 Characteristics subject to change without notice
 CAT28F020

EXAMPLE OF ORDERING INFORMATION(1)

Prefix Device # Suffix

CAT 28F020 N I -12 T

Product Temperature Range Tape & Reel

Number T: 500/Reel
(3)

Optional Package Speed

Company ID N: PLCC(2) 90: 90ns
T: TSOP (8mmx20mm)(2) 12: 120ns
TR: TSOP (Reverse Pinout)(2)
G: PLCC (Lead free, Halogen free)
L: PDIP (Lead free, Halogen free)
H: TSOP (Lead free, Halogen free)
HR: TSOP (Reverse Pinout) (Lead free, Halogen free)

ORDERING INFORMATION
Orderable Part Numbers (for Pb-Free Devices)
CAT28F020GA-12T CAT28F020HRA-12T
CAT28F020GA-90T CAT28F020HRA-90T
CAT28F020GI-12T CAT28F020HRI-12T
CAT28F020GI-90T CAT28F020HRI-90T
CAT28F020HA-12T CAT28F020LA12
CAT28F020HA-90T CAT28F020LA90
CAT28F020HI-12T CAT28F020LI12
CAT28F020HI-90T CAT28F020LI90

Notes:
(1) The device used in the above example is a CAT28F020NI-12T (PLCC, Industrial Temperature, 120 ns access time, Tape & Reel).
(2) Solder-plate (tin-lead) packages, contact Factory for availability.
(3) -40°C to +125°C is available upon request.

© 2009 SCILLC. All rights reserved. Doc. No. MD-1029, Rev. F

Characteristics subject to change without notice 15
CAT28F020

REVISION HISTORY

Date Revision Description

1-May-02 A Initial issue
10-Feb-04 B Change VCCMIN for CAT28F020-90 to 4.75 V from 4.5 V
01-Jul-04 C Added Green Packages in all areas.
15-Oct-08 D Eliminate PDIP SnPb package.
17-Nov-08 E Change logo and fine print to ON Semiconductor
31-Jul-09 F Update Absolute Maximum Ratings
Update Example of Ordering Information
Update Ordering Information table

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Doc. No. MD-1029, Rev. F © 2009 SCILLC. All rights reserved.

16 Characteristics subject to change without notice