ISL6269 Data Sheet
ISL6269 Data Sheet
ISL6269 Data Sheet
E CO
NO RE M M EN D ED F
COMM
DATASHEET
O
contac END ED R NEW DE
t our T R E PL SIGNS
1- 888-
INTER echnical Sup ACEMENT
ISL6269 SIL or
www.i port Center FN9177
ntersil a
High-Performance Notebook PWM Controller with Bias Regulator and .com/t t Rev 3.00
sc
Audio-Frequency Clamp June 25, 2009
• Network adapter
PHASE
BOOT
UG
Ordering Information
16 15 14 13
PART TEMP
VIN 1 12 PVCC NUMBER PART RANGE PACKAGE PKG.
(Note) MARKING (°C) (Pb-free) DWG. #
VCC 2 11 LG
GND ISL6269CRZ* 62 69CRZ -10 to +100 16 Ld 4x4 QFN L16.4x4
FCCM 3 10 PGND ISL6269IRZ* 62 69IRZ -40 to +100 16 Ld 4x4 QFN L16.4x4
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
EN 4 9 ISEN
reel specifications.
5 6 7 8 NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
COMP
FSET
VO
FB
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
ISL6269
VIN
VO
GND
PACKAGE BOTTOM
5V LDO
PWM FREQUENCY
FSET
CONTROL
VCC
VREF
EN gmVIN VW
R
PWM
Q
OVP
S
VR
gmVO
VCOMP
CR
UVP
BOOT
EA DRIVER UG
FB
POR DIGITAL SOFT-START
PWM CONTROL
COMP PHASE
SHOOT THROUGH
ISEN PROTECTION
OCP PVCC
IOC
30 90 60
DRIVER LG
150°OT
Page 2 of 14
PGOOD PGND
FCCM
Typical Application
ISL6269
VIN
7V TO 25V
PGOOD VIN
CIN
RPGOOD
QHIGH_SIDE
PVCC UG
RPVCC
VCC BOOT
CPVCC CVCC
CBOOT LOUT VOUT
0.6V TO 3.3V
GND PHASE
RSEN COUT
FCCM ISEN
QLOW_SIDE
EN LG
RCOMP
COMP PGND
CCOMP1
FB FSET
VO
CCOMP2 RFSET CFSET
RBOTTOM RTOP
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications These specifications apply for TA = -40°C to +100°C, unless otherwise stated. All typical specifications TA = +25°C,
PVCC = 5V, VIN = 15V. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
VIN
VIN Input Voltage Range VVIN 7.0 - 25 V
VIN Input Bias Current IVIN EN = 5V, VIN = 25V - 2.2 3.0 mA
VIN Shutdown Current IVIN_SHDN EN = GND, VIN= 25V - 0.1 1.0 µA
VCC LDO
VCC Output Voltage Range VVCC VIN = 7V to 25V, IVCC = 0mA to 80mA 4.75 5.00 5.25 V
Rising VCC POR Threshold Voltage VVCC_THR TA = -10°C to +100°C 4.35 4.45 4.55 V
4.33 4.45 4.55 V
Falling VCC POR Threshold Voltage V TA = -10°C to +100°C 4.10 4.20 4.30 V
VCC_THF
4.08 4.20 4.30 V
PVCC
PVCC Shutdown Current IPVCC_SHDN EN = GND, PVCC = 5V - 0.1 1.0 µA
REGULATION
Reference Voltage VREF - 0.6 - V
Voltage Regulation Accuracy V FB connected to COMP, TA = -10°C to +100°C -0.6 - +0.6 %
REG
FB connected to COMP, TA = -40°C to +100°C -1.0 - +1.0 %
PWM
Frequency Range fSW FCCM = 5V 200 - 600 kHz
fAUDIO FCCM = GND, TA = -10°C to +100°C 19 28 - kHz
FCCM to GND 18 28 - kHz
Frequency-Set Accuracy fSW = 300kHz -12 - +12 %
VO Range VVO 0.60 - 3.30 V
Electrical Specifications These specifications apply for TA = -40°C to +100°C, unless otherwise stated. All typical specifications TA = +25°C,
PVCC = 5V, VIN = 15V. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
VO Input Leakage IVO VO = 0.60V - 1.3 - µA
VO = 3.30V - 7.0 - µA
ERROR AMPLIFIER
FB Input Bias Current IFB FB = 0.60V -0.5 - +0.5 µA
COMP Source Current ICOMP_SRC FB = 0.40V, COMP = 3.20V - 2.5 - mA
COMP Sink Current ICOMP_SNK FB = 0.80V, COMP = 0.30V - 0.3 - mA
COMP High Clamp Voltage VCOMP_HC FB = 0.40V, Sink 50µA 3.10 3.40 3.65 V
COMP Low Clamp Voltage VCOMP_LC FB = 0.80V, Source 50µA 0.09 0.15 0.21 V
POWER GOOD
PGOOD Pull-down Impedance RPG_SS PGOOD = 5mA Sink, TA = -10°C to +100°C 75 95 125
PGOOD = 5mA Sink 67 95 125
RPG_UV PGOOD = 5mA Sink, TA = -10°C to +100°C 75 95 125
PGOOD = 5mA Sink 67 95 125
RPG_OV PGOOD = 5mA Sink, TA = -10°C to +100°C 50 63 85
PGOOD = 5mA Sink 45 63 85
RPG_OC PGOOD = 5mA Sink, TA = -10°C to +100°C 25 32 45
PGOOD = 5mA Sink 22 32 45
PGOOD Leakage Current IPGOOD PGOOD = 5V - 0.1 1.0 µA
PGOOD Maximum Sink Current - 5.0 - mA
PGOOD Soft-Start Delay tSS EN High to PGOOD High, TA = -10°C to +100°C 2.20 2.75 3.30 ms
EN High to PGOOD High 2.20 2.75 3.50 ms
GATE DRIVER
UG Pull-Up Resistance RUGPU 200mA Source Current - 1.0 1.5
UG Source Current IUGSRC UG - PHASE = 2.5V - 2.0 - A
UG Sink Resistance RUGPD 250mA Sink Current - 1.0 1.5
UG Sink Current IUGSNK UG - PHASE = 2.5V - 2.0 - A
LG Pull-Up Resistance RLGPU 250mA Source Current - 1.0 1.5
LG Source Current ILGSRC LG - PGND = 2.5V - 2.0 - A
LG Sink Resistance RLGPD 250mA Sink Current - 0.5 0.9
LG Sink Current ILGSNK LG - PGND = 2.5V - 4.0 - A
UG to LG Deadtime tUGFLGR UG falling to LG rising, no load - 21 - ns
LG to UG Deadtime tLGFUGR LG falling to UG rising, no load - 14 - ns
BOOTSTRAP DIODE
Forward Voltage VF PVCC = 5V, IF = 2mA - 0.58 - V
Reverse Leakage IR VR = 25V - 0.2 - µA
CONTROL INPUTS
EN High Threshold VENTHR 2.0 - - V
EN Low Threshold VENTHF - - 0.5 V
FCCM High Threshold VFCCMTHR 2.0 - - V
FCCM Low Threshold VFCCMTHF - - 1.0 V
EN Leakage IENL EN = 0V - 0.1 1.0 µA
IENH EN = 5.0V - 20 - µA
UG (Pin 14)
Ripple Capacitor Voltage CR Window Voltage VW
The UG pin is the output of the high-side MOSFET gate driver.
Connect to the gate of the high-side MOSFET.
output voltage enters regulation in approximately 1.5ms and the gate-driver output voltage is measured across the LG and
PGOOD pin goes to high impedance once tSS has elapsed. PGND pins. The power for the LG gate-driver is sourced
directly from the PVCC pin. The power for the UG gate-driver is
1.5ms sourced from a “boot” capacitor connected across the BOOT
VOUT
and PHASE pins. The boot capacitor is charged from a 5V bias
supply through a “boot diode” each time the low-side MOSFET
VCC
turns on, pulling the PHASE pin low. The ISL6269 has an
integrated boot diode connected from the PVCC pin to the
BOOT pin.
EN
tLGFUGR tUGFLGR
50%
PGOOD
UG
2.75ms
to 3.3V. EA
Where: FSET
Where:
FIGURE 6. COMPENSATION REFERENCE CIRCUIT
- fSW is the PWM switching frequency
- RFSET is the fSW programming resistor Your local Intersil representative can provide a PC-based tool
that can be used to calculate compensation network
- K = 75 x 10-12
component values and help simulate the loop frequency
It is recommended that whenever the control loop response. The compensation network consists of the internal
compensation network is modified, fSW should be checked for error amplifier of the ISL6269 and the external components R1,
the correct frequency and if necessary, adjust RFSET. R2, C1, and C2 as well as the frequency setting components
Compensation Design RFSET, and CFSET, are identified in the schematic Figure 6.
The LC output filter has a double pole at its resonant frequency
that causes the phase to abruptly roll downward. The R3
General Application Design Guide
modulator used in the ISL6269 makes the LC output filter This design guide is intended to provide a high-level explanation
resemble a first order system in which the closed loop stability can of the steps necessary to create a single-phase power
be achieved with a Type II compensation network. converter. It is assumed that the reader is familiar with many of
the basic skills and techniques referenced below. In addition to
this guide, Intersil provides complete reference designs that Selection of the Input Capacitor
include schematics, bills of materials, and example board The important parameters for the bulk input capacitance are
layouts. the voltage rating and the RMS current rating. For reliable
Selecting the LC Output Filter operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
The duty cycle of an ideal buck converter is a function of the
supplying the RMS current required by the switching circuit.
input and the output voltage. This relationship is written as:
Their voltage rating should be at least 1.25 times greater than
V OUT
D = ---------------- (EQ. 9) the maximum input voltage, while a voltage rating of 1.5 times
V IN
is a preferred rating. Figure 7 is a graph of the input RMS ripple
The output inductor peak-to-peak ripple current is written as: current, normalized relative to output load current, as a function
V OUT 1 – D of duty cycle that is adjusted for converter efficiency. The ripple
I PP = -------------------------------------- (EQ. 10) current calculation is written as:
f SW L OUT
2 2 2 D
A typical step-down DC/DC converter will have an IPP of 20% I MAX D – D + x I MAX ------
12
I IN_RMS = ----------------------------------------------------------------------------------------------------- (EQ. 14)
to 40% of the maximum DC output load current. The value of I MAX
IPP is selected based upon several criteria such as MOSFET
switching loss, inductor core loss, and the resistive loss of the Where:
inductor winding. The DC copper loss of the inductor can be - IMAX is the maximum continuous ILOAD of the converter
estimated by: - x is a multiplier (0 to 1) corresponding to the inductor
P COPPER = I LOAD
2
DCR (EQ. 11) peak-to-peak ripple amplitude expressed as a percentage
of IMAX (0% to 100%)
Where ILOAD is the converter output DC current. - D is the duty cycle that is adjusted to take into account the
The copper loss can be significant so attention has to be given efficiency of the converter which is written as:
to the DCR selection. Another factor to consider when V OUT
D = --------------------------
choosing the inductor is its saturation characteristics at V IN EFF (EQ. 15)
elevated temperature. A saturated inductor could cause
In addition to the bulk capacitance, some low ESL ceramic
destruction of circuit components, as well as nuisance OCP
capacitance is recommended to decouple between the drain of
faults.
the high-side MOSFET and the source of the low-side
A DC/DC buck regulator must have output capacitance COUT MOSFET.
into which ripple current IPP can flow. Current IPP develops a
NORMALIZED INPUT RMS RIPPLE CURRENT
0.60
corresponding ripple voltage VPP across COUT, which is the
0.55
sum of the voltage drop across the capacitor ESR and of the
0.50
voltage change stemming from charge moved in and out of the
0.45
capacitor. These two voltages are written as:
0.40
V ESR = I PP E SR (EQ. 12) 0.35
0.30
and 0.25 x=1
x = 0.75
I PP 0.20 x = 0.50
V C = ------------------------------------- (EQ. 13) x = 0.25
8 C OUT f 0.15 x=0
SW
0.10
If the output of the converter has to support a load with high 0.05
pulsating current, several capacitors will need to be paralleled to 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
reduce the total ESR until the required VPP is achieved. The
inductance of the capacitor can cause a brief voltage dip if the DUTY CYCLE
load transient has an extremely high slew rate. Low inductance FIGURE 7. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
capacitors constructed with reverse package geometry are
available. A capacitor dissipates heat as a function of RMS
current and frequency. Be sure that IPP is shared by a sufficient
quantity of paralleled capacitors so that they operate below the
maximum rated RMS current at fSW. Take into account that the
rated value of a capacitor can fade as much as 50% as the DC
voltage across it increases.
MOSFET Selection and Considerations As an example, suppose the high-side MOSFET has a total
Typically, a MOSFET cannot tolerate even brief excursions gate charge Qg, of 25nC at VGS = 5V, and a VBOOT of
beyond their maximum drain to source voltage rating. The 200mV. The calculated bootstrap capacitance is 0.125µF; for a
MOSFETs used in the power stage of the converter should comfortable margin select a capacitor that is double the
have a maximum VDS rating that exceeds the sum of the upper calculated capacitance, in this example 0.22µF will suffice. Use
voltage tolerance of the input power source and the voltage an X7R or X5R ceramic capacitor.
spike that occurs when the MOSFET switches off. Layout Considerations
There are several power MOSFETs readily available that are As a general rule, power should be on the bottom layer of the
optimized for DC/DC converter applications. The preferred PCB and weak analog or logic signals are on the top layer of
high-side MOSFET emphasizes low switch charge so that the the PCB. The ground-plane layer should be adjacent to the top
device spends the least amount of time dissipating power in layer to provide shielding. The ground plane layer should have
the linear region. Unlike the low-side MOSFET which has the an island located under the IC, the compensation components,
drain-source voltage clamped by its body diode during turn off, and the FSET components. The island should be connected to
the high-side MOSFET turns off with VIN - VOUT - VLacross it. the rest of the ground plane layer at one point.
The preferred low-side MOSFET emphasizes low rDS(ON)
when fully saturated to minimize conduction loss. VIAS TO GND
GROUND OUTPUT
For the low-side MOSFET, (LS), the power loss can be PLANE CAPACITORS
assumed to be conductive only and is written as: SCHOTTKY
VOUT DIODE
2
P CON_LS I LOAD r DS ON _LS 1 – D (EQ. 16) PHASE
INDUCTOR NODE LOW-SIDE
MOSFETS
HIGH-SIDE
For the high-side MOSFET, (HS), its conduction loss is written MOSFETS INPUT
as: VIN CAPACITORS
2
P CON_HS = I LOAD r DS ON _HS D (EQ. 17)
FIGURE 8. TYPICAL POWER COMPONENT PLACEMENT
For the high-side MOSFET, its switching loss is written as:
Signal Ground and Power Ground
V IN I VALLEY t ON f V IN I PEAK t OFF f The bottom of the ISL6269 QFN package is the signal ground
SW SW
P SW_HS = ----------------------------------------------------------------- + ------------------------------------------------------------- (GND) terminal for analog and logic signals of the IC. Connect
2 2
(EQ. 18) the GND pad of the ISL6269 to the island of ground plane
under the top layer using several vias, for a robust thermal and
Where: electrical conduction path. Connect the input capacitors, the
- IVALLEY is the difference of the DC component of the output capacitors, and the source of the lower MOSFETs to the
inductor current minus 1/2 of the inductor ripple current power ground plane.
- IPEAK is the sum of the DC component of the inductor
PGND (PIN 10)
current plus 1/2 of the inductor ripple current
- tON is the time required to drive the device into saturation This is the return path for the pull-down of the LG low-side
MOSFET gate driver. Ideally, PGND should be connected to
- tOFF is the time required to drive the device into cut-off
the source of the low-side MOSFET with a low-resistance, low-
Selecting The Bootstrap Capacitor inductance path.
The selection of the bootstrap capacitor is written as:
VIN (PIN 1)
Qg
C BOOT = ------------------------ (EQ. 19) The VIN pin should be connected close to the drain of the high-
V BOOT side MOSFET, using a low resistance and low inductance path.
FCCM (PIN 3), EN (PIN 4), AND PGOOD (PIN 16) LG (PIN 11)
These are logic inputs that are referenced to the GND pin. The signal going through this trace is both high dv/dt and
Treat as a typical logic signal. high di/dt, with high peak charging and discharging current.
Route this trace in parallel with the trace from the PGND pin.
COMP (PIN 5), FB (PIN 6), AND VO (PIN 8)
These two traces should be short, wide, and away from
For best results, use an isolated sense line from the output other traces. There should be no other weak signal traces in
load to the VO pin. The input impedance of the FB pin is proximity with these traces on any layer.
high, so place the voltage programming and loop
compensation components close to the VO, FB, and GND BOOT (PIN 13), UG (PIN 14), AND PHASE (PIN 15)
pins keeping the high impedance trace short. The signals going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
FSET (PIN 7)
current. Route the UG and PHASE pins in parallel with short
This pin requires a quiet environment. The resistor RFSET and wide traces. There should be no other weak signal
and capacitor CFSET should be placed directly adjacent to traces in proximity with these traces on any layer.
this pin. Keep fast moving nodes away from this pin.
Copper Size for the Phase Node
ISEN (PIN 9)
The parasitic capacitance and parasitic inductance of the
Route the connection to the ISEN pin away from the traces phase node should be kept very low to minimize ringing. It is
and components connected to the FB pin, COMP pin, and best to limit the size of the PHASE node copper in strict
FSET pin. accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
Rev 6, 02/08
4X 1.95
4.00 A 12X 0.65
B 6
13 16 PIN #1 INDEX AREA
6
PIN 1
INDEX AREA 1
12
4.00
2 . 10 ± 0 . 15
9
4
(4X) 0.15
8 5
TOP VIEW +0.15 0.10 M C A B
16X 0 . 60
-0.10 4 0.28 +0.07 / -0.05
BOTTOM VIEW
0.10 C C
1.00 MAX
BASE PLANE
( 16X 0 . 28 ) C 0 . 2 REF 5
( 16 X 0 . 8 )
0 . 00 MIN.
0 . 05 MAX.
NOTES: