a Variable Resolution,

Resolver-to-Digital Converter
AD2S83
FEATURES FUNCTIONAL BLOCK DIAGRAM
Tracking R/D Converter
REFERENCE
High Accuracy Velocity Output I/P OFFSET ADJUST

High Max Tracking Rate 1040 RPS (10 Bits) HF FILTER C3 +12V
R9
–12V
44-Lead PLCC Package
C1 R2 R3 R8
10-, 12-, 14-, or 16-Bit Resolution Set by User C2
R1 BANDWIDTH
Ratiometric Conversion SELECTION
R4
Stabilized Velocity Reference
AC ERROR O/P INTEGRATOR C5
Dynamic Performance Set by User DEMOD I/P
R5
O/P
Industrial Temperature Range C4
SIN A1
SIG SEGMENT PHASE
APPLICATIONS GND SWITCHING R – 2R DAC A3 SENSITIVE INTEGRATOR VELOCITY
COS A2 DETECTOR O/P SIGNAL
DC and AC Servo Motor Control
GND
Process Control AD2S83 R6
TRACKING
Numerical Control of Machine Tools RIPPLE
CLOCK 16-BIT UP/DOWN COUNTER VCO
I/P
RATE
SELECTION
Robotics +12V
VCO + DATA
TRANSFER C7
Axis Control –12V
OUTPUT DATA LATCH
LOGIC VCO
O/P R7
3K3
DATA SC1 SC2 ENABLE BYTE 5V DIG BUSY DIRECTION INHIBIT C6
LOAD GND 390pF
16 SELECT
DATA BITS

GENERAL DESCRIPTION PRODUCT HIGHLIGHTS

The AD2S83 is a monolithic 10-, 12-, 14-, or 16-bit tracking High Accuracy Velocity Output. A precision analog velocity
resolver-to-digital converter. signal with a typical linearity of ± 0.1% and reversion error less
The converter allows users to select their own resolution and dynamic than ± 0.3% is generated by the AD2S83. The provision of this
performance with external components. The converter allows users to signal removes the need for mechanical tachogenerators used in
select the resolution to be 10, 12, 14, or 16 bits and to track servo systems to provide loop stabilization and speed control.
resolver signals rotating at up to 1040 revs per second (62,400 rpm) Resolution Set by User. Two control pins are used to select
when set to 10-bit resolution. the resolution of the AD2S83 to be 10, 12, 14 or 16 bits allow-
The AD2S83 converts resolver format input signals into a paral- ing optimum resolution for each application.
lel natural binary digital word using a ratiometric tracking con- Ratiometric Tracking Conversion. This technique provides
version method. This ensures high noise immunity and tolerance continuous output position data without conversion delay. It
of long leads allowing the converter to be located remote from also provides noise immunity and tolerance of harmonic distor-
the resolver. tion on the reference and input signals.
The position output from the converter is presented via 3-state Dynamic Performance Set by the User. By selecting external
output pins which can be configured for operations with 8- or resistor and capacitor values the user can determine band-
16-bit bus. BYTE SELECT, ENABLE and INHIBIT pins width, maximum tracking rate and velocity scaling of the
ensure easy data transfer to 8- and 16-bit data bus, and outputs converter to match the system requirements. The component
are provided to allow for cycle or pitch counting in external values are easy to select using the free component selection
counters. software design aid.
A precise analog signal proportional to velocity is also available
and will replace a tachogenerator. MODELS AVAILABLE
Information on the models available is given in the Ordering
The AD2S83 operates over reference frequencies in the range Guide.
0 Hz to 20,000 Hz.

REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000
AD2S83–SPECIFICATIONS (
V =
12 V dc
5%; V = 5 V dc
10%; T = –40C to +85C)
S L A

Parameter Conditions Min Typ Max Unit

SIGNAL INPUTS (SIN, COS)
Frequency1 0 20,000 Hz
Voltage Level 1.8 2.0 2.2 V rms
Input Bias Current 60 150 nA
Input Impedance 1.0 MΩ
REFERENCE INPUT (REF)
Frequency 0 20,000 Hz
Voltage Level 1.0 8.0 V pk
Input Bias Current 60 150 nA
Input Impedance 1.0 MΩ
PERFORMANCE
Repeatability 1 LSB
Allowable Phase Shift (Signals to Reference) –10 +10 Degree
Max Tracking Rate 10 Bits 1040 rps
12 Bits 260 rps
14 Bits 65 rps
16 Bits 16.25 rps
Bandwidth User Selectable
ACCURACY
Angular Accuracy A, I
8 +1 LSB arc min
Monotonicity Guaranteed Monotonic
Missing Codes (16-Bit Resolution) A, I 4 Codes
VELOCITY SIGNAL
LINEARITY2, 3, 4
AD2S83AP
0 kHz–500 kHz –40°C to +85°C ± 0.15
0.25 % FSR
0.5 MHz–1 MHz –40°C to +85°C ± 0.25
1.0 % FSR
AD2S83IP
0 kHz–500 kHz –40°C to +85°C ± 0.25
0.5 % FSR
0.5 MHz–1 MHz –40°C to +85°C ± 0.25
1.0 % FSR
Reversion Error
AD2S83AP –40°C to +85°C ± 0.5
1.0 % O/P
AD2S83IP –40°C to +85°C ± 1.0
1.5 % O/P
DC Zero Offset5 ±3 mV
Gain Scaling Accuracy ± 1.5
3 % FSR
Output Voltage 1 mA Load ±8 V
Dynamic Ripple Mean Value 1.0 % rms O/P
INPUT/OUTPUT PROTECTION
Analog Inputs Overvoltage Protection ±8 V
Analog Outputs Short Circuit O/P Protection ± 5.6 ±8 ± 10.4 mA
DIGITAL POSITION
Resolution 10, 12, 14, and 16 Bits
Output Format Bidirectional Natural Binary
Load 3 LSTTL
INHIBIT 6

Sense Logic LO to INHIBIT

Time to Stable Data 240 390 490 ns
ENABLE 6
Logic LO Enables Position Output
Logic HI Outputs in High
ENABLE6/Disable Time Impedance State 35 110 ns
6
BYTE SELECT
Sense
Logic HI MS Byte DB1–DB8
Logic LO LS Byte DB1–DB8
Time to Data Available 60 140 ns
SHORT CYCLE INPUTS Internally Pulled High via
100 kΩ to +VS
SC1 SC2
0 0 10-Bit Resolution
0 1 12-Bit Resolution
1 0 14-Bit Resolution
1 1 16-Bit Resolution

–2– REV. E
 AD2S83
Parameter Conditions Min Typ Max Unit
COMPLEMENT Internally Pulled High via 100 kΩ
to +VS. Logic LO to Activate;
No Connect for Normal Operation
DATA LOAD
Sense Internally Pulled High via 100 kΩ 150 300 ns
to +VS. Logic LO Allows
Data to be Loaded into the
Counters from the Data Lines
BUSY6, 7
Sense Logic HI When Position O/P Changing
Width 150 350 ns
Load Use Additional Pull-Up (See Figure 2) 1 LSTTL
DIRECTION6
Sense Logic HI Counting Up
Logic LO Counting Down
Max Load 3 LSTTL
6
RIPPLE CLOCK
Sense Logic HI
All 1s to All 0s
All 0s to All 1s
Width Dependent on Input Velocity 300 ns
Reset Before Next Busy
Load 3 LSTTL
DIGITAL INPUTS
Input High Voltage, VIH INHIBIT, ENABLE 2.0 V
DB1–DB16, Byte Select
± VS = ± 11.4 V, VL = 5.0 V
Input Low Voltage, VIL INHIBIT, ENABLE 0.8 V
DB1–DB16, Byte Select
± VS = ± 12.6 V, VL = 5.0 V
DIGITAL INPUTS
Input High Current, IIH INHIBIT, ENABLE
100 µA
DB1–DB16
± VS = ± 12.6 V, VL = 5.5 V
Input Low Current, IIL INHIBIT, ENABLE
100 µA
DB1–DB16, Byte Select
± VS = ± 12.6 V, VL = 5.5 V
DIGITAL INPUTS
Low Voltage, VIL ENABLE = HI 1.0 V
SC1, SC2, DATA LOAD
± VS = ± 12.0 V, VL = 5.0 V
Low Current, IIL ENABLE = HI –400 µA
SC1, SC2, DATA LOAD
± VS = ± 12.0 V, VL = 5.0 V
DIGITAL OUTPUTS
High Voltage, VOH DB1–DB16 2.4 V
RIPPLE CLK, DIR
± VS = ± 12.0 V, VL = 4.5 V
IOH = 100 µA
Low Voltage, VOL DB1–DB16 0.4 V
RIPPLE CLK, DIR
± VS = ± 12.0 V, VL = 5.5 V
IOL = 1.2 mA
NOTES
1
Angular accuracy is not guaranteed <50 Hz reference frequency.
2
Linearity derates from 500 kHz–1000 kHz @ 0.0017%/kHz.
3
Refer to Definition of Linearity, “The AD2S83 as a Silicon Tachogenerator.”
4
Worst case reversion error at temperature extremes.
5
Velocity output offset dependent on value for R6.
6
Refer to timing diagram.
7
Busy pulse guaranteed up to a VCO rate of 900 kHz.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.

REV. E –3–
AD2S83–SPECIFICATIONS (
V =
12 V dc
5%; V = 5 V dc
10%; T = –40C to +85C)
S L A

Parameter Conditions Min Typ Max Unit

THREE-STATE LEAKAGE DB1–DB16 Only
Current IL ± VS = ± 12.0 V, VL = 5.5 V
20 µA
VOL = 0 V
± VS = ± 12.0 V, VL = 5.5 V
20 µA
VOH = 5.0 V
RATIO MULTIPLIER
AC Error Output Scaling 10 Bit 177.6 mV/Bit
12 Bit 44.4 mV/Bit
14 Bit 11.1 mV/Bit
16 Bit 2.775 mV/Bit
PHASE SENSITIVE DETECTOR
Output Offset Voltage 12 mV
Gain
In Phase w.r.t. REF –0.882 –0.9 –0.918 V rms/V dc
In Quadrature w.r.t. REF ± 0.02 V rms/V dc
Input Bias Current 60 150 nA
Input Impedance 1.0 MΩ
Input Voltage ±8 V
INTEGRATOR
Open-Loop Gain At 10 kHz 57 60 63 dB
Dead Zone Current (Hysteresis) 90 100 110 nA/LSB
Input Offset Voltage 1 5 mV
Input Bias Current 60 150 nA
Output Voltage Range
8 V
VCO
Maximum Rate 1.1 MHz
VCO Rate +ve DIR 8.25 8.50 8.75 kHz/µA
–ve DIR 8.25 8.50 8.75 kHz/µA
VCO Power Supply Sensitivity
Rate +VS +0.5 %/V
–VS –0.5 %/V
Input Offset Voltage 3 mV
Input Bias Current 12 50 nA
Input Bias Current Tempco +0.22 nA/°C
Linearity of Absolute Rate
AD2S83AP
0 kHz–500 kHz ± 0.15
0.25 % FSR
0.5 MHz–1 MHz ± 0.25
1.0 % FSR
AD2S83IP
0 kHz–500 kHz ± 0.25
0.5 % FSR
0.5 MHz–1 MHz ± 0.25
1.0 % FSR
Reversion Error
AD2S83AP ± 0.5
1.0 % Output
AD2S83IP ± 1.0
1.5 % Output
POWER SUPPLIES
Voltage Levels
+VS +11.4 +12.6 V
–VS –11.4 –12.6 V
+VL +4.5 +5 +VS V
Current
± IS ± VS @ ± 12 V ± 12
23 mA
± IS ± VS @ ± 12.6 V ± 19
30 mA
± IL +VL @ ± 5.0 V ± 0.5
1.5 mA

All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.

ORDERING GUIDE

Temperature Package Package

Model Range Accuracy Description Option
AD2S83AP –40°C to +85°C 8 arc min Plastic Leaded Chip Carrier P-44A
AD2S83IP –40°C to +85°C 8 arc min Plastic Leaded Chip Carrier P-44A

–4– REV. E
 AD2S83
ABSOLUTE MAXIMUM RATINGS 1 (with respect to GND) PIN FUNCTION DESCRIPTIONS
+VS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V dc
–VS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –13 V dc Pin
+VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS Nos. Mnemonic Description
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS 1 DEMOD O/P Demodulator Output
SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS 2 REFERENCE I/P Reference Signal Input
COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS
3 AC ERROR O/P Ratio Multiplier Output
Any Logical Input . . . . . . . . . . . . . . . . . . –0.4 V dc to +VL dc
Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS 4 COS Cosine Input
Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS 5 ANALOG GND Power Ground
VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS 6 SIGNAL GND Resolver Signal Ground
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW 7 SIN Sine Input
Operating Temperature 8 +VS Positive Power Supply
Industrial (AP, IP) . . . . . . . . . . . . . . . . . . . –40°C to +85°C
10–25 DB1–DB16 Parallel Output Data
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C 26 +VL Logic Power Supply
CAUTION 27 ENABLE Logic HI—Output Data Pins in
1
Absolute Maximum Ratings are those values beyond which damage to the device High Impedance State
may occur. Logic LO—Presents Active Data
2
Correct polarity voltages must be maintained on the +V S and –V S pins. to the Output Pins
RECOMMENDED OPERATING CONDITIONS 28 BYTE SELECT Logic HI—Most Significant Byte to
DB1–DB8
Power Supply Voltage (+VS, –VS) . . . . . . . . . . ± 12 V dc ± 5%
Logic LO—Least Significant Byte
Power Supply Voltage VL . . . . . . . . . . . . . . . . . +5 V dc ± 10% to DB1–DB8
Analog Input Voltage (SIN and COS) . . . . . . . 2 V rms ± 10%
30 INHIBIT Logic LO Inhibits Data Transfer
Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak
to Output Latches
Signal and Reference Harmonic Distortion . . . . . . 10% (max)
Phase Shift Between Signal and Reference . . . ±10 Degrees (max) 31 DIGITAL GND Digital Ground
Ambient Operating Temperature Range 32, 33 SC2–SC1 Select Converter Resolution
Industrial (AP, IP) . . . . . . . . . . . . . . . . . . . –40°C to +85°C 34 DATA LOAD Logic LO DB1–DB16 Inputs
Logic HI DB1–DB16 Outputs
PIN CONFIGURATION
35 COMPLEMENT Active Logic LO
36 BUSY Converter Busy, Data not Valid
INTEGRATOR O/P
INTEGRATOR I/P

While Busy HI
AC ERROR O/P
ANALOG GND
SIGNAL GND

DEMOD O/P

37 DIRECTION Logic State Defines Direction of

DEMOD I/P

VCO O/P

Input Signal Rotation

VCO I/P
COS I/P

REF I/P

38 RIPPLE CLOCK Positive Pulse When Converter Output

6 5 4 3 2 1 44 43 42 41 40 Changes from 1s to All 0s or Vice Versa
PIN 1
39 –VS Negative Power Supply
SIN I/P 7 39 –VS
IDENTIFIER
+VS 8 38 RIPPLE CLOCK
40 VCO I/P VCO Input
NC 9 37 DIRECTION 41 VCO O/P VCO Output
(MSB) DB1 10 36 BUSY 42 INTEGRATOR O/P Integrator Output
DB2 11
AD2S83
35 COMP 43 INTEGRATOR I/P Integrator Input
DB3 12 TOP VIEW 34 DATA LOAD 44 DEMOD I/P Demodulator Input
(Not to Scale)
DB4 13 33 SC1

DB5 14 32 SC2

DB6 15 31 DIGITAL GND

DB7 16 30 INHIBIT

DB8 17 29 NC

18 19 20 21 22 23 24 25 26 27 28
DB9
DB10
DB11

(LSB) DB16
+VL

ENABLE
BYTE SELECT
DB15
DB14
DB13
DB12

NC = NO CONNECT

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the AD2S83 feature proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.

REV. E –5–
AD2S83
Bit Weight Table When more than one converter is used on a card, separate de-
coupling capacitors should be used for each converter.
Binary Resolution Degrees Minutes Seconds
Bits (N) (NN) /Bit /Bit /Bit The resolver connections should be made to the SIN and COS
inputs, REFERENCE INPUT and SIGNAL GROUND as
0 1 360.0 21600.0 1296000.0 shown in Figure 11 and described in the Connecting the
1 2 180.0 10800.0 648000.0
Resolver section.
2 4 90.0 5400.0 324000.0
3 8 45.0 2700.0 162000.0 The two signal ground wires from the resolver should be joined
4 16 22.5 1350.0 81000.0 at the SIGNAL GROUND pin of the converter to minimize the
5 32 11.25 675.0 40500.0
coupling between the sine and cosine signals. For this reason it
6 64 5.625 337.5 20250.0 is also recommended that the resolver is connected using indi-
7 128 2.8125 168.75 10125.0 vidually screened twisted pair cables with the sine, cosine and
8 256 1.40625 84.375 5062.5 reference signals twisted separately.
9 512 0.703125 42.1875 2531.25 SIGNAL GROUND and ANALOG GROUND are connected
10 1024 0.3515625 21.09375 1265.625 internally. ANALOG GROUND and DIGITAL GROUND
11 2048 0.1757813 10.546875 632.8125 must be connected externally and as close to the converter as
12 4096 0.0878906 5.273438 316.40625 possible.
13 8192 0.0439453 2.636719 158.20313
14 16384 0.0219727 1.318359 79.10156 The external components required should be connected as
shown in Figure 1.
15 32768 0.0109836 0.659180 39.55078
16 65536 0.0054932 0.329590 19.77539 CONVERTER RESOLUTION
17 131072 0.0027466 0.164795 9.88770
Two major areas of the AD2S83 specification can be selected by
18 262144 0.0013733 0.082397 4.94385
the user to optimize the total system performance. The resolu-
tion of the digital output is set by the logic state of the inputs
CONNECTING THE CONVERTER SC1 and SC2 to be 10, 12, 14 or 16 bits; and the dynamic char-
The power supply voltages connected to +VS and –VS pins acteristics of bandwidth and tracking rate are selected by the
should be +12 V dc and –12 V dc and must not be reversed. choice of external components.
The voltage applied to VL can be +5 V dc to +VS. The choice of the resolution will affect the values of R4 and R6
It is recommended that the decoupling capacitors are connected which scale the inputs to the integrator and the VCO respec-
in parallel between the power lines +VS, –VS and ANALOG tively (see Component Selection section). If the resolution is
GROUND adjacent to the converter. Recommended values are changed, then new values of R4 and R6 must be switched into
100 nF (ceramic) and 10 µF (tantalum). Also capacitors of the circuit.
100 nF and 10 µF should be connected between +VL and Note: When changing resolution under dynamic conditions, do
DIGITAL GROUND adjacent to the converter. it when the BUSY is low, i.e., when data is not changing.

REFERENCE
I/P OFFSET ADJUST
R9
HF FILTER C3 +12V –12V

R3 R8
C1 R2
C2 BANDWIDTH
R1 SELECTION
R4

AC ERROR O/P INTEGRATOR C5

I/P
DEMOD R5
O/P
SIN A1 C4
PHASE
SIG GND VELOCITY
SEGMENT R - 2R DAC A3 SENSITIVE
INTEGRATOR SIGNAL
SWITCHING DETECTOR O/P
COS A2
GND AD2S83 R6 TRACKING
RIPPLE RATE
VCO
CLOCK 16-BIT UP/DOWN COUNTER I/P SELECTION
VCO + DATA C7
+12V TRANSFER 150pF
OUTPUT DATA LATCH LOGIC
–12V VCO
O/P R7
3K3
DATA SC1 SC2 ENABLE BYTE 5V DIG BUSY DIRECTION INHIBIT C6
LOAD 16 DATA BITS SELECT GND 390pF

Figure 1. Connection Diagram

–6– REV. E
 AD2S83
CONVERTER OPERATION The direction of input rotation is indicated by the DIRECTION
When connected in a circuit such as shown in Figure 10, the (DIR) logic output. This direction data is always valid in advance
AD2S83 operates as a tracking resolver-to-digital converter. of a RIPPLE CLOCK pulse and, as it is internally latched, only
The output will automatically follow the input for speeds up to changing state (1 LSB min change in input) with a correspond-
the selected maximum tracking rate. No convert command is ing change in direction.
necessary as the conversion is automatically initiated by each Both the RIPPLE CLOCK pulse and the DIRECTION data
LSB increment, or decrement, of the input. Each LSB change of are unaffected by the application of the INHIBIT. The static
the converter initiates a BUSY pulse. positional accuracy quoted is the worst case error that can occur
The AD2S83 is remarkably tolerant of input amplitude and over the full operating temperature excluding the effects of
frequency variation because the conversion depends only on the offset signals at the INTEGRATOR INPUT (which can be
ratio of the input signals. Consequently there is no need for trimmed out—see Figure 1), and with the following conditions:
accurate, stable oscillator to produce the reference signal. The input signal amplitudes are within 10% of the nominal; phase
inclusion of the phase sensitive detector in the conversion loop shift between signal and reference is less than 10 degrees.
ensures high immunity to signals that are not phase or frequency These operating conditions are selected primarily to establish a
coherent or are in quadrature with the reference signal. repeatable acceptance test procedure which can be traced to
national standards. In practice, the AD2S83 can be used well
SIGNAL CONDITIONING
outside these operating conditions providing the above points
The amplitude of the SINE and COSINE signal inputs should are observed.
be maintained within 10% of the nominal values if full perfor-
mance is required from the velocity signal. VELOCITY SIGNAL
The digital position output is relatively insensitive to amplitude The tracking converter technique generates an internal signal at
variation. Increasing the input signal levels by more than 10% the output of the integrator (INTEGRATOR OUTPUT) that is
will result in a loss in accuracy due to internal overload. Reduc- proportional to the rate of change of the input angle. This is a
ing levels will result in a steady decline in accuracy. With the dc analog output referred to as the VELOCITY signal.
signal levels at 50% of the correct value, the angular error will It is recommended that the velocity output be buffered.
increase to an amount equivalent to 1.3 LSB. At this level the
repeatability will also degrade to 2 LSB and the dynamic response The sense is positive for an increasing angular input and nega-
will also change, since the dynamic characteristics are propor- tive for decreasing angular input. The full-scale velocity output
tional to the signal level. is ± 8 V dc. The output velocity scaling and tracking rate are a
function of the resolution of the converter; this is summarized
The AD2S83 will not be damaged if the signal inputs are below.
applied to the converter without the power supplies and/or
the reference.
Max Tracking Nominal Scaling
REFERENCE INPUT Res Rate (rps) (rps/V dc)
The amplitude of the reference signal applied to the converter’s 10 1040 130
input is not critical, but care should be taken to ensure it is kept 12 260 32.5
within the recommended operating limits. 14 65 8.125
The AD2S83 will not be damaged if the reference is supplied to 16 16.25 2.03
the converter without the power supplies and/or the signal (Velocity O/P = ± 8 V dc nominal)
inputs.
The output velocity can be suitably scaled and used to replace a
HARMONIC DISTORTION conventional DC tachogenerator. For more detailed information
The amount of harmonic distortion allowable on the signal and see the AD2S83 as a Silicon Tachogenerator section.
reference lines is 10%.
DC ERROR SIGNAL
Square waveforms can be used but the input levels should be The signal at the output of the phase sensitive detector
adjusted so that the average value is 1.9 V rms. (For example, a (DEMODULATOR OUTPUT) is the signal to be nulled by
square wave should be 1.9 V peak.) Triangular and sawtooth the tracking loop and is, therefore, proportional to the error
waveforms should have a amplitude of 2 V rms. between the input angle and the output digital angle. As the
Note: The figure specified of 10% harmonic distortion is for converter is a Type 2 servo loop, the demodulator output signal
calibration convenience only. will increase if the output fails to track the input for any reason.
This is an indication that the input has exceeded the maximum
POSITION OUTPUT tracking rate of the converter or, due to some internal or exter-
The resolver shaft position is represented at the converter out- nal malfunction, the converter is unable to reach a null. By con-
put by a natural binary parallel digital word. As the digital posi- necting two external comparators, this voltage can be used as a
tion output of the converter passes through the major carries, “built-in-test.”
i.e., all “1s” to all “0s” or the inverse, a RIPPLE CLOCK (RC)
logic output is initiated indicating that a revolution or a pitch of
the input has been completed.

REV. E –7–
AD2S83
COMPONENT SELECTION 4. Maximum Tracking Rate (R6)
The following instructions describe how to select the external The VCO input resistor R6 sets the maximum tracking rate
components for the converter in order to achieve the required of the converter and hence the velocity scaling as at the max
bandwidth and tracking rate. In all cases the nearest “preferred tracking rate, the velocity output will be 8 V.
value” component should be used, and a 5% tolerance will not Decide on your maximum tracking rate, “T,” in revolutions
degrade the overall performance of the converter. Care should per second. When setting the value for R6, it should be
be taken that the resistors and capacitors will function over the remembered that the linearity of the velocity output is
required operating temperature range. The components should specified across 0 kHz–500 kHz and 500 kHz–1000 kHz.
be connected as shown in Figure 1. The following conversion can be used to determine the
Free PC compatible software is available to help users select the corresponding rps:
optimum component values for the AD2S83, and display the transfer
gain, phase and small step response. VCO Rate (Hz)
rps = N
For more detailed information and explanation, see the Circuit 2
Functions and Dynamic Performance section. Note that “T” must not exceed the maximum tracking rate
1. HF Filter (R1, R2, C1, C2) or 1/16 of the reference frequency.
The function of the HF filter is to remove any dc offset and
10
to reduce the amount of noise present on the signal inputs to 6.81 × 10
the AD2S83, reaching the Phase Sensitive Detector and R6 = Ω
affecting the outputs. R1 and C2 may be omitted—in which T ×n
case R2 = R3 and C1 = C3, calculated below—but their use where n = bits per revolution
is particularly recommended if noise from switch mode = 1,024 for 10 bits resolution
power supplies and brushless motor drive is present. = 4,096 for 12 bits
Values should be chosen so that = 16,384 for 14 bits
= 65,536 for 16 bits
15 kΩ ≤ R1= R2 ≤ 56 kΩ
5. Closed-Loop Bandwidth Selection (C4, C5, R5)
1 a. Choose the closed-loop bandwidth (fBW) required
C1= C2 = ensuring that the ratio of reference frequency to band-
2 π R1 f REF
width does not exceed the following guidelines:
and fREF = Reference Frequency (Hz)
Resolution Ratio of Reference Frequency/Bandwidth
10 2.5 : 1
This filter gives an attenuation of three times at the input to
12 4 :1
the phase sensitive detector.
14 6 :1
2. Gain Scaling Resistor (R4) (See Phase Sensitive Demodula- 16 7.5 : 1
tor section.)
If R1, C2 are used: Typical values may be 100 Hz for a 400 Hz reference fre-
quency and 500 Hz to 1000 Hz for a 5 kHz reference
frequency.
E DC 1
R4 = −9
× Ω b. Select C4 so that
100 × 10 3
21
C4 = F
where 100 × 10–9 = current/LSB R6 × fBW 2
If R1, C2 are not used:
EDC with R6 in Ω and fBW, in Hz selected above.
R4 = –9
Ω
100 × 10 c. C5 is given by
where EDC = 160 × 10–3 for 10 bits resolution C5 = 5 × C4
= 40 × 10–3 for 12 bits d. R5 is given by
= 10 × 10–3 for 14 bits 4
= 2.5 × 10–3 for 16 bits R5 = Ω
= Scaling of the DC ERROR in volts/LSB 2 × π × f BW × C5
3. AC Coupling of Reference Input (R3, C3) 6. VCO Phase Compensation
Select R3 and C3 so that there is no significant phase shift at The following values of C6 and R7 should be connected as
the reference frequency. That is, close as possible to the VCO output, Pin 41.
R3 = 100 kΩ C6 = 390 pF, R7 = 3. 3 kΩ

1 7. VCO Optimization
C3 > F To optimize the performance of the VCO a capacitor, C7,
R3 × fREF should be placed across the VCO input and output, Pins 40
with R3 in Ω. and 41.
C7 = 150 pF

–8– REV. E
 AD2S83
8. Offset Adjust BYTE SELECT Input
Offsets and bias currents at the integrator input can cause an The BYTE SELECT input selects the byte of the position data
additional positional offset at the output of the converter of to be presented at the data output DB1 to DB8. The least sig-
1 arc minute typical, 5.3 arc minutes maximum. If this can be nificant byte will be presented on data output DB9 to DB16
tolerated, then R8 and R9 can be omitted from the circuit. (with the ENABLE input taken to a logic “LO”) regardless of
If fitted, the following values of R8 and R9 should be used: the state of the BYTE SELECT pin. Note that when the AD2S83
is used with a resolution less than 16 bits the unused data lines
R8 = 4.7 MΩ, R9 = 1 MΩ potentiometer are pulled to a logic “LO.” A logic “HI” on the BYTE SELECT
To adjust the zero offset, ensure the resolver is disconnected input will present the eight most significant data bits on data
and all the external components are fitted. Connect the output DB1 and DB8. A logic “LO” will present the least sig-
COS pin to the REFERENCE INPUT and the SIN pin to nificant byte on data outputs 1 to 8, i.e., data outputs 1 to 8 will
the SIGNAL GROUND and with the power and reference duplicate data outputs 9 to 16.
applied, adjust the potentiometer to give all “0s” on the The operation of the BYTE SELECT has no effect on the con-
digital output bits. version process of the converter.
The potentiometer may be replaced with select on test resistors
if preferred. RIPPLE CLOCK
As the output of the converter passes through the major carry,
DATA TRANSFER i.e., all “1s” to all “0s” or the converse, a positive going edge on
To transfer data the INHIBIT input should be used. The data the RIPPLE CLOCK (RC) output is initiated indicating that a
will be valid 490 ns after the application of a logic “LO” to the revolution, or a pitch, of the input has been completed.
INHIBIT. This is regardless of the time when the INHIBIT is The minimum pulsewidth of the ripple clock is 300 ns. RIPPLE
applied and allows time for an active BUSY to clear. By using CLOCK is normally set high before a BUSY pulse and resets
the ENABLE input the two bytes of data can be transferred before the next positive going edge of the next BUSY pulse.
after which the INHIBIT should be returned to a logic “HI” The only exception to this is when DIR changes while the
state to enable the output latches to be updated. RIPPLE CLOCK is high. Resetting of the RIPPLE clock will
BUSY Output only occur if the DIR remains stable for two consecutive posi-
The validity of the output data is indicated by the state of the tive BUSY pulse edges.
BUSY output. When the input to the converter is changing, the If the AD2S83 is being used in a pitch and revolution counting
signal appearing on the BUSY output is a series of pulses at application, the ripple and busy will need to be gated to prevent
TTL level. A BUSY pulse is initiated each time the input moves false decrement or increment (see Figure 2).
by the analog equivalent of one LSB and the internal counter is
incremented or decremented. RIPPLE CLOCK is unaffected by INHIBIT.
INHIBIT Input 5V
The INHIBIT logic input only inhibits the data transfer from
10k 1k
the up-down counter to the output latches and, therefore, does
not interrupt the operation of the tracking loop. Releasing the TO COUNTER
INHIBIT automatically generates a BUSY pulse to refresh the RIPPLE
IN4148
2N3904
(CLOCK)

output data. CLOCK

0V
5V
ENABLE Input
The ENABLE input determines the state of the output data. A 5K1
logic “HI” maintains the output data pins in the high imped- IN4148
BUSY
ance condition, and the application of a logic “LO” presents the
NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS LOW.
data in the latches to the output pins. The operation of the
ENABLE has no effect on the conversion process. Figure 2. Diode Transistor Logic N and Gate

REV. E –9–
AD2S83
BUSY VH
t1
RIPPLE
VL
CLOCK
t2 VH
t4 VH t3

DATA

t5 VL

INHIBIT VH
t6
VH
t7
DIR
VL

t8
t9
INHIBIT
VL

ENABLE VL

t10 VH
VZ
DATA

t11 VL

BYTE VL
SELECT VH

VH

DATA

VL
t12 t13

Figure 3. Digital Timing

Parameter TMIN* TMAX* Condition

t1 150 350 BUSY WIDTH VH–VH
t2 10 25 RIPPLE CLOCK VH to BUSY VH
t3 470 580 RIPPLE CLOCK VL to Next BUSY VH
t4 16 45 BUSY VH to DATA VH
t5 3 25 BUSY VH to DATA VL
t6 70 140 INHIBIT VH to BUSY VH
t7 485 625 MIN DIR VH to BUSY VH
t8 515 670 MIN DIR VH to BUSY VH
t9 – 490 INHIBIT VL to DATA STABLE
t10 40 110 ENABLE VL to DATA VH
t11 35 110 ENABLE VL to DATA VL
t12 60 140 BYTE SELECT VL to DATA STABLE
t13 60 125 BYTE SELECT VH to DATA STABLE
*ns

–10– REV. E
 AD2S83
DIRECTION Output CIRCUIT FUNCTIONS AND DYNAMIC PERFORMANCE
The DIRECTION (DIR) output indicates the direction of the The AD2S83 allows the user great flexibility in choosing the
input rotation. Any change in the state of DIR precedes the dynamic characteristics of the resolver-to-digital conversion to
corresponding BUSY, DATA and RIPPLE CLOCK updates. ensure the optimum system performance. The characteristics
DIR can be considered as an asynchronous output and can are set by the external components shown in Figure 1. The
make multiple changes in state between two consecutive LSB Component Selection section explains how to select desired
update cycles. This occurs when the direction of rotation of the maximum tracking rate and bandwidth values. The following
input changes but the magnitude of the rotation is less than 1 LSB. paragraphs explain in greater detail the circuit of the AD2S83
and the variations in the dynamic performance available to the
COMPLEMENT user.
The COMPLEMENT input is an active low input and is inter-
Loop Compensation
nally pulled to +VS via 100 kΩ.
The AD2S83 (connected as shown in Figure 1) operates as a
Strobing DATA LOAD and COMPLEMENT pins to logic LO Type 2 tracking servo loop where the VCO/counter combination
will set the logic HI bits of the AD2S83 counter to a LO state. and Integrator perform the two integration functions inherent in
Those bits of the applied data which are logic LO will not a Type 2 loop.
change the corresponding bits in the AD2S83 counter.
Additional compensation in the form of a pole/zero pair is
For Example: required to stabilize the loop.
Initial Counter State 10101 This compensation is implemented by the integrator compo-
Applied Data Word 11000 nents (R4, C4, R5, C5).
Counter State after DATA LOAD 11000
The overall response the converter is that of a unity gain second
Initial Counter State 10101 order low-pass filter, with the angle of the resolver as the input
Applied Data Word 11000 and the digital position data as the output.
Counter State after DATA LOAD and Complement 00101
The AD2S83 does not have to be connected as tracking con-
In order to read the counter following a DATA LOAD, the verter, parts of the circuit can be used independently. This is
procedure below should be followed: particularly true of the Ratio Multiplier which can be used as a
1. Place outputs in high impedance state (ENABLE = HI). control transformer. (For more information contact Motion
Control Applications.)
2. Present data to pins.
A block diagram of the AD2S83 is given in Figure 4.
3. Pull DATA LOAD and COMPLEMENT pins to ground.
4. Wait 100 ns.
5. Remove data from pins.
6. Remove outputs from high impedance state (ENABLE =
LO).
7. Read outputs.

R5 C5
AC ERROR

C4

SIN  SIN t
PHASE R4
RATIO
SENSITIVE
MULTIPLIER
COS  SIN t A, SIN (–) SIN t DEMODULATOR
INTEGRATOR

DIGITAL CLOCK
 R6
DIRECTION VCO

VELOCITY

Figure 4. Functional Diagram

REV. E –11–
AD2S83
Ratio Multiplier Phase Sensitive Demodulator
The ratio multiplier is the input section of the AD2S83. This The phase sensitive demodulator is effectively ideal and devel-
compares the signal from the resolver (angle θ) to the digital ops a mean dc output at the DEMODULATOR OUTPUT
(angle φ) held in the counter. Any difference between these pin of
two angles results in an analog voltage at the AC ERROR
OUTPUT. This circuit function has historically been called a ±2 2
“Control Transformer” as it was originally performed by an π × (DEMODULATOR INPUT rms voltage )
electromechanical device known by that name.
for sinusoidal signals in phase or antiphase with the reference
The AC ERROR signal is given by (for a square wave the DEMODULATOR OUTPUT voltage
A1 sin (θ–φ) sin ωt will equal the DEMODULATOR INPUT). This provides a
where ω = 2 π fREF signal at the DEMODULATOR OUTPUT which is a dc level
proportional to the positional error of the converter.
fREF = reference frequency
DC Error Scaling = 160 mV/bit (10-bit resolution)
A1 = the gain of the ratio multiplier stage = 14.5. = 40 mV/bit (12-bit resolution)
So for 2 V rms inputs signals = 10 mV/bit (14-bit resolution)
AC ERROR output in volts/(bit of error) = 2.5 mV/bit (16-bit resolution)
When the tracking loop is closed, this error is nulled to zero
 360 
= 2 × sin  n  × A1 unless the converter input angle is accelerating.
 
Integrator
where n = bits per rev The integrator components (R4, C4, R5, C5) are external to the
= 1,024 for 10-bit resolution AD2S83 to allow the user to determine the optimum dynamic
= 4,096 for 12-bit resolution characteristics for any given application. The Component
= 16,384 for 14-bit resolution Selection section explains how to select components for a
= 65,536 for 16-bit resolution chosen bandwidth.
giving an AC ERROR output Since the output from the integrator is fed to the VCO INPUT,
= 178 mV/bit @ 10-bit resolution it is proportional to velocity (rate of change of output angle) and
= 44.5 mV/bit @ 12-bit resolution can be scaled by selection of R6, the VCO input resistor. This is
= 11.125 mV/bit @ 14-bit resolution explained in the Voltage Controlled Oscillator (VCO) section
= 2.78 mV/bit @ 16-bit resolution below.
The ratio multiplier will work in exactly the same way whether To prevent the converter from “flickering” (i.e., continually
the AD2S83 is connected as a tracking converter or as a control toggling by ± 1 bit when the quantized digital angle, φ, is not an
transformer, where data is preset into the counters using the exact representation of the input angle, θ) feedback is internally
DATA LOAD pin. applied from the VCO to the integrator input to ensure that the
HF Filter VCO will only update the counter when the error is greater than
The AC ERROR OUTPUT may be fed to the PSD via a simple or equal to 1 LSB. In order to ensure that this feedback “hys-
ac coupling network (R2, C1) to remove any dc offset at this teresis” is set to 1 LSB the input current to the integrator must
point. Note, however, that the PSD of the AD2S83 is a wide- be scaled to be 100 nA/bit. Therefore,
band demodulator and is capable of aliasing HF noise down to
DC Error Scaling (mV /bit )
within the loop bandwidth. This is most likely to happen where R4 =
the resolver is situated in particularly noisy environments, and 100 (nA /bit )
the user is advised to fit a simple HF filter R1, C2 prior to the
phase sensitive demodulator. Any offset at the input of the integrator will affect the accuracy
of the conversion as it will be treated as an error signal and
The attenuation and frequency response of a filter will affect the offset the digital output. One LSB of extra error will be added
loop gain and must be taken into account in deriving the loop for each 100 nA of input bias current. The method of adjusting
transfer function. The suggested filter (R1, C1, R2, C2) is out this offset is given in the Component Selection section.
shown in Figure 1 and gives an attenuation at the reference
frequency (fREF) of three times at the input to the phase sensitive Voltage Controlled Oscillator (VCO)
demodulator. The VCO is essentially a simple integrator feeding a pair of dc
level comparators. Whenever the integrator output reaches one
Values of components used in the filter must be chosen to of the comparator threshold voltages, a fixed charge is injected
ensure that the phase shift at fREF is within the allowable signal into the integrator input to balance the input current. At the
to reference phase shift of the converter. same time the counter is clocking either up or down, dependent
on the polarity of the input current. In this way the counter is
clocked at a rate proportional to the magnitude of the input
current of the VCO.

–12– REV. E
 AD2S83
During the VCO reset period the input continues to be inte- 12

grated. The reset period is constant at 40 ns.

9
The VCO rate is fixed for a given input current by the VCO
6
scaling factor:
= 8.5 kHz/µA 3

GAIN PLOT
The tracking rate in rps per µA of VCO input current can be 0
found by dividing the VCO scaling factor by the number of LSB
changes per rev (i.e., 4096 for 12-bit resolution). –3

The input resistor R6 determines the scaling between the con- –6

verter velocity signal voltage at the INTEGRATOR OUTPUT
pin and the VCO input current. Thus to achieve a 5 V output at –9

100 rps (6000 rpm) and 12-bit resolution the VCO input cur- –12
rent must be: 0.0 0.04 0.1 0.2 0.4 1 2
FREQUENCY – fBW
(100 × 4096)/(8500) = 48.2 µA
Figure 5. Gain Plot
Thus, R6 would be set to: 5/(48.2 × 10–6) = 103.7 kΩ
The velocity offset voltage depends on the VCO input resistor, 180

R6, and the VCO bias current and is given by 135

Velocity Offset Voltage = R6 × (VCO bias current)
90
The temperature coefficient of this offset is given by
Velocity Offset Tempco = R6 × (VCO bias current tempco) 45

PHASE PLOT
where the VCO bias current tempco is typically +0.22 nA/°C. 0

The maximum recommended rate for the VCO is 1.1 MHz –45
which sets the maximum possible tracking rate.
–90
Since the minimum voltage swing available at the integrator
output is ± 8 V, this implies that the minimum value for R6 is –135
62 kΩ. As
–180
0.0 0.04 0.1 0.2 0.4 1 2
1.1 × 106 FREQUENCY – fBW
Max Current = = 129 µA
8.5 × 103 Figure 6. Phase Plot
8
Min Value R6 = = 62 kΩ
129 × 10–6
Transfer Function
By selecting components using the method outlined in the sec-
tion “Component Selection,” the converter will have a critically
damped time response and maximum phase margin. The
Closed-Loop Transfer Function is given by:
θOUT 14 (1 + s N )
=
θ IN 2
( s N + 2.4)( s N + 3.4 s N + 5.8)
where, sN, the normalized frequency variable is given by:

2 s
sN = π
f BW
and fBW is the closed-loop 3 dB bandwidth (selected by the
choice of external components).
The acceleration constant KA, is given approximately by
2 –2
K A = 6 × ( f BW ) sec
The normalized gain and phase diagrams are given in Figures 5
and 6.

REV. E –13–
AD2S83
The small signal step response is shown in Figure 7. The time The only effective way to compensate for dynamic loading
from the step to the first peak is t1, and the t2 is the time from effects is to introduce a 2nd order term which will provide the
the step until the converter is settled to 1 LSB. The times t1 and motor with an acceleration or deceleration demand signal (see
t2 are given approximately by Figure 9).

1
t1 = CONTROL
f BW TERMS

5 R MOTOR
t2 = × POSITION
f BW 12 DEMAND
+
–
where R = resolution, i.e., 10, 12, 14 or 16.
VELOCITY
ELECTRONICS
t2 ACTUAL
POSITION

POSITION FEEDBACK
ELECTRONICS SOURCE

Figure 9. Position Control and Velocity Control

Traditionally this would need to be implemented by using sepa-
rate position and speed feedback transducers, e.g., an encoder
TIME
or resolver and a dc tachogenerator. The AD2S83 can decode
t1 the resolver to provide both velocity and position information.
Figure 7. Small Step Response DC Tachogenerator
The DC tachogenerator is a small permanent magnet dc
The large signal step response (for steps greater than 5 degrees)
generator. The output is a dc voltage which is proportional to
applies when the error voltage exceeds the linear range of the
the speed of the rotor and whose polarity is determined by the
converter.
direction of rotation. Physically they are similar to a resolver.
Typically the converter will take three times longer to reach the
Velocity Error Derivation
first peak for a 179 degrees step.
The velocity error is the difference between the synthesized dc
In response to a velocity step, the velocity output will exhibit velocity demand derived from the actual and demand positions
the same time response characteristics as outlined above for the and the feedback from the tachogenerator or the AD2S83. The
position output. velocity demand is usually derived via a DAC so apart from any
quantization noise it is clean. The velocity feedback, therefore,
THE AD2S83 AS A SILICON TACHOGENERATOR needs to be as close to a pure dc level as possible. The errors
Position Control Using the AD2S83 which determine the quality of the resultant acceleration demand
The AD2S83 has been optimized for use as a feedback device to the motor are explained below.
for velocity as well as position. A traditional position control
Linearity
loop shown below compares a demand position with an actual
Linearity is the maximum deviation from the ideal straight line
to derive a position error and hence a velocity demand.
velocity characteristic. The line used is given by:

POSITION
MOTOR v = mx + c
DEMAND
+ CONTROL where
– TERMS
v = velocity
m = gain scaling
x = dc voltage
ACTUAL
POSITION POSITION c = zero velocity dc offset
ELECTRONICS
FEEDBACK
Linearity is generally a function of the input velocity to the
SOURCE tachogenerator or resolver.
Figure 8. Position Control Reversion Error
Quality of control may be reduced if the load on a motor varies Reversion or reversal error is an offset which is dependent on
dynamically. System reaction and compensation for a sudden the direction of rotation of the transducer; e.g., if 10 rps =
change in the loading depends on how rapidly the system can 1.000 V dc, then –10 rps = 1.003 V dc with +0.3% reversion
update the velocity demand to the motor. This can cause rapid error and FSO = ± 8 V dc.
acceleration of the motor until the loop updates with a new Zero Velocity DC Offset
velocity demand. This is a residual dc offset present at zero input velocity. This
can be externally nulled.

–14– REV. E
 AD2S83
Ripple Content ACCELERATION ERROR
Ripple content is due to several factors. Tachogenerators suffer A tracking converter employing a Type 2 servo loop does not
from ripple due to the speed of rotation, commutator segments suffer any velocity lag, however, there is an additional error due
and the number of poles. The resolver/RDC combination has a to acceleration. This additional error can be defined using the
predominant ripple at twice the resolver reference as a result of acceleration constant KA of the converter.
the synchronous demodulator and at a frequency twice per
Input Acceleration
revolution due to the resolver windings mismatch. KA =
Error in Output Angle
Motor torque pulsations which are a consequence of excessive
velocity ripple have a detrimental effect upon the quality of The numerator and denominator must have consistent angular
speed control in servo systems. units. For example if KA is in sec–2, then the input acceleration
may be specified in degrees/sec2 and the error output in degrees.
The resultant “cogging” effect will be particularly noticeable at
low speed and when the motor is in the low torque region. KA does not define maximum input acceleration, only the error due
to acceleration. The maximum acceleration allowable before the
Other undesirable side effects such as the increase in acoustic
converter loses track is dependent on the angular accuracy
noise from a motor and a temperature rise in the motor stator
requirements of the system.
windings are possible results of the presence of torque ripple.
Angular Accuracy × KA = Degrees/sec2
For more detailed information of the causes and sources of KA can be used to predict the output position error for a
errors see the Velocity Errors section. given input acceleration. For example for an acceleration of
100 revs/sec2, KA = 2.7 × 106 sec–2 and 12-bit resolution.
AD2S83 COMPARISON WITH DC TACHOGENERATOR
Comparative tests of the AD2S83 and a dc tachogenerator were 2
Input acceleration [LSB/sec ]
carried out. The tachogenerator was connected at the nondrive Error in LSBs = –2
end of the motor shaft with the resolver located behind the drive K A [sec ]
shaft of the motor. The AD2S83 was located remotely. The
2 12
AD2S83 was set up with a 200 Hz bandwidth, reference fre- 100 [rev /sec ] × 2
= = 0.15 LSBs or 47.5 seconds of arc
quency of 2.6 kHz and resolution of 14 bits. 6
2.7 × 10
The comparative analysis can be summarized:
To determine the value of KA based on the passive components
AD2S83 DC Tacho Conditions used to define the dynamics of the converter the following
should be used.
Linearity % 0.1 0.1 0–3600 rpm 11
Reversion Error % FSO 0.3 0.25 4.04 × 10
KA = n
2 × R6 × R4 × (C4 + C5)
Note the typical operating range of dc tachogenerator is Where n = resolution of the converter.
0 rpm-3600 rpm. The resolver/AD2S83 combination will oper- R4, R6 in ohms
ate up to speeds in excess of 10000 rpm. C5, C4 in farads.
Ripple Effects
The comparative analysis of the output ripple from the tacho-
generator and the AD2S83 is illustrated below.
Minimization of the AD2S83 output ripple is discussed in detail
in the Velocity Errors section.
Other Factors
Other factors concerning choice of feedback source have to be
addressed. On average the MTBF of a tachogenerator is 347
days as opposed to typically 8 years for a resolver. Resolvers are
relatively insensitive to temperature whereas a tachogenerator
will be specified up to a maximum of 100°C with a ± 0.1%/°C
(above 25°C) degradation in output voltage. The brushless
resolver requires no preventative maintenance; the brushes on a
tachogenerator, however, will require periodic checking.

REV. E –15–
AD2S83
SOURCES OF ERRORS VELOCITY ERRORS
Integrator Offset Some “ripple” or noise will always be present in the velocity
Additional inaccuracies in the conversion of the resolver signals signal. Velocity signal ripple is caused by, or related to, the
will result from an offset at the input to the integrator. This following parameters. The resulting effects are generally addi-
offset will be treated as an error signal. The resulting angular tive. This means diagnosis needs to be an iterative process in
error will typically be 1 arc minute over the operating tempera- order to define the source of the error.
ture range. 1.0 Reference Frequency
A description of how to adjust the zero offset is given in the A ripple content at the reference frequency is superimposed
Component Selection section; the circuit required is shown in on the velocity signal output. The amplitude depends on
Figure 1. the loop bandwidth. This error is a function of a dc offset at
the input to Phase Sensitive Demodulator (PSD).
Differential Phase Shift
Phase shift between the sine and cosine signals from the resolver 2.0 Resolver Inaccuracies
is known as differential phase shift and can cause static error. Impedance mismatch occur in the sine and cosine windings
Some differential phase shift will be present on all resolvers as a of the resolver. These give rise to differential phase shift
result of coupling. A small resolver residual voltage (quadrature between the sine and cosine inputs to the RDC and varia-
voltage) indicates a small differential phase shift. Additional tions in the resolver output amplitudes.
phase shift can be introduced if the sine channel wires and the 2.1 Sine and Cosine Amplitude Mismatch
cosine channel wires are treated differently. For instance, differ- This is normally identified by the presence of asymmetrical
ent cable lengths or different loads could cause differential phase ripple voltages.
shift.
2.2 Differential Phase Shift between the Sine and Cosine Inputs
The additional error caused by differential phase shift on the The frequency of this ripple is usually twice the input veloc-
input signals approximates to ity, and the amplitude is proportional to the magnitude of
Error = 0.53 a × b arc minutes the velocity signal. The phase shift is normally induced
through the connections from the resolver to the converter.
where a = differential phase shift (degrees).
Maintaining equal lengths of screened twisted pair cable
b = signal to reference phase shift (degrees).
from the resolver to the AD2S83 will reduce the effects of
This error can be minimized by choosing a resolver with a small resistive imbalance, and therefore, reduce differential phase
residual voltage, ensuring that the sine and cosine signals are shift.
handled identically and removing the reference phase shift (see
3.0 LSB Update Ripple
the Connecting the Resolver section). By taking these precau-
LSB update noise occurs as the resolver rotates and the
tions the extra error can be made insignificant.
digital outputs of the RDC are updated. For a correctly
Most resolvers exhibit a phase shift between the signal and the scaled loop, this ripple component has a magnitude of
reference. This phase shift will, however, give rise under approximately 2 mV peak at 16-bit resolution.
dynamic conditions to an additional error defined by:
3.1 Ripple due to the LSB rate given by:
Shaft Speed (rps) × Phase Shift (Degrees ) LSB rate = N × Reference Frequency
= Error Degrees The PSD generates sums and differences of all its compo-
Reference Frequency nent input frequencies, so when the LSB update rate is an
Under static operating conditions phase shift between the refer- multiple of the reference frequency, a beat frequency is
ence and the signal lines alone will not theoretically affect the generated. The magnitude of this ripple is a function of the
converter’s static accuracy. LSB weighting, i.e., ripple is less at 16 bits.
For example, for a phase shift of 20 degrees, a shaft rotation of 4.0 Torque Ripple
22 rps and a reference frequency of 5 kHz, the converter will Torque ripple is a phenomenon associated with motors. An
exhibit an additional error of: ac motor naturally exhibits a sinusoidal back emf. In an
ideal system the current fed to the motor should, in order
22 × 20 to cancel, also be sinusoidal. In practice the current is often
= 0.088 Degrees
5000 trapezoidal. Consequently, the output torque from the motor
will not be smooth and torque ripple is created. If the load-
This effect can be eliminated by placing a phase shift in the ing on a motor is constant, the velocity of the motor shaft
reference to the converter equivalent to the phase shift in the will vary as a result of the cyclic variation of motor torque.
resolver (see the Connecting the Resolver section). The variation in velocity then appears on the velocity
Note: Capacitive and inductive crosstalk in the signal and reference output as ripple. This is not an error but a true velocity
leads and wiring can cause similar problems. variation in the system.

–16– REV. E
 AD2S83
Offset Errors 1
PHASE LEAD = ARC TAN PHASE LAG = ARC TAN 2fRC
The limiting factor in the measuring of low or “creep” speeds is 2fRC
C R
the level of dc offset present at zero velocity. The zero velocity
dc offset at the output of the AD2S83 is a function of the input R C
bias current to the VCO and the value for the input resistor R6.
PHASE SHIFT
See “Circuit Functions and Dynamic Performance VCO.” CIRCUITS

The offset can be minimized by reducing the maximum tracking Figure 10. Phase Shift Circuits
rate so reducing the value for R6. Offset is a function of tracking
rate and therefore resolution; the dc offset is lowest at 16 bits. TYPICAL CIRCUIT CONFIGURATION
To increase the dynamic range of the velocity dynamic resolu- Figure 11 shows a typical circuit configuration for the AD2S83
tion switching can be employed. (Contact MCG Applications with 12-bit resolution. Values of the external components have
for more information.) been chosen for a reference frequency of 5 kHz and a maximum
tracking rate of 260 rps with a bandwidth of 520 Hz. Placing the
CONNECTING THE RESOLVER values for R4, R6, C4, and C5 in the equation for KA gives a
The recommended connection circuit is shown in Figure 11. value of 1.65 × 106. The resistors are 0.125 W, 5% tolerance
In cases where the reference phase relative to the input signals preferred values. The capacitors are 100 V ceramic, 10% toler-
from the resolver requires adjustment, this can be easily ance components.
achieved by varying the value of the resistor R2 of the HF filter For signal and reference voltages greater than 2 V rms a simple
(see Figure 1). voltage divider circuit of resistors can be used to generate the
Assume that R1 = R2 = R and C1 = C2 = C correct signal level at the converter. Care should be taken to
ensure that the ratios of the resistors between the sine signal line
1 and ground and the cosine signal line and ground are the same.
and Reference Frequency = .
2 π RC Any difference will result in an additional position error.
By altering the value of R2, the phase of the reference relative to For more information on resistive scaling of SIN, COS, and
the input signals will change in an approximately linear manner REFERENCE converter inputs refer to the application note,
for phase shifts of up to 10 degrees. “Circuit Applications of the 2S81 and 2S80 Resolver-to-Digital
Converters.”
Increasing R2 by 10% introduces a phase lag of two degrees.
Decreasing R2 by 10% introduces a phase lead of two degrees.

R9
1M

R8
C2 R2 4.7M
C3 R3 2.2nF 15k
100nF 100k
REFERENCE
INPUT C1 VELOCITY
2.2nF R6 R4 C4 R5 C5 O/P
100nF 62k 130k 1.2nF 200k 6.2nF
R1
15k
COS HIGH C7
RESOLVER REF LOW 150pF C6
R7
SIGNAL COS LOW 390pF 100nF
3.3k
SIN LOW

6 5 4 3 2 1 44 43 42 41 40
SIN HIGH 7 39 –12V

+12V 8 38 RIPPLE CLOCK

9 37 DIRECTION
MSB 10 36 BUSY
11 35 COMPLEMENT
AD2S83
12 TOP VIEW 34 DATA LOAD
(Not to Scale)
DATA 13 33
OUTPUT 14 32 SC2 0V
15 31
16 30 INHIBIT
17 29
18 19 20 21 22 23 24 25 26 27 28
LSB
+5V

ENABLE
BYTE
SELECT

NOTE: R7, C6 AND C7 SHOULD BE CONNECTED AS

CLOSE AS POSSIBLE TO THE CONVERTER PINS.
DATA OUTPUT SIGNAL SCREENS SHOULD BE CONNECTED TO PIN 5.

Figure 11. Typical Circuit Configuration

REV. E –17–
AD2S83
APPLICATIONS OTHER PRODUCT
Control Transformer AD2S90. Low-cost resolver-to-digital converter with outputs
The ratio multiplier of the AD2S83 can be used independently which emulate optical encoders and a serial output for absolute
of the loop integrators as a control transformer. In this mode, position information. Unlike the AD2S83, the AD2S90 requires
the resolver inputs θ are multiplied by a digital angle φ, any no external components to operate. The AD2S90 is built on
difference between φ and θ will be represented by the AC LC2MOS and packaged in a 20-lead PLCC.
ERROR output as Sin ωt sin (θ–φ) or the DEMOD output AD2S80A/AD2S81A/AD2S82A. Monolithic resolver-to-digital
as sin (θ–φ). To use the AD2S83 in this mode refer to the converter. The AD2S80/AD2S82A offer selectable 10, 12, 14,
“Control Transformer” application note. 16 bits of resolution. The AD2S81A has 12-bit resolution. All
devices have user selectable dynamics. The AD2S80A is available
in 40-lead DDIP, 44-lead LCC and is qualified to MIL-STD-
883B REV. E. The is available in a 44-lead PLCC, and the
AD2S81A in a 28-lead DDIP.

–18– REV. E
 AD2S83
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

Plastic Leaded Chip Carrier (PLCC)

(P-44A)

0.180 (4.57)

C00006c–1.5–10/00 (rev. E)
0.165 (4.19)
0.048 (1.21) 0.056 (1.42)
0.025 (0.63)
0.042 (1.07) 0.042 (1.07)
0.015 (0.38)
0.048 (1.21)
6 40
0.042 (1.07) 7 39
PIN 1
IDENTIFIER 0.050
(1.27) 0.63 (16.00)
BSC 0.59 (14.99)

TOP VIEW 0.021 (0.53)

(PINS DOWN) 0.013 (0.33)

0.032 (0.81)
17 29 0.026 (0.66)
18 28
0.020 0.040 (1.01)
(0.50) 0.656 (16.66)
SQ 0.025 (0.64)
R 0.650 (16.51)
0.110 (2.79)
0.695 (17.65)
SQ 0.085 (2.16)
0.685 (17.40)

PRINTED IN U.S.A.

REV. E –19–