AD7819
AD7819
5 V, 200 kSPS
8-Bit Sampling ADC
AD7819
FEATURES FUNCTIONAL BLOCK DIAGRAM
8-Bit ADC with 4.5 s Conversion Time
On-Chip Track and Hold VDD AGND VREF
REV. B
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AD7819* PRODUCT PAGE QUICK LINKS
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(GND = 0 V, VREF = VDD = 3 V 10% to 5 V 10%. All specifications 40C
AD7819SPECIFICATIONS1 to +125C unless otherwise noted.)
Parameter Y Version Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 30 kHz, fSAMPLE = 136 kHz
Signal to (Noise + Distortion) Ratio1 48 dB min
Total Harmonic Distortion (THD)1 70 dB typ
Peak Harmonic or Spurious Noise1 70 dB typ
Intermodulation Distortion2 fa = 29.1 kHz; fb = 29.8 kHz
2nd Order Terms 77 dB typ
3rd Order Terms 77 dB typ
DC ACCURACY
Resolution 8 Bits
Minimum Resolution for Which
No Missing Codes Are Guaranteed 8 Bits
Relative Accuracy1 0.5 LSB max
Differential Nonlinearity (DNL)1 0.5 LSB max
Total Unadjusted Error1 1 LSB max
Gain Error1 0.5 LSB max
Offset Error1 0.5 LSB max
ANALOG INPUT
Input Voltage Range 0 V min
VREF V max
Input Leakage Current2 1 A max
Input Capacitance2 15 pF mx
REFERENCE INPUTS2
VREF Input Voltage Range 1.2 V min
VDD V max
Input Leakage Current 1 A max
Input Capacitance 20 pF max
LOGIC INPUTS2
VINH, Input High Voltage 2.0 V min
VINL, Input Low Voltage 0.4 V max (0.8 V max, VDD = 5 V)
Input Current, IIN 1 A max Typically 10 nA, VIN = 0 V to VDD
Input Capacitance, CIN 8 pF max
LOGIC OUTPUTS
Output High Voltage, VOH 2.4 V min ISOURCE = 200 A
Output Low Voltage, VOL 0.4 V max ISINK = 200 A
High Impedance Leakage Current 1 A max
High Impedance Capacitance 15 pF max
CONVERSION RATE
Conversion Time 4.5 s max
Track/Hold Acquisition Time1 100 ns max See DC Acquisition Section
POWER SUPPLY
VDD 2.75.5 Volts For Specified Performance
IDD Digital Inputs = 0 V or VDD
Normal Operation 3.5 mA max
Power-Down 1 A max VDD = 5 V
Power Dissipation
Normal Operation 17.5 mW max VDD = 5 V
Power-Down 5 W max
Auto Power-Down (Mode 2) VDD = 3 V
1 kSPS Throughput 57.75 W max
10 kSPS Throughput 577.5 W max
50 kSPS Throughput 2.89 mW max
NOTES
1
See Terminology section.
2
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
2 REV. B
AD7819
TIMING CHARACTERISTICS1, 2 (40C to +125C, unless otherwise noted)
Parameter VDD = 3 V 10% VDD = 5 V 10% Unit Conditions/Comments
tPOWER-UP 1.5 1.5 s (max) Power-Up Time of AD7819 after Rising Edge of CONVST.
t1 4.5 4.5 s (max) Conversion Time.
t2 30 30 ns (min) CONVST Pulsewidth.
t3 30 30 ns (max) CONVST Falling Edge to BUSY Rising Edge Delay.
t4 0 0 ns (min) CS to RD Setup Time.
t5 0 0 ns (min) CS Hold Time after RD High.
t 63 10 10 ns (max) Data Access Time after RD Low.
t73, 4 10 10 ns (max) Bus Relinquish Time after RD High.
t 83 100 100 ns (min) Data Bus Relinquish to Falling Edge of CONVST Delay.
NOTES
1
Sample tested to ensure compliance.
2
See Figures 12, 13 and 14.
3
These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V DD = 5 V 10% and
0.4 V or 2 V for V DD = 3 V 10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 7, quoted in the Timing Characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the AD7819 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.
REV. B 3
AD7819
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Description
1 VREF Reference Input, 1.2 V to VDD.
2 VIN Analog Input, 0 V to VREF.
3 GND Analog and Digital Ground.
4 CONVST Convert Start. A low-to-high transition on this pin initiates a 1.5 s pulse on an internally generated
CONVST signal. A high-to-low transition on this line initiates the conversion process if the internal
CONVST signal is low. Depending on the signal on this pin at the end of a conversion, the AD7819
automatically powers down.
5 CS Chip Select. This is a logic input. CS is used in conjunction with RD to enable outputs.
6 RD Read Pin. This is a logic input. When CS is low and RD goes low, the DB7DB0 leave their high
impedance state and data is driven onto the data bus.
7 BUSY ADC Busy Signal. This is a logic output. This signal goes logic high during the conversion process.
815 DB0DB7 Data Bit 0 to 7. These outputs are three-state TTL-compatible.
16 VDD Positive power supply voltage, 2.7 V to 5.5 V.
PIN CONFIGURATION
DIP/SOIC
VREF 1 16 VDD
VIN 2 15 DB7
GND 3 14 DB6
CONVST 4 AD7819 13 DB5
TOP VIEW
CS 5 12 DB4
(Not to Scale)
RD 6 11 DB3
BUSY 7 10 DB2
DB0 8 9 DB1
4 REV. B
AD7819
TERMINOLOGY The AD7819 is tested using the CCIF standard, where two
Signal to (Noise + Distortion) Ratio input frequencies near the top end of the input bandwidth are
This is the measured ratio of signal to (noise + distortion) at the used. In this case, the second and third order terms are of different
output of the A/D converter. The signal is the rms amplitude of significance. The second order terms are usually distanced in
the fundamental. Noise is the rms sum of all nonfundamental frequency from the original sine waves, while the third order
signals up to half the sampling frequency (fS/2), excluding dc. terms are usually at a frequency close to the input frequencies.
The ratio is dependent upon the number of quantization levels As a result, the second and third order terms are specified sepa-
in the digitization process; the more levels, the smaller the quan- rately. The calculation of the intermodulation distortion is as
tization noise. The theoretical signal to (noise + distortion) per the THD specification where it is the ratio of the rms sum
ratio for an ideal N-bit converter with a sine wave input is given of the individual distortion products to the rms amplitude of
by: the fundamental expressed in dBs.
Signal to (Noise + Distortion) = (6.02N + 1.76) dB Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum
Thus for an 8-bit converter, this is 50 dB.
deviation from a straight line passing through the endpoints of
Total Harmonic Distortion the ADC transfer function.
Total harmonic distortion (THD) is the ratio of the rms sum of
Differential Nonlinearity
harmonics to the fundamental. For the AD7819 it is defined as:
This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
2 2 2 2 2
V2 + V 3 + V 4 + V 5 + V6 Offset Error
THD (dB) = 20 log
V1 This is the deviation of the first code transition (0000 . . . 000)
where V1 is the rms amplitude of the fundamental and V2, V3, to (0000 . . . 001) from the ideal, i.e., AGND + 1 LSB.
V4, V5 and V6 are the rms amplitudes of the second through the Offset Error Match
sixth harmonics. This is the difference in Offset Error between any two channels.
Peak Harmonic or Spurious Noise Gain Error
Peak harmonic or spurious noise is defined as the ratio of the This is the deviation of the last code transition (1111 . . . 110)
rms value of the next largest component in the ADC output to (1111 . . . 111) from the ideal, i.e., VREF 1 LSB, after the
spectrum (up to fS/2 and excluding dc) to the rms value of the offset error has been adjusted out.
fundamental. Normally, the value of this specification is deter-
Gain Error Match
mined by the largest harmonic in the spectrum, but for parts
This is the difference in Gain Error between any two channels.
where the harmonics are buried in the noise floor, it will be a
noise peak. Track/Hold Acquisition Time
Track/hold acquisition time is the time required for the output
Intermodulation Distortion
of the track/hold amplifier to reach its final value, within
With inputs consisting of sine waves at two frequencies, fa and
1/2 LSB, after the end of conversion (the point at which the
fb, any active device with nonlinearities will create distortion
track/hold returns to track mode). It also applies to situations
products at sum and difference frequencies of mfa nfb where
where a change in the selected input channel takes place or
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
where there is a step input change on the input voltage applied
neither m nor n are equal to zero. For example, the second order
to the selected VIN input of the AD7819. It means that the user
terms include (fa + fb) and (fa fb), while the third order terms
must wait for the duration of the track/hold acquisition time
include (2fa + fb), (2fa fb), (fa + 2fb) and (fa 2fb).
after the end of conversion or after a step input change to VIN
before starting another conversion, to ensure that the part
operates to specification.
REV. B 5
AD7819
SUPPLY
CIRCUIT DESCRIPTION 2.7V TO 5.5V
10F 0.1F
Converter Operation
The AD7819 is a successive approximation analog-to-digital PARALLEL
VDD VREF INTERFACE
converter based around a charge redistribution DAC. The ADC
DB0-DB7
can convert analog input signals in the range 0 V to VDD. Fig-
AD7819
ures 2 and 3 below show simplified schematics of the ADC. 0V TO VREF
VIN BUSY
INPUT C/P
Figure 2 shows the ADC during its acquisition phase. SW2 is RD
closed and SW1 is in Position A, the comparator is held in a GND CS
balanced condition and the sampling capacitor acquires the sig-
CONVST
nal on VIN+.
will cause the part to power up. (See Power-Up Times section.) C1
If power consumption is of concern, the automatic power-down 3.5pF
at the end of a conversion should be used to improve power
performance. See Power vs. Throughput Rate section of the Figure 6. Equivalent Sampling Circuit
data sheet.
6 REV. B
AD7819
During the acquisition phase the sampling capacitor must be When operating in Mode 2, the ADC is powered down at the
charged to within a 1/2 LSB of its final value. The time it takes end of each conversion and powered up again before the next
to charge the sampling capacitor (TCHARGE) is given by the fol- conversion is initiated. (See Figure 8.)
lowing formula:
MODE 1
TCHARGE = 6.2 (R2 + 125 ) 3.5 pF
VDD
For small values of source impedance, the settling time associ-
ated with the sampling circuit (100 ns) is, in effect, the acquisition EXT CONVST
time of the ADC. For example, with a source impedance (R2) t POWER-UP
of 10 , the charge time for the sampling capacitor is approxi- 1.5s
t POWER-UP
POWER-UP TIMES 1.5s t CONVERT
The AD7819 has a 1.5 s power-up time. When VDD is first con- 4.5s POWER-DOWN
REV. B 7
AD7819
external CONVST and this internal CONVST are input to an
Typical Performance Characteristics OR gate. The resultant signal has the duration of the longer of
the two input signals. Once a conversion has been initiated, the
10 BUSY signal goes high to indicate a conversion is in progress. At
the end of conversion the sampling circuit returns to its track-
ing mode. The end of conversion is indicated by the BUSY
signal going low. This signal may be used to initiate an ISR on a
1 microprocessor. At this point the conversion result is latched
POWER mW
into the output register where it may be read. The AD7819 has
an 8-bit wide parallel interface. The state of the external CONVST
signal at the end of conversion also establishes the mode of
0.1 operation of the AD7819.
Mode 1 Operation (High Speed Sampling)
If the external CONVST is logic high when BUSY goes low, the
part is said to be in Mode 1 operation. While operating in Mode
0.01 1 the AD7819 will not power down between conversions. The
0 5 10 15 20 25 30 35 40 45 50
THROUGHPUT kSPS AD7819 should be operated in Mode 1 for high speed sam-
pling applications, i.e., throughputs greater than 100 kSPS.
Figure 10. Power vs. Throughput Figure 13 shows the timing for Mode 1 operation. From this
0
diagram one can see that a minimum delay of the sum of the
AD7819
conversion time and read time must be left between two succes-
10 2048 POINT FFT sive falling edges of the external CONVST. This is to ensure that
SAMPLING 136.054kHz
20 FIN = 29.961kHz a conversion is not initiated during a read.
30 Mode 2 Operation (Automatic Power-Down)
40 At slower throughput rates the AD7819 may be powered down
between conversion to give a superior power performance.
dBs
50
This is Mode 2 Operation and it is achieved by bringing the
60
CONVST signal logic low before the falling edge of BUSY. Fig-
70 ure 14 shows the timing for Mode 2 Operation. The falling edge
80 of the external CONVST signal may occur before or after the
90
falling edge of the internal CONVST signal, but it is the later
occurring falling edge of both that controls when the first conver-
100
0 7 13 20 27 33 40 47 53 60 66 sion will take place. If the falling edge of the external CONVST
FREQUENCY kHz occurs after that of the internal CONVST, it means that the
Figure 11. SNR moment of the first conversion is controlled exactly, regardless
of any jitter associated with the internal CONVST signal. The
TIMING AND CONTROL parallel interface is still fully operational while the AD7819 is
The AD7819 has only one input for timing and control, i.e., powered down. The AD7819 is powered up again on the rising
the CONVST (convert start signal). The rising edge of this edge of the CONVST signal. The gated CONVST pulse will
CONVST signal initiates a 1.5 s pulse on an internally gener- now remain high long enough for the AD7819 to fully power
ated CONVST signal. This pulse is present to ensure the part up, which takes about 1.5 s. This is ensured by the internal
has enough time to power up before a conversion is initiated. If CONVST signal, which will remain high for 1.5 s.
the external CONVST signal is low, the falling edge of the in-
ternal CONVST signal will cause the sampling circuit to go into
hold mode and initiate a conversion. If, however, the external CONVST EXT
(PIN 4)
CONVST signal is high when the internal CONVST goes low, GATED
INT
it is upon the falling edge of the external CONVST signal that
the sampling circuitry will go into hold mode and initiate a
conversion. The use of the internally generated 1.5 s pulse as 1.5s
8 REV. B
AD7819
t1
t2
EXT CONVST
t3
tPOWER-UP
INT CONVST
BUSY
CS/RD
DB7DB0 8 MSBs
EXT CONVST
tPOWER-UP
t1
INT CONVST
t3
BUSY
CS/RD
DB7DB0 8 MSBs
PARALLEL INTERFACE
BUSY goes logic high. Care must be taken to ensure that a read
The parallel interface of the AD7819 is eight bits wide. The out-
operation does not occur while BUSY is high. Data read from
put data buffers are activated when both CS and RD are logic
the AD7819 while BUSY is high will be invalid. For optimum
low. At this point the contents of the data register are placed on
performance the read operation should end at least 100 ns (t8)
the 8-bit data bus. Figure 15 shows the timing diagram for the par-
prior to the falling edge of the next CONVST.
allel port. The Parallel Interface of the AD7819 is reset when
CONVST
t2
t3 t8
BUSY
t1
CS
t4 t5
RD
t7
t6
DB7DB0 8 MSBs
REV. B 9
AD7819
MICROPROCESSOR INTERFACING
The parallel port on the AD7819 allows the device to be inter-
PSP0PSP7 DB0DB7
faced to a range of many different microcontrollers. This section
explains how to interface the AD7819 with some of the more
common microcontroller parallel interface protocols. PIC16C6x/7x* AD7819*
AD7819 to 8051 CS CS
Figure 16 shows a parallel interface between the AD7819 and
the 8051 microcontroller. The BUSY signal on the AD7819 pro-
vides an interrupt request to the 8051 when a conversion begins. RD RD
Port 0 of the 8051 may serve as an input or output port, or as in
this case when used together, may be used as a bidirectional INT BUSY
low-order address and data bus. The address latch enable out-
put of the 8051 is used to latch the low byte of the address *ADDITIONAL PINS OMITTED FOR CLARITY
during accesses to the device, while the high-order address byte
Figure 17. Interfacing to the PIC16C6x/7x
is supplied from Port 2. Port 2 latches remain stable when the
AD7819 is addressed, as they do not have to be turned around AD7819 to ADSP-21xx
(set to 1) for data input as is the case for Port 0. Figure 18 shows a parallel interface between the AD7819 and
the ADSP-21xx series of DSPs. As before, the BUSY signal on
the AD7819 provides an interrupt request to the DSP when a
conversion begins.
DB0DB7
8051*
AD0AD7
LATCH AD7819* D0D7 DB0DB7
DECODER
ALE A13A0
CS
AD7819*
A8A15 ADSP-21xx* ADDRESS
DECODE
RD RD LOGIC
INT DMS EN CS
BUSY
10 REV. B
AD7819
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C01318010/00 (rev. B)
0.840 (21.33)
0.745 (18.93)
16 9
0.280 (7.11)
0.240 (6.10)
1 8 0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
PIN 1 0.060 (1.52) 0.115 (2.93)
0.015 (0.38)
0.210 (5.33)
MAX 0.130
0.160 (4.06) (3.30)
0.115 (2.93) MIN 0.015 (0.381)
0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.008 (0.204)
0.014 (0.356) (2.54) 0.045 (1.15) PLANE
BSC
0.3937 (10.00)
0.3859 (9.80)
16 9
0.1574 (4.00) 0.2550 (6.20)
0.1497 (3.80) 1 8 0.2284 (5.80)
8
0.0500 0.0192 (0.49)
SEATING
0.0138 (0.35) 0.0099 (0.25) 0 0.0500 (1.27)
(1.27)
PLANE 0.0075 (0.19) 0.0160 (0.41)
BSC
0.201 (5.10)
0.193 (4.90)
16 9
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
8
PRINTED IN U.S.A.
PIN 1
0.006 (0.15)
0.002 (0.05) 0.0433
(1.10)
MAX 8 0.028 (0.70)
0.0256 0.0118 (0.30) 0.020 (0.50)
SEATING 0.0079 (0.20) 0
(0.65) 0.0075 (0.19)
PLANE 0.0035 (0.090)
BSC
REV. B 11