3 V/5 V, 450 16-Bit, Sigma-Delta ADC AD7715 : A Max at 3 V Supplies

a 3 V/5 V, 450 ␮A
16-Bit, Sigma-Delta ADC

AD7715*
FEATURES FUNCTIONAL BLOCK DIAGRAM
Charge-Balancing ADC
16 Bits No Missing Codes REF IN(–) REF IN(+) AVDD DVDD
0.0015% Nonlinearity
CHARGE BALANCING
Programmable Gain Front End A/D CONVERTER
Gains of 1, 2, 32 and 128 SIGMA-DELTA DIGITAL
Differential Input Capability AIN(+) MODULATOR FILTER
BUFFER PGA
Three-Wire Serial Interface AIN(–)
SPI™, QSPI™, MICROWIRE™ and DSP Compatible A = 1–128 CLOCK MCLK IN

GENERATION MCLK OUT
Ability to Buffer the Analog Input
SERIAL RESET
3 V (AD7715-3) or 5 V (AD7715-5) Operation INTERFACE
Low Supply Current: 450␣ ␮A max @ 3␣ V Supplies SCLK
REGISTER BANK CS
Low-Pass Filter with Programmable Output Update
DIN
16-Lead SOIC/DIP/TSSOP DOUT
AD7715 DRDY
AGND DGND
GENERAL DESCRIPTION CMOS construction ensures very low power dissipation, and the
The AD7715 is a complete analog front end for low frequency power-down mode reduces the standby power consumption to
measurement applications. The part can accept low level input 50␣ µW typ. The part is available in a 16-lead, 0.3 inch-wide,
signals directly from a transducer and outputs a serial digital plastic dual-in-line package (DIP) as well as a 16-lead 0.3 inch-
word. It employs a sigma-delta conversion technique to realize wide small outline (SOIC) package and a 16-lead TSSOP package.
up to 16 bits of no missing codes performance. The input signal
is applied to a proprietary programmable gain front end based PRODUCT HIGHLIGHTS
around an analog modulator. The modulator output is pro- 1. The AD7715 consumes less than 450␣ µA in total supply
cessed by an on-chip digital filter. The first notch of this digital current at 3 V supplies and 1␣ MHz master clock, making it
filter can be programmed via the on-chip control register allow- ideal for use in low-power systems. Standby current is less
ing adjustment of the filter cutoff and output update rate. than 10␣ µA.
The AD7715 features a differential analog input as well as a dif- 2. The programmable gain input allows the AD7715 to accept
ferential reference input. It operates from a single supply (+3␣ V input signals directly from a strain gage or transducer remov-
or +5␣ V). It can handle unipolar input signal ranges of 0 mV to ing a considerable amount of signal conditioning.
+20␣ mV, 0 mV to +80␣ mV, 0 V to +1.25␣ V and 0 V to +2.5␣ V. 3. The AD7715 is ideal for microcontroller or DSP processor
It can also handle bipolar input signal ranges of ±20␣ mV, ± 80␣ mV, applications with a three-wire serial interface reducing the
± 1.25␣ V and ± 2.5␣ V. These bipolar ranges are referenced to number of interconnect lines and reducing the number of
the negative input of the differential analog input. The AD7715 opto-couplers required in isolated systems. The part con-
thus performs all signal conditioning and conversion for a single- tains on-chip registers which allow software control over
channel system. output update rate, input gain, signal polarity and calibration
The AD7715 is ideal for use in smart, microcontroller or DSP modes.
based systems. It features a serial interface that can be config- 4. The part features excellent static performance specifications
ured for three-wire operation. Gain settings, signal polarity and with 16-bits no missing codes, ± 0.0015% accuracy and low
update rate selection can be configured in software using the rms noise (<550␣ nV). Endpoint errors and the effects of
input serial port. The part contains self-calibration and system temperature drift are eliminated by on-chip calibration op-
calibration options to eliminate gain and offset errors on the tions, which remove zero-scale and full-scale errors.
part itself or in the system.
SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corporation.
*Protected by U.S. Patent No: 5,134,401.
See page 30 for data sheet index.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1998
AD7715-5–SPECIFICATIONS (AVDD = +5␣ V, DVDD = +3␣ V or +5␣ V, REF IN(+) = +2.5␣ V; REF␣ IN(–) = AGND;
fCLK IN = 2.4576␣ MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
Parameter A Version1 Units Conditions/Comments
STATIC PERFORMANCE
No Missing Codes 16 Bits min Guaranteed by Design. Filter Notch ≤ 60␣ Hz
Output Noise See Tables V to VIII Depends on Filter Cutoffs and Selected Gain
Integral Nonlinearity ± 0.0015 % of FSR max Filter Notch ≤ 60␣ Hz
Unipolar Offset Error See Note 2
Unipolar Offset Drift3 0.5 µV/°C typ
Bipolar Zero Error See Note 2
Bipolar Zero Drift3 0.5 µV/°C typ
Positive Full-Scale Error 4 See Note 2
Full-Scale Drift3, 5 0.5 µV/°C typ
Gain Error6 See Note 2
Gain Drift3, 7 0.5 ppm of FSR/°C typ
Bipolar Negative Full-Scale Error 2 ± 0.0015 % of FSR max Typically ± 0.0004%
Bipolar Negative Full-Scale Drift 3 1 µV/°C typ For Gains of 1 and 2
0.6 µV/°C typ For Gains of 32 and 128
ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN Unless Noted
Input Common-Mode Rejection (CMR) 90 dB min at DC. Typically 102 dB
Normal-Mode 50 Hz Rejection 8 98 dB min For Filter Notches of 25 Hz, 50 Hz, ± 0.02 × fNOTCH
Common-Mode 50 Hz Rejection 8 150 dB min For Filter Notches of 25 Hz, 50 Hz, ± 0.02 × fNOTCH
Common-Mode Voltage Range 9 AGND to AVDD V min to V max AIN for BUF Bit of Setup Register = 0 and REF IN
Absolute AIN/REF IN Voltage 8 AGND – 30 mV V min AIN for BUF Bit of Setup Register = 0 and REF IN
AVDD + 30␣ mV V max
Absolute/Common-Mode AIN Voltage9 AGND + 50␣ mV V min BUF Bit of Setup Register = 1
AVDD – 1.5␣ V V max
AIN DC Input Current8 1 nA max
AIN Sampling Capacitance 8 10 pF max
AIN Differential Voltage Range 10 0 to +VREF/GAIN11 nom Unipolar Input Range (B/U Bit of Setup Register = 1)
± VREF/GAIN nom Bipolar Input Range (B/U Bit of Setup Register = 0)
AIN Input Sampling Rate, f S GAIN × fCLK␣ IN/64 For Gains of 1 and 2
fCLK␣ IN/8 For Gains of 32 and 128
REF IN(+) – REF IN(–) Voltage +2.5 V nom ± 1% for Specified Performance. Functional with
Lower VREF
REF IN Input Sampling Rate, f S fCLK IN/64
LOGIC INPUTS
Input Current ± 10 µA max
All Inputs Except MCLK IN
VINL, Input Low Voltage 0.8 V max DVDD = +5␣ V
VINL, Input Low Voltage 0.4 V max DVDD = +3.3␣ V
VINH, Input High Voltage 2.4 V min DVDD = +5 V
VINH, Input High Voltage 2.0 V min
MCLK IN Only
VINL, Input Low Voltage 0.8 V max DVDD = +5␣ V
VINL, Input Low Voltage 0.4 V max DVDD = +3.3␣ V
VINH, Input High Voltage 3.5 V min DVDD = +5␣ V
VINH, Input High Voltage 2.5 V min DVDD = +3.3␣ V
LOGIC OUTPUTS (Including MCLK OUT)
VOL, Output Low Voltage 0.4 V max ISINK = 800␣ µA Except for MCLK OUT12. DVDD = +5␣ V
VOL, Output Low Voltage 0.4 V max ISINK = 100␣ µA Except for MCLK OUT12. DVDD = +3.3␣ V
VOH, Output High Voltage 4.0 V min ISOURCE = 200 µA Except for MCLK OUT12. DVDD = +5␣ V
VOH, Output High Voltage DVDD – 0.6 V V min ISOURCE = 100 µA Except for MCLK OUT12. DVDD = +3.3␣ V
Floating State Leakage Current ± 10 µA max
Floating State Output Capacitance 13 9 pF typ
Data Output Coding Binary Unipolar Mode
Offset Binary Bipolar Mode
–2– REV. B
AD7715-3–SPECIFICATIONS (AV = +3␣ V, DV = +3 V, REF IN (+) = +1.25␣ V; REF␣ IN(–) = AGND; AD7715
DD DD
f = 2.4576␣ MHz unless otherwise noted. All specifications T to T unless otherwise noted.)
CLK IN MIN MAX
Parameter A Version1 Units Conditions/Comments

STATIC PERFORMANCE
No Missing Codes 16 Bits min Guaranteed by Design. Filter Notch ≤ 60␣ Hz
Output Noise See Tables IX to XII Depends on Filter Cutoffs and Selected Gain
Integral Nonlinearity ± 0.0015 % of FSR max Filter Notch ≤ 60␣ Hz
Unipolar Offset Error See Note 2
Unipolar Offset Drift3 0.2 µV/°C typ
Bipolar Zero Error See Note 2
Bipolar Zero Drift3 0.2 µV/°C typ
Positive Full-Scale Error 4 See Note 2
Full-Scale Drift3, 5 0.2 µV/°C typ
Gain Error6 See Note 2
Gain Drift3, 7 0.2 ppm of FSR/°C typ
Bipolar Negative Full-Scale Error 2 ± 0.003 % of FSR max Typically ± 0.0004%
Bipolar Negative Full-Scale Drift 3 1 µV/°C typ For Gains of 1 and 2
0.6 µV/°C typ For Gains of 32 and 128
ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN Unless Noted
Input Common-Mode Rejection (CMR) 90 dB min at DC. Typically 102 dB
Common-Mode Voltage Range 9 AGND to AVDD V min to V max AIN for BUF Bit of Setup Register = 0 and REF IN
Absolute AIN/REF IN Voltage 8 AGND – 30 mV V min AIN for BUF Bit of Setup Register = 0 and REF IN
AVDD + 30␣ mV V max
Absolute/Common-Mode AIN Voltage 9 AGND + 50␣ mV V min BUF Bit of Setup Register = 1
AVDD – 1.5␣ V V max
AIN DC Input Current8 1 nA max
AIN Sampling Capacitance 8 10 pF max
AIN Differential Voltage Range 10 0 to +VREF/GAIN11 nom Unipolar Input Range (B/U Bit of Setup Register = 1)
± VREF/GAIN nom Bipolar Input Range (B/U Bit of Setup Register = 0)
AIN Input Sampling Rate, f S GAIN × fCLK␣ IN/64 For Gains of 1 and 2
fCLK␣ IN/8 For Gains of 32 and 128
REF IN(+) – REF IN(–) Voltage +1.25 V nom ±1% for Specified Performance. Functional with Lower VREF
REF IN Input Sampling Rate, f S fCLK IN/64
LOGIC INPUTS
Input Current ± 10 µA max
All Inputs Except MCLK IN
VINL, Input Low Voltage 0.8 V max
MCLK IN Only
VINL, Input Low Voltage 0.4 V max
LOGIC OUTPUTS (Including MCLK OUT)
VOL, Output Low Voltage 0.4 V max ISINK = 100␣ µA Except for MCLK OUT12
VOH, Output High Voltage DVDD – 0.6 V min ISOURCE = 100 µA Except for MCLK OUT 12
Floating State Leakage Current ± 10 µA max
Floating State Output Capacitance 13 9 pF typ
Data Output Coding Binary Unipolar Mode
Offset Binary Bipolar Mode
REV. B –3–
AD7715–SPECIFICATIONS A (AVDD = +3␣ V to +5␣ V, DVDD = +3␣ V to +5␣ V, REF IN(+) = +1.25␣ V (AD7715-3) or +2.5␣ V
(AD7715-5); REF␣ IN(–) = AGND; MCLK␣ IN = 1␣ MHz to 2.4576␣ MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
Parameter A Version Units Conditions/Comments
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit 14 (1.05 × VREF)/GAIN V max GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
Negative Full-Scale Calibration Limit 14 –(1.05 × VREF)/GAIN V max GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
Offset Calibration Limit15 –(1.05 × VREF)/GAIN V max GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
Input Span15 0.8 × VREF/GAIN V min GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
(2.1 × VREF)/GAIN V max GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
POWER REQUIREMENTS
Power Supply Voltages
AVDD Voltage (AD7715-3) +3 to +3.6 V For Specified Performance
AVDD Voltage (AD7715-5) +4.75 to +5.25 V For Specified Performance
DVDD Voltage +3 to +5.25 V For Specified Performance
Power Supply Currents
AVDD Current AVDD = 3.3␣ V or 5␣ V. Gain = 1 to 128 (f CLK IN = 1␣ MHz) or
Gain = 1 or 2 (fCLK IN = 2.4576␣ MHz)
0.27 mA max Typically 0.2␣ mA. BUF Bit of Setup Register = 0
AVDD = 3.3␣ V or 5␣ V. Gain = 32 or 128 (fCLK IN = 2.4576␣ MHz)16
DVDD Current17 Digital I/Ps = 0␣ V or DV DD. External MCLK IN
0.18 mA max Typically 0.15␣ mA. DV DD = 3.3␣ V. fCLK IN = 1␣ MHz
0.4 mA max Typically 0.3␣ mA. DV DD = 5␣ V. fCLK IN = 1␣ MHz
0.5 mA max Typically 0.4␣ mA. DV DD = 3.3␣ V. fCLK IN = 2.4576␣ MHz
0.8 mA max Typically 0.6␣ mA. DV DD = 5␣ V. fCLK IN = 2.4576␣ MHz
Power Supply Rejection 18 See Note 19 dB typ
Normal-Mode Power Dissipation 17 AVDD = DVDD = +3.3␣ V. Digital I/Ps = 0␣ V or DVDD. External MCLK IN
1.5 mW max BUF Bit = 0. All Gains 1␣ MHz Clock
3.3 mW max BUF Bit = 0. Gain = 32 or 128 @ f CLK IN = 2.4576␣ MHz
Normal-Mode Power Dissipation 17 AVDD = DVDD = +5␣ V. Digital I/Ps = 0␣ V or DVDD. External MCLK IN
5 mW max BUF Bit = 1. All Gains 1␣ MHz Clock
Standby (Power-Down) Current 20 20 µA max External MCLK IN = 0␣ V or DV DD. Typically 10␣ µA. VDD = +5␣ V
Standby (Power-Down) Current 20 10 µA max External MCLK IN = 0␣ V or DV DD. Typically 5␣ µA. VDD = +3.3␣ V
NOTES
1
Temperature Range as follows: A Version, –40°C to +85°C.
2
A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables V to XII. This applies after calibration at the
temperature of interest.
3
Recalibration at any temperature will remove these drift errors.
4
Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.
5
Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.
6
Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error–Unipolar Offset Error for unipolar ranges and Full-Scale Error–Bipolar Zero Error
for bipolar ranges.
7
Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero scale calibrations only were performed.
8
These numbers are guaranteed by design and/or characterization.
9
This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(–) does not go more positive than A VDD + 30 mV or go more nega-
tive than AGND – 30␣ mV.
10
The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(–). The absolute voltage on the analog inputs should not go more posi-
tive than AVDD + 30␣ mV or go more negative than AGND␣ – 30␣ mV.
11
VREF = REF IN(+) – REF IN(–).
12
These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.
13
Sample tested at +25°C to ensure compliance.
14
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
15
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AVDD + 30␣ mV or go more negative than AGND –
30␣ mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
16
Assumes CLK Bit of Setup Register is set to correct status corresponding to the master clock frequency.
17
When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation will vary depending on
the crystal or resonator type (see Clocking and Oscillator Circuit section).
18
Measured at dc and applies in the selected passband. PSRR at 50␣ Hz will exceed 120␣ dB with filter notches of 25 Hz or 50␣ Hz. PSRR at 60␣ Hz will exceed 120␣ dB
with filter notches of 20 Hz or 60␣ Hz.
19
PSRR depends on gain. Gain of 1: 85 dB typ; Gain of 2: 90 dB typ; Gains of 32 and 128: 95 dB typ.
20
If the external master clock continues to run in standby mode, the standby current increases to 50␣ µA typical. When using a crystal or ceramic resonator across the
MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or
resonator type (see Standby Mode section).
Specifications subject to change without notice.
–4– REV. B
AD7715
(DVDD = +3␣ V to +5.25␣ V; AVDD = +3␣ V to +5.25␣ V; AGND = DGND = 0 V; fCLKIN = 2.4576␣ MHz;
TIMING CHARACTERISTICS1, 2 Input Logic 0 = 0 V, Logic 1 = DV DD, unless otherwise noted)
Limit at TMIN, TMAX

Parameter (A Version) Units Conditions/Comments
3, 4
fCLKIN 400 kHz min Master Clock Frequency: Crystal Oscillator or Externally Supplied
2.5 MHz max for Specified Performance
tCLK IN LO 0.4 × tCLK IN ns min Master Clock Input Low Time. t CLK IN = 1/fCLK IN
tCLK IN HI 0.4 × tCLK IN ns min Master Clock Input High Time
t1 500 × tCLK IN ns nom DRDY High Time
t2 100 ns min RESET Pulsewidth
Read Operation
t3 0 ns min DRDY to CS Setup Time
t4 120 ns min CS Falling Edge to SCLK Rising Edge Setup Time
t 55 0 ns min SCLK Falling Edge to Data Valid Delay
80 ns max DVDD = +5␣ V
100 ns max DVDD = +3.3␣ V
t6 100 ns min SCLK High Pulsewidth
t7 100 ns min SCLK Low Pulsewidth
t8 0 ns min CS Rising Edge to SCLK Rising Edge Hold Time
t 96 10 ns min Bus Relinquish Time after SCLK Rising Edge
60 ns max DVDD = +5␣ V
100 ns max DVDD = +3.3␣ V
t10 100 ns max SCLK Falling Edge to DRDY High7
Write Operation
t11 120 ns min CS Falling Edge to SCLK Rising Edge Setup Time
t12 30 ns min Data Valid to SCLK Rising Edge Setup Time
t13 20 ns min Data Valid to SCLK Rising Edge Hold Time
t14 100 ns min SCLK High Pulsewidth
t15 100 ns min SCLK Low Pulsewidth
t16 0 ns min CS Rising Edge to SCLK Rising Edge Hold Time
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of D VDD) and timed from a voltage level of 1.6 V.
2
See Figures 6 and 7.
3
CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7715 is not in Standby mode. If no clock is present in this case, the
device can draw higher current than specified and possibly become uncalibrated.
4
The AD7715 is production tested with f CLKIN at 2.4576␣ MHz (1␣ MHz for some I DD tests). It is guaranteed by characterization to operate at 400␣ kHz.
5
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.
6
These numbers are derived from the measured time taken by the data output to change 0.5␣ V when loaded with the circuit of Figure 1. The measured number is
then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and as such are independent of external bus loading capacitances.
7
DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although care
should be taken that subsequent reads do not occur close to the next output update.
Specifications subject to change without notice.
ISINK (800mA at DVDD = +5V

100mA at DVDD = +3.3V)
TO
OUTPUT +1.6V
PIN
50pF
ISOURCE (200mA at DVDD = +5V

100mA at DVDD = +3.3V)
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
REV. B –5–
AD7715
ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION
(TA = +25°C unless otherwise noted) DIP, SOIC and TSSOP
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7␣ V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7␣ V
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7␣ V SCLK 1 16 DGND
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7␣ V MCLK IN 2 15 DVDD
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7␣ V MCLK OUT 3 14 DIN
Analog Input Voltage to AGND . . . . . –0.3 V to AVDD + 0.3␣ V CS 4 AD7715 13 DOUT
Reference Input Voltage to AGND . . . –0.3 V to AVDD + 0.3␣ V TOP VIEW
RESET 5 (Not to Scale) 12 DRDY
Digital Input Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V
AVDD 6 11 AGND
Digital Output Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
AIN(+) 7 10 REF IN(–)
Operating Temperature Range
AIN(–) 8 9 REF IN(+)
Commercial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 128°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4000 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
AVDD Temperature Package

Model Supply Range Options*
AD7715AN-5 5V –40°C to +85°C N-16
AD7715AR-5 5V –40°C to +85°C R-16
AD7715ARU-5 5V –40°C to +85°C RU-16
AD7715AN-3 3V –40°C to +85°C N-16
AD7715AR-3 3V –40°C to +85°C R-16
AD7715ARU-3 3V –40°C to +85°C RU-16
AD7715AChips-5 5V –40°C to +85°C Die
AD7715AChips-3 3V –40°C to +85°C Die
EVAL-AD7715-5EB 5V Evaluation Board
EVAL-AD7715-3EB 3V Evaluation Board
*N = Plastic DIP; R = SOIC RU = TSSOP.
–6– REV. B
AD7715
PIN FUNCTION DESCRIPTION
Pin No. Mnemonic Function

1 SCLK Serial Clock. Logic Input. An external serial clock is applied to this input to access serial data from
the AD7715. This serial clock can be a continuous clock with all data transmitted in a continuous
train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmit-
ted to the AD7715 in smaller batches of data.
2 MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal/resonator or exter-
nal clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alterna-
tively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left
unconnected. The part is specified with clock input frequencies of both 1␣ MHz and 2.4576␣ MHz.
3 MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected be-
tween MCLK IN and MCLK␣ OUT. If an external clock is applied to MCLK IN, MCLK␣ OUT
provides an inverted clock signal. This clock can be used to provide a clock source for external
circuitry.
4 CS Chip Select. Active low Logic Input used to select the AD7715. With this input hardwired low, the
AD7715 can operate in its three-wire interface mode with SCLK, DIN and DOUT used to inter-
face to the device. CS can be used to select the device in systems with more than one device on the
serial bus or as a frame synchronization signal in communicating with the AD7715.
5 RESET Logic Input. Active low input which resets the control logic, interface logic, calibration coefficients,
digital filter and analog modulator of the part to power-on status.
6 AVDD Analog Positive Supply Voltage, +3.3␣ V nominal (AD7715-3) or +5␣ V nominal (AD7715-5).
7 AIN(+) Analog Input. Positive input of the programmable gain differential analog input to the AD7715.
8 AIN(–) Analog Input. Negative input of the programmable gain differential analog input to the AD7715.
9 REF IN(+) Reference Input. Positive input of the differential reference input to the AD7715. The reference
input is differential with the provision that REF IN(+) must be greater than REF IN(–).
REF␣ IN(+) can lie anywhere between AVDD and AGND.
10 REF IN(–) Reference Input. Negative input of the differential reference input to the AD7715. The REF␣ IN(–)
can lie anywhere between AVDD and AGND provided REF␣ IN(+) is greater than REF␣ IN(–).
11 AGND Ground reference point for analog circuitry. For correct operation of the AD7715, no voltage on
any of the other pins should go more than 30 mV negative with respect to AGND.
12 DRDY Logic Output. A logic low on this output indicates that a new output word is available from the
AD7715 data register. The DRDY pin will return high upon completion of a read operation of a full
output word. If no data read has taken place between output updates, the DRDY line will return
high for 500 × tCLK␣ IN cycles prior to the next output update. While DRDY is high, a read operation
should not be attempted or in progress to avoid reading from the data register as it is being updated.
The DRDY line will return low again when the update has taken place. DRDY is also used to indi-
cate when the AD7715 has completed its on-chip calibration sequence.
13 DOUT Serial Data Output with serial data being read from the output shift register on the part. This output
shift register can contain information from the setup register, communications register or data regis-
ter depending on the register selection bits of the Communications Register.
14 DIN Serial Data Input with serial data being written to the input shift register on the part. Data from this
input shift register is transferred to the setup register or communications register depending on the
register selection bits of the Communications Register.
15 DVDD Digital Supply Voltage, +3.3␣ V or +5 V nominal.
16 DGND Ground reference point for digital circuitry.
REV. B –7–
AD7715
TERMINOLOGY Positive Full-Scale Overrange
Integral Nonlinearity Positive full-scale overrange is the amount of overhead available
This is the maximum deviation of any code from a straight line to handle input voltages on AIN(+) input greater than AIN(–) +
passing through the endpoints of the transfer function. The end- VREF/GAIN (for example, noise peaks or excess voltages due to
points of the transfer function are Zero-Scale (not to be confused system gain errors in system calibration routines) without intro-
with Bipolar Zero), a point 0.5 LSB below the first code transition ducing errors due to overloading the analog modulator or over-
(000 . . . 000 to 000 . . . 001) and Full-Scale, a point 0.5␣ LSB flowing the digital filter.
above the last code transition (111 . . . 110 to 111 . . . 111). The Negative Full-Scale Overrange
error is expressed as a percentage of full scale. This is the amount of overhead available to handle voltages on
Positive Full-Scale Error AIN(+) below AIN(–) –VREF/GAIN without overloading the
Positive Full-Scale Error is the deviation of the last code transi- analog modulator or overflowing the digital filter. Note that the
tion (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage analog input will accept negative voltage peaks even in the uni-
(AIN(–) + VREF/GAIN –3/2 LSBs). It applies to both unipolar polar mode provided that AIN(+) is greater than AIN(–) and
and bipolar analog input ranges. greater than AGND –␣ 30␣ mV.
Unipolar Offset Error Offset Calibration Range
Unipolar Offset Error is the deviation of the first code transition In the system calibration modes, the AD7715 calibrates its
from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper- offset with respect to the analog input. The offset calibration
ating in the unipolar mode. range specification defines the range of voltages that the
Bipolar Zero Error
AD7715 can accept and still calibrate offset accurately.
This is the deviation of the midscale transition (0111 . . . 111 Full-Scale Calibration Range
to 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) This is the range of voltages that the AD7715 can accept in the
– 0.5␣ LSB) when operating in the bipolar mode. system calibration mode and still calibrate full scale correctly.
Gain Error Input Span
This is a measure of the span error of the ADC. It includes full- In system calibration schemes, two voltages applied in sequence
scale errors but not zero-scale errors. For unipolar input ranges to the AD7715’s analog input define the analog input range.
it is defined as (full scale error–unipolar offset error) while for The input span specification defines the minimum and maxi-
bipolar input ranges it is defined as (full-scale error–bipolar zero mum input voltages from zero to full scale that the AD7715 can
error). accept and still calibrate gain accurately.
Bipolar Negative Full-Scale Error
This is the deviation of the first code transition from the ideal
AIN(+) voltage (AIN(–) – VREF/GAIN + 0.5␣ LSB), when oper-
ating in the bipolar mode.
ON-CHIP REGISTERS
The part contains four on-chip registers which can be accessed by via the serial port on the part. The first of these is a Communica-
tions Register that decides whether the next operation is a read or write operation and also decides which register the read or write
operation accesses. All communications to the part must start with a write operation to the Communications Register. After power-
on or RESET, the device expects a write to its Communications Register. The data written to this register determines whether the
next operation to the part is a write or a read operation and also determines to which register this read or write operation occurs.
Therefore, write access to any of the other registers on the part starts with a write operation to the Communications Register fol-
lowed by a write to the selected register. A read operation from any register on the part (including the Communications Register itself
and the output data register) starts with a write operation to the Communications Register followed by a read operation from the
selected register. The Communication Register also controls the standby mode and the operating gain of the part. The DRDY status
is also available by reading from the Communications Register. The second register is a Setup Register that determines calibration
modes, filter selection and bipolar/unipolar operation. The third register is the Data Register from which the output data from the
part is accessed. The final register is a Test Register that is accessed when testing the device. It is advised that the user does not
attempt to access or change the contents of the test register as it may lead to unspecified operation of the device. The registers are
discussed in more detail in the following sections.
–8– REV. B
AD7715
Communications Register (RS1, RS0 = 0, 0)
The Communications Register is an eight-bit register from which data can either be read or to which data can be written. All com-
munications to the part must start with a write operation to the Communications Register. The data written to the Communications
Register determines whether the next operation is a read or write operation and to which register this operation takes place. Once the
subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to
the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7715 is in this
default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, if a
write operation to the device of sufficient duration (containing at least 32 serial clock cycles) takes place with DIN high, the AD7715
returns to this default state. Table I outlines the bit designations for the Communications Register.
Table I. Communications Register
0/DRDY ZERO RS1 RS0 R/W STBY G1 G0
0/DRDY For a write operation, a 0 must be written to this bit so that the write operation to the Communications Reg-
ister actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the regis-
ter. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to this bit, the next 7 bits
will be loaded to the Communications Register. For a read operation, this bit provides the status of the
DRDY flag from the part. The status of this bit is the same as the DRDY output pin.
ZERO For a write operation, a 0 must be written to this bit for correct operation of the part. Failure to do this will
result in unspecified operation of the device. For a read operation, a 0 will be read back from this bit location.
RS1– RS0 Register Selection Bits. These bits select to which one of four on-chip registers the next read or write opera-
tion takes place as shown in Table II along with the register size. When the read or write to the selected regis-
ter is complete, the part returns to where it is waiting for a write operation to the Communications Register.
It does not remain in a state where it will continue to access the selected register.
R/W Read/Write Select. This bit selects whether the next operation is a read or write operation to the selected
register. A 0 indicates a write cycle as the next operation to the appropriate register, while a 1 indicates a read
operation from the appropriate register.
Table II. Register Selection
RS1 RS0 Register Register Size

0 0 Communications Register 8 Bits
0 1 Setup Register 8 Bits
1 0 Test Register 8 Bits
1 1 Data Register 16 Bits
STBY Standby. Writing a 1 to this bit puts the part in its standby or power-down mode. In this mode, the part
consumes only 10␣ µA of power supply current. The part retains its calibration and control word information
when in STANDBY. Writing a 0 to this bit places the part in its normal operating mode. The default value
for this bit after power-on or RESET is 0.
G2 G1 Gain Setting
0 0 1
0 1 2
1 0 32
1 1 128
REV. B –9–
AD7715
Setup Register (RS1, RS0 = 0, 1); Power On/Reset Status: 28␣ Hex
The Setup Register is an eight-bit register from which data can either be read or to which data can be written. This register controls
the setup which the device is to operate in such as the calibration mode, output rate, unipolar/bipolar operation etc. Table III out-
lines the bit designations for the Setup Register.
Table III. Setup Register
MD1 MD0 CLK FS1 FS0 B/U BUF FSYNC
MD1 MD0 Operating Mode

0 0 Normal Mode; this is the normal mode of operation of the device whereby the device is performing normal
conversions. This is the default condition of these bits after Power-On or RESET.
0 1 Self-Calibration; this activates self-calibration on the part. This is a one step calibration sequence and when
complete the part returns to Normal Mode with MD1 and MD0 returning to 0, 0. The DRDY output or bit
goes high when calibration is initiated and returns low when this self-calibration is complete and a new valid
word is available in the data register. The zero-scale calibration is performed at the selected gain on internally
shorted (zeroed) inputs and the full-scale calibration is performed at the selected gain on an internally
generated VREF/Selected Gain.
1 0 Zero-Scale System Calibration; this activates zero-scale system calibration on the part. Calibration is per-
formed at the selected gain on the input voltage provided at the analog input during this calibration sequence.
This input voltage should remain stable for the duration of the calibration. The DRDY output or bit goes
high when calibration is initiated and returns low when this zero-scale calibration is complete and a new valid
word is available in the data register. At the end of the calibration, the part returns to Normal Mode with
MD1 and MD0 returning to 0, 0.
1 1 Full-Scale System Calibration; this activates full-scale system calibration on the part. Calibration is per-
formed at the selected gain on the input voltage provided at the analog input during this calibration sequence.
This input voltage should remain stable for the duration of the calibration. Once again, the DRDY output or
bit goes high when calibration is initiated and returns low when this full-scale calibration is complete and a
new valid word is available in the data register. At the end of the calibration, the part returns to Normal
Mode with MD1 and MD0 returning to 0, 0.
CLK Clock Bit. This bit should be set in accordance with the operating frequency of the AD7715. If the device has
a master clock frequency of 2.4576␣ MHz, then this bit should be set to a 1. If the device has a master clock
frequency of 1␣ MHz, then this bit should be set to a 0. This bit sets up the correct scaling currents for a given
master clock and also chooses (along with FS1 and FS0) the output update rate for the device. If this bit is
not set correctly for the master clock frequency of the device, then the device may not operate to specifica-
tion. The default value for this bit after power-on or RESET is 1.
FS1, FS0 Filter Selection Bits. Along with the CLK bit, FS1 and FS0 determine the output update rate, filter first
notch and –3 dB frequency as outlined in Table IV. The on-chip digital filter provides a Sinc3 (or (Sinx/x)3 )
filter response. In association with the gain selection, it also determines the output noise (and hence the
resolution) of the device. Changing the filter notch frequency, as well as the selected gain, impacts resolution.
Tables V through XII show the effect of the filter notch frequency and gain on the output noise and effective
resolution of the part. The output data rate (or effective conversion time) for the device is equal to the fre-
quency selected for the first notch of the filter. For example, if the first notch of the filter is selected at 50␣ Hz
then a new word is available at a 50 Hz rate or every 20␣ ms. If the first notch is at 500␣ Hz, a new word is
available every 2␣ ms. The default value for these bits is 1, 0.
The settling-time of the filter to a full-scale step input change is worst case 4 × 1/(output data rate). For
example, with the first filter notch at 50␣ Hz, the settling time of the filter to a full-scale step input change is
80␣ ms max. If the first notch is at 500␣ Hz, the settling time of the filter to a full-scale input step is 8␣ ms max.
This settling-time can be reduced to 3 × 1/(output data rate) by synchronizing the step input change to a
reset of the digital filter. In other words, if the step input takes place with the FSYNC bit high, the settling-
time time will be 3 × 1/(output data rate) from when FSYNC returns low.
The –3 dB frequency is determined by the programmed first notch frequency according to the relationship:
filter –3 dB frequency = 0.262 × filter first notch frequency.
–10– REV. B
AD7715
Table IV. Output Update Rates
CLK* FS1 FS0 Output Update Rate –3␣ dB Filter Cutoff

0 0 0 20␣ Hz 5.24␣ Hz
0 0 1 25␣ Hz 6.55␣ Hz
0 1 0 100␣ Hz 26.2␣ Hz
0 1 1 200␣ Hz 52.4␣ Hz
1 0 0 50␣ Hz 13.1␣ Hz
1 0 1 60␣ Hz 15.7␣ Hz Default Status
1 1 0 250␣ Hz 65.5␣ Hz
1 1 1 500␣ Hz 131␣ Hz
*Assumes correct clock frequency at MCLK IN pin
B/U Bipolar/Unipolar Operation. A 0 in this bit selects Bipolar Operation. This is the default (Power-On or
RESET) status of this bit. A 1 in this bit selects unipolar operation.
BUF Buffer Control. With this bit low, the on-chip buffer on the analog input is shorted out. With the buffer
shorted out, the current flowing in the AVDD line is reduced to 250␣ µA (all gains at fCLK IN = 1 MHz and gain
of 1 or 2 at fCLK IN = 2.4576 MHz) or 500␣ µA (gains of 32 and 128 @ fCLK IN = 2.4576 MHz) and the output
noise from the part is at its lowest. When this bit is high, the on-chip buffer is in series with the analog input
allowing the input to handle higher source impedances.
FSYNC Filter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic and the
calibration control logic are held in a reset state and the analog modulator is also held in its reset state. When
this bit goes low, the modulator and filter start to process data and a valid word is available in 3 × 1/(output
update rate), i.e., the settling-time of the filter. This FSYNC bit does not affect the digital interface and does
not reset the DRDY output if it is low.
Test Register (RS1, RS0 = 1, 0)
The part contains a Test Register which is used in testing the device. The user is advised not to change the status of any of the
bits in this register from the default (Power-On or RESET) status of all 0s as the part will be placed in one of its test modes and
will not operate correctly. If the part enters one of its test modes, exercising RESET will exit the part from the mode. An alterna-
tive scheme for getting the part out of one of its test modes, is to reset the interface by writing 32 successive 1s to the part and
then load all 0s to the Test Register.
Data Register (RS1, RS0 = 1, 1)

The Data Register on the part is a read-only 16-bit register which contains the most up-to-date conversion result from the
AD7715. If the Communications Register data sets up the part for a write operation to this register, a write operation must actu-
ally take place to return the part to where it is expecting a write operation to the Communications Register (the default state of
the interface). However, the 16 bits of data written to the part will be ignored by the AD7715.
OUTPUT NOISE
AD7715-5
Table V shows the AD7715-5 output rms noise for the selectable notch and –3␣ dB frequencies for the part, as selected by FS1
and FS0 of the Setup Register. The numbers given are for the bipolar input ranges with a VREF of +2.5␣ V. These numbers are
typical and are generated at a differential analog input voltage of 0␣ V with the part used in unbuffered mode (BUF bit of the
Setup Register = 0). Table VI meanwhile shows the output peak-to-peak noise for the selectable notch and –3␣ dB frequencies for
the part. It is important to note that these numbers represent the resolution for which there will be no code flicker. They are not calculated
based on rms noise but on peak-to-peak noise. The numbers given are for the bipolar input ranges with a VREF of +2.5␣ V and for the
BUF bit of the Setup Register = 0. These numbers are typical, are generated at an analog input voltage of 0␣ V and are rounded
to the nearest LSB.
Meanwhile, Table VII and Table VIII show rms noise and peak-to-peak resolution respectively with the AD7715-5 operating
under the same conditions as above except that now the part is operating in buffered mode (BUF Bit of the Setup Register = 1).
REV. B –11–
AD7715
Table V. Output RMS Noise vs. Gain and Output Update Rate for AD7715-5 (Unbuffered Mode)
Filter First Notch & O/P Data Rate –3␣ dB Frequency Typical Output RMS Noise in ␮V
MCLK IN = MCLK IN = MCLK IN = MCLK IN =

2.4576 MHz 1 MHz 2.4576 MHz 1 MHz GAIN = 1 GAIN = 2 GAIN = 32 GAIN = 128
50␣ Hz 20␣ Hz 13.1␣ Hz 5.24␣ Hz 3.8 1.9 0.6 0.52
60␣ Hz 25␣ Hz 15.72␣ Hz 6.55␣ Hz 4.8 2.4 0.6 0.62
250␣ Hz 100␣ Hz 65.5␣ Hz 26.2␣ Hz 103 45 3.0 1.6
500␣ Hz 200␣ Hz 131␣ Hz 52.4␣ Hz 530 250 18 5.5
Table VI. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-5 (Unbuffered Mode)
Filter First Notch & O/P Data Rate –3␣ dB Frequency Typical Peak-to-Peak Resolution in Bits

50␣ Hz 20␣ Hz 13.1␣ Hz 5.24␣ Hz 16 16 16 14
60␣ Hz 25␣ Hz 15.72␣ Hz 6.55␣ Hz 16 16 16 13
250␣ Hz 100␣ Hz 65.5␣ Hz 26.2␣ Hz 13 13 13 12
500␣ Hz 200␣ Hz 131␣ Hz 52.4␣ Hz 10 10 10 10
Table VII. Output RMS Noise vs. Gain and Output Update Rate for AD7715-5 (Buffered Mode)

50␣ Hz 20␣ Hz 13.1␣ Hz 5.24␣ Hz 4.3 2.2 0.9 0.9
60␣ Hz 25␣ Hz 15.72␣ Hz 6.55␣ Hz 5.1 3.1 1.0 1.0
250␣ Hz 100␣ Hz 65.5␣ Hz 26.2␣ Hz 103 50 3.9 2.1
500␣ Hz 200␣ Hz 131␣ Hz 52.4␣ Hz 550 280 18 6
Table VIII. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-5 (Buffered Mode)

50␣ Hz 20␣ Hz 13.1␣ Hz 5.24␣ Hz 16 16 15 13
60␣ Hz 25␣ Hz 15.72␣ Hz 6.55␣ Hz 16 16 15 13
250␣ Hz 100␣ Hz 65.5␣ Hz 26.2␣ Hz 13 13 13 12
500␣ Hz 200␣ Hz 131␣ Hz 52.4␣ Hz 10 10 10 10
AD7715-3
Table IX shows the AD7715-3 output rms noise for the selectable notch and –3␣ dB frequencies for the part, as selected by FS1 and
FS0 of the Setup Register. The numbers given are for the bipolar input ranges with a VREF of +1.25␣ V. These numbers are typical
and are generated at an analog input voltage of 0␣ V with the part used in unbuffered mode (BUF bit of the Setup Register = 0).
Table X meanwhile shows the output peak-to-peak noise for the selectable notch and –3␣ dB frequencies for the part. It is important to
note that these numbers represent the resolution for which there will be no code flicker. They are not calculated based on rms noise but on peak-
to-peak noise. The numbers given are for the bipolar input ranges with a VREF of +1.25␣ V and for the BUF bit of the Setup Register =
0. These numbers are typical, are generated at an analog input voltage of 0␣ V and are rounded to the nearest LSB.
Meanwhile, Table XI and Table XII show rms noise and peak-to-peak resolution respectively with the AD7715-3 operating under
the same conditions as above except that now the part is operating in buffered mode (BUF Bit of the Setup Register = 1).
–12– REV. B
AD7715
Table IX. Output RMS Noise vs. Gain and Output Update Rate for AD7715-3 (Unbuffered Mode)

50␣ Hz 20␣ Hz 13.1␣ Hz 5.24␣ Hz 3.0 1.7 0.7 0.65
60␣ Hz 25␣ Hz 15.72␣ Hz 6.55␣ Hz 3.4 2.1 0.7 0.7
250␣ Hz 100␣ Hz 65.5␣ Hz 26.2␣ Hz 45 20 2.2 1.6
500␣ Hz 200␣ Hz 131␣ Hz 52.4␣ Hz 270 135 9.7 3.3
Table X. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-3 (Unbuffered Mode)

50␣ Hz 20␣ Hz 13.1␣ Hz 5.24␣ Hz 16 16 14 12
60␣ Hz 25␣ Hz 15.72␣ Hz 6.55␣ Hz 16 16 14 12
250␣ Hz 100␣ Hz 65.5␣ Hz 26.2␣ Hz 13 13 13 11
500␣ Hz 200␣ Hz 131␣ Hz 52.4␣ Hz 11 11 10 10
Table XI. Output RMS Noise vs. Gain and Output Update Rate for AD7715-3 (Buffered Mode)
50␣ Hz 20␣ Hz 13.1␣ Hz 5.24␣ Hz 4.5 2.4 0.9 0.9
60␣ Hz 25␣ Hz 15.72␣ Hz 6.55␣ Hz 5.1 2.9 0.9 1.0
250␣ Hz 100␣ Hz 65.5␣ Hz 26.2␣ Hz 50 25 2.6 2
500␣ Hz 200␣ Hz 131␣ Hz 52.4␣ Hz 270 135 9.7 3.3
Table XII. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-3 (Buffered Mode)
50␣ Hz 20␣ Hz 13.1␣ Hz 5.24␣ Hz 16 16 14 12
60␣ Hz 25␣ Hz 15.72␣ Hz 6.55␣ Hz 16 16 14 12
250␣ Hz 100␣ Hz 65.5␣ Hz 26.2␣ Hz 13 13 12 11
500␣ Hz 200␣ Hz 131␣ Hz 52.4␣ Hz 10 11 10 10
REV. B –13–
AD7715
CALIBRATION SEQUENCES
The AD7715 contains a number of calibration options as outlined previously. Table XIII summarizes the calibration types, the op-
erations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to
monitor when DRDY returns low at the end of the sequence. DRDY not only indicates when the sequence is complete but also that
the part has a valid new sample in its data register. This valid new sample is the result of a normal conversion which follows the cali-
bration sequence. The second method of determining when calibration is complete is to monitor the MD1 and MD0 bits of the
Setup Register. When these bits return to 0, 0 following a calibration command, it indicates that the calibration sequence is com-
plete. This method does not give any indication of there being a valid new result in the data register. However, it gives an earlier
indication than DRDY that calibration is complete. The duration to when the Mode Bits (MD1 and MD0) return to 0, 0 represents
the duration of the calibration carried out. The sequence to when DRDY goes low also includes a normal conversion and a pipeline
delay, tP, to correctly scale the results of this first conversion. tP will never exceed 2000 × tCLK IN. The time for both methods is given
in the table.
Table XIII. Calibration Sequences
Calibration Type MD1, MD0 Calibration Sequence Duration to Mode Bits Duration to DRDY
Self Calibration 0, 1 Internal ZS Cal @ Selected Gain + 6 × 1/Output Rate 9 × 1/Output Rate + tP
Internal FS Cal @ Selected Gain
ZS System Calibration 1, 0 ZS Cal on AIN @ Selected Gain 3 × 1/Output Rate 4 × 1/Output Rate + tP
FS System Calibration 1, 1 FS Cal on AIN @ Selected Gain 3 × 1/Output Rate 4 × 1/Output Rate + tP
CIRCUIT DESCRIPTION information. The programmable gain function on the analog

The AD7715 is a sigma-delta A/D converter with on-chip digital input is also incorporated in this sigma-delta modulator with the
filtering, intended for the measurement of wide dynamic range, input sampling frequency being modified to give the higher
low frequency signals such as those in industrial control or pro- gains. A sinc3 digital low-pass filter processes the output of the
cess control applications. It contains a sigma-delta (or charge- sigma-delta modulator and updates the output register at a rate
balancing) ADC, a calibration microcontroller with on-chip determined by the first notch frequency of this filter. The out-
static RAM, a clock oscillator, a digital filter and a bidirectional put data can be read from the serial port randomly or periodi-
serial communications port. The part consumes only 450␣ µA of cally at any rate up to the output register update rate. The first
power supply current, making it ideal for battery-powered or notch of this digital filter (and hence its –3␣ dB frequency) can be
loop-powered instruments. The part comes in two versions, the programmed via the Setup Register bits FS0 and FS1. With a
AD7715-5 which is specified for operation from a nominal master clock frequency of 2.4576␣ MHz, the programmable
+5␣ V analog supply (AVDD) and the AD7715-3 which is speci- range for this first notch frequency is from 50␣ Hz to 500␣ Hz
fied for operation from a nominal +3.3␣ V analog supply. Both giving a programmable range for the –3␣ dB frequency of
versions can be operated with a digital supply (DVDD) voltage of 13.1␣ Hz to 131␣ Hz. With a master clock frequency of 1␣ MHz,
+3.3␣ V or +5␣ V. the programmable range for this first notch frequency is from
The part contains a programmable-gain fully differential analog 20␣ Hz to 200␣ Hz giving a programmable range for the –3␣ dB
input channel. The selectable gains on this input are 1, 2, 32 frequency of 5.24␣ Hz to 52.4␣ Hz.
and 128 allowing the part to accept unipolar signals of between The basic connection diagram for the AD7715-5 is shown in
0 mV to +20␣ mV and 0 V to +2.5␣ V or bipolar signals in the Figure 2. This shows both the AVDD and DVDD pins of the
range from ± 20␣ mV to ± 2.5␣ V when the reference input voltage AD7715 being driven from the analog +5␣ V supply. Some
equals +2.5␣ V. With a reference voltage of +1.25␣ V, the input applications will have AVDD and DVDD driven from separate
ranges are from 0 mV to +10␣ mV to 0 V to +1.25␣ V in unipolar supplies. An AD780, precision +2.5 V reference, provides the
mode and from ± 10␣ mV to ± 1.25 V in bipolar mode. Note that reference source for the part. On the digital side, the part is
the bipolar ranges are with respect to AIN(–) and not with re- configured for three-wire operation with CS tied to DGND. A
spect to AGND. quartz crystal or ceramic resonator provides the master clock
The input signal to the analog input is continuously sampled at source for the part. In most cases, it will be necessary to connect
a rate determined by the frequency of the master clock, capacitors on the crystal or resonator to ensure that it does
MCLK␣ IN, and the selected gain. A charge-balancing A/D not oscillate at overtones of its fundamental operating fre-
converter (sigma-delta modulator) converts the sampled signal quency. The values of capacitors will vary depending on the
into a digital pulse train whose duty cycle contains the digital manufacturer’s specifications.
–14– REV. B
AD7715
ANALOG CSAMP must be charged through RSW and through any external
+5V SUPPLY 10mF 0.1mF 0.1mF source impedances every input sample cycle. Therefore, in
AVDD DVDD
unbuffered mode, source impedances mean a longer charge time
AD7715 for CSAMP, and this may result in gain errors on the part. Table
DRDY DATA READY XIV shows the allowable external resistance/capacitance values,
AIN(+)
DIFFERENTIAL CS for unbuffered mode, such that no gain error to the 16-bit level
ANALOG INPUT AIN(–)
DOUT
is introduced on the part. Note that these capacitances are total
RECEIVE (READ)
ANALOG capacitances on the analog input, external capacitance plus
AGND
GROUND DIN SERIAL DATA 10 pF capacitance from the pins and lead frame of the device.
ANALOG
+5V SUPPLY DIGITAL SCLK SERIAL CLOCK
DGND Table XIV. External R, C Combination for No 16-Bit Gain
GROUND
VIN RESET +5V
Error (Unbuffered Mode Only)
VOUT REF IN(+)
AD780 10mF 0.1mF

MCLK IN Gain External Capacitance (pF)
CRYSTAL OR
GND REF IN(–) CERAMIC
MCLK OUT RESONATOR 10 50 100 500 1000 5000
1 152 kΩ 53.9 kΩ 31.4 kΩ 8.4 kΩ 4.76 kΩ 1.36 kΩ
Figure 2. AD7715-5 Basic Connection Diagram 2 75.1 kΩ 26.6 kΩ 15.4 kΩ 4.14 kΩ 2.36 kΩ 670 Ω
32 16.7 kΩ 5.95 kΩ 3.46 kΩ 924 Ω 526 Ω 150 Ω
ANALOG INPUT
128 16.7 kΩ 5.95 kΩ 3.46 kΩ 924 Ω 526 Ω 150 Ω
Analog Input Ranges
The AD7715 contains a differential analog input pair AIN(+) In buffered mode, the analog inputs look into the high imped-
and AIN(–). This input pair provides a programmable-gain, ance inputs stage of the on-chip buffer amplifier. CSAMP is
differential input channel which can handle either unipolar or charged via this buffer amplifier such that source impedances do
bipolar input signals. It should be noted that the bipolar input not affect the charging of CSAMP. This buffer amplifier has an
signals are referenced to the respective AIN(–) input of the offset leakage current of 1 nA. In this buffered mode, large
input pair. source impedances result in a small dc offset voltage developed
In unbuffered mode, the common-mode range of the input is across the source impedance but not in a gain error.
from AGND to AVDD provided that the absolute value of the Input Sample Rate
analog input voltage lies between AGND␣ –␣ 30␣ mV and The modulator sample frequency for the AD7715 remains at
AVDD␣ +␣ 30␣ mV. This means that in unbuffered mode the part fCLK␣ IN/128 (19.2␣ kHz @ fCLK IN = 2.4576␣ MHz) regardless of
can handle both unipolar and bipolar input ranges for all gains. the selected gain. However, gains greater than 1 are achieved by
In buffered mode, the analog inputs can handle much larger a combination of multiple input samples per modulator cycle
source impedances but the absolute input voltage range is re- and a scaling of the ratio of reference capacitor to input capaci-
stricted to between AGND␣ + 50␣ mV to AVDD – 1.5␣ V which tor. As a result of the multiple sampling, the input sample rate
also places restrictions on the common-mode range. This means of the device varies with the selected gain (see Table XV). In
that in buffered mode there are some restrictions on the allow- buffered mode, the input is buffered before the input sampling
able gains for bipolar input ranges. Care must be taken in set-
ting up the common-mode voltage and input voltage range so Table XV. Input Sampling Frequency vs. Gain
that the above limits are not exceeded, otherwise there will be a
degradation in linearity performance. Gain Input Sampling Freq (fS)
In unbuffered mode, the analog inputs look directly into the 1 fCLK IN/64 (38.4␣ kHz @ fCLK IN = 2.4576␣ MHz)
input sampling capacitor, CSAMP. The dc input leakage current 2 2 × fCLK IN/64 (76.8␣ kHz @ fCLK IN = 2.4576␣ MHz)
in this unbuffered mode is 1␣ nA maximum. As a result, the 32 8 × fCLK IN/64 (307.2␣ kHz @ fCLK IN = 2.4576␣ MHz)
analog inputs see a dynamic load that is switched at the input 128 8 × fCLK IN/64 (307.2␣ kHz @ fCLK IN = 2.4576␣ MHz)
sample rate (see Figure 3). This sample rate depends on master
clock frequency and selected gain. CSAMP is charged to AIN(+) capacitor. In unbuffered mode, where the analog input looks
and discharged to AIN(–) every input sample cycle. The effec- directly into the sampling capacitor, the effective input imped-
tive on-resistance of the switch, RSW, is typically 7␣ kΩ. ance is 1/CSAMP × fS where CSAMP is the input sampling capaci-
tance and fS is the input sample rate.
Bipolar/Unipolar Inputs
AIN(+) The analog input on the AD7715 can accept either unipolar or
RSW (7kV TYP) HIGH
IMPEDANCE bipolar input voltage ranges. Bipolar input ranges do not imply
CSAMP 1GV
AIN(–)
(10pF )
that the part can handle negative voltages on its analog input
VBIAS
since the analog input cannot go more negative than –30␣ mV to
SWITCHING FREQUENCY ensure correct operation of the part. The input channel is fully
DEPENDS ON fCLKIN differential. As a result, the voltage to which the unipolar and
AND SELECTED GAIN
bipolar signals on the AIN(+) input are referenced is the voltage
on the respective AIN(–) input. For example, if AIN(–) is
Figure 3. Unbuffered Analog Input Structure +2.5␣ V and the AD7715 is configured for unipolar operation
REV. B –15–
AD7715
with a gain of 2 and a VREF of +2.5␣ V, the input voltage range DIGITAL FILTERING
on the AIN(+) input is +2.5␣ V to +3.75␣ V. If AIN(–) is +2.5␣ V The AD7715 contains an on-chip low-pass digital filter that
and the AD7715 is configured for bipolar mode with a gain of 2 processes the output of the part’s sigma-delta modulator. There-
and a VREF of +2.5␣ V, the analog input range on the AIN(+) fore, the part not only provides the analog-to-digital conversion
input is +1.25␣ V to +3.75 V (i.e., 2.5␣ V ± 1.25␣ V). If AIN(–) is function but it also provides a level of filtering. There are a
at AGND, the part cannot be configured for bipolar ranges in number of system differences when the filtering function is
excess of ± 30␣ mV. provided in the digital domain rather than the analog domain
Bipolar or unipolar options are chosen by programming the B/U and the user should be aware of these.
bit of the Setup Register. This programs the channel for either First, since digital filtering occurs after the A-to-D conversion
unipolar or bipolar operation. Programming the channel for process, it can remove noise injected during the conversion
either unipolar or bipolar operation does not change any of the process. Analog filtering cannot do this. Also, the digital filter
input signal conditioning; it simply changes the data output can be made programmable far more readily than an analog
coding and the points on the transfer function where calibra- filter. Depending on the digital filter design, this gives the user
tions occur. the capability of programming cutoff frequency and output
update rate.
REFERENCE INPUT
The AD7715’s reference inputs, REF␣ IN(+) and REF␣ IN(–), On the other hand, analog filtering can remove noise superim-
provide a differential reference input capability. The common- posed on the analog signal before it reaches the ADC. Digital
mode range for these differential inputs is from AGND to filtering cannot do this and noise peaks riding on signals near
AVDD. The nominal reference voltage, VREF (REF␣ IN(+)␣ – full scale have the potential to saturate the analog modulator
REF␣ IN(–)), for specified operation is +2.5␣ V for the AD7715-5 and digital filter, even though the average value of the signal is
and +1.25␣ V for the AD7715-3. The part is functional with within limits. To alleviate this problem, the AD7715 has over-
VREF voltages down to 1 V but with degraded performance as range headroom built into the sigma-delta modulator and digital
the output noise will, in terms of LSB size, be larger. REF␣ IN(+) filter which allows overrange excursions of 5% above the analog
must always be greater than REF␣ IN(–) for correct operation of input range. If noise signals are larger than this, consideration
the AD7715. should be given to analog input filtering, or to reducing the
input channel voltage so that its full scale is half that of the
Both reference inputs provide a high impedance, dynamic load analog input channel full scale. This will provide an overrange
similar to the analog inputs in unbuffered mode. The maximum capability greater than 100% at the expense of reducing the
dc input leakage current is ± 1 nA over temperature and source dynamic range by 1 bit (50%).
resistance may result in gain errors on the part. In this case, the
sampling switch resistance is 5␣ kΩ typ and the reference capaci- In addition, the digital filter does not provide any rejection at
tor (CREF) varies with gain. The sample rate on the reference integer multiples of the digital filter’s sample frequency. How-
inputs is fCLK IN/64 and does not vary with gain. For gains of 1 ever, the input sampling on the part provides attenuation at
and 2, CREF is 8␣ pF; for a gain of 32, it is 4.25␣ pF, and for a gain multiples of the digital filter’s sampling frequency so that the
of 128, it is 3.3125␣ pF. unattenu-ated bands actually occur around multiples of the
sampling frequency fS (as defined in Table XV). Thus the unat-
The output noise performance outlined in Tables V through XII
tenuated bands occur at n × fS (where n = 1, 2, 3. . . ). At these
is for an analog input of 0␣ V which effectively removes the effect
frequencies, there are frequency bands, ± f3 dB wide (f3 dB is the
of noise on the reference. To obtain the same noise performance
cutoff frequency of the digital filter) at either side where noise
as shown in the noise tables over the full input range requires a
passes unattenuated to the output.
low noise reference source for the AD7715. If the reference
noise in the bandwidth of interest is excessive, it will degrade Filter Characteristics
the performance of the AD7715. In applications where the The AD7715’s digital filter is a low-pass filter with a (sinx/x)3
excitation voltage for the bridge transducer on the analog input response (also called sinc3). The transfer function for this filter
also derives the reference voltage for the part, the effect of the is described in the z-domain by:
noise in the excitation voltage will be removed as the application 3
 1 1– z 
−N
is ratiometric. Recommended reference voltage sources for the H (z ) =  × –1 

AD7715-5 include the AD780, REF43 and REF192, while the N 1– z 
recommended reference sources for the AD7715-3 include the
AD589 and AD1580. It is generally recommended to decouple and in the frequency domain by:
the output of these references in order to further reduce the 3
 f
noise level. Sin  N × π × 
1  fs 
|H( f )|= ×
N  f
Sin  π × 
 fs 
where N is the ratio of the modulator rate to the output rate and
fMOD is the modulator rate.
–16– REV. B
AD7715
Figure 4 shows the filter frequency response for a cutoff fre- 26.2␣ Hz. Post-filtering can be applied to this to reduce the
quency of 15.72␣ Hz which corresponds to a first filter notch bandwidth and output noise, to the 7.86␣ Hz bandwidth level,
frequency of 60␣ Hz. The plot is shown from dc to 390␣ Hz. This while maintaining an output rate of 100␣ Hz.
response is repeated at either side of the digital filter’s sample Post-filtering can also be used to reduce the output noise from
frequency and at either side of multiples of the filter’s sample the device for bandwidths below 13.1␣ Hz. At a gain of 128 and
frequency. a bandwidth of 13.1␣ Hz, the output rms noise is 520␣ nV. This
is essentially device noise or white noise and since the input is
0
chopped, the noise has a primarily flat frequency response. By
–20
reducing the bandwidth below 13.1␣ Hz, the noise in the result-
–40
ant passband can be reduced. A reduction in bandwidth by a
–60
factor of 2 results in a reduction of approximately 1.25 in the
–80 output rms noise. This additional filtering will result in a longer
GAIN – dB
–100 settling time.

–120
–140 ANALOG FILTERING
–160 The digital filter does not provide any rejection at integer mul-
–180 tiples of the modulator sample frequency, as outlined earlier.
–200 However, due to the AD7715’s high oversampling ratio, these
–220 bands occupy only a small fraction of the spectrum and most
–240 broadband noise is filtered. This means that the analog filtering
0 60 120 180 240 300 360
FREQUENCY – Hz requirements in front of the AD7715 are considerably reduced
versus a conventional converter with no on-chip filtering. In
Figure 4. Frequency Response of AD7715 Filter addition, because the part’s common-mode rejection perfor-
The response of the filter is similar to that of an averaging filter mance of 95␣ dB extends out to several kHz, common-mode
but with a sharper roll-off. The output rate for the digital filter noise in this frequency range will be substantially reduced.
corresponds with the positioning of the first notch of the filter’s Depending on the application, however, it may be necessary to
frequency response. Thus, for the plot of Figure 4 where the provide attenuation prior to the AD7715 in order to eliminate
output rate is 60␣ Hz, the first notch of the filter is at 60␣ Hz. The unwanted frequencies from these bands which the digital filter
notches of this (sinx/x)3 filter are repeated at multiples of the will pass. It may also be necessary in some applications to pro-
first notch. The filter provides attenuation of better than 100␣ dB vide analog filtering in front of the AD7715 to ensure that dif-
at these notches. ferential noise signals outside the band of interest do not
The cutoff frequency of the digital filter is determined by the saturate the analog modulator.
value loaded to bits FS0 to FS1 in the Setup Register. Pro- If passive components are placed in front of the AD7715, in
gramming a different cutoff frequency via FS0 and FS1 does not unbuffered mode, care must be taken to ensure that the source
alter the profile of the filter response; it changes the frequency of impedance is low enough so as not to introduce gain errors in
the notches. The output update of the part and the frequency of the system. This significantly limits the amount of passive anti-
the first notch correspond. aliasing filtering which can be provided in front of the AD7715
Since the AD7715 contains this on-chip, low-pass filtering, when it is used in unbuffered mode. However, when the part is
there is a settling time associated with step function inputs and used in buffered mode, large source impedances will simply
data on the output will be invalid after a step change until the result in a small dc offset error (a 10␣ kΩ source resistance will
settling time has elapsed. The settling time depends upon the cause an offset error of less than 10␣ µV). Therefore, if the sys-
output rate chosen for the filter. The settling time of the filter tem requires any significant source impedances to provide pas-
to a full-scale step input can be up 4 times the output data sive analog filtering in front of the AD7715, it is recommended
period. For a synchronized step input (using the FSYNC func- that the part be operated in buffered mode.
tion), the settling time is 3 times the output data period.
Post-Filtering CALIBRATION
The on-chip modulator provides samples at a 19.2␣ kHz output The AD7715 provides a number of calibration options that can
rate with fCLK IN at 2.4576␣ MHz. The on-chip digital filter be programmed via the MD1 and MD0 bits of the Setup Regis-
decimates these samples to provide data at an output rate which ter. The different calibration options are outlined in the Setup
corresponds to the programmed output rate of the filter. Since Register and Calibration Sequences sections. A calibration cycle
the output data rate is higher than the Nyquist criterion, the may be initiated at any time by writing to these bits of the Setup
output rate for a given bandwidth will satisfy most application Register. Calibration on the AD7715 removes offset and gain
requirements. However, there may be some applications which errors from the device. A calibration routine should be initiated
require a higher data rate for a given bandwidth and noise per- on the device whenever there is a change in the ambient operat-
formance. Applications that need this higher data rate will ing temperature or supply voltage. It should also be initiated if
require some post-filtering following the digital filter of the there is a change in the selected gain, filter notch or bipolar/
AD7715. unipolar input range.
For example, if the required bandwidth is 7.86␣ Hz but the re- The AD7715 offers self-calibration and system-calibration facili-
quired update rate is 100␣ Hz, the data can be taken from the ties. For full calibration to occur on the selected channel, the
AD7715 at the 100␣ Hz rate giving a –3 dB bandwidth of on-chip microcontroller must record the modulator output for
two different input conditions. These are “zero-scale” and
REV. B –17–
AD7715
“full-scale” points. These points are derived by performing a step is complete. Once the system zero scale voltage has been set
conversion on the different input voltages provided to the input up, a ZS System Calibration is then initiated by writing the ap-
of the modulator during calibration. As a result, the accuracy of propriate values (1, 0) to the MD1 and MD0 bits of the Setup
the calibration can only be as good as the noise level that it Register. The zero-scale system calibration is performed at the
provides in normal mode. The result of the “zero-scale” calibra- selected gain. The duration of the calibration is 3 × 1/Output
tion conversion is stored in the Zero-Scale Calibration Register Rate. At this time the MD1 and MD0 bits in the Setup Register
while the result of the “full-scale” calibration conversion is return to 0, 0. This gives the earliest indication that the calibration
stored in the Full-Scale Calibration Register. With these read- sequence is complete. The DRDY line goes high when calibration
ings, the on-chip microcontroller can calculate the offset and the is initiated and does not return low until there is a valid new
gain slope for the input to output transfer function of the con- word in the data register. The duration time from the calibra-
verter. Internally, the part works with a resolution of 33 bits to tion command being issued to DRDY going low is 4 × 1/Output
determine its conversion result of 16 bits. Rate as the part performs a normal conversion on the AIN volt-
Self-Calibration age before DRDY goes low. If DRDY is low before (or goes low
A self-calibration is initiated on the AD7715 by writing the during) the calibration command write to the Setup Register, it
appropriate values (0, 1) to the MD1 and MD0 bits of the may take up to one modulator cycle (MCLK␣ IN/128) before
Setup Register. In the self-calibration mode with a unipolar DRDY goes high to indicate that calibration is in progress.
input range, the zero-scale point used in determining the cali- Therefore, DRDY should be ignored for up to one modulator
bration coefficients is with the inputs of the differential pair cycle after the last bit is written to the Setup Register in the
internally shorted on the part (i.e., AIN(+) = AIN(–) = Internal calibration command.
Bias Voltage). The PGA is set for the selected gain (as per G1 After the zero-scale point is calibrated, the full-scale point is
and G0 bits in the Communications Register) for this zero-scale applied to AIN and the second step of the calibration process is
calibration conversion. The full-scale calibration conversion is initiated by again writing the appropriate values (1, 1) to MD1
performed at the selected gain on an internally generated voltage and MD0. Again the full-scale voltage must be set up before
of VREF/Selected Gain. the calibration is initiated and it must remain stable throughout
The duration time for the calibration is 6 × 1/Output Rate. This the calibration step. The full-scale system calibration is per-
is made up of 3 × 1/Output Rate for the zero-scale calibration formed at the selected gain. The duration of the calibration is
and 3 × 1/Output Rate for the full-scale calibration. At this time 3 × 1/Output Rate. At this time the MD1 and MD0 bits in the
the MD1 and MD0 bits in the Setup Register return to 0, 0. Setup Register return to 0, 0. This gives the earliest indication
This gives the earliest indication that the calibration sequence is that the calibration sequence is complete. The DRDY line goes
complete. The DRDY line goes high when calibration is initi- high when calibration is initiated and does not return low until
ated and does not return low until there is a valid new word in there is a valid new word in the data register. The duration time
the data register. The duration time from the calibration com- from the calibration command being issued to DRDY going low
mand being issued to DRDY going low is 9 × 1/Output Rate. is 4 × 1/Output Rate as the part performs a normal conversion
This is made up of 3 × 1/Output Rate for the zero-scale calibra- on the AIN voltage before DRDY goes low. If DRDY is low
tion, 3 × 1/Output Rate for the full-scale calibration, 3 × 1/ before (or goes low during) the calibration command, write to
Output Rate for a conversion on the analog input and some the Setup Register, it may take up to one modulator cycle
overhead to set up the coefficients correctly. If DRDY is low (MCLK␣ IN/128) before DRDY goes high to indicate that cali-
before (or goes low during) the calibration command write to bration is in progress. Therefore, DRDY should be ignored for
the Setup Register, it may take up to one modulator cycle up to one modulator cycle after the last bit is written to the
(MCLK␣ IN/128) before DRDY goes high to indicate that cali- Setup Register in the calibration command.
bration is in progress. Therefore, DRDY should be ignored for In the unipolar mode, the system calibration is performed be-
up to one modulator cycle after the last bit is written to the tween the two endpoints of the transfer function; in the bipolar
Setup Register in the calibration command. mode, it is performed between midscale (zero differential volt-
For bipolar input ranges in the self-calibrating mode, the se- age) and positive full scale.
quence is very similar to that just outlined. In this case, the two The fact that the system calibration is a two-step calibration
points are exactly the same as above, but since the part is config- offers another feature. After the sequence of a full system cali-
ured for bipolar operation, the shorted inputs point is actually bration has been completed, additional offset or gain calibra-
midscale of the transfer function. tions can be performed by themselves to adjust the system zero
System Calibration reference point or the system gain. Calibrating one of the pa-
System calibration allows the AD7715 to compensate for system rameters, either system offset or system gain, will not affect the
gain and offset errors as well as its own internal errors. System other parameter.
calibration performs the same slope factor calculations as self- System calibration can also be used to remove any errors from
calibration but uses voltage values presented by the system to source impedances on the analog input when the part is used in
the AIN inputs for the zero- and full-scale points. Full System unbuffered mode. A simple R, C antialiasing filter on the front
calibration requires a two step process, a ZS System Calibration end may introduce a gain error on the analog input voltage but
followed by a FS System Calibration. the system calibration can be used to remove this error.
For a full system calibration, the zero-scale point must be pre- Span and Offset Limits
sented to the converter first. It must be applied to the converter Whenever a system calibration mode is used, there are limits on
before the calibration step is initiated and remain stable until the the amount of offset and span which can be accommodated.
The overriding requirement in determining the amount of offset
–18– REV. B
AD7715
and gain that can be accommodated by the part is the require- USING THE AD7715
ment that the positive full-scale calibration limit is ≤ 1.05 × Clocking and Oscillator Circuit
VREF/GAIN. This allows the input range to go 5% above the The AD7715 requires a master clock input, which may be an
nominal range. The in-built headroom in the AD7715’s analog external CMOS compatible clock signal applied to the MCLK␣ IN
modulator ensures that the part will still operate correctly with a pin with the MCLK␣ OUT pin left unconnected. Alternatively, a
positive full-scale voltage which is 5% beyond the nominal. crystal or ceramic resonator of the correct frequency can be
The range of input span in both the unipolar and bipolar modes connected between MCLK␣ IN and MCLK␣ OUT in which case
has a minimum value of 0.8 × VREF/GAIN and a maximum the clock circuit will function as an oscillator, providing the
value of 2.1 × VREF/GAIN. However, the span (which is the clock source for the part. The input sampling frequency, the
difference between the bottom of the AD7715’s input range and modulator sampling frequency, the –3␣ dB frequency, output
the top of its input range) must take into account the limitation update rate and calibration time are all directly related to the
on the positive full-scale voltage. The amount of offset that can master clock frequency, fCLK␣ IN. Reducing the master clock
be accommodated depends on whether the unipolar or bipolar frequency by a factor of 2 will halve the above frequencies and
mode is being used. Once again, the offset must take into ac- update rate and double the calibration time. The current drawn
count the limitation on the positive full-scale voltage. In unipo- from the DVDD power supply is also directly related to fCLK␣ IN.
lar mode, there is considerable flexibility in handling negative Reducing fCLK␣ IN by a factor of 2 will halve the DVDD current
(with respect to AIN(–)) offsets. In both unipolar and bipolar but will not affect the current drawn from the AVDD power
modes, the range of positive offsets which can be handled by the supply.
part depends on the selected span. Therefore, in determining Using the part with a crystal or ceramic resonator between the
the limits for system zero-scale and full-scale calibrations, the MCLK IN and MCLK OUT pins generally causes more cur-
user has to ensure that the offset range plus the span range does rent to be drawn from DVDD than when the part is clocked from
exceed 1.05 × VREF/GAIN. This is best illustrated by looking at a driven clock signal at the MCLK IN pin. This is because the
a few examples. on-chip oscillator circuit is active in the case of the crystal or
If the part is used in unipolar mode with a required span of ceramic resonator. Therefore, the lowest possible current on
0.8 × VREF/GAIN, then the offset range which the system cali- the AD7715 is achieved with an externally applied clock at the
bration can handle is from –1.05 × VREF/GAIN to +0.25 × VREF/ MCLK IN pin with MCLK OUT unconnected and unloaded.
GAIN. If the part is used in unipolar mode with a required span of The amount of additional current taken by the oscillator de-
VREF/GAIN, then the offset range which the system calibration can pends on a number of factors—first, the larger the value of
handle is from –1.05 × VREF/GAIN to +0.05 × VREF/GAIN. Simi- capacitor placed on the MCLK␣ IN and MCLK␣ OUT pins, then
larly, if the part is used in unipolar mode and required to re- the larger the DVDD current consumption on the AD7715. Care
move an offset of 0.2 × VREF/GAIN, then the span range which should be taken not to exceed the capacitor values recommended
the system calibration can handle is 0.85 × VREF/GAIN. by the crystal and ceramic resonator manufacturers to avoid
If the part is used in bipolar mode with a required span of consuming unnecessary DVDD current. Typical values recom-
± 0.4 × VREF/GAIN, then the offset range which the system cali- mended by crystal or ceramic resonator manufacturers are in the
bration can handle is from –0.65 × VREF/GAIN to +0.65 × VREF/ range of 30␣ pF to 50␣ pF, and if the capacitor values on MCLK
GAIN. If the part is used in bipolar mode with a required span IN and MCLK OUT are kept in this range, they will not result
of ± VREF/GAIN, then the offset range which the system calibra- in any excessive DVDD current. Another factor that influences
tion can handle is from –0.05 × VREF/GAIN to +0.05 × VREF/ the DVDD current is the effective series resistance (ESR) of the
GAIN. Similarly, if the part is used in bipolar mode and required crystal which appears between the MCLK IN and MCLK OUT
to remove an offset of ± 0.2 × VREF/GAIN, then the span range pins of the AD7715. As a general rule, the lower the ESR value
which the system calibration can handle is ± 0.85 × VREF/GAIN. then the lower the current taken by the oscillator circuit.
Power-Up and Calibration When operating with a clock frequency of 2.4576␣ MHz, there is
On power-up, the AD7715 performs an internal reset that sets 50␣ µA difference in the DVDD current between an externally
the contents of the internal registers to a known state. There applied clock and a crystal resonator when operating with a
are default values loaded to all registers after a power-on or DVDD of +3␣ V. With DVDD = +5␣ V and fCLK IN = 2.4576␣ MHz,
reset. The default values contain nominal calibration coefficients the typical DVDD current increases by 200␣ µA for a crystal/
for the calibration registers. However, to ensure correct calibra- resonator supplied clock versus an externally applied clock. The
tion for the device a calibration routine should be performed ESR values for crystals and resonators at this frequency tend to
after power-up. be low and as a result there tends to be little difference between
different crystal and resonator types.
The power dissipation and temperature drift of the AD7715 are
low, and no warm-up time is required before the initial calibra- When operating with a clock frequency of 1␣ MHz, the ESR value
tion is performed. However, if an external reference is being for different crystal types varies significantly. As a result, the DVDD
used, this reference must have stabilized before calibration is current drain varies across crystal types. When using a crystal
initiated. Similarly, if the clock source for the part is generated with an ESR of 700␣ Ω or when using a ceramic resonator, the
from a crystal or resonator across the MCLK pins, the start-up increase in the typical DVDD current over an externally-applied
time for the oscillator circuit should elapse before a calibration clock is 50␣ µA with DVDD = +3␣ V and 175␣ µA with DVDD =
is initiated on the part (see below). +5␣ V. When using a crystal with an ESR of 3␣ kΩ, the increase in
the typical DVDD current over an externally applied clock is
100␣ µA with DVDD = +3␣ V and 400␣ µA with DVDD = +5␣ V.
REV. B –19–
AD7715
The on-chip oscillator circuit also has a start-up time associated conditions after a RESET and it is generally necessary to set up
with it before it is oscillating at its correct frequency and correct all registers and carry out a calibration after a RESET command.
voltage levels. The typical start-up time for the circuit is 10␣ ms The AD7715’s on-chip oscillator circuit continues to function
with a DVDD of +5␣ V and 15␣ ms with a DVDD of +3␣ V. At 3␣ V even when the RESET input is low. The master clock signal
supplies, depending on the loading capacitances on the MCLK continues to be available on the MCLK OUT pin. Therefore, in
pins, a 1␣ MΩ feedback resistor may be required across the crys- applications where the system clock is provided by the AD7715’s
tal or resonator in order to keep the start up times around the clock, the AD7715 produces an uninterrupted master clock
15␣ ms duration. during RESET commands.
The AD7715’s master clock appears on the MCLK OUT pin of Standby Mode
the device. The maximum recommended load on this pin is one The STBY bit in the Communications Register of the AD7715
CMOS load. When using a crystal or ceramic resonator to gen- allows the user to place the part in a power-down mode when it
erate the AD7715’s clock, it may be desirable to then use this is not required to provide conversion results. The AD7715
clock as the clock source for the system. In this case, it is recom- retains the contents of all its on-chip registers (including the
mended that the MCLK OUT signal is buffered with a CMOS data register) while in standby mode. When released from
buffer before being applied to the rest of the circuit. standby mode, the part starts to process data and a new word is
System Synchronization available in the data register in 3 × 1/Output Rate from when a 0
The FSYNC bit of the Setup Register allows the user to reset is written to the STBY bit.
the modulator and digital filter without affecting any of the The STBY bit does not affect the digital interface, and it does
setup conditions on the part. This allows the user to start gath- not affect the status of the DRDY line. If DRDY is high when
ering samples of the analog input from a known point in time, the STBY bit is brought low, it will remain high until there is a
i.e., when the FSYNC is changed from 1 to 0. valid new word in the data register. If DRDY is low when the
With a 1 in the FSYNC bit of the Setup Register, the digital STBY bit is brought low, it will remain low until the data regis-
filter and analog modulator are held in a known reset state and ter is updated at which time the DRDY line will return high for
the part is not processing any input samples. When a 0 is then 500 × tCLK IN before returning low again. If DRDY is low when
written to the FSYNC bit, the modulator and filter are taken the part enters its standby mode (indicating a valid unread word
out of this reset state and on the next master clock edge the part in the data register), the data register can be read while the part
starts to gather samples again. is in standby. At the end of this read operation, the DRDY will
The FSYNC input can also be used as a software start convert be reset high as normal.
command allowing the AD7715 to be operated in a conven- Placing the part in standby mode reduces the total current to
tional converter fashion. In this mode, writing to the FSYNC bit 5␣ µA typical when the part is operated from an external master
starts conversion and the falling edge of DRDY indicates when clock provided this master clock is stopped. If the external clock
conversion is complete. The disadvantage of this scheme is that continues to run in standby mode, the standby current increases
the settling time of the filter has to be taken into account for to 150␣ µA typical with 5 V supplies and 75 µA typical with 3.3 V
every data register update. This means that the rate at which the supplies. If a crystal or ceramic resonator is used as the clock
data register is updated is three times slower in this mode. source, then the total current in standby mode is 400␣ µA typical
Since the FSYNC bit resets the digital filter, the full settling with 5 V supplies and 90 µA with 3.3 V supplies. This is because
time of 3 × 1/Output Rate must elapse before there is a new the on-chip oscillator circuit continues to run when the part is in
word loaded to the output register on the part. If the DRDY its standby mode. This is important in applications where the
signal is low when FSYNC goes to a 0, the DRDY signal will system clock is provided by the AD7715’s clock, so that the
not be reset high by the FSYNC command. This is because the AD7715 produces an uninterrupted master clock even when it is
AD7715 recognizes that there is a word in the data register that in its standby mode.
has not been read. The DRDY line will stay low until an update Accuracy
of the data register takes place at which time it will go high for Sigma-delta ADCs, like VFCs and other integrating ADCs, do
500 × tCLK IN before returning low again. A read from the data not contain any source of nonmonotonicity and inherently offer
register resets the DRDY signal high, and it will not return low no missing codes performance. The AD7715 achieves excellent
until the settling time of the filter has elapsed (from the FSYNC linearity by the use of high quality, on-chip capacitors, which
command) and there is a valid new word in the data register. If have a very low capacitance/voltage coefficient. The device also
the DRDY line is high when the FSYNC command is issued, achieves low input drift through the use of chopper-stabilized
the DRDY line will not return low until the settling time of the techniques in its input stage. To ensure excellent performance
filter has elapsed. over time and temperature, the AD7715 uses digital calibration
Reset Input techniques which minimize offset and gain error.
The RESET input on the AD7715 resets all the logic, the digital Drift Considerations
filter and the analog modulator while all on-chip registers are The AD7715 uses chopper stabilization techniques to minimize
reset to their default state. DRDY is driven high and the AD7715 input offset drift. Charge injection in the analog switches and
ignores all communications to any of its registers while the dc leakage currents at the sampling node are the primary
RESET input is low. When the RESET input returns high, the sources of offset voltage drift in the converter. The dc input
AD7715 starts to process data, and DRDY will return low in leakage current is essentially independent of the selected gain.
3 × 1/Output Rate indicating a valid new word in the data Gain drift within the converter depends primarily upon the
register. However, the AD7715 operates with its default setup temperature tracking of the internal capacitors. It is not af-
fected by leakage currents.
–20– REV. B
AD7715
Measurement errors due to offset drift or gain drift can be elimi- As a result, the AD7715 is more immune to noise interference
nated at any time by recalibrating the converter. Using the sys- that a conventional high resolution converter. However, because
tem calibration mode can also minimize offset and gain errors in the resolution of the AD7715 is so high and the noise levels
the signal conditioning circuitry. Integral and differential linear- from the AD7715 so low, care must be taken with regard to
ity errors are not significantly affected by temperature changes. grounding and layout.
The printed circuit board which houses the AD7715 should be
POWER SUPPLIES designed such that the analog and digital sections are separated
There is no specific power sequence required for the AD7715; and confined to certain areas of the board. This facilitates the
either the AVDD or the DVDD supply can come up first. While use of ground planes which can be separated easily. A minimum
the latch-up performance of the AD7715 is good, it is important etch technique is generally best for ground planes as it gives the
that power is applied to the AD7715 before signals at REF␣ IN, best shielding. Digital and analog ground planes should only be
AIN or the logic input pins in order to avoid excessive currents. joined in one place. If the AD7715 is the only device requiring
If this is not possible, then the current which flows in any of an AGND to DGND connection, then the ground planes
these pins should be limited. If separate supplies are used for should be connected at the AGND and DGND pins of the
the AD7715 and the system digital circuitry, then the AD7715 AD7715. If the AD7715 is in a system where multiple devices
should be powered up first. If it is not possible to guarantee require AGND to DGND connections, the connection should
this, then current limiting resistors should be placed in series still be made at one point only, a star ground point which
with the logic inputs to again limit the current. should be established as close as possible to the AD7715.
Supply Current Avoid running digital lines under the device as these will couple
The current consumption on the AD7715 is specified for sup- noise onto the die. The analog ground plane should be allowed
plies in the range +3␣ V to +3.6␣ V and in the range +4.75␣ V to to run under the AD7715 to avoid noise coupling. The power
+5.25␣ V. The part operates over a +2.85␣ V to +5.25␣ V supply supply lines to the AD7715 should use as large a trace as pos-
range and the IDD for the part varies as the supply voltage varies sible to provide low impedance paths and reduce the effects of
over this range. Figure 5 shows the variation of the typical glitches on the power supply line. Fast switching signals like
IDD with VDD voltage for both a 1 MHz external clock and a clocks should be shielded with digital ground to avoid radiating
2.4576 MHz external clock at +25°C. The AD7715 is operated noise to other sections of the board and clock signals should
in unbuffered mode. The relationship shows that the IDD is never be run near the analog inputs. Avoid crossover of digital
minimized by operating the part with lower VDD voltages. IDD and analog signals. Traces on opposite sides of the board should
on the AD7715 is also minimized by using an external master run at right angles to each other. This will reduce the effects of
clock or by optimizing external components when using the on- feedthrough through the board. A microstrip technique is by far
chip oscillator circuit. the best but is not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
1.0
ground planes while signals are placed on the solder side.
0.9
SUPPLY CURRENT (AVDD & DV DD) – mA
Good decoupling is important when using high resolution

0.8
ADCs. All analog supplies should be decoupled with 10␣ µF
0.7 MCLK IN = 2.4576MHz tantalum in parallel with 0.1␣ µF capacitors to AGND. To
0.6
achieve the best from these decoupling components, they must
be placed as close as possible to the device, ideally right up
0.5
against the device. All logic chips should be decoupled with
0.4 MCLK IN = 1MHz 0.1␣ µF disc ceramic capacitors to DGND. In systems where a
0.3 common supply voltage is used to drive both the AVDD and
DVDD of the AD7715, it is recommended that the system’s
0.2
AVDD supply is used. This supply should have the recom-
0.1 mended analog supply decoupling capacitors between the AVDD
0 pin of the AD7715 and AGND and the recommended digital
2.85 3.15 3.45 3.75 4.05 4.35 4.65 4.95 5.25
SUPPLY VOLTAGE (AVDD & DV DD) – Volts
supply decoupling capacitor between the DVDD pin of the
AD7715 and DGND.
Figure 5. IDD vs. Supply Voltage
Evaluating the AD7715 Performance
Grounding and Layout The recommended layout for the AD7715 is outlined in the
Since the analog inputs and reference input are differential, evaluation board for the AD7715. The evaluation board pack-
most of the voltages in the analog modulator are common-mode age includes a fully assembled and tested evaluation board,
voltages. The excellent common-mode rejection of the part will documentation, software for controlling the board over the
remove common-mode noise on these inputs. The analog and printer port of a PC and software for analyzing the AD7715’s
digital supplies to the AD7715 are independent and separately performance on the PC. For the AD7715-5, the evaluation
pinned out to minimize coupling between the analog and digital board order number is EVAL-AD7715-5EB and for the
sections of the device. The digital filter will provide rejection of AD7715-3, the order number is EVAL-AD7715-3EB.
broadband noise on the power supplies, except at integer mul-
Noise levels in the signals applied to the AD7715 may also
tiples of the modulator sampling frequency. The digital filter
affect performance of the part. The AD7715 software evaluation
also removes noise from the analog and reference inputs pro-
package allows the user to evaluate the true performance of the
vided those noise sources do not saturate the analog modulator.
part, independent of the analog input signal. The scheme
REV. B –21–
AD7715
involves using a test mode on the part where the differential that a data read is not attempted while the register is being
inputs to the AD7715 are internally shorted together to provide updated. CS is used to select the device. It can be used to de-
a zero differential voltage for the analog modulator. External to code the AD7715 in systems where a number of parts are con-
the device, the AIN(–) input should be connected to a voltage nected to the serial bus.
which is within the allowable common-mode range of the part. Figures 5 and 6 show timing diagrams for interfacing to the
This scheme should be used after a calibration has been per- AD7715 with CS used to decode the part. Figure 5 is for a read
formed on the part. operation from the AD7715’s output shift register, while Figure
6 shows a write operation to the input shift register. It is pos-
DIGITAL INTERFACE sible to read the same data twice from the output register even
The AD7715’s programmable functions are controlled using a though the DRDY line returns high after the first read opera-
set of on-chip registers as outlined previously. Data is written to tion. Care must be taken, however, to ensure that the read
these registers via the part’s serial interface and read access to operations have been completed before the next output update
the on-chip registers is also provided by this interface. All com- is about to take place.
munications to the part must start with a write operation to the
Communications Register. After power-on or RESET, the de- The AD7715 serial interface can operate in three-wire mode by
vice expects a write to its Communications Register. The data tying the CS input low. In this case, the SCLK, DIN and
written to this register determines whether the next operation to DOUT lines are used to communicate with the AD7715 and
the part is a read or a write operation and also determines to the status of DRDY can be obtained by interrogating the MSB
which register this read or write operation occurs. Therefore, of the Communications Register. This scheme is suitable for
write access to any of the other registers on the part starts with a interfacing to microcontrollers. If CS is required as a decoding
write operation to the Communications Register followed by a signal, it can be generated from a port bit. For microcontroller
write to the selected register. A read operation from any other interfaces, it is recommended that the SCLK idles high between
register on the part (including the output data register) starts data transfers.
with a write operation to the Communications Register followed The AD7715 can also be operated with CS used as a frame
by a read operation from the selected register. synchronization signal. This scheme is suitable for DSP inter-
The AD7715’s serial interface consists of five signals, CS, faces. In this case, the first bit (MSB) is effectively clocked out
SCLK, DIN, DOUT and DRDY. The DIN line is used for by CS since CS would normally occur after the falling edge of
transferring data into the on-chip registers while the DOUT line SCLK in DSPs. The SCLK can continue to run between data
is used for accessing data from the on-chip registers. SCLK is transfers provided the timing numbers are obeyed.
the serial clock input for the device and all data transfers (either The serial interface can be reset by exercising the RESET input
on DIN or DOUT) take place with respect to this SCLK signal. on the part. It can also be reset by writing a series of 1s on the
The DRDY line is used as a status signal to indicate when data DIN input. If a logic 1 is written to the AD7715 DIN line for at
is ready to be read from the AD7715’s data register. DRDY least 32 serial clock cycles, the serial interface is reset. This
goes low when a new data word is available in the output regis- ensures that in three-wire systems that if the interface gets lost
ter. It is reset high when a read operation from the data register either via a software error or by some glitch in the system, it can
is complete. It also goes high prior to the updating of the output be reset back into a known state. This state returns the interface
register to indicate when not to read from the device to ensure
DRDY
t3 t10
CS
t4 t6 t8
SCLK
t5 t7 t9
DOUT MSB LSB
Figure 6. Read Cycle Timing Diagram
CS
t11 t14 t16
SCLK
t12 t15
t13
DIN MSB LSB
Figure 7. Write Cycle Timing Diagram
–22– REV. B
AD7715
to where the AD7715 is expecting a write operation to its Com- CONFIGURING THE AD7715
munications Register. This operation in itself does not reset the The AD7715 contains three on-chip registers which the user
contents of any registers, but since the interface was lost, the accesses via the serial interface. Communication with any of
information which was written to any of the registers is un- these registers is initiated by writing to the Communications
known and it is advisable to set up all registers again. Register first. Figure 8 outlines a flow diagram of the sequence
Some microprocessor or microcontroller serial interfaces have a which is used to configure all registers after a power-up or reset.
single serial data line. In this case, it is possible to connect the The flowchart also shows two different read options—the first
AD7715’s DATA OUT and DATA IN lines together and con- where the DRDY pin is polled to determine when an update of
nect then to the single data line of the processor. A 10 kΩ pull- the data register has taken place, the second where the DRDY
up resistor should be used on this single data line. In this case, if bit of the Communications Register is interrogated to see if a
the interface gets lost, because the read and write operations data register update has taken place. Also included in the flow-
share the same line the procedure to reset it back to a known ing diagram is a series of words which should be written to the
state is somewhat different than described previously. It requires registers for a particular set of operating conditions. These con-
a read operation of 24 serial clocks followed by a write operation ditions are gain of 1, no filter sync, bipolar mode, buffer off,
where a logic 1 is written for at least 32 serial clock cycles to clock of 2.4576␣ MHz and an output rate of 60 Hz.
ensure that the serial interface is back into a known state.
START
POWER-ON/RESET FOR AD7715
CONFIGURE & INITIALIZE mC/mP SERIAL PORT
WRITE TO COMMUNICATIONS REGISTER SETTING UP

GAIN & SETTING UP NEXT OPERATION TO BE A WRITE
TO THE SETUP REGISTER (10 HEX)
WRITE TO SETUP REGISTER SETTING UP REQUIRED

VALUES & INITIATING A SELF CALIBRATION (68 HEX)
POLL DRDY PIN

WRITE TO COMMUNICATIONS REGISTER SETTING UP SAME
GAIN & SETTING UP NEXT OPERATION TO BE A READ
FROM THE COMMUNICATIONS REGISTER (08 HEX)
NO DRDY
LOW? READ FROM COMMUNICATIONS REGISTER
YES
POLL DRDY BIT OF COMMUNICATIONS REGISTER
SAME GAIN & SETTING UP NEXT OPERATION TO BE A
READ FROM THE DATA REGISTER (38 HEX)
NO DRDY
READ FROM DATA REGISTER LOW?
YES
SAME GAIN & SETTING UP NEXT OPERATION TO BE A
READ FROM THE DATA REGISTER (38 HEX)
READ FROM DATA REGISTER
Figure 8. Flowchart for Setting Up and Reading from the AD7715
REV. B –23–
AD7715
MICROCOMPUTER/MICROPROCESSOR INTERFACING DVDD DVDD
The AD7715’s flexible serial interface allows for easy interface
to most microcomputers and microprocessors. The flowchart of SS RESET
Figure 8 outlines the sequence which should be followed when
interfacing a microcontroller or microprocessor to the AD7715. SCK SCLK
Figures 9, 10 and 11 show some typical interface circuits. 68HC11 AD7715

The serial interface on the AD7715 has the capability of operat- MISO DATA OUT
ing from just three wires and is compatible with SPI interface MOSI DATA IN
protocols. The three-wire operation makes the part ideal for
isolated systems where minimizing the number of interface lines CS
minimizes the number of opto-isolators required in the system.

The rise and fall times of the digital inputs to the AD7715 Figure 9. AD7715 to 68HC11 Interface
(especially the SCLK input) should be no longer than 1␣ µs.
Most of the registers on the AD7715 are 8-bit registers. This lines to four, is to monitor the DRDY output line from the
facilitates easy interfacing to the 8-bit serial ports of microcon- AD7715. The monitoring of the DRDY line can be done in two
trollers. Some of the registers on the part are up to 16 bits, but ways. First, DRDY can be connected to one of the 68HC11’s
data transfers to these 16-bit registers can consist of a full 16-bit port bits (such as PC0) which is configured as an input. This
transfer or two 8-bit transfers to the serial port of the microcon- port bit is then polled to determine the status of DRDY. The
troller. DSP processors and microprocessors generally transfer second scheme is to use an interrupt driven system, in which
16 bits of data in a serial data operation. Some of these proces- case the DRDY output is connected to the IRQ input of the
sors, such as the ADSP-2105, have the facility to program the 68HC11. For interfaces that require control of the CS input on
amount of cycles in a serial transfer. This allows the user to the AD7715, one of the port bits of the 68HC11 (such as PC1),
tailor the number of bits in any transfer to match the register which is configured as an output, can be used to drive the CS
length of the required register in the AD7715. input.
Even though some of the registers on the AD7715 are only eight The 68HC11 is configured in the master mode with its CPOL
bits in length, communicating with two of these registers in bit set to a logic one and its CPHA bit set to a logic one. When
successive write operations can be handled as a single 16-bit the 68HC11 is configured like this, its SCLK line idles high
data transfer if required. For example, if the Setup Register is to between data transfers. The AD7715 is not capable of full du-
be updated, the processor must first write to the Communica- plex operation. If the AD7715 is configured for a write opera-
tions Register (saying that the next operation is a write to the tion, no data appears on the DATA OUT lines even when the
Setup Register) and then write eight bits to the Setup Register. SCLK input is active. Similarly, if the AD7715 is configured for
This can all be done in a single 16-bit transfer if required be- a read operation, data presented to the part on the DATA IN
cause once the eight serial clocks of the write operation to the line is ignored even when SCLK is active.
Communications Register have been completed, the part imme- Coding for an interface between the 68HC11 and the AD7715
diately sets itself up for a write operation to the Setup Register. is given in Table XVI. In this example, the DRDY output line
AD7715 to 68HC11 Interface of the AD7715 is connected to the PC0 port bit of the 68HC11
Figure 9 shows an interface between the AD7715 and the and is polled to determine its status.
68HC11 microcontroller. The diagram shows the minimum
(three-wire) interface with CS on the AD7715 hardwired low.
In this scheme, the DRDY bit of the Communications Register
is monitored to determine when the Data Register is updated.
An alternative scheme, which increases the number of interface
–24– REV. B
AD7715
AD7715 to 8XC51 Interface AD7715 to ADSP-2103/ADSP-2105 Interface
An interface circuit between the AD7715 and the 8XC51 Figure 11 shows an interface between the AD7715 and the
microcontroller is shown in Figure 10. The diagram shows the ADSP-2103/ADSP-2105 DSP processor. In the interface
minimum number of interface connections with CS on the shown, the DRDY bit of the Communications Register is again
AD7715 hardwired low. In the case of the 8XC51 interface, the monitored to determine when the Data Register is updated. The
minimum number of interconnects is just two. In this scheme, alternative scheme is to use an interrupt driven system, in which
the DRDY bit of the Communications Register is monitored to case the DRDY output is connected to the IRQ2 input of the
determine when the Data Register is updated. The alternative ADSP-2103/ADSP-2105. The serial interface of the ADSP-
scheme, which increases the number of interface lines to three, 2103/ADSP-2105 is set up for alternate framing mode. The
is to monitor the DRDY output line from the AD7715. The RFS and TFS pins of the ADSP-2103/ADSP-2105 are config-
monitoring of the DRDY line can be done in two ways. First, ured as active low outputs, and the ADSP-2103/ADSP-2105
DRDY can be connected to one of the 8XC51’s port bits (such serial clock line, SCLK, is also configured as an output. The CS
as P1.0) which is configured as an input. This port bit is then for the AD7715 is active when either the RFS or TFS outputs
polled to determine the status of DRDY. The second scheme is from the ADSP-2103/ADSP-2105 are active. The serial clock
to use an interrupt driven system in which case, the DRDY rate on the ADSP-2103/ADSP-2105 should be limited to
output is connected to the INT1 input of the 8XC51. For inter- 3␣ MHz to ensure correct operation with the AD7715.
faces that require control of the CS input on the AD7715, one
of the port bits of the 8XC51 (such as P1.1), which is config- DVDD
ured as an output, can be used to drive the CS input.
RESET
The 8XC51 is configured in its Mode 0 serial interface mode.
RFS
Its serial interface contains a single data line. As a result, the CS
TFS
DATA OUT and DATA IN pins of the AD7715 should be
connected together with a 10 kΩ pull-up resistor. The serial ADSP-2103/2105 AD7715
clock on the 8XC51 idles high between data transfers. The DR DATA OUT
8XC51 outputs the LSB first in a write operation while the
DT DATA IN
AD7715 rearranged before being written to the output serial
register. Similarly, the AD7715 outputs the MSB first during a SCLK SCLK
read operation while the 8XC51 expects the LSB first. There-
fore, the data which is read into the serial buffer needs to be
rearranged before the correct data word from the AD7715 is Figure 11. AD7715 to ADSP-2103/ADSP-2105 Interface
available in the accumulator.
CODE FOR SETTING UP THE AD7715
DVDD Table XVI gives a set of read and write routines in C code for
RESET
interfacing the 68HC11 microcontroller to the AD7715. The
DVDD sample program sets up the various registers on the AD7715
8XC51 AD7715 and reads 1000 samples from the part into the 68HC11. The
10kV
setup conditions on the part are exactly the same as those out-
P3.0 DATA OUT
lined for the flowchart of Figure 8. In the example code given
DATA IN here, the DRDY output is polled to determine if a new valid
word is available in the data register.
P3.1 SCLK
CS
The sequence of the events in this program are as follows:
1. Write to the Communications Register, setting the gain to 1
with standby inactive.
Figure 10. AD7715 to 8XC51 Interface
2. Write to the Setup Register, setting bipolar mode, buffer off,
no filter synchronization, confirming a clock frequency of
2.4576␣ MHz, setting the output rate for 60␣ Hz and initiating
a self-calibration.
3. Poll the DRDY Output.
4. Read the data from the Data Register.
5. Loop around doing Steps 3 and 4 until the specified number
of samples have been taken.
REV. B –25–
AD7715
Table XVI. C Code for Interfacing AD7715 to 68HC11
/* This program has read and write routines for the 68HC11 to interface to the AD7715 and the sample
program sets the various registers and then reads 1000 samples from the part. */
#include <math.h>
#include <io6811.h>
#define NUM_SAMPLES 1000 /* change the number of data samples */
#define MAX_REG_LENGTH 2 /* this says that the max length of a register is 2 bytes */
Writetoreg (int);
Read (int,char);
char *datapointer = store;
char store[NUM_SAMPLES*MAX_REG_LENGTH + 30];
void main()
{
/* the only pin that is programmed here from the 68HC11 is the /CS and this is why the PC2 bit
of PORTC is made as an output */
char a;
DDRC = 0x04; /* PC2 is an output the rest of the port bits are inputs */
PORTC | = 0x04; /* make the /CS line high */
Writetoreg(0x10); /* set the gain to 1, standby off and set the next operation as write to the setup
register */
Writetoreg(0x68); /* set bipolar mode, buffer off, no filter sync, confirm clock as 2.4576MHz, set
output rate to 60Hz and do a self calibration */
while(PORTC & 0x10); /* wait for /DRDY to go low */
for(a=0;a<NUM_SAMPLES;a++);
{
Writetoreg(0x38); /*set the next operation for 16 bit read from the data register */
Read(NUM_SAMPLES,2);
}
}
Writetoreg(int byteword);
{
int q;
SPCR = 0x3f;
SPCR = 0X7f; /* this sets the WiredOR mode(DWOM=1), Master mode(MSTR=1), SCK idles high(CPOL=1), /SS
can be low always (CPHA=1), lowest clock speed(slowest speed which is master clock /32 */
DDRD = 0x18; /* SCK, MOSI outputs */
q = SPSR;
q = SPDR; /* the read of the staus register and of the data register is needed to clear the interrupt
which tells the user that the data transfer is complete */
PORTC &= 0xfb; /* /CS is low */
SPDR = byteword; /* put the byte into data register */
while(!(SPSR & 0x80)); /* wait for /DRDY to go low */
PORTC |= 0x4; /* /CS high */
}
Read(int amount, int reglength)
{
int q;
SPCR = 0x3f;
SPCR = 0x7f; /* clear the interrupt */
DDRD = 0x10; /* MOSI output, MISO input, SCK output */
while(PORTC & 0x10); /* wait for /DRDY to go low */
PORTC & 0xfb ; /* /CS is low */
for(b=0;b<reglength;b++)
{
SPDR = 0;
while(!(SPSR & 0x80)); /* wait until port ready before reading */
*datapointer++=SPDR; /* read SPDR into store array via datapointer */
}
PORTC|=4; /* /CS is high */
}
–26– REV. B
AD7715
APPLICATIONS +20␣ mV to 0 V to +2.5␣ V and bipolar inputs of ± 20 mV to
The AD7715 provides a low cost, high resolution analog-to- ± 2.5 V. Because the part operates from a single supply, these
digital function. Because the analog-to-digital function is pro- bipolar ranges are with respect to a biased-up differential input.
vided by a sigma-delta architecture, it makes the part more Pressure Measurement
immune to noisy environments thus making the part ideal for One typical application of the AD7715 is pressure measurement.
use in industrial and process control applications. It also Figure 12 shows the AD7715 used with a pressure transducer,
provides a programmable gain amplifier, a digital filter and the BP01 from Sensym. The pressure transducer is arranged in a
calibration options. Thus, it provides far more system level bridge network and gives a differential output voltage between
functionality than off-the-shelf integrating ADCs without the its OUT(+) and OUT(–) terminals. With rated full-scale pres-
disadvantage of having to supply a high quality integrating ca- sure (in this case 300 mmHg) on the transducer, the differential
pacitor. In addition, using the AD7715 in a system allows the output voltage is 3 mV/V of the input voltage (i.e., the voltage
system designer to achieve a much higher level of resolution between its IN(+) and IN(–) terminals).
because noise performance of the AD7715 is significantly better
than that of the integrating ADCs. Assuming a 5 V excitation voltage, the full-scale output range
from the transducer is 15 mV. The excitation voltage for the
The on-chip PGA allows the AD7715 to handle an analog input bridge is also used to generate the reference voltage for the
voltage range as low as 10 mV full-scale with VREF = +1.25␣ V. AD7715. Therefore, variations in the excitation voltage do not
The differential inputs of the part allow this analog input range introduce errors in the system. Choosing resistor values of 24␣ kΩ
to have an absolute value anywhere between AGND and AVDD and 15 kΩ as per the diagram give a 1.92 V reference voltage for
when the part is operated in unbuffered mode. It allows the user the AD7715 when the excitation voltage is 5 V.
to connect the transducer directly to the input of the AD7715.
The programmable gain front end on the AD7715 allows the Using the part with a programmed gain of 128 results in the full-
part to handle unipolar analog input ranges from 0 mV to scale input span of the AD7715 being 15 mV which corresponds
with the output span from the transducer.
+5V
EXCITATION VOLTAGE = +5V
AVDD DVDD
IN+ AD7715
CHARGE BALANCING A/D
OUT– OUT+ AIN(+)
CONVERTER
AIN(–) BUFFER PGA
AUTO-ZEROED DIGITAL
IN– FILTER
A = 1–128 MODULATOR
24kV MCLK IN
CLOCK
GENERATION
SERIAL INTERFACE MCLK OUT
REF IN (+)
REGISTER BANK
RESET
REF IN (–)
15kV
DRDY
AGND
DGND DOUT DIN CS SCLK
Figure 12. Pressure Measurement Using the AD7715
REV. B –27–
AD7715
Temperature Measurement resistances RL1 and RL4, but these simply shift the common-
Another application area for the AD7715 is in temperature mode voltage. There is no voltage drop across lead resistances
measurement. Figure 13 outlines a connection from a thermo- RL2 and RL3 as the input current to the AD7715 is very low. The
couple to the AD7715. In this application, the AD7715 is oper- lead resistances present a small source impedance so it would
ated in its buffered mode to allow large decoupling capacitors not generally be necessary to turn on the buffer on the AD7715.
on the front end to eliminate any noise pickup which there may If the buffer is required, the common-mode voltage should be
have been in the thermocouple leads. When the AD7715 is set accordingly by inserting a small resistance between the bot-
operated in buffered mode, it has a reduced common-mode tom end of the RTD and AGND of the AD7715. In the appli-
range. In order to place the differential voltage from the thermo- cation shown an external 400␣ µA current source provides the
couple on a suitable common-mode voltage, the AIN(–) input of excitation current for the PT100 and it also generates the refer-
the AD7715 is biased up at the reference voltage, +2.5␣ V. ence voltage for the AD7715 via the 6.25 kΩ resistor. Variations
Figure 14 shows another temperature measurement application in the excitation current do not affect the circuit as both the
for the AD7715. In this case, the transducer is an RTD (Resis- input voltage and the reference voltage vary ratiometrically with
tive Temperature Device), a PT100. The arrangement is a 4- the excitation current. However, the 6.25␣ kΩ resistor must have
lead RTD configuration. There are voltage drops across the lead a low temperature coefficient to avoid errors in the reference
voltage over temperature.
+5V
AVDD DVDD
AD7715
THERMOCOUPLE
CHARGE BALANCING A/D
JUNCTION R AIN (+)
CONVERTER
R AIN (–) BUFFER PGA AUTO-ZEROED DIGITAL
FILTER
C C A = 1–128 MODULATOR
MCLK IN
+5V CLOCK
GENERATION
+VIN
REF192 VOUT REF IN (+)

REGISTER BANK
RESET
REF IN (–)
DRDY
GND
AGND
DGND DOUT DIN CS SCLK
Figure 13. Thermocouple Measurement Using the AD7715
+5V
400mA AVDD DVDD

REF IN (+)
RL1 6.25kV AD7715

REF IN (–)
RL2 AIN(+) CHARGE BALANCING A/D

CONVERTER
RTD BUFFER PGA AUTO-ZEROED DIGITAL

RL3 AIN(–) FILTER
MODULATOR
A = 1–128
RL4 MCLK IN
CLOCK
GENERATION
AGND
REGISTER BANK
RESET
DRDY
DGND
DOUT DIN CS SCLK
Figure 14. RTD Measurement Using the AD7715
–28– REV. B
AD7715
Smart Transmitters The AD7715 consumes only 450␣ µA, leaving 3␣ mA available for
Another area where the low power, single supply, three-wire the rest of the transmitter. Figure 15 shows a block diagram of a
interface capabilities is of benefit is in smart transmitters. Here, smart transmitter which includes the AD7715. Not shown in
the entire smart transmitter must operate from the 4␣ mA to Figure 15 is the isolated power source required to power the
20␣ mA loop. Tolerances in the loop mean that the amount of front end.
current available to power the transmitter is as low as 3.5␣ mA.
ISOLATION
BARRIER MAIN TRANSMITTER ASSEMBLY
ISOLATED SUPPLY 3V VOLTAGE
REGULATOR
VOLTAGE VOLTAGE
REFERENCE VCC REFERENCE
DVDD AVDD REF IN
INPUT/OUTPUT
D/A STAGE
MICROCONTROLLER UNIT CONVERTER SIGNAL 4–20mA
SENSORS CONDITIONER
RTD AD7715 MCLK *PID LOOP
mV IN *RANGE SETTING COM RTN
ohm *CALIBRATION
TC *LINEARIZATION 3V
*OUTPUT CONTROL
WAVEFORM BANDPASS
MCLK *SERIAL COMMUNICATION HART
SHAPER FILTER
OUT *HART PROTOCOL MODEM
BELL 202
DGND AGND COM
ISOLATED GROUND
Figure 15. Smart Transmitter Using the AD7715
REV. B –29–
AD7715
Topic Page
PAGE INDEX
Topic Page
CODE FOR SETTING UP AD7715 . . . . . . . . . . . . . . . . . 25
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pressure Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . 28
AD7715-5 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 2 Smart Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AD7715-3 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 31
TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5
TABLE INDEX
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6
Table Title
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table I Communications Register . . . . . . . . . . . . . . . . . . 9
PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . 7 Table II Register Selection . . . . . . . . . . . . . . . . . . . . . . . . 9
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table III Setup Register . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Communications Register . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table IV Output Update Rates . . . . . . . . . . . . . . . . . . . . 11
Setup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table V Output RMS Noise vs. Gain and Output Update
Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Rate for AD7715-5 (Unbuffered Mode) . . . . . . 12
Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table VI Peak-to-Peak Resolution vs. Gain and Output
OUTPUT NOISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Update Rate for AD7715-5 (Unbuffered Mode) . . 12
AD7715-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AD7715-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table VII Output RMS Noise vs. Gain and Output Update
AD7715-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Rate for AD7715-5 (Buffered Mode) . . . . . . . . . 12
CALIBRATION SEQUENCES . . . . . . . . . . . . . . . . . . . . . 14 Table VIII Peak-to-Peak Resolution vs. Gain and Output
CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 14 Update Rate for AD7715-5 (Buffered Mode) . . 12
ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table IX Output RMS Noise vs. Gain and Output Update
Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Rate for AD7715-3 (Unbuffered Mode) . . . . . . 13
Input Sample Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bipolar/Unipolar Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table X Peak-to-Peak Resolution vs. Gain and Output
REFERENCE INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Update Rate for AD7715-3 (Unbuffered Mode) . . 13
DIGITAL FILTERING . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table XI Output RMS Noise vs. Gain and Output Update
Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Rate for AD7715-5 (Buffered Mode) . . . . . . . . 13
Post-Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ANALOG FILTERING . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table XII Peak-to-Peak Resolution vs. Gain and Output
CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Update Rate for AD7715-3 (Buffered Mode) . . 13
Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table XIII Calibration Sequences . . . . . . . . . . . . . . . . . . . . 14
System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table XIV External R, C Combination for No 16-Bit
Span and Offset Limits . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-Up and Calibration . . . . . . . . . . . . . . . . . . . . . . . . 19
USING THE AD7715 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table XV Input Sampling Frequency vs. Gain . . . . . . . . . 15
Clocking and Oscillator Circuit . . . . . . . . . . . . . . . . . . . . 19 Table XVI C Code for Interfacing AD7715 to 68HC11 . . . 26
System Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Drift Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Evaluating the AD7715 Performance . . . . . . . . . . . . . . . . 21
DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CONFIGURING THE AD7715 . . . . . . . . . . . . . . . . . . . . . 23
MICROCOMPUTER/MICROPROCESSOR
INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AD7715 to 68HC11 Interface . . . . . . . . . . . . . . . . . . . . . 24
AD7715 to 8XC51 Interface . . . . . . . . . . . . . . . . . . . . . . 25
AD7715 to ADSP-2103/ADSP-2105 Interface . . . . . . . . 25
–30– REV. B
AD7715
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic DIP

(N-16)
C2016a–0–7/98
0.840 (21.33)
0.745 (18.93)
16 9
0.280 (7.11)
1 8 0.240 (6.10) 0.325 (8.25)
0.195 (4.95)
0.300 (7.62)
PIN 1 0.060 (1.52) 0.115 (2.93)
0.015 (0.38)
0.210 (5.33)
MAX 0.130
0.160 (4.06) (3.30)
0.115 (2.93) MIN
0.015 (0.381)
0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.008 (0.204)
0.014 (0.356) (2.54) 0.045 (1.15) PLANE
BSC
16-Lead SOIC
(R-16)
0.4133 (10.50)
0.3977 (10.00)
16 9
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
1 8
PIN 1 0.1043 (2.65) 0.0291 (0.74)

0.0118 (0.30) 3 45°
0.0926 (2.35) 0.0098 (0.25)
0.0040 (0.10)
8 0.0500 (1.27)
0.0500 0.0192 (0.49) 0
SEATING 0.0125 (0.32) 0.0157 (0.40)
(1.27) 0.0138 (0.35)
PLANE 0.0091 (0.23)
BSC
16-Lead TSSOP
(RU-16)
0.201 (5.10)
0.193 (4.90)
16 9
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1 PRINTED IN U.S.A.
8
PIN 1
0.006 (0.15)
0.002 (0.05) 0.0433
(1.10)
MAX 0.028 (0.70)
8°
0.0256 0.0118 (0.30) 0° 0.020 (0.50)
SEATING (0.65) 0.0079 (0.20)
PLANE BSC 0.0075 (0.19)
0.0035 (0.090)
REV. B –31–

3 V/5 V, 450 16-Bit, Sigma-Delta ADC AD7715 : A Max at 3 V Supplies

Uploaded by

Copyright:

Available Formats

3 V/5 V, 450 16-Bit, Sigma-Delta ADC AD7715 : A Max at 3 V Supplies

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

3 V/5 V, 450 16-Bit, Sigma-Delta ADC AD7715 : A Max at 3 V Supplies

Uploaded by

Copyright:

Available Formats

a 3 V/5 V, 450 ␮A

16-Bit, Sigma-Delta ADC

SPI™, QSPI™, MICROWIRE™ and DSP Compatible A = 1–128 CLOCK MCLK IN

SPI and QSPI are trademarks of Motorola, Inc.

Parameter A Version1 Units Conditions/Comments

Limit at TMIN, TMAX

ISINK (800mA at DVDD = +5V

ISOURCE (200mA at DVDD = +5V

AVDD Temperature Package

Pin No. Mnemonic Function

Table I. Communications Register

0/DRDY ZERO RS1 RS0 R/W STBY G1 G0

Table II. Register Selection

RS1 RS0 Register Register Size

MD1 MD0 CLK FS1 FS0 B/U BUF FSYNC

MD1 MD0 Operating Mode

CLK* FS1 FS0 Output Update Rate –3␣ dB Filter Cutoff

Data Register (RS1, RS0 = 1, 1)

MCLK IN = MCLK IN = MCLK IN = MCLK IN =

MCLK IN = MCLK IN = MCLK IN = MCLK IN =

MCLK IN = MCLK IN = MCLK IN = MCLK IN =

MCLK IN = MCLK IN = MCLK IN = MCLK IN =

MCLK IN = MCLK IN = MCLK IN = MCLK IN =

MCLK IN = MCLK IN = MCLK IN = MCLK IN =

Table XIII. Calibration Sequences

CIRCUIT DESCRIPTION information. The programmable gain function on the analog

AD780 10mF 0.1mF

is ratiometric. Recommended reference voltage sources for the H (z ) =  × –1 

–100 settling time.

Good decoupling is important when using high resolution

DOUT MSB LSB

Figure 6. Read Cycle Timing Diagram

t11 t14 t16

DIN MSB LSB

Figure 7. Write Cycle Timing Diagram

POWER-ON/RESET FOR AD7715

CONFIGURE & INITIALIZE mC/mP SERIAL PORT

WRITE TO COMMUNICATIONS REGISTER SETTING UP

WRITE TO SETUP REGISTER SETTING UP REQUIRED

POLL DRDY PIN

READ FROM DATA REGISTER

Figure 8. Flowchart for Setting Up and Reading from the AD7715

Figures 9, 10 and 11 show some typical interface circuits. 68HC11 AD7715

minimizes the number of opto-isolators required in the system.

DGND DOUT DIN CS SCLK

Figure 12. Pressure Measurement Using the AD7715

REF192 VOUT REF IN (+)

DGND DOUT DIN CS SCLK

Figure 13. Thermocouple Measurement Using the AD7715

400mA AVDD DVDD

RL1 6.25kV AD7715

RL2 AIN(+) CHARGE BALANCING A/D

RTD BUFFER PGA AUTO-ZEROED DIGITAL

DOUT DIN CS SCLK

Figure 14. RTD Measurement Using the AD7715

Figure 15. Smart Transmitter Using the AD7715

16-Lead Plastic DIP

PIN 1 0.1043 (2.65) 0.0291 (0.74)

You might also like