SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

D 15-V Digital or ±7.5-V Peak-to-Peak D Matched Control-Input to Signal-Output

Switching Capacitance: Reduces Output Signal
D 125-Ω Typical On-State Resistance for 15-V Transients
Operation D Frequency Response, Switch On = 40 MHz
D Switch On-State Resistance Matched to Typical
Within 5 Ω Over 15-V Signal-Input Range D 100% Tested for Quiescent Current at 20 V
D On-State Resistance Flat Over Full D 5-V, 10-V, and 15-V Parametric Ratings
Peak-to-Peak Signal Range D Meets All Requirements of JEDEC Tentative
D High On/Off Output-Voltage Ratio: 80 dB Standard No. 13-B, Standard Specifications
Typical at fis = 10 kHz, RL = 1 kΩ for Description of “B” Series CMOS
D High Degree of Linearity: <0.5% Distortion Devices
Typical at fis = 1 kHz, Vis = 5 V p-p, D Applications:
VDD − VSS ≥ 10 V, RL = 10 kΩ − Analog Signal Switching/Multiplexing:
D Extremely Low Off-State Switch Leakage, Signal Gating, Modulator, Squelch
Resulting in Very Low Offset Current and Control, Demodulator, Chopper,
High Effective Off-State Resistance: 10 pA Commutating Switch
Typical at VDD − VSS = 10 V, TA = 25°C − Digital Signal Switching/Multiplexing
− Transmission-Gate Logic Implementation
D Extremely High Control Input Impedance
− Analog-to-Digital and Digital-to-Analog
(Control Circuit Isolated From Signal
Conversion
Circuit): 1012 Ω Typical
− Digital Control of Frequency, Impedance,
D Low Crosstalk Between Switches: −50 dB Phase, and Analog-Signal Gain
Typical at fis = 8 MHz, RL = 1 kΩ

E, F, M, NS, OR PW PACKAGE
(TOP VIEW)

SIG A IN/OUT 1 14 VDD

SIG A OUT/IN 2 13 CONTROL A
SIG B OUT/IN 3 12 CONTROL D
SIG B IN/OUT 4 11 SIG D IN/OUT
CONTROL B 5 10 SIG D OUT/IN
CONTROL C 6 9 SIG C OUT/IN
VSS 7 8 SIG C IN/OUT

description/ordering information
The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals.
It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the
on-state resistance is relatively constant over the full signal-input range.
The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices
in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the
n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch
is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and,
thus, keeps the on-state resistance low over the full operating-signal range.
The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply
voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold
applications, the CD4016B is recommended.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.


     !"   #!$% &"' Copyright  2003, Texas Instruments Incorporated
&!   #" #" (" "  ") !"
&& *+' &! #", &"  ""%+ %!&"
",  %% #""'

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1





    

SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

description/ordering information (continued)

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
CDIP − F Tube of 25 CD4066BF3A CD4066BF3A
PDIP − E Tube of 25 CD4066BE CD4066BE
Tube of 50 CD4066BM
SOIC − M Reel of 2500 CD4066BM96 CD4066BM
−55°C to 125°C
Reel of 250 CD4066BMT
SOP − NS Reel of 2000 CD4066BNSR CD4066B
Tube of 90 CD4066BPW
TSSOP − PW CM066B
Reel of 2000 CD4066BPWR
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Switch

Control
In
Vis

p n

p
Out
n Vos

Control n
VC†
VSS

VDD

VSS

† All control inputs are protected by the CMOS protection network.

NOTES: A. All p substrates are connected to VDD.
B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS
C. Signal-level range: VSS ≤ Vis ≤ VDD 92CS-29113

Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
DC supply-voltage range, VDD (voltages referenced to VSS terminal) . . . . . . . . . . . . . . . . . . . . −0.5 V to 20 V
Input voltage range, Vis (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDD + 0.5 V
DC input current, IIN (any one input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Package thermal impedance, θJA (see Note 1): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Lead temperature (during soldering):
At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 265°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

MIN MAX UNIT
VDD Supply voltage 3 18 V
TA Operating free-air temperature −55 125 °C

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

electrical characteristics
LIMITS AT INDICATED TEMPERATURES
PARAMETER TEST CONDITIONS VIN VDD 25°C UNIT
−55°C −40°C 85°C 125°C
(V) (V) TYP MAX
0, 5 5 0.25 0.25 7.5 7.5 0.01 0.25
Quiescent device 0, 10 10 0.5 0.5 15 15 0.01 0.5
IDD µA
A
current 0, 15 15 1 1 30 30 0.01 1
0, 20 20 5 5 150 150 0.02 5
Signal Inputs (Vis) and Outputs (Vos)
VC = VDD, 5 800 850 1200 1300 470 1050
RL = 10 kΩ returned
On-state resistance ǒV DD * V SSǓ
ron 10 310 330 500 550 180 400 Ω
(max) to 2 ,
Vis = VSS to VDD 15 200 210 300 320 125 240

On-state resistance 5 15
∆ron difference between RL = 10 kΩ, VC = VDD 10 10 Ω
any two switches 15 5
VC = VDD = 5 V, VSS = −5 V,
Total harmonic
THD Vis(p-p) = 5 V (sine wave centered on 0 V), 0.4 %
distortion
RL = 10 kΩ, fis = 1-kHz sine wave
−3-dB cutoff
VC = VDD = 5 V, VSS = −5 V, Vis(p-p) = 5 V
frequency 40 MHz
(sine wave centered on 0 V), RL = 1 kΩ
(switch on)
−50-dB feedthrough VC = VSS = −5 V, Vis(p-p) = 5 V
1 MHz
frequency (switch off) (sine wave centered on 0 V), RL = 1 kΩ
Input/output leakage VC = 0 V, Vis = 18 V, Vos = 0 V;
Iis current (switch off) and 18 ±0.1 ±0.1 ±1 ±1 ±10−5 ±0.1 µA
(max) VC = 0 V, Vis = 0 V, Vos = 18 V
VC(A) = VDD = 5 V,
−50-dB crosstalk VC(B) = VSS = −5 V,
8 MHz
frequency Vis(A) = 5 Vp-p, 50-Ω source,
RL = 1 kΩ
RL = 200 kΩ, VC = VDD, 5 20 40
Propagation delay VSS = GND, CL = 50 pF,
tpd (signal input to Vis = 10 V 10 10 20 ns
signal output) (square wave centered on 5 V),
tr, tf = 20 ns 15 7 15
Cis Input capacitance VDD = 5 V, VC = VSS = −5 V 8 pF
Cos Output capacitance VDD = 5 V, VC = VSS = −5 V 8 pF
Cios Feedthrough VDD = 5 V, VC = VSS = −5 V 0.5 pF

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

electrical characteristics (continued)

LIMITS AT INDICATED TEMPERATURES
CHARACTERISTIC TEST CONDITIONS VDD 25°C UNIT
−55°C −40°C 85°C 125°C
(V) TYP MAX
Control (VC)

|Iis| < 10 µA, 5 1 1 1 1 1

Control input,
VILC Vis = VSS, VOS = VDD, and 10 2 2 2 2 2 V
low voltage (max)
Vis = VDD, VOS = VSS 15 2 2 2 2 2
5 3.5 (MIN)
Control input,
VIHC See Figure 6 10 7 (MIN) V
high voltage
15 11 (MIN)
Vis ≤ VDD, VDD − VSS = 18 V,
IIN Input current (max) 18 ±0.1 ±0.1 ±1 ±1 ±10−5 ±0.1 µA
VCC ≤ VDD − VSS
Crosstalk (control input VC = 10 V (square wave),
10 50 mV
to signal output) tr, tf = 20 ns, RL = 10 kΩ
5 35 70
Turn-on and turn-off VIN = VDD, tr, tf = 20 ns,
10 20 40 ns
propagation delay CL = 50 pF, RL = 1 kΩ
15 15 30
Vis = VDD, VSS = GND, 5 6
RL = 1 kΩ to GND, CL = 50 pF,
Maximum control input
VC = 10 V (square wave 10 9 MHz
repetition rate
centered on 5 V), tr, tf = 20 ns,
Vos = 1/2 Vos at 1 kHz 15 9.5
CI Input capacitance 5 7.5 pF

switching characteristics
SWITCH INPUT SWITCH
VDD OUTPUT, Vos
(V) Vis Iis (mA) (V)
(V) −55°C −40°C 25°C 85°C 125°C MIN MAX
5 0 0.64 0.61 0.51 0.42 0.36 0.4
5 5 −0.64 −0.61 −0.51 −0.42 −0.36 4.6
10 0 1.6 1.5 1.3 1.1 0.9 0.5

10 10 −1.6 −1.5 −1.3 −1.1 −0.9 9.5

15 0 4.2 4 3.4 2.8 2.4 1.5

15 15 −4.2 −4 −3.4 −2.8 −2.4 13.5

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

TYPICAL ON-STATE RESISTANCE TYPICAL ON-STATE RESISTANCE

vs vs
INPUT SIGNAL VOLTAGE (ALL TYPES) INPUT SIGNAL VOLTAGE (ALL TYPES)
300

r − Channel On-State Resistance − Ω

600 Supply Voltage (VDD − VSS) = 5 V Supply Voltage (VDD − VSS) = 10 V
r − Channel On-State Resistance − Ω

TA = 125°C
500 250 TA = 125°C

400 200
+25°C
300 150
+25°C −55°C
200 100
−55°C
100 50

on
on

0
−4 −3 −2 −1 0 1 2 3 4 −10 −7.5 −5 −2.5 0 2.5 5 7.5 10

Vis − Input Signal Voltage − V Vis − Input Signal Voltage − V

92CS-27326RI 92CS-27327RI

Figure 2 Figure 3

TYPICAL ON-STATE RESISTANCE TYPICAL ON-STATE RESISTANCE

vs vs
INPUT SIGNAL VOLTAGE (ALL TYPES) INPUT SIGNAL VOLTAGE (ALL TYPES)
Supply Voltage (VDD − VSS) = 15 V TA = 125°C
r − Channel On-State Resistance − Ω
r − Channel On-State Resistance − Ω

300 600

250 500 Supply Voltage (VDD − VSS) = 5 V

200 400
TA = 125°C
150 300

100 +25°C 200

−55°C 10 V
50 100 −15 V

0 0
on
on

−10 −7.5 −5 −2.5 0 2.5 5 7.5 10 −10 −7.5 −5 −2.5 0 2.5 5 7.5 10
Vis − Input Signal Voltage − V Vis − Input Signal Voltage − V
92CS-27329RI 92CS-27330RI
Figure 4 Figure 5

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

Iis CD4066B
Vis Vos
1 of 4 Switches

|Vis − Vos|
ron =
|Iis|
92CS-30966

Figure 6. Determination of ron as a Test Condition for Control-Input High-Voltage (VIHC) Specification

Keithley
VDD 160 Digital
Multimeter

TG
10 kΩ 1-kΩ
On
Range Y
H. P.
VSS X-Y
Moseley
Plotter 7030A

92CS-22716

Figure 7. Channel On-State Resistance Measurement Circuit

POWER DISSIPATION PER PACKAGE

TYPICAL ON CHARACTERISTICS vs
FOR 1 OF 4 CHANNELS SWITCHING FREQUENCY
104
6 TA = 25°C
3 4
PD − Power Dissipation Per Package − µ W

2
2 103
Supply Voltage
6
(VDD) = 15 V
VO − Output Voltage − V

4
1
2
10 V
102
0 6 5V VDD
VC = VDD VDD 14
4 5
Vos 2
CD4066B 6
−1 Vis 1 of 4
Switches 101 12
CD4066B
RL
6 13
−2
VSS 4
7
All unused terminals are 2 VSS
connected to VSS
−3 10 2 4 6 2 4 6
−3 −2 −1 0 1 2 3 4 10 102 103

VI − Input Voltage − V f − Switching Frequency − kHz

92CS-30919 92C-30920
Figure 8 Figure 9

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

Cios

VC = −5 V VDD = 5 V

CD4066B VDD
1 of 4 VC = VSS
Switches Vos
CD4066B
Vis = VDD
Cis 1 of 4
VSS = −5 V Cos Switches I

VSS
92CS-30921
Measured on Boonton capacitance bridge, model 75a (1 MHz); 92CS-30922
test-fixture capacitance nulled out. All unused terminals are connected to VSS.
Figure 10. Typical On Characteristics Figure 11. Off-Switch Input or Output Leakage
for One of Four Channels

VDD
VC = VDD
+10 V VC VDD
Vos
Vis CD4066B
1 of 4 tr = tf = 20 ns Vis V
CD4066B os
Switches
1 of 4
200 kΩ
VSS 50 pF 1 kΩ Switches 10 kΩ
VDD VSS
tr = tf = 20 ns
92CS-30923 92CS-30924
All unused terminals are connected to VSS. All unused terminals are connected to VSS.

Figure 12. Propagation Delay Time Signal Input Figure 13. Crosstalk-Control Input
(Vis) to Signal Output (Vos) to Signal Output

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

VDD VDD
tr = tf = 20 ns VC = VDD
Vos
VDD CD4066B
1 of 4
Switches
1 kΩ
VSS 50 pF

NOTES: A. All unused terminals are connected to VSS. 92CS-30925

B. Delay is measured at Vos level of +10% from ground (turn-on) or on-state output level (turn-off).

Figure 14. Propagation Delay, tPLH, tPHL Control-Signal Output

tr tf
VC 10 V
90%
10% 50%
0V
Repetition
Rate
tr = tf = 20 ns
Vos V OS at 1 kHz
V OS +
2

VDD = 10 V
VC V OS at 1 kHz
V OS +
2
Vis = 10 V CD4066B
1 of 4
Switches
50 pF 1 kΩ
VSS

All unused terminals are connected to VSS. 92CS-30925

Figure 15. Maximum Allowable Control-Input Repetition Rate

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS
VDD

Inputs

VDD

VSS

VSS 92CS-27555

Measure inputs sequentially to both VDD and VSS. Connect all unused inputs to either VDD or VSS. Measure control inputs only.

Figure 16. Input Leakage-Current Test Circuit

10 2 3 7 9 12
10 2 3 7 9 12 Clock
Clock 14 P E J1 J2 J3 J4 J5
14 P E J1 J2 J3 J4 J5 External
Reset 15 CD4018B
15 CD4018B 13 Reset
1 Q1 Q2
1 Q1 Q2
5 4
1 1/4 CD4066B 2
5 4

13 12 9 8 6 5 2 1
1
3
2 7 6

3 1/3 CD4049B
2 5
4 9 10 CD4001B
CD4001B

1/3 CD4049B 6
11 10 4 3
5 4
8
10
9
12 6 5 11 Signal
12 6 5 13 Outputs
11
13 Channel 1
2 LPF
Signal 12 11 12
Inputs 10 k Ω
Channel 1 1/6 CD4049B
1 2
1
Channel 2 5
4 CD4066B 3 Channel 2
4 3 LPF
Channel 3
8 9 10 kΩ
4 1/4 CD4066B CD4066B
Channel 4 3 8
11 10
11 Channel 3
Package Count 9 LPF
10 kΩ
2 - CD4001B 10 kΩ
1 - CD4049B
3 - CD4066B
2 - CD4018B VDD 10 LPF Channel 4
Clock
Maximum 10 kΩ
Allowable 30% (VDD − VSS)
VSS
Signal Level Chan 1 Chan 2 Chan 3 Chan 4

92CM-30928

Figure 17. Four-Channel PAM Multiplex System Diagram

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS
5V
Analog Inputs (±5 V)
0
−5 V
VDD = 5 V
VDD = 5 V

CD4066B
5V SWA
0 SWB
IN CD4054B
SWC

SWD
Digital
Control
Inputs
VSS = 0 V
VEE = −5 V VSS = −5 V
Analog Outputs (±5 V)

92CS-30927

Figure 18. Bidirectional Signal Transmission Via Digital Control Logic

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

APPLICATION INFORMATION

In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability
should exceed VDD/RL (RL = effective external load of the four CD4066B bilateral switches). This provision avoids
any permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4066B.
In certain applications, the external load-resistor current can include both VDD and signal-line components. To avoid
drawing VDD current when switch current flows into terminals 1, 4, 8, or 11, the voltage drop across the bidirectional
switch must not exceed 0.8 V (calculated from ron values shown).
No VDD current will flow through RL if the switch current flows into terminals 2, 3, 9, or 10.

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 18-Oct-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

CD4066BE ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD4066BE
(RoHS)
CD4066BEE4 ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD4066BE
(RoHS)
CD4066BF ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD4066BF

CD4066BF3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD4066BF3A

CD4066BF3AS2283 OBSOLETE CDIP J 14 TBD Call TI Call TI

CD4066BF3AS2534 OBSOLETE CDIP J 14 TBD Call TI Call TI
CD4066BM ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
& no Sb/Br)
CD4066BM96 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CD4066BM
& no Sb/Br)
CD4066BM96E4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
& no Sb/Br)
CD4066BM96G4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
& no Sb/Br)
CD4066BME4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
& no Sb/Br)
CD4066BMG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
& no Sb/Br)
CD4066BMT ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
& no Sb/Br)
CD4066BMTE4 ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
& no Sb/Br)
CD4066BMTG4 ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
& no Sb/Br)
CD4066BNSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066B
& no Sb/Br)
CD4066BNSRE4 ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066B
& no Sb/Br)
CD4066BNSRG4 ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066B
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 18-Oct-2013

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

CD4066BPW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B
& no Sb/Br)
CD4066BPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B
& no Sb/Br)
CD4066BPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B
& no Sb/Br)
CD4066BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B
& no Sb/Br)
CD4066BPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B
& no Sb/Br)
CD4066BPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B
& no Sb/Br)
JM38510/05852BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
05852BCA
M38510/05852BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
05852BCA

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 18-Oct-2013

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD4066B, CD4066B-MIL :

• Catalog: CD4066B
• Automotive: CD4066B-Q1, CD4066B-Q1
• Military: CD4066B-MIL

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD4066BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BM96G4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BM96G4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BMT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4066BPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4066BM96 SOIC D 14 2500 367.0 367.0 38.0
CD4066BM96 SOIC D 14 2500 333.2 345.9 28.6
CD4066BM96G4 SOIC D 14 2500 367.0 367.0 38.0
CD4066BM96G4 SOIC D 14 2500 333.2 345.9 28.6
CD4066BMT SOIC D 14 250 367.0 367.0 38.0
CD4066BNSR SO NS 14 2000 367.0 367.0 38.0
CD4066BPWR TSSOP PW 14 2000 367.0 367.0 35.0

Pack Materials-Page 2
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