SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003

D Zero Reading for 0-V Input DW OR N PACKAGE

(TOP VIEW)
D Precision Null Detection With True Polarity
at Zero
VCC − 1 28 UNDER RANGE
D 1-pA Typical Input Current REF 2 27 OVER RANGE
D True Differential Input ANLG COMMON 3 26 STROBE
D Multiplexed Binary-Coded-Decimal (BCD) INT OUT 4 25 RUN/HOLD
Output AUTO ZERO 5 24 DGTL GND
D Low Rollover Error: ± 1 Count Max BUFF OUT 6 23 POLARITY
Cref − 7 22 CLK
D Control Signals Allow Interfacing With
Cref + 8 21 BUSY
UARTs or Microprocessors
IN − 9 20 D1
D Autoranging Capability With Over- and IN + 10 19 D2
Under-Range Signals VCC + 11 18 D3
D TTL-Compatible Outputs D5 12 17 D4
D Second Source to Teledyne TSC7135, B1 13 16 B8
Intersil ICL7135, Maxim ICL7135, and B2 14 15 B4
Siliconix Si7135
D CMOS Technology

DESCRIPTION
The ICL7135C and TLC7135C converters are manufactured with Texas Instruments highly efficient CMOS
technology. These 4 1/2-digit, dual-slope-integrating, analog-to-digital converters (ADCs) are designed to
provide interfaces to both a microprocessor and a visual display. The digit-drive outputs D1 through D4 and
multiplexed binary-coded-decimal outputs B1, B2, B4, and B8 provide an interface for LED or LCD
decoder/drivers as well as microprocessors.
The ICL7135C and TLC7135C offer 50-ppm (one part in 20,000) resolution with a maximum linearity error of
one count. The zero error is less than 10 µV and zero drift is less than 0.5 µV/°C. Source-impedance errors are
minimized by low input current (less than 10 pA). Rollover error is limited to ± 1 count.
The BUSY, STROBE, RUN/HOLD, OVER RANGE, and UNDER RANGE control signals support
microprocessor-based measurement systems. The control signals also can support remote data acquisition
systems with data transfer through universal asynchronous receiver transmitters (UARTs).
The ICL7135C and TLC7135C are characterized for operation from 0°C to 70°C.
AVAILABLE OPTIONS
PACKAGE
TA PLASTIC DIP SMALL OUTLINE
(N) (DW)
ICL7135CN
0°C to 70°C
TLC7135CN TLC7135CDW

Caution. These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam
during storage or handlilng to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.


   ! " #$%! "  &$'(#! )!%* Copyright  1999−2003, Texas Instruments Incorporated
)$#!" # ! "&%##!" &% !+% !%"  %,"
"!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/  (( &%!%"*

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SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003

FUNCTIONAL BLOCK DIAGRAM

DIGITAL SECTION

23 20
POLARITY Polarity D1 (LSD)
Latch 19
From Analog Flip-Flop D2 Digit
Section 18 Drive
D3
17 Output
D4
Zero Latch 12
D5 (MSD)
Cross
Detect Control Counters
22 Logic Latch
CLK Multiplexer
25
RUN/HOLD
27
OVER RANGE 13
28 Latch
UNDER RANGE B1 (LSB) Binary
26 14
B2 Coded
STROBE 15 Decimal
21 B4
BUSY Output
24 Latch 16
DGTL GND B8 (MSB)

ANALOG SECTION

RINT CAZ CINT

Cref
BUFF AUTO
Cref + Cref − OUT
8 7 6 5 ZERO 4 INT OUT

Buffer Integrator
Comparator
A/Z − −
2 +
REF Input + +
High
− To
INT A/Z Digital
10 Section
IN +
DE(−) DE(+) Z/I

A/Z
A/Z

DE(+) DE(−) Input

Low
3
ANLG
COMMON

INT A/Z, DE( ±), Z/I

9
IN −

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SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)
UNIT
Supply voltage (VCC+ with respect to VCC −) 15 V
Analog input voltage (IN − or IN +) VCC − to VCC+
Reference voltage range VCC − to VCC+
Clock input voltage range 0 V to VCC+
Operating free-air temperature range, TA 0°C to 70°C
Storage temperature range, Tstg −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package 260°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT
Supply voltage, VCC+ 4 5 6 V
Supply voltage, VCC− −3 −5 −8 V
Reference voltage, Vref 1 V
High-level input voltage, CLK, RUN/HOLD, VIH 2.8 V
Low-level input voltage, CLK, RUN/HOLD, VIL 0.8 V
Differential input voltage, VID VCC − +1 VCC+ − 0.5 V
Maximum operating frequency, fclock (see Note 1) 1.2 2 MHz
Operating free-air temperature range, TA 0 70 °C
NOTE 1: Clock frequency range extends down to 0 Hz.

ELECTRICAL CHARACTERISTICS
VCC + = 5 V, VCC − = 5 V, Vref = 1 V, fclock = 120 kHz, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
D1-D5, B1,B2,B4,B8 IO = − 1 mA 2.4 5
VOH High-level output voltage V
Other outputs IO = − 10 µA 4.9 5
VOL Low-level output voltage IO = 1.6 mA 0.4 V
VON(PP) Peak-to-peak output noise voltage (see Note 1) VID = 0, Full scale = 2 V 15 µV
αVO Zero-reading temperature coefficient of output voltage VID = 0, 0°C ≤ TA ≤ 70°C 0.5 2 µV/°C
IIH High-level input current VI = 5 V, 0°C ≤ TA ≤ 70°C 0.1 10 µA
IIL Low-level input current VI = 0 V, 0°C ≤ TA ≤ 70°C −0.02 −0.1 mA
TA = 25°C 1 10
II Input leakage current, IN − and IN + VID = 0 pA
0°C ≤ TA ≤ 70°C 250
TA = 25°C 1 2
ICC + Positive supply current fclock = 0 mA
0°C ≤ TA ≤ 70°C 3
TA = 25°C −0.8 −2
ICC − Negative supply current fclock = 0 mA
0°C ≤ TA ≤ 70°C −3
Cpd Power dissipation capacitance See Note 2 40 pF
NOTES: 1. This is the peak-to-peak value that is not exceeded 95% of the time.
2. Factor-relating clock frequency to increase in supply current. At VCC+ = 5 V, ICC+ = ICC+(fclock = 0) + Cpd × 5 V × fclock

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SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003

OPERATING CHARACTERISTICS
VCC + = 5 V, VCC − = 5 V, Vref = 1 V, fclock = 120 kHz, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
αFS Full-scale temperature coefficient (see Note 1) VID = 2 V, 0°C ≤ TA ≤ 70°C 5 ppm/°C
EL Linearity error −2 V ≤ VID ≤ 2 V 0.5 count
ED Differential linearity error (see Note 2) −2 V ≤ VID ≤ 2 V 0.01 LSB
EFS ± Full-scale symmetry error (rollover error) (see Note 3) VID = ± 2 V 0.5 1 count
Digital
Display reading with 0-V input VID = 0, 0°C ≤ TA ≤ 70°C −0.0000 ± 0.0000 0.0000
Reading
VID = Vref, TA = 25°C 0.9998 0.9999 1.0000 Digital
Display reading in ratiometric operation
0°C ≤ TA ≤ 70°C 0.9995 0.9999 1.0005 Reading
NOTES: 1. This parameter is measured with an external reference having a temperature coefficient of less than 0.01 ppm/°C.
2. The magnitude of the difference between the worst case step of adjacent counts and the ideal step.
3. Rollover error is the difference between the absolute values of the conversion for 2 V and − 2 V.

TIMING DIAGRAMS
End of Conversion

BUSY†

B1 −B8 D5 D4 D3 D2 D1 D5

STROBE†
200 Counts

D5
201 Counts 200 Counts

D4
200 Counts

D3
200 Counts

D2
200 Counts

D1
200 Counts
† Delay between BUSY going low and the first STROBE pulse is dependent upon the analog input.

Figure 1

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SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003

Digital Scan
D5
for OVER-RANGE
D4

D3

D2

D1
1000 Counts

Figure 2

Integrator Output

AUTO ZERO Signal Int De-Integrate

10,001 Counts 10,000 20,001 Counts Max
Counts

Full Measurement Cycle

40,002 Counts

BUSY

OVER RANGE
When Applicable

UNDER RANGE
When Applicable

Figure 3

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SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003

STROBE

AUTO ZERO
Signal Integrate Deintegrate†
Digit Scan D5†
for OVER RANGE

D4

D3

D2

D1

† First D5 of AUTO ZERO and deintegrate is one count longer.

Figure 4

PRINCIPLES OF OPERATION

A measurement cycle for the ICL7135C and TLC7135C consists of the following four phases.
1. Auto-Zero Phase. The internal IN + and IN− inputs are disconnected from the terminals and internally
connected to ANLG COMMON. The reference capacitor is charged to the reference voltage. The
system is configured in a closed loop and the auto-zero capacitor is charged to compensate for offset
voltages in the buffer amplifier, integrator, and comparator. The auto-zero accuracy is limited only by the
system noise, and the overall offset, as referred to the input, is less than 10 µV.
2. Signal Integrate Phase. The auto-zero loop is opened and the internal IN + and IN − inputs are
connected to the external terminals. The differential voltage between these inputs is integrated for a
fixed period of time. When the input signal has no return with respect to the converter power supply, IN−
can be tied to ANLG COMMON to establish the correct common-mode voltage. Upon completion of this
phase, the polarity of the input signal is recorded.
3. Deintegrate Phase. The reference is used to perform the deintegrate task. The internal IN− is internally
connected to ANLG COMMON and IN+ is connected across the previously charged reference
capacitor. The recorded polarity of the input signal ensures that the capacitor is connected with the
correct polarity so that the integrator output polarity returns to zero. The time required for the output to
return to zero is proportional to the amplitude of the input signal. The return time is displayed as a digital
reading and is determined by the equation 10,000 × (VID/Vref). The maximum or full-scale conversion
occurs when VID is two times Vref.
4. Zero Integrator Phase. The internal IN− is connected to ANLG COMMON. The system is configured in a
closed loop to cause the integrator output to return to zero. Typically, this phase requires 100 to 200
clock pulses. However, after an over-range conversion, 6200 pulses are required.

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SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003

DESCRIPTION OF ANALOG CIRCUITS

Input Signal Range
The common mode range of the input amplifier extends from 1 V above the negative supply to 1 V below the
positive supply. Within this range, the common-mode rejection ratio (CMRR) is typically 86 dB. Both differential
and common-mode voltages cause the integrator output to swing. Therefore, care must be exercised to ensure
that the integrator output does not become saturated.
Analog Common
Analog common (ANLG COMMON) is connected to the internal IN− during the auto-zero, deintegrate, and zero
integrator phases. When IN− is connected to a voltage that is different from analog common during the signal
integrate phase, the resulting common-mode voltage is rejected by the amplifier. However, in most applications,
IN− is set at a known fixed voltage (i.e., power supply common for instance). In this application, analog common
should be tied to the same point, thus removing the common-mode voltage from the converter. Removing the
common-mode voltage in this manner slightly increases conversion accuracy.
Reference
The reference voltage is positive with respect to analog common. The accuracy of the conversion result is
dependent upon the quality of the reference. Therefore, to obtain a high accuracy conversion, a high quality
reference should be used.

DESCRIPTION OF DIGITAL CIRCUITS

RUN/HOLD Input
When RUN/HOLD is high or open, the device continuously performs measurement cycles every 40,002 clock
pulses. When this input is taken low, the integrated circuit continues to perform the ongoing measurement cycle
and then hold the conversion reading for as long as the terminal is held low. When the terminal is held low after
completion of a measurement cycle, a short positive pulse (greater than 300 ns) initiates a new measurement
cycle. When this positive pulse occurs before the completion of a measurement cycle, it will not be recognized.
The first STROBE pulse, which occurs 101 counts after the end of a measurement cycle, is an indication of the
completion of a measurement cycle. Thus, the positive pulse could be used to trigger the start of a new
measurement after the first STROBE pulse.
STROBE Input
Negative going pulses from this input transfer the BCD conversion data to external latches, UARTs, or
microprocessors. At the end of the measurement cycle, STROBE goes high and remains high for 201 counts.
The most significant digit (MSD) BCD bits are placed on the BCD terminals. After the first 101 counts, halfway
through the duration of output D1−D5 going high, the STROBE terminal goes low for 1/2 clock pulse width. The
placement of the STROBE pulse at the midpoint of the D5 high pulse allows the information to be latched into
an external device on either a low-level or an edge. Such placement of the STROBE pulse also ensures that
the BCD bits for the second MSD are not yet competing for the BCD lines and latching of the correct bits is
ensured. The above process is repeated for the second MSD and the D4 output. Similarly, the process is
repeated through the least significant digit (LSD). Subsequently, inputs D5 through D1 and the BCD lines
continue scanning without the inclusion of STROBE pulses. This subsequent continuous scanning causes the
conversion results to be continuously displayed. Such subsequent scanning does not occur when an over-range
condition occurs.

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SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003

BUSY Output
The BUSY output goes high at the beginning of the signal integrate phase. BUSY remains high until the first
clock pulse after zero crossing or at the end of the measurement cycle when an over-range condition occurs.
It is possible to use the BUSY terminal to serially transmit the conversion result. Serial transmission can be
accomplished by ANDing the BUSY and CLOCK signals and transmitting the ANDed output. The transmitted
output consists of 10,001 clock pulses, which occur during the signal integrate phase, and the number of clock
pulses that occur during the deintegrate phase. The conversion result can be obtained by subtracting 10,001
from the total number of clock pulses.
OVER-RANGE Output
When an over-range condition occurs, this terminal goes high after the BUSY signal goes low at the end of the
measurement cycle. As previously noted, the BUSY signal remains high until the end of the measurement cycle
when an over-range condition occurs. The OVER RANGE output goes high at the end of BUSY and goes low
at the beginning of the deintegrate phase in the next measurement cycle.
UNDER-RANGE Output
At the end of the BUSY signal, this terminal goes high when the conversion result is less than or equal to 9%
(count of 1800) of the full-scale range. The UNDER-RANGE output is brought low at the beginning of the signal
integrate phase of the next measurement cycle.
POLARITY Output
The POLARITY output is high for a positive input signal and updates at the beginning of each deintegrate phase.
The polarity output is valid for all inputs including ± 0 and OVER RANGE signals.
Digit-Drive (D1, D2, D4 and D5) Outputs
Each digit-drive output (D1 through D5) sequentially goes high for 200 clock pulses. This sequential process
is continuous unless an over-range occurs. When an over-range occurs, all of the digit-drive outputs are blanked
from the end of the strobe sequence until the beginning of the deintegrate phase (when the sequential digit-drive
activation begins again). The blanking activity during an over-range condition can cause the display to flash and
indicate the over-range condition.
BCD Outputs
The BCD bits (B1, B2, B4 and B8) for a given digit are sequentially activated on these outputs. Simultaneously,
the appropriate digit-drive line for the given digit is activated.

System Aspects
Integrating Resistor
The value of the integrating resistor (RINT) is determined by the full-scale input voltage and the output current
of the integrating amplifier. The integrating amplifier can supply 20 µA of current with negligible nonlinearity. The
equation for determining the value of this resistor is:
Full Scale Voltage
R +
INT I
INT
Integrating amplifier current, IINT, from 5 to 40 µA yields good results. However, the nominal and recommended
current is 20 µA.

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SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003

Integrating Capacitor
The product of the integrating resistor and capacitor should be selected to give the maximum voltage swing
without causing the integrating amplifier output to saturate and get too close to the power supply voltages. When
the amplifier output is within 0.3 V of either supply, saturation occurs. With ± 5-V supplies and ANLG COMMON
connected to ground, the designer should design for a ± 3.5-V to ± 4-V integrating amplifier swing. A nominal
capacitor value is 0.47 µF. The equation for determining the value of the integrating capacitor (CINT) is:
10, 000 Clock Period I
C + INT
INT Integrator Output Voltage Swing
where
IINT is nominally 20 µA.

Capacitors with large tolerances and high dielectric absorption can induce conversion inaccuracies. A capacitor
that is too small could cause the integrating amplifier to saturate. High dielectric absorption causes the effective
capacitor value to be different during the signal integrate and deintegrate phases. Polypropylene capacitors
have very low dielectric absorption. Polystyrene and polycarbonate capacitors have higher dielectric
absorption, but also work well.
Auto-Zero and Reference Capacitor
Large capacitors tend to reduce noise in the system. Dielectric absorption is unimportant except during power
up or overload recovery. Typical values are 1 µF.
Reference Voltage
For high-accuracy absolute measurements, a high quality reference should be used.
Rollover Resistor and Diode
The ICL7135C and TLC7135C have a small rollover error; however, it can be corrected. The correction is to
connect the cathode of any silicon diode to INT OUT and the anode to a resistor. The other end of the resistor
is connected to ANLG COMMON or ground. For the recommended operating conditions, the resistor value is
100 kΩ. This value may be changed to correct any rollover error that has not been corrected. In many noncritical
applications the resistor and diode are not needed.
Maximum Clock Frequency
For most dual-slope A/D converters, the maximum conversion rate is limited by the frequency response of the
comparator. In this circuit, the comparator follows the integrator ramp with a 3-µs delay. Therefore, with a
160-kHz clock frequency (6-µs period), half of the first reference integrate clock period is lost in delay. Hence,
the meter reading changes from 0 to 1 with a 50-µV input, 1 to 2 with a 150-µV input, 2 to 3 with a 250-µV input,
etc. This transition at midpoint is desirable; however, when the clock frequency is increased appreciably above
160 kHz, the instrument flashes 1 on noise peaks even when the input is shorted. The above transition points
assume a 2-V input range is equivalent to 20,000 clock cycles.
When the input signal is always of one polarity, comparator delay need not be a limitation. Clock rates of 1 MHz
are possible since nonlinearity and noise do not increase substantially with frequency. For a fixed clock
frequency, the extra count or counts caused by comparator delay are a constant and can be subtracted out
digitally.
For signals with both polarities, the clock frequency can be extended above 160 kHz without error by using a
low value resistor in series with the integrating capacitor. This resistor causes the integrator to jump slightly
towards the zero-crossing level at the beginning of the deintegrate phase, and thus compensates for the
comparator delay. This series resistor should be 10 Ω to 50 Ω. This approach allows clock frequencies up to
480 kHz.

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SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003

Minimum Clock Frequency

The minimum clock frequency limitations result from capacitor leakage from the auto-zero and reference
capacitors. Measurement cycles as high as 10 µs are not influenced by leakage error.
Rejection of 50-Hz or 60-Hz Pickup
To maximize the rejection of 50-Hz or 60-Hz pickup, the clock frequency should be chosen so that an integral
multiple of 50-Hz or 60-Hz periods occur during the signal integrate phase. To achieve rejection of these signals,
some clock frequencies that can be used are:
50 Hz: 250, 166.66, 125, 100 kHz, etc.
60 Hz: 300, 200, 150, 120, 100, 40, 33.33 kHz, etc.
Zero-Crossing Flip-Flop
This flip-flop interrogates the comparator’s zero-crossing status. The interrogation is performed after the
previous clock cycle and the positive half of the ongoing clock cycle has occurred, so any comparator transients
that result from the clock pulses do not affect the detection of a zero-crossing. This procedure delays the
zero-crossing detection by one clock cycle. To eliminate the inaccuracy, which is caused by this delay, the
counter is disabled for one clock cycle at the beginning of the deintegrate phase. Therefore, when the
zero-crossing is detected one clock cycle later than the zero-crossing actually occurs, the correct number of
counts is displayed.
Noise
The peak-to-peak noise around zero is approximately 15 µV (peak-to-peak value not exceeded 95% of the
time). Near full scale, this value increases to approximately 30 µV. Much of the noise originates in the auto-zero
loop, and is proportional to the ratio of the input signal to the reference.
Analog and Digital Grounds
For high-accuracy applications, ground loops must be avoided. Return currents from digital circuits must not
be sent to the analog ground line.
Power Supplies
The ICL7135C and TLC7135C are designed to work with ± 5-V power supplies. However, 5-V operation is
possible when the input signal does not vary more than ± 1.5 V from midsupply.

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TLC7135CDW ACTIVE SOIC DW 28 20 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC7135C Samples

TLC7135CDWR ACTIVE SOIC DW 28 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC7135C Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC7135CDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC7135CDWR SOIC DW 28 1000 350.0 350.0 66.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TLC7135CDW DW SOIC 28 20 506.98 12.7 4826 6.6

Pack Materials-Page 3
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