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Datasheet 3
Datasheet 3
1FEATURES DESCRIPTION
•
2 Easy Interface to All Microprocessors The ADC0844 and ADC0848 are CMOS 8-bit
successive approximation A/D converters with
• Operates Ratiometrically or with 5 VDC Voltage versatile analog input multiplexers. The 4-channel or
Reference 8-channel multiplexers can be software configured for
• No Zero or Full-Scale Adjust Required single-ended, differential or pseudo-differential modes
• 4-Channel or 8-Channel Multiplexer with of operation.
Address Logic The differential mode provides low frequency input
• Internal Clock common mode rejection and allows offsetting the
• 0V to 5V Input Range with Single 5V Power analog range of the converter. In addition, the A/D's
reference can be adjusted enabling the conversion of
Supply
reduced analog ranges with 8-bit resolution.
• Standard Width 20-Pin or 24-Pin PDIP
The A/Ds are designed to operate from the control
• 28 Pin PLCC Package bus of a wide variety of microprocessors. TRI-STATE
output latches that directly drive the data bus permit
KEY SPECIFICATIONS the A/Ds to be configured as memory locations or I/O
• Resolution: 8 Bits devices to the microprocessor with no interface logic
necessary.
• Total Unadjusted Error: ±½ LSB and ± 1 LSB
• Single Supply: 5 VDC
• Low Power: 15 mW
• Conversion Time: 40 μs
Block Diagram
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADC0844, ADC0848
SNAS523D – JUNE 1999 – REVISED MARCH 2013 www.ti.com
Connection Diagram
Figure 1. PLCC Package (Top View) Figure 2. 20-Pin PDIP (Top View)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its specified operating conditions.
(2) All voltages are measured with respect to the ground pins.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(4) When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V−or VIN > V+) the absolute value of the current at that pin
should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply
boundaries with a 5 mA current limit to four.
(5) Human body model, 100 pF discharged through a 1.5 kΩ resistor.
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its specified operating conditions.
(2) All voltages are measured with respect to the ground pins.
(3) Product/package combination obsolete; shown for reference only.
Electrical Characteristics
The following specifications apply for VCC = 5 VDC unless otherwise specified. Boldface limits apply from TMIN to TMAX; all
other limits TA = Tj = 25°C.
ADC0844CCN,
ADC0848BCN,
ADC0844BCJ (1)
ADC0848CCN,
ADC0844CCJ (1) Limit
Parameter Conditions ADC0848BCV,
ADC0848CCV Units
Tested Design Tested Design
Typ (2) Typ (2)
Limit (3) Limit (4) Limit (3) Limit (4)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total
ADC0844BCN,
±½ ±½ LSB
ADC0848BCN, BCV
Unadjusted VREF = 5.00 VDC (5)
ADC0844CCN,
Error ±1 ±1 LSB
ADC0848CCN, CCV
ADC0844CCJ (1) ±1 LSB
Minimum Reference Input Resistance 2.4 1.1 2.4 1.2 1.1 kΩ
Maximum Reference Input Resistance 2.4 5.9 2.4 5.4 5.9 kΩ
VCC + VCC + VCC +
Maximum Common-Mode Input Voltage See (6) V
0.05 0.05 0.05
GND − GND − GND −
Minimum Common-Mode Input Voltage See (6) V
0.05 0.05 0.05
DC Common-Mode Error Differential Mode ±1/16 ±¼ ±1/16 ±¼ ±¼ LSB
Power Supply Sensitivity VCC = 5V±5% ±1/16 ±⅛ ±1/16 ±⅛ ±⅛ LSB
On Channel = 5V, Off
−1 −0.1 −1 μA
Channel = 0V (7)
Off Channel Leakage Current
On Channel = 0V, Off
1 0.1 1 μA
Channel = 5V
DIGITAL AND DC CHARACTERISTICS
VIN(1), Logical “1” Input Voltage (Min) VCC = 5.25V 2.0 2.0 2.0 V
VIN(0), Logical “0” Input Voltage (Max) VCC = 4.75V 0.8 0.8 0.8 V
IIN(1), Logical “1” Input Current (Max) VIN = 5.0V 0.005 1 0.005 1 μA
IIN(0), Logical “0” Input Current (Max) VIN = 0V −0.005 −1 −0.005 −1 μA
AC Electrical Characteristics
The following specifications apply for VCC = 5VDC, tr = tf = 10 ns unless otherwise specified. Boldface limits apply from TMIN
to TMAX; all other limits TA = Tj = 25°C.
Tested Design
Parameter Conditions Typ (1) Units
Limit (2) Limit (3)
tC, Maximum Conversion Time (See Figure 7) 30 40 60 μs
tW(WR), Minimum WR Pulse Width See (4) 50 150 ns
tACC, Maximum Access Time (Delay from Falling Edge of RD to
CL = 100 pF (4) 145 225 ns
Output Data Valid)
t1H, t0H, TRI-STATE Control (Maximum Delay from Rising Edge of
CL = 10 pF, RL = 10k (4) 125 200 ns
RD to Hi-Z State)
tWI, tRI, Maximum Delay from Falling Edge of WR or RD to Reset
200 400 ns
of INTR
See (4)
tDS, Minimum Data Set-Up Time 50 100 ns
tDH, Minimum Data Hold Time 0 50 ns
CIN, Capacitance of Logic Inputs 5 pF
COUT, Capacitance of Logic Outputs 5 pF
(1) Typical figures are at 25°C and represent most likely parametric norm.
(2) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
(3) Design limits are specified by not 100% tested. These limits are not used to calculate outgoing quality levels.
(4) The temperature coefficient is 0.3%/°C.
Figure 4. Figure 5.
Figure 6. Figure 7.
Figure 8. Figure 9.
Figure 10.
t1H t1H, CL = 10 pF
t0H t0H, CL = 10 pF
tr = 20 ns
Timing Diagrams
Read strobe must occur at least 600 ns after the assertion of interrupt to ensure reset of INTR .
MA stands for MUX address.
Figure 11. Using the Previously Selected Channel Configuration and Starting a Conversion
Functional Description
The ADC0844 and ADC0848 contain a 4-channel and 8-channel analog input multiplexer (MUX) respectively.
Each MUX can be configured into one of three modes of operation differential, pseudo-differential, and single
ended. These modes are discussed in Applications Information. The specific mode is selected by loading the
MUX address latch with the proper address (see Table 1 and Table 2). Inputs to the MUX address latch (MA0-
MA4) are common with data bus lines (DB0-DB4) and are enabled when the RD line is high. A conversion is
initiated via the CS and WR lines. If the data from a previous conversion is not read, the INTR line will be low.
The falling edge of WR will reset the INTR line high and ready the A/D for a conversion cycle. The rising edge of
WR, with RD high, strobes the data on the MA0/DB0-MA4/DB4 inputs into the MUX address latch to select a
new input configuration and start a conversion. If the RD line is held low during the entire low period of WR the
previous MUX configuration is retained, and the data of the previous conversion is the output on lines DB0-DB7.
After the conversion cycle (tC ≤ 40 μs), which is set by the internal clock frequency, the digital data is transferred
to the output latch and the INTR is asserted low. Taking CS and RD low resets INTR output high and outputs the
conversion result on the data lines (DB0-DB7).
APPLICATIONS INFORMATION
MULTIPLEXER CONFIGURATION
The design of these converters utilizes a sampled-data comparator structure which allows a differential analog
input to be converted by a successive approximation routine.
The actual voltage converted is always the difference between an assigned “+” input terminal and a “−” input
terminal. The polarity of each input terminal of the pair being converted indicates which line the converter expects
to be the most positive. If the assigned “+” input is less than the “−” input the converter responds with an all zeros
output code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels. The input channels
can be software configured into three modes: differential, single ended, or pseudo-differential. Figure 12 shows
the three modes using the 4-channel MUX ADC0844. The eight inputs of the ADC0848 can also be configured in
any of the three modes. In the differential mode, the ADC0844 channel inputs are grouped in pairs, CH1 with
CH2 and CH3 with CH4. The polarity assignment of each channel in the pair is interchangeable. The single-
ended mode has CH1–CH4 assigned as the positive input with the negative input being the analog ground
(AGND) of the device. Finally, in the pseudo-differential mode CH1–CH3 are positive inputs referenced to CH4
which is now a pseudo-ground. This pseudo-ground input can be set to any potential within the input common-
mode range of the converter. The analog signal conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flexibility. One converter package can now handle ground
referenced inputs and true differential inputs as well as signals with some arbitrary reference voltage.
The analog input voltages for each channel can range from 50 mV below ground to 50 mV above VCC (typically
5V) without degrading conversion accuracy.
3 Pseudo-Differential Combined
REFERENCE CONSIDERATIONS
The voltage applied to the reference input of these converters defines the voltage span of the analog input (the
difference between VIN(MAX) and VIN(MIN)) over which the 256 possible output codes apply. The devices can be
used in either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be
connected to a voltage source capable of driving the minimum reference input resistance of 1.1 kΩ. This pin is
the top of a resistor divider string used for the successive approximation conversion.
In a ratiometric system (Figure 13), the analog input voltage is proportional to the voltage used for the A/D
reference. This voltage is typically the system power supply, so the VREF pin can be tied to VCC. This technique
relaxes the stability requirements of the system reference as the analog input and A/D reference move together
maintaining the same output code for a given input condition. For absolute accuracy (Figure 14), where the
analog input varies between very specific voltage limits, the reference pin can be biased with a time and
temperature stable voltage source. The LM385 and LM336 reference diodes are good low current devices to use
with these converters.
The maximum value of the reference is limited to the VCC supply voltage. The minimum value, however, can be
quite small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing
less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and system
error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1
LSB equals VREF/256).
where
• fCM is the frequency of the common-mode signal
• Vpeak is its peak voltage value
• tC is the conversion time
For a 60 Hz common-mode signal to generate a ¼ LSB error (≈5 mV) with the converter running at 40 μS, its
peak value would have to be 5.43V. This large a common-mode signal is much greater than that generally found
in a well designed data acquisition system.
Input Current
Due to the sampling nature of the analog inputs, short duration spikes of current enter the “+” input and exit the
“−” input at the clock edges during the actual conversion. These currents decay rapidly and do not cause errors
as the internal comparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average
these currents and cause an effective DC current to flow through the output resistance of the analog signal
source. Bypass capacitors should not be used if the source resistance is greater than 1 kΩ.
OPTIONAL ADJUSTMENTS
Zero Error
The zero of the A/D does not require adjustment. If the minimum analog input voltage value, VIN(MIN), is not
ground, a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum
input voltage by biasing any VIN (−) input at this VIN(MIN) value. This is useful for either differential or pseudo-
differential modes of input channel configuration.
The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be
measured by grounding the V− input and applying a small magnitude positive voltage to the V+ input. Zero error
is the difference between actual DC input voltage which is necessary to just cause an output digital code
transition from 0000 0000 to 0000 0001 and the ideal ½ LSB value (½ LSB=9.8 mV for VREF=5.000 VDC).
Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1 ½ LSB down from the
desired analog full-scale voltage range and then adjusting the magnitude of the VREF input for a digital output
code changing from 1111 1110 to 1111 1111.
The full-scale adjustment should be made [with the proper VIN (−) voltage applied] by forcing a voltage to the VIN
(+) input which is given by:
where
• VMAX = the high end of the analog input range
• VMIN = the low end (the offset zero) of the analog range. (Both are ground referenced.) (1)
The VREF (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the
adjustment procedure.
For an example see the Zero-Shift and Span Adjust circuit below.
Figure 16. Differential Voltage Input 9-Bit A/D Figure 17. Span Adjust (0V ≤ VIN ≤ 3V)
Diodes are 1N914
DO = all 1s if VIN(+)>VIN(−)
DO = all 0s if VIN(+)<VIN(−)
Figure 18. Protecting the Input Figure 19. High Accuracy Comparators
* VIN(−)=0.15 VCC
15% of VCC≤VXDR≤85% of VCC
Note: DUT pin numbers in parentheses are for ADC0844, others are for ADC0848.
Sample Program for ADC0844 - INS8039 Interface Converting Two Ratiometric Differential Signals
ORG 0H
0000 04 10 JMP BEGIN ;START PROGRAM AT ADDR 10
ORG 10H ;MAIN PROGRAM
0010 B9 FF BEGIN: MOV R1,#0FFH ;LOAD R1 WITH AN UNUSED ADDR
;LOCATION
0012 B8 20 MOV R0,#20H ;A/D DATA ADDRESS
0014 89 FF ORL P1,#0FFH ;SET PORT 1 OUTPUTS HIGH
0016 23 00 MOV A,00H ;LOAD THE ACC WITH A/D MUX DATA
;CH1 AND CH2 DIFFERENTIAL
0018 14 50 CALL CONV ;CALL THE CONVERSION SUBROUTINE
001A 23 02 MOV A,#02H ;LOAD THE ACC WITH A/D MUX DATA
;CH3 AND CH4 DIFFERENTIAL
001C 18 INC R0 ;INCREMENT THE A/D DATA ADDRESS
001D 14 50 CALL CONV ;CALL THE CONVERSION SUBROUTINE
;CONVERSION SUBROUTINE
;ENTRY:ACC-A/D MUX DATA
;EXIT:ACC-CONVERTED DATA
ORG 50H
0050 99 FE CONV: ANL P1#0FEH ;CHIP SELECT THE A/D
0052 91 MOVX @R1,A ;LOAD A/D MUX & START CONVERSION
0053 09 LOOP: IN A,P1 ;INPUT INTR STATE
0054 32 53 JB1 LOOP ;IF INTR = 1 GOTO LOOP
0056 81 MOVX A,@R1 ;IF INTR = 0 INPUT A/D DATA
0057 89 01 ORL P1,&01H ;CLEAR THE A/D CHIP SELECT
0059 A0 MOV @R0,A ;STORE THE A/D DATA
005A 83 RET ;RETURN TO MAIN PROGRAM
END
Note: This routine sequentially programs the MUX data latch in the signal-ended mode. For CH1-CH8 a
conversion is started, then a 50 μs wait for the A/D to complete a conversion and the data is stored at address
ADDTA for CH1, ADDTA + 1 for CH2, etc.
REVISION HISTORY
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PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
NAM0024D
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MECHANICAL DATA
N0020A
NFH0020A
N20A (Rev G)
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MECHANICAL DATA
Seating Plane
0.004 (0,10)
0.032 (0,81)
0.026 (0,66)
4 18
D2 / E2
E E1
D2 / E2
8 14
NO. OF D/E D1 / E1 D2 / E2
PINS
** MIN MAX MIN MAX MIN MAX
20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29)
28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56)
44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10)
52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37)
68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005 / B 03/95
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
Mouser Electronics
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ADC0844CCN ADC0844CCN/NOPB ADC0848BCV ADC0848BCV/NOPB ADC0848BCVX ADC0848BCVX/NOPB
ADC0848CCN ADC0848CCN/NOPB ADC0848CCV ADC0848CCV/NOPB ADC0848CCVX ADC0848CCVX/NOPB