Features

• Low-voltage and Standard-voltage Operation

– 1.8v (VCC = 1.8V to 3.6V)
– 2.5v (VCC = 2.5V to 3.6V)
• Internally Organized 65,536 x 8
• Two-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (3.6V), 400 kHz (1.8V, 2.5V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
•
•
128-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Max)
Two-wire Serial
• High Reliability
– Endurance: 1,000,000 Write Cycles
EEPROM
– Data Retention: 40 Years
• Lead-free/Halogen-free Devices 512K (65,536 x 8)
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-ball dBGA2, and
8-lead Ultra Thin Small Array (SAP) Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Die
AT24C512B
with Three Device Address Inputs
Description
The AT24C512B provides 524,288 bits of serial electrically erasable and programma-
ble read only memory (EEPROM) organized as 65,536 words of 8 bits each. The
device’s cascadable feature allows up to eight devices to share a common two-wire Preliminary
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space-saving 8-pin PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP,
8-ball dBGA2 and 8-lead Ultra Thin SAP packages. In addition, the entire family is
available in a 1.8V (1.8V to 3.6V) version.

8-lead TSSOP 8-lead PDIP

Table 1. Pin Configurations
Pin Name Function A0 1 8 VCC A0 1 8 VCC
A1 2 7 WP A1 2 7 WP
A0–A2 Address Inputs A2 3 6 SCL A2 3 6 SCL
GND 4 5 SDA GND 4 5 SDA
SDA Serial Data
SCL Serial Clock Input 8-lead SOIC
WP Write Protect
A0 1 8 VCC
NC No Connect
A1 2 7 WP
A2 3 6 SCL
GND 4 5 SDA

8-ball dBGA2
8-lead Ultra Thin SAP
VCC 8 1 A0
VCC 8 1 A0
WP 7 2 A1
WP 7 2 A1
SCL 6 3 A2
SCL 6 3 A2
SDA 5 4 GND
SDA 5 4 GND

Bottom View Bottom View

Rev. 5112C–SEEPR–1/07

1
Absolute Maximum Ratings*
Operating Temperature..................................–55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature .....................................–65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground .................................... –1.0V to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage ............................................ 4.3V conditions for extended periods may affect
device reliability.
DC Output Current........................................................ 3.0 mA

Figure 1. Block Diagram

2 AT24C512B [Preliminary]
5112C–SEEPR–1/07
 AT24C512B [Preliminary]

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device
address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other
AT24Cxx devices. When the pins are hardwired, as many as eight 512K devices may be
addressed on a single bus system. (Device addressing is discussed in detail under
“Device Addressing,” page 8.) A device is selected when a corresponding hardware and
software match is true. If these pins are left floating, the A2, A1, and A0 pins will be
internally pulled down to GND. However, due to capacitive coupling that may appear
during customer applications, Atmel® recommends always connecting the address pins
to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-
mal write operations. When WP is connected directly to Vcc, all write operations to the
memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down
to GND. However, due to capacitive coupling that may appear during customer applica-
tions, Atmel recommends always connecting the WP pins to a known state. When using
a pull-up resistor, Atmel recommends using 10kΩ or less.

Memory Organization AT24C512B, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages
of 128-bytes each. Random word addressing requires a 16-bit data word address.

3
5112C–SEEPR–1/07
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from: TA = 25°C, f = 1.0 MHz, VCC = +1.8V to +3.6V
Symbol Test Condition Max Units Conditions
CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN Input Capacitance (A0, A1, SCL) 6 pF VIN = 0V
Note: 1. This parameter is characterized and is not 100% tested.

Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +3.6V (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 3.6 V
ICC1 Supply Current VCC = 3.6V READ at 400 kHz 1.0 2.0 mA
ICC2 Supply Current VCC = 3.6V WRITE at 400 kHz 2.0 3.0 mA

Standby Current VCC = 1.8V 1.0 µA

ISB1 VIN = VCC or VSS
(1.8V option) VCC = 3.6V 3.0 µA

Standby Current VCC = 2.5V 2.0 µA

ISB2 VIN = VCC or VSS
(2.5V option) VCC = 3.6V 3.0 µA
ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA
Output Leakage
ILO VOUT = VCC or VSS 0.05 3.0 µA
Current
VIL Input Low Level(1) −0.6 VCC x 0.3 V
VIH Input High Level(1) VCC x 0.7 VCC + 0.5 V
VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V
Note: 1. VIL min and VIH max are reference only and are not tested.

4 AT24C512B [Preliminary]
5112C–SEEPR–1/07
 AT24C512B [Preliminary]
Table 4. AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from TAI = −40°C to +85°C, VCC = +1.8V to +3.6V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
1.8-volt, 2.5-volt 3.6-volt
Symbol Parameter Min Max Min Max Units
fSCL Clock Frequency, SCL 400 1000 kHz
tLOW Clock Pulse Width Low 1.3 0.4 µs
tHIGH Clock Pulse Width High 0.6 0.4 µs
(1)
ti Noise Suppression Time 100 50 ns
tAA Clock Low to Data Out Valid 0.05 0.9 0.05 0.55 µs
Time the bus must be free before a
tBUF 1.3 0.5 µs
new transmission can start(1)
tHD.STA Start Hold Time 0.6 0.25 µs
tSU.STA Start Set-up Time 0.6 0.25 µs
tHD.DAT Data In Hold Time 0 0 µs
tSU.DAT Data In Set-up Time 100 100 ns
(1)
tR Inputs Rise Time 0.3 0.3 µs
(1)
tF Inputs Fall Time 300 100 ns
tSU.STO Stop Set-up Time 0.6 0.25 µs
tDH Data Out Hold Time 50 50 ns
tWR Write Cycle Time 5 5 ms
Write
Endurance(1) 25°C, Page Mode, 3.3V 1,000,000
Cycles
Notes: 1. This parameter is ensured by characterization.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 3.6V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 VCC

Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.

5
5112C–SEEPR–1/07
 STANDBY MODE: The AT24C512B features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.
Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire
part can be protocol reset by following these steps: (a) Create a start bit condition, (b)
clock 9 cycles, (c) create another start bit followed by stop bit condition as shown below.
The device is ready for next communication after above steps have been completed.

Figure 1. Protocol Reset Condition

Start bit Dummy Clock Cycles Start bit Stop bit

SCL 1 2 3 8 9

SDA

Note: The write cycle time twr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)

6 AT24C512B [Preliminary]
5112C–SEEPR–1/07
 AT24C512B [Preliminary]

Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)

SCL

SDA 8th BIT ACK

WORDn
(1)
twr
STOP START
CONDITION CONDITION

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

Figure 4. Data Validity

Figure 5. Start and Stop Definition

7
5112C–SEEPR–1/07
Figure 6. Output Acknowledge

Device Addressing
The 512K EEPROM requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see Figure 7 on page 9). The device
address word consists of a mandatory “1”, “0” sequence for the first four most significant
bits as shown. This is common to all two-wire EEPROM devices.
The 512K uses the three device address bits A2, A1, A0 to allow as many as eight
devices on the same bus. These bits must compare to their corresponding hardwired
input pins. The A2, A1 and A0 pins use an internal proprietary circuit that biases them to
a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is
not made, the device will return to a standby state.
DATA SECURITY: The AT24C512B has a hardware data protection scheme that allows
the user to Write Protect the whole memory when the WP pin is at VCC.

Write Operations BYTE WRITE: A write operation requires two 8-bit data word addresses following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a “0” and then clock in the first 8-bit data word. Following receipt
of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a
microcontroller, then must terminate the write sequence with a stop condition. At this
time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory.
All inputs are disabled during this write cycle and the EEPROM will not respond until the
write is complete (see Figure 8 on page 10).
PAGE WRITE: The 512K EEPROM is capable of 128-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not
send a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to 127
more data words. The EEPROM will respond with a “0” after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (see
Figure 9 on page 10).

8 AT24C512B [Preliminary]
5112C–SEEPR–1/07
 AT24C512B [Preliminary]

The data word address lower 7 bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than 128 data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten. The address roll over during write is from the
last byte of the current page to the first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The Read/Write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a “0”, allowing the read or write sequence to continue.

Read Operations
Read operations are initiated the same way as write operations with the exception that
the Read/Write select bit in the device address word is set to “1”. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by “1”. This
address stays valid between operations as long as the chip power is maintained. The
address roll over during read is from the last byte of the last memory page, to the first
byte of the first page.
Once the device address with the Read/Write select bit set to “1” is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input “0” but does generate a following
stop condition (see Figure 10 on page 10).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the Read/Write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a “0” but does generate a following stop condition (see Figure 11 on page 10).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will roll over and the sequential
read will continue. The sequential read operation is terminated when the microcontroller
does not respond with a “0” but does generate a following stop condition (see Figure 12
on page 10).

Figure 7. Device Address

1 0 1 0 A2 A1 A0 R/W

MSB LSB

9
5112C–SEEPR–1/07
Figure 8. Byte Write

Figure 9. Page Write

Figure 10. Current Address Read

Figure 11. Random Read

Figure 12. Sequential Read

10 AT24C512B [Preliminary]
5112C–SEEPR–1/07
 AT24C512B [Preliminary]

Ordering Information
Ordering Code Voltage Package Operation Range
AT24C512B-PU (Bulk form only) 1.8 8P3
AT24C512B-PU25 (Bulk form only) 2.5 8P3
AT24C512BN-SH-B(1) (NiPdAu Lead Finish) 1.8 8S1
AT24C512BN-SH-T(2) (NiPdAu Lead Finish) 1.8 8S1
(1)
AT24C512BN-SH25-B (NiPdAu Lead Finish) 2.5 8S1
(2)
AT24C512BN-SH25-T (NiPdAu Lead Finish) 2.5 8S1
AT24C512BW-SH-B(1) (NiPdAu Lead Finish) 1.8 8S2
(2)
AT24C512BW-SH-T (NiPdAu Lead Finish) 1.8 8S2 Lead-free/Halogen-free/
(1) Industrial Temperature
AT24C512BW-SH25-B (NiPdAu Lead Finish) 2.5 8S2
AT24C512BW-SH25-T(2) (NiPdAu Lead Finish) 2.5 8S2 (–40°C to 85°C)
AT24C512B-TH-B(1) (NiPdAu Lead Finish) 1.8 8A2
(2)
AT24C512B-TH-T (NiPdAu Lead Finish) 1.8 8A2
(1)
AT24C512B-TH25-B (NiPdAu Lead Finish) 2.5 8A2
(2)
AT24C512B-TH25-T (NiPdAu Lead Finish) 2.5 8A2
AT24C512BY7-YH-T(2) (NiPdAu Lead Finish) 1.8 8Y7
(2)
AT24C512BY7-YH25-T (NiPdAu Lead Finish) 2.5 8Y7
(2)
AT24C512BU4-UU-T (NiPdAu Lead Finish) 1.8 8U4-1
(3)
AT24C512B-W-11 1.8 Die Sale Industrial Temperature
(–40°C to 85°C)
Notes: 1. “-B” denotes bulk
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP and dBGA2 = 5K per reel. SAP = 3K per reel. EIAJ = 2K per reel.
3. Available in waffle pack, tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon
request. Please contact Serial EEPROM Marketing.

Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2 8-lead, 0.200” Wide Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8Y7 8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP)
8U4-1 8-ball, die Ball Grid Array Package (dBGA2)
Options
–1.8 Low-voltage (1.8V to 3.6V)
–2.5 Low-voltage (2.5V to 3.6V)

11
5112C–SEEPR–1/07
Packaging Information
8P3 – PDIP

1
E

E1

Top View c
eA

End View

COMMON DIMENSIONS
D (Unit of Measure = inches)
e
D1 SYMBOL MIN NOM MAX NOTE
A2 A
A – – 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
b2 L D1 0.005 – – 3
b3 E 0.300 0.310 0.325 4
4 PLCS b E1 0.240 0.250 0.280 3
e 0.100 BSC
Side View
eA 0.300 BSC 4
L 0.115 0.130 0.150 2

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE DRAWING NO. REV.
2325 Orchard Parkway 8P3, 8-lead, 0.300" Wide Body, Plastic Dual
8P3 B
R San Jose, CA 95131 In-line Package (PDIP)

12 AT24C512B [Preliminary]
5112C–SEEPR–1/07
 AT24C512B [Preliminary]

8S1 – JEDEC SOIC

E E1

N L

∅
Top View
End View
e B
COMMON DIMENSIONS
A
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1 A 1.35 – 1.75
A1 0.10 – 0.25
B 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.00
D
E1 3.81 – 3.99
E 5.79 – 6.20
Side View e 1.27 BSC
L 0.40 – 1.27
∅ 0° – 8°

Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

10/7/03
TITLE DRAWING NO. REV.
1150 E. Cheyenne Mtn. Blvd. 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Colorado Springs, CO 80906 8S1 B
R
Small Outline (JEDEC SOIC)

13
5112C–SEEPR–1/07
8S2 - EIAJ SOIC

E E1

L
N

TOP VIEW θ

END VIEW
e b COMMON DIMENSIONS
A (Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1 A 1.70 2.16
A1 0.05 0.25
b 0.35 0.48 5
C 0.15 0.35 5
D 5.13 5.35
D
E1 5.18 5.40 2, 3
E 7.70 8.26
L 0.51 0.85
SIDE VIEW θ 0˚ 8˚
e 1.27 BSC 4
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs aren't included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
4/7/06

TITLE DRAWING NO. REV.

2325 Orchard Parkway 8S2, 8-lead, 0.209" Body, Plastic Small 8S2 D
R San Jose, CA 95131 Outline Package (EIAJ)

14 AT24C512B [Preliminary]
5112C–SEEPR–1/07
 AT24C512B [Preliminary]

8A2 – TSSOP

3 2 1

Pin 1 indicator
this corner

E1 E

L1

N
L
Top View End View
COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A D 2.90 3.00 3.10 2, 5

b E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20

e A2 A2 0.80 1.00 1.05

b 0.19 – 0.30 4
D
e 0.65 BSC
Side View L 0.45 0.60 0.75
L1 1.00 REF

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02
TITLE DRAWING NO. REV.
2325 Orchard Parkway 8A2, 8-lead, 4.4 mm Body, Plastic
8A2 B
R San Jose, CA 95131 Thin Shrink Small Outline Package (TSSOP)

15
5112C–SEEPR–1/07
8U4-1 - dBGA2

D
A1 BALL PAD CORNER

5. b

A1
TOP VIEW
A2

A1 BALL PAD CORNER

A

2 1 SIDE VIEW

B
e
C

D
(e1)

(d1)

BOTTOM VIEW COMMON DIMENSIONS

8 SOLDER BALLS (Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.81 0.91 1.00
A1 0.15 0.20 0.25
A2 0.40 0.45 0.50
b 0.25 0.30 0.35
D 2.47 BSC
E 4.07 BSC
e 0.75 BSC
e1 0.74 REF
d 0.75 BSC
5. Dimension 'b' is measured at the maximum solder ball diameter.
d1 0.80 REF

This drawing is for general information only.

1/5/05
TITLE DRAWING NO. REV.
1150 E. Cheyenne Mtn. Blvd.
8U4-1, 8-ball, 2.47 x 4.07 mm Body, 0.75 mm pitch,
Colorado Springs, CO 80906 PO8U4-1 A
Small Die Ball Grid Array Package (dBGA2)
R

16 AT24C512B [Preliminary]
5112C–SEEPR–1/07
 AT24C512B [Preliminary]

8Y7 – UTSAP

PIN 1 INDEX AREA

A

PIN 1 ID

D1
D
E1

E A1
b e
e1
A
COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 0.60
A1 0.00 – 0.05
D 5.80 6.00 6.20
E 4.70 4.90 5.10
D1 3.30 3.40 3.50
E1 3.90 4.00 4.10
b 0.35 0.40 0.45
e 1.27 TYP
e1 3.81 REF
L 0.50 0.60 0.70

10/13/05
TITLE DRAWING NO. REV.
1150 E. Cheyenne Mtn. Blvd. 8Y7, 8-lead (6.00 x 4.90 mm Body) Ultra-Thin SOIC Array
Colorado Springs, CO 80906 8Y7 B
R
Package (UTSAP) Y7

17
5112C–SEEPR–1/07
Revision History

Doc. Rev. Date Comments

5112C 1/2007 Modify 8-ball dBGA2 drawing on page 1
Add lines between Ordering Information table on page 11
Remove AT24C512BU4-UU25-T offering from ordering information
Add 2.5V offering
Delete 2.7V offering
Add 8Y7 package drawing
Add dBGA2 package
Add AT24C512BU4-UU-T to page 1 and ordering information
Add 2.7V offering and 2.7V characteristics
5112B 7/2006 Pg 1
Remove Preliminary
Add Advance Information
Add EIAJ SOIC part number offering to Pg 1 and Pg 12
Add EIAJ pkg drawing
Changes to Ordering information, page 12; replaced 8Y4 package
with 8Y7 (UTSAP) package drawing
Page 1 - added ultra thin SAP to features and description
5112A 8/2005 Initial document release

18 AT24C512B [Preliminary]
5112C–SEEPR–1/07
 Atmel Corporation Atmel Operations
2325 Orchard Parkway Memory RF/Automotive
San Jose, CA 95131, USA 2325 Orchard Parkway Theresienstrasse 2
Tel: 1(408) 441-0311 San Jose, CA 95131, USA Postfach 3535
Fax: 1(408) 487-2600 Tel: 1(408) 441-0311 74025 Heilbronn, Germany
Fax: 1(408) 436-4314 Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
Regional Headquarters Microcontrollers
Europe 2325 Orchard Parkway 1150 East Cheyenne Mtn. Blvd.
Atmel Sarl San Jose, CA 95131, USA Colorado Springs, CO 80906, USA
Route des Arsenaux 41 Tel: 1(408) 441-0311 Tel: 1(719) 576-3300
Case Postale 80 Fax: 1(408) 436-4314 Fax: 1(719) 540-1759
CH-1705 Fribourg
Switzerland La Chantrerie Biometrics/Imaging/Hi-Rel MPU/
Tel: (41) 26-426-5555 BP 70602 High Speed Converters/RF Datacom
Fax: (41) 26-426-5500 44306 Nantes Cedex 3, France Avenue de Rochepleine
Tel: (33) 2-40-18-18-18 BP 123
Asia Fax: (33) 2-40-18-19-60 38521 Saint-Egreve Cedex, France
Room 1219 Tel: (33) 4-76-58-30-00
Chinachem Golden Plaza ASIC/ASSP/Smart Cards Fax: (33) 4-76-58-34-80
77 Mody Road Tsimshatsui Zone Industrielle
East Kowloon 13106 Rousset Cedex, France
Hong Kong Tel: (33) 4-42-53-60-00
Tel: (852) 2721-9778 Fax: (33) 4-42-53-60-01
Fax: (852) 2722-1369
1150 East Cheyenne Mtn. Blvd.
Japan Colorado Springs, CO 80906, USA
9F, Tonetsu Shinkawa Bldg. Tel: 1(719) 576-3300
1-24-8 Shinkawa Fax: 1(719) 540-1759
Chuo-ku, Tokyo 104-0033
Japan Scottish Enterprise Technology Park
Tel: (81) 3-3523-3551 Maxwell Building
Fax: (81) 3-3523-7581 East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743

Literature Requests
www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.

©2007 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are ® and others, are registered trade-
marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

Printed on recycled paper.

5112C–SEEPR–1/07