Three-Wire Serial Eeprom: Features
Three-Wire Serial Eeprom: Features
Three-Wire Serial Eeprom: Features
Description
The AT93C86A provides 16384 bits of serial electrically erasable programmable read
AT93C86A
only memory (EEPROM), organized as 1024 words of 16 bits each when the ORG pin
is connected to VCC and 2048 words of eight bits each when it is tied to ground. The
device is optimized for use in many industrial and commercial applications where low-
power and low-voltage operations are essential. The AT93C86A is available in space
Preliminary
saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead mini-MAP (MLP 2x3) , and 8-lead
TSSOP packages.
8-lead PDIP
CS 1 8 VCC
Table 1. Pin Configurations SK 2 7 DC
Pin Name Function DI 3 6 ORG
DO 4 5 GND
CS Chip Select
SK Serial Data Clock 8-lead SOIC
DI Serial Data Input
CS 1 8 VCC
DO Serial Data Output SK 2 7 DC
DI 3 6 ORG
GND Ground DO 4 5 GND
VCC 8 1 CS
DC 7 2 SK
ORG 6 3 DI
GND 5 4 DO
Bottom View
Rev. 3408F–SEEPR–11/05
1
The AT93C86A is enabled through the Chip Select pin (CS), and accessed via a three-
wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a Read instruction at DI, the address is decoded and the data is
clocked out serially on the data output pin DO. The Write cycle is completely self-timed
and no separate Erase cycle is required before Write. The Write cycle is only enabled
when the part is in the Erase/Write Enable state. When CS is brought “high” following
the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part. The
AT93C86A is available in a 2.7V to 5.5V version.
MEMORY ARRAY
ADDRESS
ORG 2048 x 8 DECODER
OR
1024 x 16
DATA
REGISTER
DI OUTPUT
BUFFER
MODE
DECODE
CS LOGIC
CLOCK DO
SK GENERATOR
Note: When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organization
is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1
Meg ohm pullup, then the x 16 organization is selected. This feature is not available on the 1.8V devices.
2 AT93C86A [Preliminary]
3408F–SEEPR–11/05
AT93C86A [Preliminary]
Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V,
TAE = −40°C to +125°C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Unit
VCC1 Supply Voltage 1.8 5.5 V
VCC2 Supply Voltage 2.7 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
READ at 1.0 MHz 0.5 2.0 mA
ICC Supply Current VCC = 5.0V
WRITE at 1.0 MHz 0.5 2.0 mA
ISB1 Standby Current VCC = 1.8V CS = 0V 0 0.1 µA
ISB2 Standby Current VCC = 2.7V CS = 0V 6.0 10.0 µA
ISB3 Standby Current VCC = 5.0V CS = 0V 17 30 µA
IIL Input Leakage VIN = 0V to VCC 0.1 3.0 µA
IOL Output Leakage VIN = 0V to VCC 0.1 3.0 µA
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Table 4. AC Characteristics
Applicable over recommended operating range from TAI = −40°C to + 85°C, TAE = −40°C to +125°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
4.5V ≤ VCC ≤ 5.5V 0 2
SK Clock
fSK 2.7V ≤ VCC ≤ 5.5V 0 1 MHz
Frequency
1.8V ≤ VCC ≤ 5.5V 0 0.25
10 ms
tWP Write Cycle Time
4.5V ≤ VCC ≤ 5.5V 0.1 4 ms
(1)
Endurance 5.0V, 25°C, Page Mode 1M Write Cycles
Note: 1. This parameter is characterized and is not 100% tested.
4 AT93C86A [Preliminary]
3408F–SEEPR–11/05
AT93C86A [Preliminary]
Functional The AT93C86A is accessed via a simple and versatile three-wire serial communication
interface. Device operation is controlled by seven instructions issued by the host pro-
Description
cessor. A valid instruction starts with a rising edge of CS and consists of a Start Bit
(logic “1”) followed by the appropriate Op Code and the desired memory address
location.
READ (READ): The Read (READ) instruction contains the address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C86A sup-
ports sequential read operations. The device will automatically increment the internal
address pointer and clock out the next memory location as long as CS is held high. In
this case, the dummy bit (logic “0”) will not be clocked out between memory locations,
thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the EWEN state, programming remains enabled
until an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the Ready/Busy sta-
tus of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A
logic “1” at pin DO indicates that the selected memory location has been erased, and the
part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle tWP starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of
250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1”
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3408F–SEEPR–11/05
indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
Ready/Busy status cannot be obtained if the CS is brought high after the end of the self-
timed programming cycle tWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
The WRAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturbance, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the READ instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
6 AT93C86A [Preliminary]
3408F–SEEPR–11/05
AT93C86A [Preliminary]
Timing Diagrams
Figure 2. Synchronous Data Timing
7
3408F–SEEPR–11/05
Figure 4. EWEN Timing
tCS
CS
SK
DI 1 0 0 1 1 ...
tCS
CS
SK
DI 1 0 0 0 0 ...
tCS
CS
SK
DI 1 0 1 AN ... A0 DN ... D0
HIGH IMPEDANCE
DO BUSY READY
tWP
8 AT93C86A [Preliminary]
3408F–SEEPR–11/05
AT93C86A [Preliminary]
tCS
CS
SK
DI 1 0 0 0 1 ... DN ... D0
BUSY
HIGH IMPEDANCE
DO READY
tWP
tCS
CS CHECK STANDBY
STATUS
SK
tSV tDF
tWP
9
3408F–SEEPR–11/05
Figure 9. ERAL Timing(1)
10 AT93C86A [Preliminary]
3408F–SEEPR–11/05
AT93C86A [Preliminary]
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8Y6 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)
Options
−2.7 Low Voltage (2.7V to 5.5V)
−1.8 Low Voltage (1.8V to 5.5V)
11
3408F–SEEPR–11/05
Packaging Information
8P3 – PDIP
1
E
E1
Top View c
eA
End View
COMMON DIMENSIONS
D (Unit of Measure = inches)
e
D1 SYMBOL MIN NOM MAX NOTE
A2 A
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
b2 L D1 0.005 3
b3 E 0.300 0.310 0.325 4
4 PLCS b E1 0.240 0.250 0.280 3
e 0.100 BSC
Side View
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE DRAWING NO. REV.
2325 Orchard Parkway 8P3, 8-lead, 0.300" Wide Body, Plastic Dual
8P3 B
R San Jose, CA 95131 In-line Package (PDIP)
12 AT93C86A [Preliminary]
3408F–SEEPR–11/05
AT93C86A [Preliminary]
A D2 b
(8X)
Pin 1
Index
Area
E2
E
Pin 1 ID
L (8X)
D
e (6X)
A2 A1
1.50 REF.
A3
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
8/26/05
TITLE DRAWING NO. REV.
2325 Orchard Parkway
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, 8Y6 C
R San Jose, CA 95131 Dual No Lead Package (DFN) ,(MLP 2x3)
13
3408F–SEEPR–11/05
8S1 – JEDEC SOIC
E E1
N L
∅
Top View
End View
e B
COMMON DIMENSIONS
A
(Unit of Measure = mm)
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
TITLE DRAWING NO. REV.
1150 E. Cheyenne Mtn. Blvd. 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Colorado Springs, CO 80906 8S1 B
R
Small Outline (JEDEC SOIC)
14 AT93C86A [Preliminary]
3408F–SEEPR–11/05
AT93C86A [Preliminary]
8A2 – TSSOP
3 2 1
Pin 1 indicator
this corner
E1 E
L1
N
L
Top View End View
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02
TITLE DRAWING NO. REV.
2325 Orchard Parkway 8A2, 8-lead, 4.4 mm Body, Plastic
8A2 B
R San Jose, CA 95131 Thin Shrink Small Outline Package (TSSOP)
15
3408F–SEEPR–11/05
8Y1 - MAP
1 2 3 4
E1
D D1
8 7 6 5
A1 b e
E
2/28/03
TITLE DRAWING NO. REV.
2325 Orchard Parkway 8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
San Jose, CA 95131 8Y1 C
R
(MAP) Y1
16 AT93C86A [Preliminary]
3408F–SEEPR–11/05
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3408F–SEEPR–11/05