DATASHEET

CA5260, CA5260A FN1929

3MHz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Rev 8.00
Output August 3, 2010

The CA5260A and CA5260 are integrated-circuit operational Features

amplifiers that combine the advantage of both CMOS and
bipolar transistors on a monolithic chip. The CA5260 series • MOSFET Input Stage provides
circuits are dual versions of the popular CA5160 series. - Very High ZI . . . . . . . . . . . . . 1.5T (1.5 x 1012) (Typ)
They are designed and guaranteed to operate in - Very Low II . . . . . . . . . . . . . 5pA (Typ) at 15V Operation
microprocessor or logic systems that use +5V supplies. 2pA (Typ) at 5V Operation
• Ideal for Single Supply Applications
Gate-protected P-Channel MOSFET (PMOS) transistors are
• Common Mode Input Voltage Range Includes 
used in the input circuit to provide very-high-input
Negative Supply Rail; Input Terminals Can be 
impedance, very-low-input current, and exceptional speed
Swung 0.5V Below Negative Supply Rail
performance. The use of PMOS field-effect transistors in the
input stage results in common-mode input-voltage capability • CMOS Output Stage Permits Signal Swing to Either (or
down to 0.5V below the negative-supply terminal, an Both) Supply Rails
important attribute in single-supply applications. • CA5260A, CA5260 Have Full Military Temperature Range
Guaranteed Specifications for V+ = 5V
A complementary-symmetry MOS (CMOS) transistor-pair,
capable of swinging the output voltage to within 10mV of • CA5260A, CA5260 are Guaranteed to Operate Down to
either supply-voltage terminal (at very high values of load 4.5V for AOL
impedance), is employed as the output circuit. • Fully Guaranteed to Operate from -55°C to +125°C at
The CA5260 Series circuits operate at supply voltages V+ = 5V, V- = GND
ranging from 4.5V to 16V, or ±2.25V to ±8V when using split • Pb-Free Available (RoHS Compliant)
supplies.

The CA5260, CA5260A have guaranteed specifications for

Applications
5V operation over the full military temperature range of • Ground Referenced Single Supply Amplifiers
-55°C to +125°C.
• Fast Sample-Hold Amplifiers
Pinout • Long Duration Timers/Monostables
CA5260, CA5260A • Ideal Interface with Digital CMOS
(8 LD SOIC)
TOP VIEW • High Input Impedance Wideband Amplifiers
• Voltage Followers (e.g., Follower for Single Supply D/A
OUTPUT (A) 1 8 V+ Converter)
A
• Voltage Regulators (Permits Control of Output Voltage
INV. INPUT (A) 2 7 OUTPUT (B)
- + Down to 0V)
B
NON INV. INPUT (A) 3
+ -
6 INV. INPUT (B) • Wien Bridge Oscillators

V- 4 5 NON INV. INPUT (B) • Voltage Controlled Oscillators

• Photo Diode Sensor Amplifiers
• 5V Logic Systems
• Microprocessor Interface

FN1929 Rev 8.00 Page 1 of 7

August 3, 2010
CA5260, CA5260A

Ordering Information
PART NUMBER PART TEMP. RANGE PACKAGE PKG.
(Note 3) MARKING (°C) (Pb-Free) DWG. #

CA5260AM96 (Note 1) 5260A -55 to +125 8 Ld SOIC (Tape and Reel) M8.15
CA5260MZ96 (Note 2) CA5260 MZ -55 to +125 8 Ld SOIC M8.15

CA5260M (Notes 1) 5260 -55 to +125 8 Ld SOIC (Tape and Reel) M8.15

CA5260MZ (Note 2) CA5260 MZ -55 to +125 8 Ld SOIC M8.15

NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for CA5260, CA5260A. For more information on MSL please see
techbrief TB363.

FN1929 Rev 8.00 Page 2 of 7

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CA5260, CA5260A

Absolute Maximum Ratings Thermal Information

Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . 16V Thermal Resistance (Typical, Note 5) JA (°C/W)
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . 175°C
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Maximum Junction Temperature (Plastic Package) . . . . . . +150°C
Output Short Circuit Duration (Note 4). . . . . . . . . . . . . . . . Indefinite Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.

NOTES:
4. Short circuit may be applied to ground or to either supply.
5. JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, TA = +25°C, Unless Otherwise Specified
TYPICAL VALUES

PARAMETER SYMBOL TEST CONDITIONS CA5260 CA5260A UNITS

Input Resistance RI 1.5 1.5 T

Input Capacitance CI f = 1MHz 4.3 4.3 pF

Unity Gain Crossover Frequency fT 3 3 MHz

Slew Rate SR VOUT = 2.5VP-P 5 5 V/µs

Transient Response CL = 25pF, RL = 2k

Rise Time tr (Voltage Follower) 0.09 0.09 µs

Overshoot OS 10 10 %

Settling Time (To <0.1%, VIN = 4VP-P) tS CL = 25pF, RL = 2k 1.8 1.8 µs
(Voltage Follower)

Electrical Specifications TA = +25°C, V+ = 5V, V- = 0V

CA5260 CA5260A
TEST
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Input Offset Voltage VIO VO = 2.5V - 2 15 - 1.5 4 mV

Input Offset Current IIO VO = 2.5V - 1 10 - 1 10 pA

Input Current II VO = 2.5V - 2 15 - 2 15 pA

Common Mode Rejection CMRR VCM = 0V to 1V 70 85 - 74 85 - dB
Ratio
VCM = 0V to 2.5V 50 55 - 50 55 - dB

Common Mode Input VlCR+ 2.5 3 - 2.5 3 - V

Voltage Range
VlCR- - -0.5 0 - -0.5 0 V

Power Supply Rejection PSRR V+ = 1V; V- = 1V 70 84 - 75 84 - dB

Ratio
Large Signal Voltage Gain AOL RL = , VO = 0.5V to 4V - 111 - - 113 - dB
(Note 6)
RL = 10k,  80 86 - 83 86 - dB
VO = 0.5V to 3.6V
Source Current ISOURCE VO = 0V 1.75 2.2 - 1.75 2.2 - mA

Sink Current ISINK VO = 5V 1.70 2 - 1.70 2 - mA

FN1929 Rev 8.00 Page 3 of 7

August 3, 2010
CA5260, CA5260A

Electrical Specifications TA = +25°C, V+ = 5V, V- = 0V (Continued)

CA5260 CA5260A
TEST
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Output Voltage VOM+ RL =  4.99 5 - 4.99 5 - V

VOM- - 0 0.01 - 0 0.01 V

VOM+ RL = 10k 4.4 4.7 - 4.4 4.7 - V

VOM- - 0 0.01 - 0 0.01 V

VOM+ RL = 2k 3 3.4 - 3 3.4 - V

VOM- - 0 0.01 - 0 0.01 V

Supply Current ISUPPLY VO = 0V - 1.60 2.0 - 1.60 2.0 mA

VO = 2.5V - 1.80 2.25 - 1.80 2.25 mA

NOTE:
6. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10k

Electrical Specifications TA = -55°C to +125°C, V+ = 5V, V- = 0V

CA5260 CA5260A
TEST MIN MAX MIN MAX
PARAMETER SYMBOL CONDITIONS (Note 8) TYP (Note 8) (Note 8) TYP (Note 8) UNITS
Input Offset Voltage VIO VO = 2.5V - 3 20 - 2 15 mV
Input Offset Current IIO VO = 2.5V - 1 10 - 1 10 nA
Input Current II VO = 2.5V - 2 15 - 2 15 nA
Common Mode Rejection Ratio CMRR VCM = 0 to 1V 60 78 - 65 78 - dB
VCM = 0 to 2.5V 50 60 - 50 60 - dB
Common Mode Input Voltage VlCR+ 2.5 3 - 2.5 3 - V
Range
VlCR- - -0.5 0 - -0.5 0 V
Power Supply Rejection Ratio PSRR V+ = 1V;  60 65 - 62 65 - dB
V- = 1V
Large Signal Voltage Gain (Note 7) AOL RL = , 70 78 - 70 78 - dB
VO = 0.5 to 4V
RL = 10k,  60 65 - 60 65 - dB
VO = 0.5 to 3.6V
Source Current ISOURCE VO = 0V 1.3 1.6 - 1.3 1.6 - mA
Sink Current ISINK VO = 5V 1.2 1.4 - 1.2 1.4 - mA
Output Voltage VOM+ RL =  4.99 5 - 4.99 5 - V
VOM- - 0 0.01 - 0 0.01 V
VOM+ RL = 10k 4.2 4.4 - 4.2 4.4 - V
VOM- - 0 0.01 - 0 0.01 V
VOM+ RL = 2k 2.5 2.7 - 2.5 2.7 - V
VOM- - 0 0.01 - 0 0.01 V
Supply Current ISUPPLY VO = 0V - 1.65 2.2 - 1.65 2.2 mA
VO = 2.5V - 1.95 2.35 - 1.95 2.35 mA
NOTES:
7. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10k
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.

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 CA5260, CA5260A

Electrical Specifications Each Amplifier at TA = +25°C, V+ = 15V, V- = 0V, Unless Otherwise Specified

CA5260 CA5260A
TEST
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Input Offset Voltage VIO VS = 7.5 - 6 15 - 2 5 mV

Input Offset Current IIO VS = 7.5 - 0.5 30 - 0.5 20 pA

Input Current II VS = 7.5 - 5 50 - 5 30 pA

Large Signal Voltage Gain AOL VO = 10VP-P, 40 320 - 40 320 - kV/V

RL = 10k
92 110 - 92 110 - dB

Common Mode Rejection Ratio CMRR 70 90 - 80 95 - dB

Common Mode Input Voltage VlCR 10 -0.5 to 12 0 10 -0.5 to 12 0 V
Range

Power Supply Rejection Ratio, PSRR VS = 7.5 - 32 320 - 32 150 µV/V

VIO/ V

Maximum Output Voltage VOM+ RL = 10k 11 13.3 - 11 13.3 - V

VOM- - 0.002 0.01 - 0.002 0.01 V

VOM+ RL =  14.99 15 - 14.99 15 - V

VOM- - 0 0.01 - 0 0.01 V

Maximum Output Current IOM+ VO = 7.5V 12 22 45 12 22 45 mA

(Source)

IOM- (Sink) 12 20 45 12 20 45 mA

Total Supply Current, RL =  I+ VO (Amp A) = 7.5V - 9 16.5 - 9 16.5 mA

VO (Amp B) = 7.5V
VO (Amp A) = 0V - 1.2 4 - 1.2 4 mA
VO (Amp B) = 0V

VO (Amp A) = 0V VO - 5 9.5 - 5 9.5 mA

(Amp B) = 7.5V

Input Offset Voltage VIO/T - 8 - - 6 - µV/oC

Temperature Drift
Crosstalk f = 1kHz - 120 - - 120 - dB

FN1929 Rev 8.00 Page 5 of 7

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CA5260, CA5260A

Schematic Diagram
V+
8

AMPLIFIER A AMPLIFIER B

Q6 Q7 Q21 Q20
Q11 Q10 Q9 Q23 Q25

D2 D3 D6 D7 Q24

D1 D4 D5 D8
R5 R12
2k 2k
Q1 Q2 Q8 Q22 Q16
Q12 C1 C2 Q15 Q26
R4 30pF 30pF R11
Q14 Q13 R3 1k 1k R10 Q27 Q28
1k Q5 Q19 1k C4 R13
R6
200k C3 200k
R7 Q3 Q4 Q18 Q17 R14
300k 300
R1 R2 R9 R8
1k 1k 1k 1k

3 2 1 7 6 5 4
+IN -IN OUT -IN +IN V-

FN1929 Rev 8.00 Page 6 of 7

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 CA5260, CA5260A

Small Outline Plastic Packages (SOIC)

N
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA H 0.25(0.010) M B M
INCHES MILLIMETERS
E
SYMBOL MIN MAX MIN MAX NOTES
-B-
A 0.0532 0.0688 1.35 1.75 -

1 2 3 A1 0.0040 0.0098 0.10 0.25 -

L
B 0.013 0.020 0.33 0.51 9
SEATING PLANE C 0.0075 0.0098 0.19 0.25 -
-A-
A h x 45°
D 0.1890 0.1968 4.80 5.00 3
D
E 0.1497 0.1574 3.80 4.00 4
-C- e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -
e A1
C h 0.0099 0.0196 0.25 0.50 5
B 0.10(0.004)
L 0.016 0.050 0.40 1.27 6
0.25(0.010) M C A M B S
N 8 8 7
NOTES:  0° 8° 0° 8° -
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Rev. 1 6/05
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

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FN1929 Rev 8.00 Page 7 of 7

August 3, 2010