Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Low Input Current High Gain Split Darlington Optocouplers

Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Low Input Current High Gain Split Darlington Optocouplers
July 2005
Single-Channel: 6N138, 6N139

Dual-Channel: HCPL-2730, HCPL-2731
Low Input Current High Gain Split
Darlington Optocouplers
Features Description
■ Low current - 0.5 mA The 6N138/9 and HCPL-2730/HCPL-2731 optocouplers consist
■ Superior CTR-2000% of an AlGaAs LED optically coupled to a high gain split darling-
ton photodetector.
■ Superior CMR-10 kV/µs
■ CTR guaranteed 0-70°C The split darlington configuration separating the input photo-
■ U.L. recognized (File # E90700) diode and the first stage gain from the output transistor permits
lower output saturation voltage and higher speed operation than
■ VDE recognized (File # 120915) Ordering option
possible with conventional darlington phototransistor optocou-
V, e.g., 6N138V
pler. In the dual channel devices, HCPL-2730/HCPL2731, an
■ Dual Channel - HCPL-2730 integrated emitter - base resistor provides superior stability over
■ HCPL-2731 temperature.
The combination of a very low input current of 0.5 mA and a
Applications high current transfer ratio of 2000% makes this family particu-
■ Digital logic ground isolation larly useful for input interface to MOS, CMOS, LSTTL and EIA
■ Telephone ring detector RS232C, while output compatibility is ensured to CMOS as well
as high fan-out TTL requirements. An internal noise shield pro-
■ EIA-RS-232C line receiver
vides exceptional common mode rejection of 10 kV/µs.
■ High common mode noise line receiver
■ µP bus isolation
■ Current loop receiver
Package Schematic
N/C 1 8 VCC + 1 8 VCC
V
F1
8
+ 2 7 VB _ 2 7 V01
1 VF
_ _
3 6 VO 3 6 V02
VF2
N/C 4 5 GND + 4 5 GND
8
8 6N138 / 6N139 HCPL-2730 / HCPL-2731
1
1
©2005 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com

Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Rev. 1.0.0
Absolute Maximum Ratings (TA = 25°C unless otherwise specified)
Parameter Symbol Value Units
Storage Temperature TSTG -55 to +125 °C
Operating Temperature TOPR -40 to +85 °C
Lead Solder Temperature (Wave solder only. See recommended reflow profile graph for TSOL 260 for 10 sec °C
SMD mounting)
EMITTER
DC/Average Forward Input Current Each Channel IF (avg) 20 mA
Peak Forward Input Current (50% duty cycle, 1 ms P.W.) Each Channel IF (pk) 40 mA
Peak Transient Input Current - (≤1 µs P.W., 300 pps) IF (trans) 1.0 A
Reverse Input Voltage Each Channel VR 5 V
Input Power Dissipation Each Channel PD 35 mW
DETECTOR
Average Output Current Each Channel IO (avg) 60 mA
Emitter-Base Reverse Voltage (6N138 and 6N139) VER 0.5 V
Supply Voltage, Output Voltage (6N138, HCPL-2730) VCC, VO -0.5 to 7 V
(6N139, HCPL-2731) -0.5 to 18
Output Power Dissipation Each Channel PO 100 mW
Electrical Characteristics (TA = 0 to 70°C Unless otherwise specified)

Individual Component Characteristics
Parameter Test Conditions Symbol Device Min Typ** Max Unit
EMITTER TA =25°C VF All 1.30 1.7 V
Input Forward Voltage Each channel (IF = 1.6 mA) 1.75
Input Reverse Breakdown Voltage (TA = 25°C, IR = 10 µA) BVR All 5.0 20 V
Each Channel
Temperature coefficient of forward voltage (IF = 1.6 mA) (∆VF/∆TA) All -1.8 mV/°C
DETECTOR
Logic high output current (IF = 0 mA, VO = VCC = 18 V) IOH 6N139 0.01 100 µA
Each Channel HCPL-2731
(IF = 0 mA, VO = VCC = 7 V) 6N138 0.01 250
Logic low supply (IF = 1.6 mA, VO = Open) ICCL 6N138 0.4 1.5 mA
(VCC = 18 V) 6N139
(IF1 = IF2 = 1.6 mA, VCC = 18 V) HCPL-2731 1.3 3
(VO1 - VO2 = Open, VCC = 7 V HCPL-2730
Logic high supply (IF = 0 mA, VO = Open, ICCH 6N135 0.05 10 µA
VCC = 18 V) 6N136
(IF1 = IF2 = 0 mA, VCC = 18 V) HCPL-2731 0.10 20
(VO1 - VO2 = Open, VCC = 7 V HCPL-2730
** All Typicals at TA = 25°C
2 www.fairchildsemi.com
Transfer Characteristics (TA = 0 to 70°C Unless otherwise specified)
COUPLED (IF = 0.5 mA, VO = 0.4 V, VCC = 4.5 V) CTR 6N139 400 1100 %
Current transfer ratio Each Channel HCPL-2731 3500
(Note 1, 2) (IF = 1.6 mA, VO = 0.4 V, VCC = 4.5 V) 6N139 500 1300 %
Each Channel HCPL-2731 2500
(IF = 1.6 mA, VO = 0.4 V, VCC = 4.5 V) 6N138 300 1300 %
Logic low output voltage (IF = 0.5 mA, IO = 2 mA, VCC = 4.5 V) VOL 6N139 0.08 0.4 V
output voltage (Note 2) (IF = 1.6 mA, IO = 8 mA, VCC = 4.5 V) 6N139 0.01 0.4
(IF = 0.5 mA, IO = 15 mA, VCC = 4.5 V) 6N139 0.13 0.4
(IF = 12 mA, IO = 24 mA, VCC = 4.5 V) 6N139 0.20 0.4
(IF = 1.6 mA, IO = 4.8 mA, VCC = 4.5 V) 6N138 0.10 0.4
Switching Characteristics (TA = 0 to 70°C unless otherwise specified., VCC = 5 V)
Propagation delay (RL = 4.7 kΩ, IF = 0.5 mA) TPHL 6N139 30 µs
time to logic low TA = 25°C 4 25
(Note 2) (Fig. 22)
(RL = 4.7 kΩ, IF = 0.5 mA) HCPL-2731 120
Each Channel TA = 25°C 3 100
(RL = 270 Ω, IF = 12 mA) 6N139 2
TA = 25°C 0.2 1
(RL = 270 Ω, IF = 12 mA) HCPL-2730 3
Each Channel TA = 25°C HCPL-2731 0.3 2
(RL = 2.2 kΩ, IF = 1.6 mA) 6N138 15
TA = 25°C 1.5 10
(RL = 2.2 kΩ, IF = 1.6 mA) HCPL-2731 25
HCPL-2730
Each Channel TA = 25°C 1 20
Propagation delay (RL = 4.7 kΩ, IF = 0.5 mA) TPLH 6N139 90 µs
time to logic high Each Channel HCPL-2731
(Note 2) (Fig. 22)
(RL = 4.7 kΩ, IF = 0.5 mA) TA = 25°C 6N139 12 60
(RL = 270 Ω, IF = 12 mA) 6N139 10
TA = 25°C 1.3 7
(RL = 270 Ω, IF = 12 mA) Each Channel HCPL-2730 15
HCPL-2731
TA = 25°C 5 10
(RL = 2.2 kΩ, IF = 1.6 mA) 6N138 50
Each Channel HCPL-2730/1
(RL = 2.2 kΩ, IF = 1.6 mA) TA = 25°C 6N138 7 35
Each Channel HCPL-2730/1 16
Common mode (IF = 0 mA, |VCM| = 10 VP-P) |CMH| 6N138 1,000 10,000 V/µs
transient immunity TA = 25°C, (RL = 2.2 kΩ) (Note 3) (Fig. 23) 6N139
at logic high Each Channel HCPL-2730
HCPL-2731
Common mode (IF = 1.6 mA, |VCM| = 10 VP-P, RL = 2.2 kΩ) |CML| 6N138 1,000 10,000 V/µs
transient immunity TA = 25°C, (Note 3) (Fig. 23) 6N139
at logic low Each Channel HCPL-2730
HCPL-2731
Isolation Characteristics (TA = 0 to 70°C Unless otherwise specified)
Characteristics Test Conditions Symbol Min Typ** Max Unit
Input-output (Relative humidity = 45%) II-O 1.0 µA
insulation leakage current (TA = 25°C, t = 5 s)
(VI-O = 3000 VDC)
(Note 8)
Withstand insulation test voltage (RH ≤ 50%, TA = 25°C) VISO 2500 VRMS
(Note 4) ( t = 1 min.)
Resistance (input to output) (Note 4) (VI-O = 500 VDC) RI-O 1012 Ω
Capacitance (input to output) (Note 4, 5) (f = 1 MHz) CI-O 0.6 pF
Input-Input (RH ≤ 45%, VI-I = 500 VDC) (Note 6) II-I 0.005 µA
Insulation leakage current t = 5 s, (HCPL-2730/2731 only)
Input-Input Resistance (VI-I = 500 VDC) (Note 6) RI-I 1011 Ω
(HCPL-2730/2731 only)
Input-Input Capacitance (f = 1 MHz) (Note 6) CI-I 0.03 pF
(HCPL-2730/2731 only)
Notes
1. Current Transfer Ratio is defined as a ratio of output collector current, IO, to the forward LED input current, IF, times 100%.
2. Pin 7 open. (6N138 and 6N139 only)
3. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge of the com-
mon mode pulse signal VCM, to assure that the output will remain in a logic high state (i.e., VO>2.0 V). Common mode transient
immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode pulse signal,
VCM, to assure that the output will remain in a logic low state (i.e., VO<0.8 V).
4. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together.
5. For dual channel devices, CI-O is measured by shorting pins 1 and 2 or pins 3 and 4 together and pins 5 through 8 shorted
together.
6. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
I
Electrical Characteristics (TA = 25°C unless otherwise specified)
Current Limiting Resistor Calculations
R1 (Non-Invert) = VDD1 - VDF - VOL1
OUTPUT
IF
R1 (Invert) = VDD1 - VOH1 - VDF CMOS CMOS
INPUT R1 (V) 74XX 74LXX 74SXX 74LSXX 74HXX
@ 5V @ 10 V
IF
R2 (V) R2 (V) R2 (V) R2 (V) R2 (V) R2 (V) R2 (V)
R2 = VDD2 - = VOLX (@ IL - I2)
CMOS NON-INV. 2000 1000 2200 750 1000 1000 1000 560
IL @5V INV. 510
CMOS NON-INV. 5100
@ 10 V INV. 4700
Where: 74XX NON-INV. 2200
VDD1 - Input Supply Voltage INV. 180
VDD2 - Output Supply Voltage 74LXX NON-INV. 1800
VDF - Diode Forward Voltage INV. 100
VOL1 - Logic “0” Voltage of Driver 74SXX NON-INV. 2000
VOH1 - Logic “1” Voltage of Driver INV. 360
IF - Diode Forward Current 74LSXX NON-INV. 2000
VOLX - Saturation Voltage of INV. 180

Output Transistor 74HXX NON-INV. 2000
IL - Load Current Through INV. 180
Resistor R2
Fig. 1 Resistor Values for Logic Interface
I2 - Input Current of Output Gate
VDD1 VDD2 VDD2
1 8 1 8
R2 IN R2
2 7 2 7
3 6 3 6 OUT
IN R1 OUT R1
4 5 4 5
Fig. 2 Non-Inverting Logic Interface Fig. 3 Inverting Logic Interface
Fig. 4 LED Forward Current vs. Forward Voltage Fig. 5 LED Forward Voltage vs. Temperature
100 1.5
IF = 1.6 mA
10
FORWARD CURRENT - IF (mA)
FORWARD VOLTAGE - VF (V)

1.4
TA = 85˚C
1 TA = 70˚C
1.3
0.1
1.2
0.01
TA = 25˚C
TA = -40˚C
TA = 0˚C
0.001 1.1
1.0 1.1 1.2 1.3 1.4 1.5 1.6 -40 -20 0 20 40 60 80 100
FORWARD VOLTAGE - VF (V) TEMPERATURE - TA (˚C)
Fig. 6 Non-saturated Rise and Fall Times vs. Fig. 7 Non-saturated Rise and Fall Times vs.
Load Resistance (6N138 / 6N139 Only) Load Resistance (HCPL-2730 / HCPL-2731 Only)
100
TA = 25˚C
TA = 25˚C
tf
tf
10
TIME, T (µs)
TIME - µs
10
tr
tr
IF ADJUSTED FOR VOL = 2 V
1
0.1 1 10 0.1 1 10
RL - LOAD RESISTANCE (kΩ) RL - LOAD RESISTANCE (kΩ)
Fig. 8 Propagation Delay To Logic Low

vs. Base-Emitter Resistance Fig. 9 Current Transfer Ratio vs. Forward Current
(HCPL-2730 / HCPL-2731 Only) (6N138 / 6N139 Only)
6
TPHL - PROPAGATION DELAY TO LOGIC LOW - (µs)
VCC = 5 V
IF = 1.6 mA, VCC = 5 V VO= 0.4 V
1600
RL = 2.2 K, TA = 25°C
CURRENT TRANSFER RATIO - CTR (%)
5 Normalized to RBE = None
4 1200
3 TA = 85˚C
800
2
TA = 70˚C
TA = 25˚C
400
1 TA = 0˚C
TA = -40˚C
0 0
0.01 0.1 1 10 0.01 0.1 1 10
RBE - BASE-EMITTER RESISTANCE - MΩ IF - FORWARD CURRENT - mA
Fig. 10 Current Transfer Ratio vs. Base-Emitter Resistance Fig. 11 Current Transfer Ratio vs. Forward Current
(6N138 / 6N139 Only) (HCPL-2730 / HCPL-2731 Only)
1600 5000
VCC = 5 V
CTR - CURRENT TRANSFER RATIO (%)
1400 VO = 0.4 V
CTR - CURRENT TRANSFER RATIO - %

4000
TA = 70˚C
1200
TA = 85˚C
TA = 25˚C
1000
3000
TA = 0˚C
800
600 2000 TA = -40˚C
400
1000
IF = 1.6 mA
200 VCC = 5 V
VO = 0.4 V
0 0
1 10 100 1000 0.1 1 10 100
RBE - BASE RESISTANCE (kΩ) IF - FORWARD CURRENT - mA
Fig. 12 Output Current vs Output Voltage Fig. 13 Output Current vs Output Voltage
60 120
VCC = 5V 5 mA 4.5 mA IF = 5.0 mA
TA = 25˚C 4 mA TA = 25˚C
VCC = 5.0 V IF = 4.5 mA
3.5 mA
50 100
3 mA IF = 4.0 mA
IO-OUTPUT CURRENT - mA
IO - OUTPUT CURRENT (mA)
IF = 3.5 mA
2.5 mA
40 80 IF = 3.0 mA
IF = 2.5 mA
2 mA
IF = 2.0 mA
30 60
IF = 1.5 mA
1.5 mA
20 40 IF = 1.0 mA
1 mA
10 20
IF = 0.5 mA
0
0 1 2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VO - OUTPUT VOLTAGE (V) VO - OUTPUT VOLTAGE (V)
Fig. 14 Output Current vs. Input Diode Forward Current Fig. 15 Output Current vs
(6N138 / 6N139 Only) Input Diode Forward Current
(HCPL-2730 / HCPL-2731 Only)
100 100
VCC = 5.0 V
VO = 0.4 V
TA = 85˚C
VCC = 5 V
VO = 0.4 V
10
IO - OUTPUT CURRENT - mA
IO - OUTPUT CURRENT (mA)
10
TA = 25˚C
1
TA = 85˚C 1
TA = -40˚C
TA = 70˚C
0
TA = 25˚C
TA = 0˚C
TA = -40˚C
0.1
0
0.01 0.1 1 10 0.1 1 10 100
IF - INPUT DIODE FORWARD CURRENT - mA IF - INPUT DIODE FORWARD CURRENT - mA
Fig. 16 Logic Low Supply Current vs. Fig. 17 Logic Low Supply Current vs.
Input Diode Forward Current Input Diode Forward Current
4.0 100
TA = 25˚C
3.5
ICCL - LOGIC LOW SUPPLY CURRENT (mA)
ICCL - LOGIC LOW SUPPLY CURRENT - mA

HCPL-2731
3.0 VCC = 18 V
10
2.5
HCPL-2730
VCC = 5 V
HCPL-2731
2.0 VCC = 7 V
VCC = 18 V
1.5
1
1.0
0.5
0.0 0.1
0 2 4 6 8 10 12 14 16 0.1 1 10 100
IF - FORWARD CURRENT (mA) IF - INPUT DIODE FORWARD CURRENT - mA
Fig. 18 Propagation Delay vs. Input Diode Forward Current Fig. 19 Propagation Delay vs. Input Diode Forward Current
70 70
VCC = 5 V VCC = 5 V
TA = 25˚C TA = 25˚C
60 60
tP - PROPAGATION DELAY - µs
50 50
(tPHL) RL = 2.2 kΩ or 4.7 kΩ (tPHL) RL = 2.2 kΩ or 4.7 kΩ

40 40
30 30
(tPLH) RL = 4.7 kΩ
20 (tPLH) RL = 4.7 kΩ 20 (tPLH) RL = 2.2 kΩ
10 10
(tPLH) RL = 2.2 kΩ
0 0
0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10
IF - INPUT DIODE FORWARD CURRENT - mA IF - INPUT DIODE FORWARD CURRENT - mA
Fig. 20 Propagation Delay to Logic Low vs. Pulse Period Fig. 21 Propagation Delay to Logic Low vs. Pulse Period
(HCPL-2730 / HCPL-2731 Only)
(6N138 / 6N139 Only)
100 100
tPHL - PROPAGATION DELAY to LOGIC LOW - µs
tPHL - PROPAGATION DELAY to LOGIC LOW - µs
6N139
IF = 0.5 mA
RL = 4.7 kΩ HCPL-2731
IF = 0.5 mA
10 10 RL = 4.7 kΩ
6N138
IF = 1.6 mA
RL = 2.2 kΩ
1 1
HCPL-2730
HCPL-2731
IF =1.6 mA TA = 25˚C
RL = 2.2kΩ
TA = 25˚C
0.1 0.1
0.01 0.1 1 10 0.01 0.1 1 10
T - INPUT PULSE PERIOD - ms T - INPUT PULSE PERIOD - ms
Fig. 22 Propagation Delay vs. Temperature Fig. 23 Propagation Delay vs. Temperature
50 50
HCPL-2730 : IF = 1.6 mA, RL = 2.2 k HCPL-2730 : IF = 1.6 mA, RL = 2.2 k
HCPL-2731 : IF = 0.5 mA, RL = 4.7 k HCPL-2731 : IF = 0.5 mA, RL = 4.7 k
40 40
tPLH (HCPL-2731) tPLH (HCPL-2731)
30 30
20 20
tPLH (HCPL-2730) tPLH (HCPL-2730)
tPHL (HCPL-2731) tPHL (HCPL-2731)

10 tPHL (HCPL-2730) 10 tPHL (HCPL-2730)
0 0
0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80
TA - TEMPERATURE (˚C) TA - TEMPERATURE (˚C)
Noise Pulse Noise
VCC IF + Shield
Shield Generator VCC
1 8 +5 V tr = 5ns 1 8 +5 V
Pulse Z O = 50 V
Generator VF1 RL 0.1 µF
IF VB
tr = 5ns - V01
Z O = 50 V 2 7 RL 10% DUTY CYCLE 2 7 VO
I/f < 100 µS
10% D.C. VF
I/ f< 100 ms C L = 15 pF*
VO V02
3 6 VO - 3 6
IF
0.1 µF VF2
MONITOR
I F Monitor GND
4 5 Rm + 4 5
Rm GND C L = 15 pF*
Test Circuit for 6N138, 6N139 Test Circuit for HCPL-2730 and HCPL-2731
IF
VO 5V
1.5 V 1.5 V
VOL
TPHL TPLH
Fig. 22 Switching Time Test Circuit
IF Noise Noise
Shield VCC Shield VCC
+
1 8 +5 V 1 8 +5 V
IF
VF1 RL
VB - V01
RL
2 7 2 7 VO
VF A
0.1 µF
A VO B V02
-
B
3 6 VO 3 6
VFF
0.1 µF VF2
VFF +
GND GND
4 5 - 4 5
VCM
+ -
VCM
Pulse Gen + -
Pulse Gen
Test Circuit for 6N138 and 6N139 Test Circuit for HCPL-2730 and HCPL-2731
VCM 10 V
90% 90%
10% 10%
0V
tr tf
VO
5V
Switch at A : I F = 0 mA
VO
VOL
Switch at B : I F = 1.6 mA
Fig. 23 Common Mode Immunity Test Circuit
Package Dimensions (Through Hole) Package Dimensions (Surface Mount)
0.390 (9.91)
0.370 (9.40)
PIN 1 PIN 1
ID. 4 3 2 1 ID.
4 3 2 1
0.270 (6.86)
0.250 (6.35) 0.270 (6.86)
0.250 (6.35)
5 6 7 8
5 6 7 8
0.390 (9.91)
0.370 (9.40)
SEATING PLANE
0.070 (1.78) 0.300 (7.62)

0.070 (1.78) TYP
0.045 (1.14)
0.045 (1.14)
0.200 (5.08) 0.020 (0.51) MIN 0.020 (0.51) 0.016 (0.41)

0.140 (3.55) MIN 0.008 (0.20)
0.154 (3.90)
0.120 (3.05) 0.045 [1.14]
0.022 (0.56)
0.022 (0.56) 15° MAX 0.016 (0.41)
0.016 (0.40) 0.315 (8.00)
0.016 (0.41)
0.008 (0.20) 0.100 (2.54) MIN
0.300 (7.62)
0.100 (2.54) TYP TYP
TYP 0.405 (10.30)
Lead Coplanarity : 0.004 (0.10) MAX MIN
Package Dimensions (0.4"Lead Spacing) Recommended Pad Layout for

Surface Mount Leadform
PIN 1
4 3 2 1
ID.
0.070 (1.78)
0.270 (6.86)
0.250 (6.35)
0.060 (1.52)
5 6 7 8
0.390 (9.91)
0.370 (9.40)
0.100 (2.54)
SEATING PLANE
0.070 (1.78) 0.295 (7.49)

0.045 (1.14) 0.030 (0.76)
0.415 (10.54)
0.200 (5.08) 0.004 (0.10) MIN
0.140 (3.55)
0.154 (3.90)
0.120 (3.05)
0.022 (0.56) 0° to 15°
0.016 (0.40)
0.016 (0.41)
0.008 (0.20)
0.400 (10.16)
0.100 (2.54) TYP
TYP
NOTE
All dimensions are in inches (millimeters)
Ordering Information
Option Example Part Number Description
S 6N138S Surface Mount Lead Bend
SD 6N138SD Surface Mount; Tape and reel
W 6N138W 0.4" Lead Spacing
V 6N138V VDE0884
TV 6N138TV VDE0884; 0.4” lead spacing
SV 6N138SV VDE0884; surface mount
SDV 6N138SDV VDE0884; surface mount; tape and reel
Marking Information
2730 2
6
V XX YY T1
3 4 5
Definitions
1 Fairchild logo
2 Device number
VDE mark (Note: Only appears on parts ordered with VDE
3
option – See order entry table)
4 Two digit year code, e.g., ‘03’
5 Two digit work week ranging from ‘01’ to ‘53’
6 Assembly package code
Tape Specifications
12.0 ± 0.1
4.90 ± 0.20
4.0 ± 0.1 Ø1.55 ± 0.05
0.30 ± 0.05 4.0 ± 0.1
1.75 ± 0.10
7.5 ± 0.1
13.2 ± 0.2 16.0 ± 0.3
10.30 ± 0.20
0.1 MAX 10.30 ± 0.20 Ø1.6 ± 0.1
User Direction of Feed
Reflow Profile
300
215 C, 10–30 s
250
Temperature (°C)
225 C peak
200
150
100 Time above 183C, 60–150 sec
50 Ramp up = 3C/sec
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Time (Minute)
• Peak reflow temperature: 225C (package surface temperature)

• Time of temperature higher than 183C for 60–150 seconds
• One time soldering reflow is recommended
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ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
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systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.
Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I16

Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Low Input Current High Gain Split Darlington Optocouplers

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Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Low Input Current High Gain Split Darlington Optocouplers

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Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Low Input Current High Gain Split Darlington Optocouplers

Single-Channel: 6N138, 6N139

N/C 1 8 VCC + 1 8 VCC

N/C 4 5 GND + 4 5 GND

©2005 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com

Electrical Characteristics (TA = 0 to 70°C Unless otherwise specified)

** All Typicals at TA = 25°C

** All Typicals at TA = 25°C

** All Typicals at TA = 25°C

** All Typicals at TA = 25°C

IF - Diode Forward Current 74LSXX NON-INV. 2000

VOLX - Saturation Voltage of INV. 180

VDD1 VDD2 VDD2

Fig. 2 Non-Inverting Logic Interface Fig. 3 Inverting Logic Interface

FORWARD VOLTAGE - VF (V)

IF ADJUSTED FOR VOL = 2 V

RL - LOAD RESISTANCE (kΩ) RL - LOAD RESISTANCE (kΩ)

Fig. 8 Propagation Delay To Logic Low

5 Normalized to RBE = None

RBE - BASE-EMITTER RESISTANCE - MΩ IF - FORWARD CURRENT - mA

CTR - CURRENT TRANSFER RATIO - %

600 2000 TA = -40˚C

RBE - BASE RESISTANCE (kΩ) IF - FORWARD CURRENT - mA

IF - INPUT DIODE FORWARD CURRENT - mA IF - INPUT DIODE FORWARD CURRENT - mA

ICCL - LOGIC LOW SUPPLY CURRENT - mA

IF - FORWARD CURRENT (mA) IF - INPUT DIODE FORWARD CURRENT - mA

(tPHL) RL = 2.2 kΩ or 4.7 kΩ (tPHL) RL = 2.2 kΩ or 4.7 kΩ

20 (tPLH) RL = 4.7 kΩ 20 (tPLH) RL = 2.2 kΩ

tPHL (HCPL-2731) tPHL (HCPL-2731)

TA - TEMPERATURE (˚C) TA - TEMPERATURE (˚C)

Fig. 22 Switching Time Test Circuit

Fig. 23 Common Mode Immunity Test Circuit

0.070 (1.78) 0.300 (7.62)

0.200 (5.08) 0.020 (0.51) MIN 0.020 (0.51) 0.016 (0.41)

Package Dimensions (0.4"Lead Spacing) Recommended Pad Layout for

0.070 (1.78) 0.295 (7.49)

0.1 MAX 10.30 ± 0.20 Ø1.6 ± 0.1

User Direction of Feed

100 Time above 183C, 60–150 sec

• Peak reflow temperature: 225C (package surface temperature)

LIFE SUPPORT POLICY

Datasheet Identification Product Status Definition

Preliminary First Production This datasheet contains preliminary data, and

Obsolete Not In Production This datasheet contains specifications on a product

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