High-Speed, Low-Power Dual Operational Amplifier: S Slew Rate
High-Speed, Low-Power Dual Operational Amplifier: S Slew Rate
High-Speed, Low-Power Dual Operational Amplifier: S Slew Rate
1k
VS
3.3F 5V 500ns
100
90
CL = 100pF
0.01F
VIN 1k
HP PULSE 2
GENERATOR TEKTRONIX TEKTRONIX
50 1/2 1
P6201 FET 7A24 FET
AD826 VOUT PROBE PREAMP
3
10 CL = 1000pF
0.01F 0%
CL
5V
3.3F
–VS
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/461-3113 © Analog Devices, Inc., 2010
AD826–SPECIFICATIONS (@ T = +25C, unless otherwise noted)
A
–2– REV. C
AD826
Parameter Conditions VS Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Voltage Swing RLOAD = 500 Ω ±5 V 3.3 3.8 ±V
RLOAD = 150 Ω ±5 V 3.2 3.6 ±V
RLOAD = 1 kΩ ± 15 V 13.3 13.7 ±V
RLOAD = 500 Ω ± 15 V 12.8 13.4 ±V
RLOAD = 500 Ω 0, +5 V +1.5,
+3.5 V
Output Current ± 15 V 50 mA
±5 V 50 mA
0, +5 V 30 mA
Short-Circuit Current ± 15 V 90 mA
Output Resistance Open Loop 8 Ω
MATCHING CHARACTERISTICS
Dynamic
Crosstalk f = 5 MHz ± 15 V –80 dB
Gain Flatness Match G = +1, f = 40 MHz ± 15 V 0.2 dB
Slew Rate Match G = –1 ± 15 V 10 V/µs
DC
Input Offset Voltage Match TMIN –TMAX ± 5 V to ± 15 V 0.5 2 mV
Input Bias Current Match TMIN –TMAX ± 5 V to ± 15 V 0.06 0.8 µA
Open-Loop Gain Match VO = ± 10 V, RLOAD = 1 kΩ,
TMIN –TMAX ± 15 V 0.15 0.01 mV/V
Common-Mode Rejection Ratio Match VCM = ± 12 V, TMIN –TMAX ± 15 V 80 100 dB
Power Supply Rejection Ratio Match ± 5 V to ± 15 V, TMIN –TMAX 80 100 dB
POWER SUPPLY
Operating Range Dual Supply ± 2.5 ± 18 V
Single Supply +5 +36 V
Quiescent Current/Amplifier ±5 V 6.6 7.5 mA
TMIN to TMAX ±5 V 7.5 mA
± 15 V 7.5 mA
TMIN to TMAX ± 15 V 6.8 7.5 mA
Power Supply Rejection Ratio VS = ± 5 V to ± 15 V, TMIN to TMAX 75 86 dB
NOTES
1
Full power bandwidth = slew rate/2 π VPEAK. ESD SUSCEPTIBILITY
Specifications subject to change without notice. ESD (electrostatic discharge) sensitive device. Electrostatic charges
as high as 4000 volts, which readily accumulate on the human
ABSOLUTE MAXIMUM RATINGS 1 body and on test equipment, can discharge without detection.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Although the AD826 features proprietary ESD protection cir-
Internal Power Dissipation2 cuitry, permanent damage may still occur on these devices
Plastic (N) . . . . . . . . . . . . . . . . . . . . . See Derating Curves if they are subjected to high energy electrostatic discharges.
Small Outline (R) . . . . . . . . . . . . . . . . See Derating Curves Therefore, proper ESD precautions are recommended to avoid
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . ± VS any performance degradation or loss of functionality.
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 6 V
Output Short Circuit Duration . . . . . . . See Derating Curves 2.0
TJ = +150C
Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C 8-LEAD MINI-DIP PACKAGE
MAXIMUM POWER DISSIPATION – Watts
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
1.0
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability .
2
Specification is for device in free air: 8-lead plastic package, θJA = 100°C/watt;
0.5
8-lead SOIC package, θJA = 155°C/watt.
8-LEAD SOIC PACKAGE
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – C
REV. C –3–
AD826 – Typical Characteristics
20 7.7
15 7.2
+VCM
+85C +25C
10 6.7
–VCM –40C
5 6.2
0 5.7
0 5 10 15 20 0 5 10 15 20
SUPPLY VOLTAGE – Volts SUPPLY VOLTAGE – Volts
Figure 1. Common-Mode Voltage Range vs. Supply Figure 4. Quiescent Supply Current per Amp vs. Supply
Voltage for Various Temperatures
20 400
OUTPUT VOLTAGE SWING – Volts
15 350
SLEW RATE – V/s
RL = 500V
10 300
RL = 150V
5 250
0 200
0 5 10 15 20 0 5 10 15 20
SUPPLY VOLTAGE – Volts SUPPLY VOLTAGE – Volts
Figure 2. Output Voltage Swing vs. Supply Figure 5. Slew Rate vs. Supply Voltage
30 100
CLOSED-LOOP OUTPUT IMPEDANCE –
OUTPUT VOLTAGE SWING – Volts p-p
25
VS = 15V 10
20
15 1
10
VS = 5V 0.1
5
0 0.01
10 100 1k 10k 1k 10k 100k 1M 10M 100M
LOAD RESISTANCE – FREQUENCY – Hz
Figure 3. Output Voltage Swing vs. Load Resistance Figure 6. Closed-Loop Output Impedance vs. Frequency
–4– REV. C
AD826
7 100 +100
PHASE 5V OR
15V SUPPLIES
6 80 +80
INPUT BIAS CURRENT – A
4 40 +40
GAIN 5V SUPPLIES
3 20 +20
2 0 0
RL = 1k
1 –20
–60 –40 –20 0 20 40 60 80 100 120 140 1k 10k 100k 1M 10M 100M 1G
TEMPERATURE – C FREQUENCY – Hz
Figure 7. Input Bias Current vs. Temperature Figure 10. Open-Loop Gain and Phase Margin
vs. Frequency
130
7
15V
6
SHORT CIRCUIT CURRENT – mA
110
70
3
50
2
30 1
–60 –40 –20 0 20 40 60 80 100 120 140 100 1k 10k
TEMPERATURE – C LOAD RESISTANCE –
Figure 8. Short Circuit Current vs. Temperature Figure 11. Open-Loop Gain vs. Load Resistance
100 100
90
UNITY GAIN BANDWIDTH – MHz
80
PHASE MARGIN – Degrees
80 80
PHASE MARGIN POSITIVE
70 SUPPLY
PSR – dB
60 NEGATIVE
60 60 SUPPLY
50
40
GAIN BANDWIDTH
40 40
30
20
20 20
10
–60 –40 –20 0 20 40 60 80 100 120 140 100 1k 10k 100k 1M 10M 100M
TEMPERATURE – C FREQUENCY – Hz
Figure 9. Unity Gain Bandwidth and Phase Margin Figure 12. Power Supply Rejection vs. Frequency
vs. Temperature
REV. C –5–
AD826
140 –40
VIN = 1V p-p
GAIN = +2
–50
HARMONIC DISTORTION – dB
120
–60
CMR – dB
100 –70
–80
2ND HARMONIC
80
–90
3RD HARMONIC
60 –100
1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
FREQUENCY – Hz FREQUENCY – Hz
Figure 13. Common-Mode Rejection vs. Frequency Figure 16. Harmonic Distortion vs. Frequency
30 50
Hz
40
OUTPUT VOLTAGE – Volts p-p
RL = 1k
INPUT VOLTAGE NOISE – nV/
20
30
20
10 RL = 150
10
0 0
100k 1M 10M 100M 3 10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz FREQUENCY – Hz
Figure 14. Large Signal Frequency Response Figure 17. Input Voltage Noise Spectral Density
10 380
0.1%
8
OUTPUT SWING FROM 0 TO V
6
360
4
SLEW RATE – V/s
1% 0.01%
2
0 340
–2
1% 0.01%
–4
320
–6
0.1%
–8
–10 300
0 20 40 60 80 100 120 140 160 –60 –40 –20 0 20 40 60 80 100 120 140
SETTLING TIME – ns TEMPERATURE – C
Figure 15. Output Swing and Error vs. Settling Time Figure 18. Slew Rate vs. Temperature
–6– REV. C
AD826
5 5
1 VS = 15V 1
GAIN – dB
GAIN – dB
VS = 15V
0 0
–1 –1 VS = 5V
VS = 5V
–2 –2
VS = 5V VS = 5V
–3 –3
–4 –4
–5 –5
100k 1M 10M 100M 100k 1M 10M 100M
FREQUENCY – Hz FREQUENCY – HZ
Figure 19. Closed-Loop Gain vs. Frequency Figure 22. Closed-Loop Gain vs. Frequency, Gain = –1
0.13 1.0
DIFFERENTIAL GAIN – Percent
0.8
0.4
DIFFERENTIAL PHASE – Degrees
0.12 –0.2
DIFF PHASE VS = 5V
–0.4
VS = +5V
0.11 –0.6
–0.8
0.10 –1.0
5 10 15 100k 1M 10M 100M
FREQUENCY – Hz
SUPPLY VOLTAGE – Volts
Figure 20. Differential Gain and Phase vs. Supply Voltage Figure 23. Gain Flatness Matching vs. Supply, G = +1
VS VOUT
–30
0.1F
–40
–50 3 8 1F 5
1/2 1 7 1/2
CROSSTALK – dB
–100 –VS
Figure 21. Crosstalk vs. Frequency Figure 24. Crosstalk Test Circuit
REV. C –7–
AD826
1k
VS
3.3F
0.01F
RL
3.3F
–VS
100 100
90 90
10 10
0% 0%
5V 200mV
Figure 26. Noninverting Large Signal Pulse Response, Figure 28. Noninverting Small Signal Pulse Response,
RL = 1 kΩ RL = 1 kΩ
5V 50ns 5V
200mV 50ns
100 100
90 90
10 10
0% 0%
5V 200mV
Figure 27. Noninverting Large Signal Pulse Response, Figure 29. Noninverting Small Signal Pulse Response,
RL = 150 Ω RL = 150 Ω
–8– REV. C
AD826
1k
VS
3.3F
0.01F
RIN
PULSE (LS) VIN 1k
OR FUNCTION (SS)
GENERATOR 1/2 TEKTRONIX TEKTRONIX
50 P6201 FET 7A24
AD826
VOUT PROBE PREAMP
0.01F
RL
3.3F
–VS
100 100
90 90
10 10
0% 0%
5V 200mV
Figure 31. Inverting Large Signal Pulse Response, Figure 33. Inverting Small Signal Pulse Response,
RL = 1 kΩ RL = 1 kΩ
100 100
90 90
10 10
0% 0%
5V 200mV
Figure 32. Inverting Large Signal Pulse Response, Figure 34. Inverting Small Signal Pulse Response,
RL = 150 Ω RL = 150 Ω
REV. C –9–
AD826
THEORY OF OPERATION
The AD826 is a low cost, wide band, high performance dual For high performance circuits, it is recommended that a
operational amplifier which can drive heavy capacitive and “balancing” resistor be used to reduce the offset errors caused
resistive loads. It also achieves a constant slew rate, bandwidth by bias current flowing through the input and feedback resistors.
and settling time over its entire specified temperature range. The balancing resistor equals the parallel combination of RIN
The AD826 (Figure 35) consists of a degenerated NPN and RF and thus provides a matched impedance at each input
differential pair driving matched PNPs in a folded-cascode gain terminal. The offset voltage error will then be reduced by more
stage. The output buffer stage employs emitter followers in a than an order of magnitude.
class AB amplifier which delivers the necessary current to the APPLYING THE AD826
load while maintaining low levels of distortion. The AD826 is a breakthrough dual amp that delivers precision
+VS
and speed at low cost with low power consumption. The AD826
offers excellent static and dynamic matching characteristics,
combined with the ability to drive heavy resistive and capacitive
loads. As with all high frequency circuits, care should be taken
to maintain overall device performance as well as their matching.
CF
The following items are presented as general design considerations.
OUTPUT Circuit Board Layout
Input and output runs should be laid out so as to physically
–IN
isolate them from remaining runs. In addition, the feedback
resistor of each amplifier should be placed away from the
feedback resistor of the other amplifier, since this greatly
reduces inter-amp coupling.
+IN
Choosing Feedback and Gain Resistors
In order to prevent the stray capacitance present at each
amplifier’s summing junction from limiting its performance,
–VS
the feedback resistors should be ≤1 kΩ. Since the summing
NULL1 NULL8 junction capacitance may cause peaking, a small capacitor
Figure 35. Simplified Schematic (1 pF–5pF) maybe paralleled with RF to neutralize this effect.
Finally, sockets should be avoided, because of their tendency to
The capacitor, CF, in the output stage mitigates the effect of
increase interlead capacitance.
capacitive loads. With low capacitive loads, the gain from the
compensation node to the output is very close to unity. In this Power Supply Considerations
case, CF is bootstrapped and does not contribute to the overall To ensure the proper operation of the AD826, connect the
compensation capacitance of the device. As the capacitive load positive supply before the negative supply. Also, proper power
is increased, a pole is formed with the output impedance of the supply decoupling is critical to preserve the integrity of high
output stage. This reduces the gain, and therefore, CF is frequency signals. In carefully laid out designs, decoupling
incompletely bootstrapped. Effectively, some fraction of CF capacitors should be placed in close proximity to the supply
contributes to the overall compensation capacitance, reducing pins, while their lead lengths should be kept to a minimum.
the unity gain bandwidth. As the load capacitance is further These measures greatly reduce undesired inductive effects on
increased, the bandwidth continues to fall, maintaining the the amplifier’s response.
stability of the amplifier.
Though two 0.1 μF capacitors will typically be effective in
INPUT CONSIDERATIONS decoupling the supplies, several capacitors of different values
An input protection resistor (RIN in Figure 25) is required in can be paralleled to cover a wider frequency range.
circuits where the input to the AD826 will be subjected to
transient or continuous overload voltages exceeding the ±6 V
maximum differential limit. This resistor provides protection
for the input transistors by limiting their maximum base current.
-10- Rev. C
AD826
SINGLE SUPPLY OPERATION R3 and C2 reduce the effect of the power supply changes on the
An exciting feature of the AD826 is its ability to perform well in a
single supply configuration (see Figure 37). The AD826 is ideally 1
output by low-pass filtering with a corner at .
suited for applications that require low power dissipation and high 2πR3C2
output current and those which need to drive large capacitive The values for RL and CL were chosen to demonstrate the
loads, such as high speed buffering and instrumentation. AD826’s exceptional output drive capability. In this configura-
Referring to Figure 36, careful consideration should be given to tion, the output is centered around 2.5 V. In order to eliminate
the proper selection of component values. The choices for this the static dc current associated with this level, C3 was inserted
particular circuit are: (R1 + R3)储R2 combine with C1 to form a in series with RL.
low frequency corner of approximately 30 Hz.
VS
500mV
100
90
R3
1k
3.3F
C2
0.1F
R1 0.01F
9k
COUT 10
C1
1/2 0%
AD826 VOUT
1F
VIN RL CL 500mV 100ns
R2 150 200pF
10k C3
0.1F
Figure 37. Single Supply Pulse Response, G = +1,
RL = 150 Ω, CL = 200 pF
Figure 36. Single Supply Amplifier Configuration
1k
RL
R2
1/2 5
1k AD826
0.1F
–VS 1F
1k
REV. C –11–
AD826
SINGLE-ENDED TO DIFFERENTIAL LINE DRIVER
Outstanding CMRR (> 80 dB @ 5 MHz), high bandwidth, wide 2V 200ns
supply voltage range, and the ability to drive heavy loads, make
100
the AD826 an ideal choice for many line driving applications. 90
In this application, the AD830 high speed video difference
amp serves as the differential line receiver on the end of a back
terminated, 50 ft., twisted-pair transmission line (see Figure 40).
The overall system is configured in a gain of +1 and has a –3 dB
bandwidth of 14 MHz. Figure 39 is the pulse response with a
2 V p-p, 1 MHz signal input. 10
0%
2V
15V 0.01F
15V 0.01F
36
1/2
1.05k AD826
36
VOUT
BNC 5pF 1.05k AD830
36
5pF
1/2
AD826 0.01F
0.01F
–15V 0.1F
0.1F
5V VS
100F
25V
COMMON –VS
100F
25V 1k
–5V –VS
REV. C –13–
AD826
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8 5 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
4
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC 0.060 (1.52) 0.195 (4.95)
0.210 (5.33) MAX 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38) 0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.115 (2.92) PLANE 0.014 (0.36)
SEATING
PLANE 0.010 (0.25)
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
070606-A
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 44. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284)
4
-14- Rev. C
AD826
REVISION HISTORY
Changed Power Supply Bypassing Section to Power Supply
Considerations Section ...................................................................10
Changes to Power Supply Considerations Section ....................10
Updated Outline Dimensions ........................................................14
Changes to Ordering Guide ...........................................................14
Rev. C -15-