High Gain Bandwidth Product,

Precision Fast FET™ Op Amp

Data Sheet AD8067
FEATURES CONNECTION DIAGRAM (TOP VIEW)
FET input amplifier: 0.6 pA input bias current SOT-23-5 (RT-5)

Stable for gains ≥8

High speed VOUT 1 5 +VS
54 MHz, −3 dB bandwidth (G = +10)
640 V/µs slew rate
–VS 2
Low noise
6.6 nV/√Hz
0.6 fA/√Hz +IN 3 4 –IN

Low offset voltage (1.0 mV max) Figure 1.

Wide supply voltage range: 5 V to 24 V
No phase reversal
Low input capacitance
Single-supply and rail-to-rail output
Excellent distortion specs: SFDR 95 dBc @ 1 MHz
High common-mode rejection ratio: −106 dB
Low power: 6.5 mA typical supply current
Low cost
Small packaging: SOT-23-5

APPLICATIONS
Photodiode preamplifiers
Precision high gain amplifiers
High gain, high bandwidth composite amplifiers

GENERAL DESCRIPTION
The AD8067 FastFET amp is a voltage feedback amplifier with The AD8067 amplifier is available in a SOT-23-5 package and is
FET inputs offering wide bandwidth (54 MHz @ G = +10) and rated to operate over the industrial temperature range of –40°C
high slew rate (640 V/µs). The AD8067 is fabricated in a to +85°C.
proprietary, dielectrically isolated eXtra Fast Complementary
Bipolar process (XFCB) that enables high speed, low power, and 28
G = +20
high performance FET input amplifiers. 26

24
The AD8067 is designed to work in applications that require
high speed and low input bias current, such as fast photodiode 22
G = +10
preamplifiers. As required by photodiode applications, the laser 20
GAIN – dB

trimmed AD8067 has excellent dc voltage offset (1.0 mV max)

18
and drift (15 µV/°C max). G = +8
16
The FET input bias current (5 pA max) and low voltage noise 14
(6.6 nV/√Hz) also contribute to making it appropriate for precision
12
applications. With a wide supply voltage range (5 V to 24 V)
and rail-to-rail output, the AD8067 is well suited for a variety of 10

applications that require wide dynamic range and low distortion. 8

0.1 1 10 100
FREQUENCY – MHz

Figure 2. Small Signal Frequency Response

Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2002–2012 Analog Devices, Inc. All rights reserved.
AD8067* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017

COMPARABLE PARTS REFERENCE MATERIALS

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• MT-047: Op Amp Noise
DOCUMENTATION
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Application Notes Noise, and Equivalent Noise Bandwidth
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Design Constraints in Low Voltage High Speed Systems Second-Order System
• AN-581: Biasing and Decoupling Op Amps in Single • MT-052: Op Amp Noise Figure: Don't Be Misled
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• AN-649: Using the Analog Devices Active Filter Design SFDR, MTPR
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Data Sheet
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FET™ Op Amp Datasheet
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User Guides Capacitance on VFB and CFB Op Amps Used in Current-to-
• UG-838: Evaluation Board for Single, High Speed Op Amps Voltage Converters
Offered in 5-Lead SOT-23 and 6-Lead SOT-23 Packages • MT-060: Choosing Between Voltage Feedback and
Current Feedback Op Amps
TOOLS AND SIMULATIONS
• Analog Filter Wizard DESIGN RESOURCES
• Analog Photodiode Wizard • AD8067 Material Declaration
• Power Dissipation vs Die Temp • PCN-PDN Information
• VRMS/dBm/dBu/dBV calculators • Quality And Reliability
• AD8067 SPICE Macro Model • Symbols and Footprints

DISCUSSIONS
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AD8067 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Resistor Selection for Wideband Operation............................... 14

Applications ....................................................................................... 1 DC Error Calculations ............................................................... 15

Connection Diagram (Top View)................................................... 1 Input and Output Overload Behavior ..................................... 15

General Description ......................................................................... 1 Input Protection ......................................................................... 16

Revision History ............................................................................... 2 Capacitive Load Drive ............................................................... 16

Specifications for ±5 V ..................................................................... 3 Layout, Grounding, and Bypassing Considerations .............. 16

Specifications for +5 V ..................................................................... 4 Applications..................................................................................... 18

Specifications for ±12 V ................................................................... 5 Wideband Photodiode Preamp ................................................ 18

Absolute Maximum Ratings ............................................................ 6 Using the AD8067 at Gains of Less Than 8 ............................ 19

Maximum Power Dissipation ..................................................... 6 Single-Supply Operation ........................................................... 20

ESD Caution .................................................................................. 6 High Gain, High Bandwidth Composite Amplifier .............. 20

Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 22

Test Circuits ..................................................................................... 12 Ordering Guide .......................................................................... 22

Theory of Operation ...................................................................... 13

Basic Frequency Response ........................................................ 13

REVISION HISTORY
4/12—Rev. A to Rev. B
Changes to Basic Frequency Response Section .......................... 13
Changes to Figure 54 Caption....................................................... 19
Changes to Figure 55 Caption....................................................... 20
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22

5/06—Rev. 0 to Rev. A
Changes to Figure 51 ...................................................................... 18
Changes to Figure 54 ...................................................................... 19
Changes to Figure 57 ...................................................................... 21
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22

11/02—Revision 0: Initial Version

Rev. B | Page 2 of 24
Data Sheet AD8067

SPECIFICATIONS FOR ±5 V
VS = ±5 V (@ TA = +25°C, G = +10, RF = RL =1 kΩ, unless otherwise noted.)
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VO = 0.2 V p-p 39 54 MHz
VO = 2 V p-p 54 MHz
Bandwidth for 0.1 dB Flatness VO = 0.2 V p-p 8 MHz
Output Overdrive Recovery Time (Pos/Neg) VI = ±0.6 V 115/190 ns
Slew Rate VO = 5 V step 500 640 V/µs
Settling Time to 0.1% VO = 5 V step 27 ns
NOISE/DISTORTION PERFORMANCE
Spurious-Free Dynamic Range (SFDR) fC = 1 MHz, 2 V p-p 95 dBc
fC = 1 MHz, 8 V p-p 84 dBc
fC = 5 MHz, 2 V p-p 82 dBc
fC = 1 MHz, 2 V p-p, RL = 150 Ω 72 dBc
Input Voltage Noise f = 10 kHz 6.6 nV/√Hz
Input Current Noise f = 10 kHz 0.6 fA/√Hz
DC PERFORMANCE
Input Offset Voltage 0.2 1.0 mV
Input Offset Voltage Drift 1 15 µV/°C
Input Bias Current 0.6 5 pA
TMIN to TMAX 25 pA
Input Offset Current 0.2 1 pA
TMIN to TMAX 1 pA
Open-Loop Gain VO = ±3 V 103 119 dB
INPUT CHARACTERISTICS
Common-Mode Input Impedance 1000||1.5 GΩ||pF
Differential Input Impedance 1000||2.5 GΩ||pF
Input Common-Mode Voltage Range −5.0 2.0 V
Common-Mode Rejection Ratio (CMRR) VCM = –1 V to +1 V −85 −106 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 1 kΩ −4.86 to +4.83 −4.92 to +4.92 V
RL = 150 Ω −4.67 to +4.72 V
Output Current SFDR > 60 dBc, f = 1 MHz 30 mA
Short Circuit Current 105 mA
Capacitive Load Drive 30% overshoot 120 pF
POWER SUPPLY
Operating Range 5 24 V
Quiescent Current 6.5 6.8 mA
Power Supply Rejection Ratio (PSRR) −90 −109 dB

Rev. B | Page 3 of 24
AD8067 Data Sheet

SPECIFICATIONS FOR +5 V
VS = +5 V (@ TA = +25°C, G = +10, RL = RF = 1 kΩ, unless otherwise noted.)
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VO = 0.2 V p-p 36 54 MHz
VO = 2 V p-p 54 MHz
Bandwidth for 0.1 dB Flatness VO = 0.2 V p-p 8 MHz
Output Overdrive Recovery Time (Pos/Neg) VI = +0.6 V 150/200 ns
Slew Rate VO = 3 V step 390 490 V/µs
Settling Time to 0.1% VO = 2 V step 25 ns
NOISE/DISTORTION PERFORMANCE
Spurious-Free Dynamic Range (SFDR) fC = 1 MHz, 2 V p-p 86 dBc
fC = 1 MHz, 4 V p-p 74 dBc
fC = 5 MHz, 2 V p-p 60 dBc
fC = 1 MHz, 2 V p-p, RL = 150 Ω 72 dBc
Input Voltage Noise f = 10 kHz 6.6 nV/√Hz
Input Current Noise f = 10 kHz 0.6 fA/√Hz
DC PERFORMANCE
Input Offset Voltage 0.2 1.0 mV
Input Offset Voltage Drift 1 15 µV/°C
Input Bias Current 0.5 5 pA
TMIN to TMAX 25 pA
Input Offset Current 0.1 1 pA
Open-Loop Gain VO = 0.5 V to 4.5 V 100 117 dB
INPUT CHARACTERISTICS
Common-Mode Input Impedance 1000||2.3 GΩ||pF
Differential Input Impedance 1000||2.5 GΩ||pF
Input Common-Mode Voltage Range 0 2.0 V
Common-Mode Rejection Ratio (CMRR) VCM = 0.5 V to 1.5 V −81 −98 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 1 kΩ 0.07 to 4.89 0.03 to 4.94 V
RL =150 Ω 0.08 to 4.83 V
Output Current SFDR > 60 dBc, f = 1 MHz 22 mA
Short Circuit Current 95 mA
Capacitive Load Drive 30% overshoot 120 pF
POWER SUPPLY
Operating Range 5 24 V
Quiescent Current 6.4 6.7 mA
Power Supply Rejection Ratio (PSRR) −87 −103 dB

Rev. B | Page 4 of 24
Data Sheet AD8067

SPECIFICATIONS FOR ±12 V

VS = ±12 V (@ TA = +25°C, G = +10, RL = RF = 1 kΩ, unless otherwise noted.)
Table 3.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth VO = 0.2 V p-p 39 54 MHz
VO = 2 V p-p 53 MHz
Bandwidth for 0.1 dB Flatness VO = 0.2 V p-p 8 MHz
Output Overdrive Recovery Time (Pos/Neg) VI = ±1.5 V 75/180 ns
Slew Rate VO = 5 V step 500 640 V/µs
Settling Time to 0.1% VO = 5 V step 27 ns
NOISE/DISTORTION PERFORMANCE
Spurious-Free Dynamic Range (SFDR) fC = 1 MHz, 2 V p-p 92 dBc
fC = 1 MHz, 20 V p-p 84 dBc
fC = 5 MHz, 2 V p-p 74 dBc
fC = 1 MHz, 2 V p-p, RL = 150 Ω 72 dBc
Input Voltage Noise f = 10 kHz 6.6 nV/√Hz
Input Current Noise f = 10 kHz 0.6 fA/√Hz
DC PERFORMANCE
Input Offset Voltage 0.2 1.0 mV
Input Offset Voltage Drift 1 15 µV/°C
Input Bias Current 1.0 5 pA
TMIN to TMAX 25 pA
Input Offset Current 0.2 1 pA
Open-Loop Gain VO = ±10 V 107 119 dB
INPUT CHARACTERISTICS
Common-Mode Input Impedance 1000||1.5 GΩ||pF
Differential Input Impedance 1000||2.5 GΩ||pF
Input Common-Mode Voltage Range −12.0 +9.0 V
Common-Mode Rejection Ratio (CMRR) VCM = –1 V to +1 V −89 −108 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 1 kΩ −11.70 to +11.70 −11.85 to +11.84 V
RL = 500 Ω −11.31 to +11.73 V
Output Current SFDR > 60 dBc, f = 1 MHz 26 mA
Short Circuit Current 125 mA
Capacitive Load Drive 30% overshoot 120 pF
POWER SUPPLY
Operating Range 5 24 V
Quiescent Current 6.6 7.0 mA
Power Supply Rejection Ratio (PSRR) −86 −97 dB

Rev. B | Page 5 of 24
AD8067 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 4. PD = Quiescent Power + (Total Drive Power − Load Power)
Parameter Rating
V V  VOUT 2
Supply Voltage 26.4 V PD = (VS × I S )+  S × OUT –
 R
 2 RL  L
Power Dissipation See Figure 3
Common-Mode Input Voltage VEE – 0.5 V to VCC + 0.5 V
If RL is referenced to VS− as in single-supply operation, then the
Differential Input Voltage 1.8 V
total drive power is VS × IOUT.
Storage Temperature Range –65°C to +125°C
Operating Temperature Range –40°C to +85°C If the rms signal levels are indeterminate, then consider the
Lead Temperature (Soldering 10 sec) 300°C worst case, when VOUT = VS/4 for RL to midsupply:
Junction Temperature 150°C
PD = (VS × I S ) +
(VS /4 )2
RL
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress In single-supply operation with RL referenced to VS−, worst case
rating only; functional operation of the device at these or any is VOUT = VS/2.
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute Airflow increases heat dissipation effectively, reducing θJA. In
maximum rating conditions for extended periods may affect addition, more metal directly in contact with the package leads
device reliability. from metal traces, through holes, ground, and power planes
reduces the θJA.
MAXIMUM POWER DISSIPATION
The associated raise in junction temperature (TJ) on the die Figure 3 shows the maximum safe power dissipation in the
limits the maximum safe power dissipation in the AD8067 package vs. the ambient temperature for the SOT-23-5
package. At approximately 150°C, which is the glass transition (180°C/W) package on a JEDEC standard 4-layer board. θJA
temperature, the plastic changes its properties. Even temporarily values are approximations.
exceeding this temperature limit can change the stresses that the It should be noted that for every 10°C rise in temperature, IB
package exerts on the die, permanently shifting the parametric approximately doubles (see Figure 22).
performance of the AD8067. Exceeding a junction temperature
2.0
of 175°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
MAXIMUM POWER DISSIPATION – W

The power dissipated in the package (PD) is the sum of the 1.5

quiescent power dissipation and the power dissipated in the

package due to the load drive. The quiescent power is the
voltage between the supply pins (VS) times the quiescent 1.0

current (IS). Assuming the load (RL) is referenced to midsupply,

the total drive power is VS/2 × IOUT, some of which is dissipated SOT-23-5

in the package and some in the load (VOUT × IOUT). The 0.5

difference between the total drive power and the load power is
the drive power dissipated in the package. RMS output voltages
should be considered. 0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
AMBIENT TEMPERATURE – °C

Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 6 of 24
Data Sheet AD8067

TYPICAL PERFORMANCE CHARACTERISTICS

Default Conditions: VS = ±5 V (@ TA = +25°C, G = +10, RL = RF = 1 kΩ, unless otherwise noted.)

28 20.7
VOUT = 200mV p-p VOUT = 0.2V p-p
G = +20
26 20.6
VOUT = 0.7V p-p
24 20.5
VOUT = 1.4V p-p
22 20.4
G = +10

GAIN – dB
20
GAIN – dB

20.3
G = +8
18
20.2
G = +6
16
20.1
14
20.0
12
19.9
10
19.8
8 1 10 100
1 10 100 FREQUENCY – MHz
FREQUENCY – MHz

Figure 4. Small Signal Frequency Response for Various Gains Figure 7. 0.1 dB Flatness Frequency Response

24
22 VOUT = 200mV p-p CL = 100pF
VOUT = 200mV p-p VS = +5V 23
21
VS = ±5V 22
CL = 25pF
20 21
VS = ±12V
20
GAIN – dB

19
GAIN – dB

19 CL = 100pF
18 RSNUB = 24.9Ω
18
17
17

16 16
CL = 5pF
15 15

14
14 1 10 100
1 10 100 FREQUENCY – MHz
FREQUENCY – MHz

Figure 5. Small Signal Frequency Response for Various Supplies Figure 8. Small Signal Frequency Response for Various CLOAD

22 22
VOUT = 2V p-p VS = +5V
21 21
VS = ±5V VOUT = 0.2V p-p, 2V p-p
20 20
VS = ±12V VOUT = 4V p-p
19 19
GAIN – dB

GAIN – dB

18 18

17 17

16 16

15 15

14 14
1 10 100 1 10 100
FREQUENCY – MHz FREQUENCY – MHz

Figure 6. Large Signal Frequency Response for Various Supplies Figure 9. Frequency Response for Various Output Amplitudes

Rev. B | Page 7 of 24
AD8067 Data Sheet
22 90 120
VOUT = 200mV p-p RF = 2k
80 90
21
RF = 1k
70 60
20 PHASE
60 30
RF = 499

PHASE – Degrees
19
50 0

GAIN – dB
GAIN – dB

18 40 –30
GAIN
30 –60
17
20 –90
16
10 –120

15 0 –150

14 –10 –180
1 10 100 0.01 0.1 1 10 100 1000
FREQUENCY – MHz FREQUENCY – MHz

Figure 10. Small Signal Frequency Response for Various RF Figure 13. Open-Loop Gain and Phase

–40 –40
HD2 RLOAD = 150 G = +10
–50 –50 VOUT = 2V p-p

–60 –60

–70 –70
DISTORTION – dBc

DISTORTION – dBc

HD3 RLOAD = 150 HD2 VS = 12V

–80 HD2 –80
RLOAD = 1k
–90 –90
HD2 VS = 5V
–100 –100

–110 –110
HD3 RLOAD = 1k VOUT = 2V p-p HD3 VS = 12V
–120 –120
HD3 VS = 5V
G = +10
–130 VS = 5V –130

–140 –140
0.1 1 10 100 0.1 1 10 100
FREQUENCY – MHz FREQUENCY – MHz
Figure 11. Distortion vs. Frequency for Various Loads Figure 14. Distortion vs. Frequency for Various Supplies

–20 –30
VS = 12V VS = 12V
G = +10 –40 f = 1MHz
–40 G = +10
–50
HD2 RLOAD = 150
–60
DISTORTION – dBc

DISTORTION – dBc

–60
–70
HD3 RLOAD = 150
–80 –80
HD2 VOUT = 20V p-p

HD3 VOUT = 2V p-p –90

–100 HD2 RLOAD = 1k
HD2 VOUT = 2V p-p –100

HD3 VOUT = 20V p-p –110

–120 HD3 RLOAD = 1k
–120

–140 –130
0.1 1 10 100 0 2 4 6 8 10 12 14 16 18 20 22 24
FREQUENCY – MHz OUTPUT AMPLITUDE – V p-p
Figure 12. Distortion vs. Frequency for Various Amplitudes Figure 15. Distortion vs. Output Amplitude for Various Loads

Rev. B | Page 8 of 24
Data Sheet AD8067

G = +10 CL = 100pF G = +10

VIN = 20mV p-p VIN = 20mV p-p
CL = 0pF

1.5V

50mV/DIV 25ns/DIV 50mV/DIV 25ns/DIV

Figure 16. Small Signal Transient Response 5 V Supply Figure 19. Small Signal Transient Response ± 5 V Supply

10VIN VOUT G = +10 VS = 12V

VIN = 2V p-p
G = +10

2V/DIV 200ns/DIV 5V/DIV 50ns/DIV

Figure 17. Output Overdrive Recovery Figure 20. Large Signal Transient Response

VOUT (1V/DIV) G = +10

VIN (100mV/DIV)

VOUT – 10VIN (5mV/DIV)

+0.1% +0.1%
VIN (100mV/DIV)

VOUT – 10VIN (5mV/DIV)

–0.1% –0.1%

5s/DIV t=0 5ns/DIV

Figure 18. Long-Term Settling Time Figure 21. 0.1% Short-Term Settling Time

Rev. B | Page 9 of 24
AD8067 Data Sheet

14 10

8
12 VS = 12V VS = 5V VS = +5V
6
INPUT BIAS CURRENT – pA

INPUT BIAS CURRENT – pA

10 4

2
8
0
6
–2
VS = ±12V
4 –4

–6
2
–8
VS = ±5V
0 –10
25 35 45 55 65 75 85 –14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14
TEMPERATURE – °C COMMON-MODE VOLTAGE – V

Figure 22. Input Bias Current vs. Temperature Figure 25. Input Bias Current vs. Common-Mode Voltage

1800 5
N = 12255
SD = 0.203
1600 4
MEAN = –0.033
VS = 12V

INPUT OFFSET VOLTAGE – mV

1400 3
VS = 5V
2
1200
1
1000
COUNT

VS = +5V
0
800
–1
600
–2
400
–6

200 –4

0 –5
–1 0 1 –14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14
INPUT OFFSET VOLTAGE – mV COMMON-MODE VOLTAGE – V
Figure 23. Input Offset Voltage Histogram Figure 26. Input Offset Voltage vs. Common-Mode Voltage

1000 –40

–50

–60
100
NOISE – nV/ Hz

–70
CMRR – dB

–80

–90
10

–100

–110

1 –120
1 10 100 1k 10k 100k 1M 10M 100M 0.1 1 10 100
FREQUENCY – Hz FREQUENCY – MHz
Figure 24. Voltage Noise Figure 27. CMRR vs. Frequency

Rev. B | Page 10 of 24
Data Sheet AD8067
6.7
100
G = +10 VS = ±12V
6.6

QUIESCENT CURRENT – mA
10 VS = ±5V
6.5
OUTPUT IMPEDANCE – Ω

VS = +5V
6.4
1

6.3

0.1
6.2

0.01 6.1

6.0
0.001 –40 –20 0 20 40 60 80
0.01 0.1 1 10 100 1000 TEMPERATURE – °C
FREQUENCY – MHz

Figure 28. Output Impedance vs. Frequency Figure 31. Quiescent Current vs. Temperature for Various Supply Voltages

0.30
200
RL = 1kΩ
180
OUTPUT SATURATION VOLTAGE – V

(VCC – VOH), (VOL – VEE), VS = ±12V

OUTPUT SATURATION VOLTAGE – mV

0.25
VCC – VOH 160

0.20 140
VOL – VEE
120
0.15
100
(VCC – VOH), (VOL – VEE), VS = ±5V
80
0.10
VCC – VOH, VS = +5V
60

0.05 40 VOL – VEE, VS = +5V

20
0
0 5 10 15 20 25 30 35 40 0
ILOAD – mA –40 –20 0 20 40 60 80
TEMPERATURE – °C

Figure 29. Output Saturation Voltage vs. Output Load Current Figure 32. Output Saturation Voltage vs. Temperature

0
140
–10
130
–20

–30
120
–PSRR VS = ±12V
OPEN-LOOP GAIN – dB

–40 110
PSRR – dB

–50 100
–60
90
+PSRR
–70 VS = ±5V
80
–80
VS = +5V
70
–90

–100 60
0.01 0.1 1 10 100
FREQUENCY – MHz 50
0 5 10 15 20 25 30 35 40
ILOAD – mA

Figure 30. PSRR vs. Frequency Figure 33. Open-Loop Gain vs. Load Current for Various Supplies

Rev. B | Page 11 of 24
AD8067 Data Sheet

TEST CIRCUITS
+VCC +VCC

10µF 10µF
+ +
0.1µF 0.1µF

110Ω 1kΩ 110Ω 1kΩ

5
VIN 5
4 4
VOUT
AD8067 1 VOUT AD8067 1
49.9Ω 110Ω
VIN 3 RL = 1kΩ 3
2 2 1kΩ
0.1µF 1kΩ 0.1µF

10µF 10µF
+ +
AV = 10

–VEE –VEE

Figure 34. Standard Test Circuit Figure 37. CMRR Test Circuit

+VCC
VIN
10µF
110Ω 1kΩ
+ +VCC
0.1µF

110Ω V– 1kΩ
5
4
VOUT
AD8067 1
5
4 3
VOUT 2 1kΩ
AD8067 1
100Ω 0.1µF
100Ω
3
2 1kΩ
0.1µF 10µF
+
10µF
VOUT
AOL = +
V– –VEE

–VEE

Figure 35. Open-Loop Gain Test Circuit Figure 38. Positive PSRR Test Circuit

+VCC +VCC

10µF
10µF
+
+ 0.1µF
0.1µF

110Ω 1kΩ
110Ω 1kΩ

5
5 4
4 VOUT
RSNUB AD8067 1
AD8067 1 VOUT 100Ω NETWORK ANALYZER
49.9Ω 3
VIN 3 2
2 CLOAD 1kΩ 0.1µF
0.1µF

10µF
10µF
+
+
AV = 10
–VEE
–VEE

Figure 36. Test Circuit for Capacitive Load Figure 39. Output Impedance Test Circuit

Rev. B | Page 12 of 24
Data Sheet AD8067

THEORY OF OPERATION
The AD8067 is a low noise, wideband, voltage feedback 90 120

operational amplifier that combines a precision JFET input 80 90

stage with Analog Devices’ dielectrically isolated eXtra Fast 70 60

Complementary Bipolar (XFCB) process BJTs. Operating 60
PHASE
30
supply voltages range from 5 V to 24 V. The amplifier features a

PHASE – Degrees
50 0
patented rail-to-rail output stage capable of driving within

GAIN – dB
0.25 V of either power supply while sourcing or sinking 30 mA. 40 –30
GAIN
The JFET input, composed of N-channel devices, has a 30 –60
common-mode input range that includes the negative supply 20 –90
rail and extends to 3 V below the positive supply. In addition,
10 –120
the potential for phase reversal behavior was eliminated for all
input voltages within the power supplies. 0 –150

–10 –180
The combination of low noise, dc precision, and high 0.01 0.1 1 10 100 1000
FREQUENCY – MHz
bandwidth makes the AD8067 uniquely suited for wideband,
Figure 41. Open-Loop Frequency Response
very high input impedance, high gain buffer applications. It is
also useful in wideband transimpedance applications, such as a The bandwidth formula only holds true when the phase margin
photodiode interface, that require very low input currents and of the application approaches 90°, which it will in high gain
dc precision. configurations. The bandwidth of the AD8067 used in a
BASIC FREQUENCY RESPONSE G = +10 buffer is 54 MHz, considerably faster than the 30 MHz
predicted by the closed loop –3 dB frequency equation. This
The AD8067’s typical open-loop response (see Figure 41) shows
extended bandwidth is due to the phase margin being at 60°
a phase margin of 60° at a gain of +10. Typical configurations instead of 90°. Gains lower than +10 show an increased amount
for noninverting and inverting voltage gain applications are of peaking, as shown in Figure 4. For gains lower than +7, use
shown in Figure 40 and Figure 42.
the AD8065, a unity gain stable JFET input op amp with a unity
The closed-loop frequency response of a basic noninverting gain bandwidth of 145 MHz, or refer to the Applications section
gain configuration can be approximated by: for using the AD8067 in a lower gain configuration.

RG Table 5. Recommended Values of RG and RF

Closed Loop–3 dB Frequency = (GBP ) ×
(RF + RG ) Gain RG (Ω) RF (kΩ) BW (MHz)
10 110 1 54
DC Gain = RF/RG + 1 20 49.9 1 15
50 20 1 6
GBP is the gain bandwidth product of the amplifier. Typical
100 10 1 3
GBP for the AD8067 is 300 MHz. See Table 5 for the
recommended values for RG and RF.
RF +VS
Noninverting Configuration Noise Gain = +1 0.1µF
+
10µF
RG RX
+
+VS AD8067
+
0.1µF 10µF – RLOAD
RS RX +
+ VOUT
0.1µF 10µF –
AD8067 +
VI
RLOAD RS RG –VS
– +
VOUT RF
0.1µF 10µF – VI
SIGNAL +
SOURCE –VS

RF SIGNAL
RG SOURCE
FOR BEST PERFORMANCE,
SET RS + RX = RG || RF FOR BEST PERFORMANCE, SET RX = (RS + RG) || RF

Figure 40. Noninverting Gain Configuration Figure 42. Inverting Gain Configuration

Rev. B | Page 13 of 24
AD8067 Data Sheet
For inverting voltage gain applications, the source impedance of
+
the input signal must be considered because it sets the application’s RS

noise gain as well as the apparent closed-loop gain. The basic +

CPAR
CM
frequency equation for inverting applications is CD
VI
CM +
RG  RS – VOUT
Closed-Loop –3 dB Frequency  (GBP )  – –
R F  R G  RS
SIGNAL SOURCE RF

RF CPAR
DC Gain  –
RG  RS
RG

where GBP is the gain bandwidth product of the amplifier, and Figure 43. Input and Board Capacitances
RS is the signal source resistance.
RF  RG  RS There is a pole in the feedback loop response formed by
Inverting Configuration Noise Gain  the source impedance seen by the amplifier’s negative input
RG  RS
(RG RF) and the sum of the amplifier’s differential input
It is important that the noise gain for inverting applications be capacitance, common-mode input capacitance, and any board
kept above 6 for stability reasons. If the signal source driving parasitic capacitance. This decreases the loop phase margin and
the inverter is another amplifier, take care that the driving can cause stability problems, that is, unacceptable peaking and
amplifier shows low output impedance through the frequency ringing in the response. To avoid this problem, it is recommended
span of the expected closed-loop bandwidth of the AD8067. that the resistance at the AD8067’s negative input be kept below
200 Ω for all wideband voltage gain applications.
RESISTOR SELECTION FOR WIDEBAND OPERATION
Matching the impedances at the inputs of the AD8067 is also
Voltage feedback amplifiers can use a wide range of resistor
recommended for wideband voltage gain applications. This
values to set their gain. Proper design of the application’s
minimizes nonlinear common-mode capacitive effects that can
feedback network requires consideration of the following issues:
significantly degrade settling time and distortion performance.
 Poles formed by the amplifier’s input capacitances with the
The AD8067 has a low input voltage noise of 6.6 nV/Hz.
resistances seen at the amplifier’s input terminals
Source resistances greater than 500 Ω at either input terminal
 Effects of mismatched source impedances notably increases the apparent referred-to-input (RTI) voltage
noise of the application.
 Resistor value impact on the application’s output
voltage noise The amplifier must supply output current to its feedback
network, as well as to the identified load. For instance, the
 Amplifier loading effects load resistance presented to the amplifier in Figure 40 is
RLOAD  (RF + RG). For an RLOAD of 100 Ω, RF of 1 kΩ, and RG of
The AD8067 has common-mode input capacitances (CM) of
100 Ω, the amplifier is driving a total load resistance of about
1.5 pF and a differential input capacitance (CD) of 2.5 pF. This is
92 Ω. This becomes more of an issue as RF decreases. The
illustrated in Figure 43. The source impedance driving the
AD8067 is rated to provide 30 mA of low distortion output
positive input of a noninverting buffer forms a pole primarily
current. Heavy output drive requirements also increase the
with the amplifier’s common-mode input capacitance as well as
part’s power dissipation and should be taken into account.
any parasitic capacitance due to the board layout (CPAR). This
limits the obtainable bandwidth. For G = +10 buffers, this
bandwidth limit becomes apparent for source impedances >1 kΩ.

Rev. B | Page 14 of 24
Data Sheet AD8067
DC ERROR CALCULATIONS INPUT AND OUTPUT OVERLOAD BEHAVIOR
Figure 44 illustrates the primary dc errors associated with a A simplified schematic of the AD8067 input stage is shown in
voltage feedback amplifier. For both inverting and noninverting Figure 45. This shows the cascoded N-channel JFET input pair,
configurations: the ESD and other protection diodes, and the auxiliary NPN
input stage that eliminates phase inversion behavior.
 R + RF 
Output Voltage Error due to VOS = VOS  G 

 RG  When the common-mode input voltage to the amplifier is
driven to within approximately 3 V of the positive power
 R + RG  supply, the input JFET’s bias current turns off, and the bias of
Output Voltage Error due to I B = I B + × RS  F  – I B– × RF

 RG  the NPN pair turns on, taking over control of the amplifier. The
NPN differential pair now sets the amplifier’s offset, and the
Total error is the sum of the two. input bias current is now in the range of several tens of
microamps. This behavior is illustrated in Figure 25 and Figure 26.
DC common-mode and power supply effects can be added by
Normal operation resumes when the common-mode voltage
modeling the total VOS with the expression:
goes below the 3 V from the positive supply threshold.
ΔVS ΔVCM
VOS (tot ) = VOS (nom) + + The output transistors have circuitry included to limit the
PSR CMR
extent of their saturation when the output is overdriven. This
where: improves output recovery time. A plot of the output recovery
time for the AD8067 used as a G = +10 buffer is shown in
VOS (nom) is the offset voltage specified at nominal conditions Figure 17.
(1 mV max).

∆VS is the change in power supply voltage from nominal VCC

TO REST OF AMP
conditions.
VTHRESHOLD
PSR is power supply rejection (90 dB minimum).
SWITCH VCC VCC
CONTROL
∆VCM is the change in common-mode voltage from nominal test
conditions. VN VP
VBIAS

CMR is the common-mode rejection (85 dB minimum for the

AD8067).
RF VEE VEE

+VOS–
RG
–
IB– + VOUT – VEE

RS Figure 45. Simplified Input Schematic

– VI + +
IB+

Figure 44. Op Amp DC Error Sources

Rev. B | Page 15 of 24
AD8067 Data Sheet
INPUT PROTECTION LAYOUT, GROUNDING, AND BYPASSING
The inputs of the AD8067 are protected with back-to-back CONSIDERATIONS
diodes between the input terminals as well as ESD diodes to Layout
either power supply. The result is an input stage with picoamp In extremely low input bias current amplifier applications, stray
level input currents that can withstand 2 kV ESD events leakage current paths must be kept to a minimum. Any voltage
(human body model) with no degradation. differential between the amplifier inputs and nearby traces sets
up a leakage path through the PCB. Consider a 1 V signal and
Excessive power dissipation through the protection devices
100 GΩ to ground present at the input of the amplifier. The
destroys or degrades the performance of the amplifier.
resultant leakage current is 10 pA; this is 10× the input bias
Differential voltages greater than 0.7 V result in an input
current of the amplifier. Poor PCB layout, contamination, and
current of approximately (| V+ – V− | − 0.7 V)/(RI + RG)),
the board material can create large leakage currents. Common
where RI and RG are the resistors (see Figure 46). For input
contaminants on boards are skin oils, moisture, solder flux, and
voltages beyond the positive supply, the input current is about
cleaning agents. Therefore, it is imperative that the board be
(VI – VCC – 0.7 V)/RI. For input voltages beyond the negative
thoroughly cleaned and the board surface be free of contaminants
supply, the input current is about (VI – VEE + 0.7 V)/RI. For any
to fully take advantage of the AD8067’s low input bias currents.
of these conditions, RI should be sized to limit the resulting
input current to 50 mA or less. To significantly reduce leakage paths, a guard-ring/shield
– + RI
around the inputs should be used. The guard-ring circles the
VI RI > (VI – VEE + 0.7V)/50mA
RI > (VI – VCC – 0.7V)/50mA
input pins and is driven to the same potential as the input
AD8067 FOR VI BEYOND signal, thereby reducing the potential difference between pins.
+ SUPPLY VOLTAGES
RI > ( |V+ – V– | –0.7V)/50mA
RF VOUT For the guard ring to be completely effective, it must be driven
FOR LARGE |V+ – V– | –
RG
by a relatively low impedance source and should completely
surround the input leads on all sides, above, and below, using a
multilayer board (see Figure 47). The SOT-23-5 package
Figure 46. Current Limiting Resistor presents a challenge in keeping the leakage paths to a minimum.
The pin spacing is very tight, so extra care must be used when
CAPACITIVE LOAD DRIVE constructing the guard ring (see Figure 48 for recommended
Capacitive load introduces a pole in the amplifier loop response guard-ring construction).
due to the finite output impedance of the amplifier. This can GUARD RING
cause excessive peaking and ringing in the response. The
AD8067 with a gain of +10 handles up to a 30 pF capacitive
load without an excessive amount of peaking (see Figure 8). If GUARD RING
greater capacitive load drive is required, consider inserting a INVERTING NONINVERTING
small resistor in series with the load (24.9 Ω is a good value to
Figure 47. Guard-Ring Configurations
start with). Capacitive load drive capability also increases as the
gain of the amplifier increases.
VOUT +V VOUT +V
AD8067 AD8067
–V –V

+IN –IN +IN –IN

INVERTING NONINVERTING

Figure 48. Guard-Ring Layout SOT-23-5

Rev. B | Page 16 of 24
Data Sheet AD8067
Grounding Power Supply Bypassing
To minimize parasitic inductances and ground loops in high Power supply pins are actually inputs and care must be taken to
speed, densely populated boards, a ground plane layer is critical. provide a clean, low noise dc voltage source to these inputs. The
Understanding where the current flows in a circuit is critical in bypass capacitors have two functions:
the implementation of high speed circuit design. The length of
the current path is directly proportional to the magnitude of the • Provide a low impedance path for unwanted frequencies
parasitic inductances and thus the high frequency impedance of from the supply inputs to ground, thereby reducing the effect
the path. Fast current changes in an inductive ground return of noise on the supply lines
creates unwanted noise and ringing.
• Provide localized charge storage—this is usually
The length of the high frequency bypass capacitor leads is accomplished with larger electrolytic capacitors
critical. A parasitic inductance in the bypass grounding works
Decoupling methods are designed to minimize the bypassing
against the low impedance created by the bypass capacitor.
impedance at all frequencies. This can be accomplished with a
Because load currents flow from supplies as well as ground, the
combination of capacitors in parallel to ground. Good quality
load should be placed at the same physical location as the
ceramic chip capacitors (X7R or NPO) should be used and
bypass capacitor ground. For large values of capacitors, which
always kept as close to the amplifier package as possible. A
are intended to be effective at lower frequencies, the current
parallel combination of a 0.1 µF ceramic and a 10 µF electrolytic,
return path length is less critical.
covers a wide range of rejection for unwanted noise. The 10 µF
capacitor is less critical for high frequency bypassing, and in
most cases, one per supply line is sufficient.

Rev. B | Page 17 of 24
AD8067 Data Sheet

APPLICATIONS
WIDEBAND PHOTODIODE PREAMP The preamp’s output noise over frequency is shown in Figure 50.
CF
Table 6. RMS Noise Contributions of Photodiode Preamp
RF RMS
Noise
Contributor Expression (µV)1
– RF × 2 2 × 4 kT × R F × f 2 × 1.57 152
CM
IPHOTO CS RSH = 1011Ω CD VOUT Amp to f1 VNOISE × f 1 4.3
CM
(C S + C M + C F + 2C D ) ×
+
Amp (f2 − f1) 96
VB
AD8067 VNOISE × f 2 – f1
CF

(C S + C M + C F + 2C D ) ×
CF + CS RF Amp (Past f2) 684
VNOISE × f 3 × 1.57
CF

Figure 49. Wideband Photodiode Preamp RSS Total 708

1
RMS noise with RF = 50 kΩ, CS = 0.67 pF, CF = 0.33 pF, CM = 1.5 pF, and CD = 2.5 pF.
Figure 49 shows an I/V converter with an electrical model of a
photodiode.

The basic transfer function is 1

f1 = 2 πR (C + C + C + 2C )
F F S M D

I PHOTO × RF 1
VOUT = f2 = 2 πR C
F F
1 + sC F RF
VOLTAGE NOISE – nV/ Hz

GBP
f3 = (C + C + 2C + C )/C
S M D F F

where IPHOTO is the output current of the photodiode, and the

parallel combination of RF and CF sets the signal bandwidth.

The stable bandwidth attainable with this preamp is a function RF NOISE

of RF, the gain bandwidth product of the amplifier, and the total
f3
capacitance at the amplifier’s summing junction, including CS f2 VEN (C F + C S + C M + 2C D )/C F

and the amplifier input capacitance. RF and the total capacitance

f1
produce a pole in the amplifier’s loop transmission that can
result in peaking and instability. Adding CF creates a zero in the VEN NOISE DUE TO AMPLIFIER

loop transmission that compensates for the pole’s effect and

reduces the signal bandwidth. It can be shown that the signal FREQUENCY – Hz

bandwidth resulting in a 45° phase margin (f(45)) is defined by Figure 50. Photodiode Voltage Noise Contributions

GBP Figure 51 shows the AD8067 configured as a transimpedance

f ( 45 ) =
2π × RF × C S photodiode amplifier. The amplifier is used in conjunction with
a JDS uniphase photodiode detector. This amplifier has a
GBP is the unit gain bandwidth product, RF is the feedback bandwidth of 9.6 MHz, as shown in Figure 52, and is verified by
resistance, and CS is the total capacitance at the amplifier the design equations shown in Figure 50.
summing junction (amplifier + photodiode + board parasitics).
0.33pF

The value of CF that produces f(45) can be shown to be 49.9kΩ

+5V
CS 10µF
CF =
2π × RF × GBP 0.1µF
–5V
50Ω
AD8067 VOUT
The frequency response in this case shows about 2 dB of EPM 605 LL

peaking and 15% overshoot. Doubling CF and cutting the 0.1µF

bandwidth in half results in a flat frequency response, with 0.33pF 49.9kΩ
NOTES
about 5% transient overshoot. ID @ –5V = 0.074nA 10µF
CD @ –5V = 0.690pF –5V
RB @ 1550nm = –49dB

Figure 51. Photodiode Preamplifier

Rev. B | Page 18 of 24
Data Sheet AD8067
Test data for the preamp is shown in Figure 52 and Figure 53. USING THE AD8067 AT GAINS OF LESS THAN 8
100 A common technique used to stabilize de-compensated
amplifiers is to increase the noise gain, independent of the
95
signal gain. The AD8067 can be used in applications where the
TRANSIMPEDANCE GAIN – dB

90
signal gain is less than 8, if proper care is taken to ensure that
the noise gain of the amplifier is set to at least the recommended
85 minimum signal gain of 8 (see Figure 54).
80 The signal and noise gain equations for a noninverting
75
amplifier are:
R3
70 Signal Gain = 1 +
R1
65
R3
Noise Gain = 1 +
60 R1
0.01 0.1 1 10 100
FREQUENCY – MHz The addition of resistor R2 modifies the noise gain equation.
Figure 52. Photodiode Preamplifier Frequency Response Note the signal gain equation has not changed.
R3
Noise Gain = 1 +
R1 || R2
C1 RISE
R3
31.2ns 600Ω

T +5V C1
10µF

R1 C2
301Ω 4 5 0.1µF R4
R2 1 51Ω
C1 FALL AD8067 VOUT
50Ω 3
31.6ns VIN 2 C4
0.1µF RL

C3
CH1 500mV M 50ns CH1 830mV –5V 10µF

Figure 54. Gain = 3 Schematics

Figure 53. Photodiode Preamplifier Pulse Response

This technique allows the designer to use the AD8067 in gain

configurations of less than 8. The drawback to this type of
compensation is that the input noise and offset voltages are
also amplified by the value of the noise gain. In addition, the
distortion performance is degraded. To avoid excessive
overshoot and ringing when driving a capacitive load, the
AD8067 should be buffered by a small series resistor; in this
case, a 51 Ω resistor was used.

Rev. B | Page 19 of 24
AD8067 Data Sheet
Reference network:
VOUT
1
V+ REF − 3 dB Bandwidth =
2π(R2 || R3 )C2
T VIN
Resistors R4 and R1 set the gain, in this case, an inverting gain
of 10 was selected. In this application, the input and output
bandwidths were set for approximately 10 Hz. The reference
network was set for a tenth of the input and output bandwidth,
at approximately 1 Hz.
R4
2.7kΩ

+5V C3
CH1 200mV CH2 200mV M 50ns CH1 288mV 10µF

C1 R1
Figure 55. Gain of 3 Pulse Response 47µF 300Ω 4 5 C4 C5
VIN 15µF
0.1µF VOUT
SINGLE-SUPPLY OPERATION 3
AD8067
1
2
The AD8067 is well suited for low voltage single-supply RL
R2 R3 1kΩ
applications, given its N-channel JFET input stage and rail-to- 70kΩ 30kΩ
+5V
rail output stage. It is fully specified for 5 V supplies. Successful
C2
single-supply applications require attention to keep signal 6.8µF
voltages within the input and output headroom limits of the
amplifier. The input stage headroom extends to 1.7 V Figure 56. Single-Supply Operation Schematic
(minimum) on a 5 V supply. The center of the input range is
0.85 V. The output saturation limit defines the hard limit of the
HIGH GAIN, HIGH BANDWIDTH COMPOSITE
output headroom. This limit depends on the amount of current
AMPLIFIER
the amplifier is sourcing or sinking, as shown in Figure 29. The composite amplifier takes advantage of combining key
parameters that can otherwise be mutually exclusive of a
Traditionally, an offset voltage is introduced in the input conventional single amplifier. For example, most precision
network replacing ground as a reference. This allows the output amplifiers have good dc characteristics but lack high speed ac
to swing about a dc reference point, typically midsupply. characteristics. Composite amplifiers combine the best of both
Attention to the required headroom of the amplifier is amplifiers to achieve superior performance over their single op
important, in this case, the required headroom from the amp counterparts. The AD8067 and the AD8009 are well suited
positive supply is 3 V; therefore, 1.5 V was selected as a for a composite amplifier circuit, combining dc precision with
reference, which allows for a 100 mV signal at the input. Figure 56 high gain and bandwidth. The circuit runs off a ±5 V power
shows the AD8067 configured for 5 V supply operation with a supply at approximately 20 mA of bias current. With a gain of
reference voltage of 1.5 V. Capacitors C1 and C5 ac couple the approximately 40 dB, the composite amplifier offers <1 pA
signal into and out of the amplifier and partially determine the input current, a gain bandwidth product of 6.1 GHz, and a slew
bandwidth of the input and output structures. rate of 630 V/µs.
1
VINPUT – 3 dB Bandwidth =
2πR1C1
1
VOUTPUT – 3 dB Bandwidth =
2πRL C5

Resistors R2 and R3 set a 1.5 V output bias point for the output
signal to swing about. It is critical to have adequate bypassing to
provide a good ac ground for the reference voltage. Generally,
the bandwidth of the reference network (R2, R3, and C2) is
selected to be one tenth that of the input bandwidth. This
ensures that any frequencies below the input bandwidth do not
pass through the reference network into the amplifier.

Rev. B | Page 20 of 24
Data Sheet AD8067
R2 44
4.99kΩ
42
+5V C1
10µF C8
C7 +5V 40
10µF 0.1µF
R1 38
51.1Ω 4 C2
5
1 0.1µF 3 7 C6 36
INPUT AD8067 0.001µF OUTPUT
C4 C5 6

dB
3 AD8009 34
2 0.1µF 5pF
2 C10 R5
4 0.001µF 50Ω 32

C3 30
–5V 10µF C9 C11
10µF –5V 0.01µF 28
R4
200Ω
26
R3
21.5Ω 24
0.1 1 10 100
FREQUENCY – MHz
Figure 57. AD8067/AD8009 Composite Amplifier AV = 100, GBWP = 6.1 GHz
Figure 58. Gain Bandwidth Response
The composite amplifier is set for a gain of 100. The overall gain
is set by
VO R2
= +1 C1 AMPL
VI R1 4V

The output stage is set for a gain of 10; therefore, the AD8067
has an effective gain of 10, thereby allowing it to maintain a
bandwidth in excess of 55 MHz. T

The circuit can be tailored for different gain values; keeping the
ratios roughly the same ensures that the bandwidth integrity is
maintained. Depending on the board layout, Capacitor C5 can
be required to reduce ringing on the output. The gain bandwidth
and pulse responses are shown in Figure 58, Figure 59, and CH1 1V M 25ns CH1 0V
Figure 60.
Figure 59. Large Signal Response
Layout of this circuit requires attention to the routing and
length of the feedback path. It should be kept as short as
possible to minimize stray capacitance.
C1 AMPL
480mV

CH1 200mV M 25ns CH1 0V

Figure 60. Small Signal Response

Rev. B | Page 21 of 24
AD8067 Data Sheet

OUTLINE DIMENSIONS
3.00
2.90
2.80

5 4 3.00
1.70
1.60 2.80
1.50 2.60
1 2 3

0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX 0.20 MAX
0.95 MIN 0.08 MIN
0.55
0.15 MAX 10° 0.45
0.05 MIN SEATING 5° 0.60
0.50 MAX PLANE BSC 0.35
0.35 MIN 0°

11-01-2010-A
COMPLIANT TO JEDEC STANDARDS MO-178-AA

Figure 61. 5-Lead Small Outline Transistor Package [SOT-23}

(RJ-5)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option Branding 2
AD8067ART-REEL –40°C to +85°C 5-Lead SOT-23 RT-5 HAB
AD8067ART-R2 –40°C to +85°C 5-Lead SOT-23 RT-5 HAB
AD8067ARTZ-REEL –40°C to +85°C 5-Lead SOT-23 RT-5 HAB#
AD8067ARTZ-REEL7 –40°C to +85°C 5-Lead SOT-23 RT-5 HAB#
AD8067ARTZ-R2 –40°C to +85°C 5-Lead SOT-23 RT-5 HAB#
AD8067ART-EBZ –40°C to +85°C Evaluation Board for 5-Lead SOT-23
1
Z = RoHS Compliant Part.
2
# denotes lead-free product may be top or bottom marked.

Rev. B | Page 22 of 24
Data Sheet AD8067

NOTES

Rev. B | Page 23 of 24
AD8067 Data Sheet

NOTES

©2002–2012 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D03205–0–4/12(B)

Rev. B | Page 24 of 24