Tas 5706
Tas 5706
Tas 5706
www.ti.com
SLOS550A – DECEMBER 2007 – REVISED DECEMBER 2007
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 PurePath Digital is a trademark of Texas Instruments.
3 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas Copyright © 2007, Texas Instruments Incorporated
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TAS5706
www.ti.com
SLOS550A – DECEMBER 2007 – REVISED DECEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DVDD/AVDD AVCC/PVCC
OUT_A
LRCLK
SCLK BST_A
Digital
Audio MCLK LCBTL* Left
Source BST_B
SDIN1
SDIN2
OUT_B
2 OUT_C
I C SDA
Control SCL
BST_C
LCBTL* Right
BST_D
MUTE
Control HPSEL OUT_D
Inputs RESET
PDN TAS5601 10 V–26 V
SUB_PWM+ PWM_AP
OUT_A
PWM_AN
SUB_PWM– PWM_BP BST_A
PLL_FLTP LCBTL* Subwoofer
Loop BST_B
Filter PWM_BN
PLL_FLTM OUT_B
BKND_ERR FAULT
VALID RESET
HPR_PWM
RC
Filter
HPL_PWM
TPA6110A2
(HP Amplifier)
* Refer to TI Application Note (SLOA119) on LC filter design for BTL (AD/BD mode) configuration.
B0264-02
DVDD/AVDD AVCC/PVCC
OUT_A LCSE*
LRCLK
SCLK BST_A
Digital
Audio MCLK
Source
SDIN1
BST_B
SDIN2
OUT_B LCSE*
2 SDA
I C
Control SCL
MUTE OUT_C
Control HPSEL
Inputs RESET BST_C
LCBTL*
PDN
BST_D
OUT_D
PLL_FLTP
Loop
Filter SUB_PWM+
PLL_FLTM SUB_PWM–
BKND_ERR
VALID
HPR_PWM
RC
Filter
HPL_PWM
TPA6110A2
(HP Amplifier)
DVDD/AVDD AVCC/PVCC
OUT_A LCSE*
LRCLK
SCLK BST_A
Digital
Audio MCLK
Source
SDIN1
BST_B
SDIN2
OUT_B LCSE*
2 SDA
I C
Control SCL
Control HPSEL
Inputs RESET BST_C
PDN
BST_D
OUT_D LCSE*
PLL_FLTP
Loop
Filter SUB_PWM+
PLL_FLTM SUB_PWM–
BKND_ERR
VALID
HPR_PWM
RC
Filter
HPL_PWM
TPA6110A2
(HP Amplifier)
FUNCTIONAL VIEW
TERMINAL FUNCTIONS
TERMINAL TYPE 5-V TERMINATION
(1) (2) DESCRIPTION
NAME NO. TOLERANT
AGND 57 P Analog ground for power stage
AVCC 58 P Analog power supply for power stage. Connect externally to same
potential as PVCC.
AVDD 10 P 3.3-V analog power supply
AVSS 11 P Analog 3.3-V supply ground
BKND_ERR 35 DI Pullup Active-low. A back-end error sequence is generated by applying logic
LOW to this terminal. This terminal is connected to an external power
stage. If no external power stage is used, connect this terminal directly
to DVDD.
(1) Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are
not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) 5-V tolerant inputs are PDN, RESET, MUTE, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDA, SCL, and HPSEL.
DISSIPATION RATINGS
TA = 25°C TA = 45°C TA = 70°C
PACKAGE (1) DERATING FACTOR
POWER RATING POWER RATING POWER RATING
10-mm × 10-mm QFP 29 mW/°C 2.89 W 2.31 W 1.59 W
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ELECTRICAL CHARACTERISTICS
DC Characteristics, TA = 25°C, PVCC_X, AVCC = 18 V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1)
VOH High-level output voltage 3.3-V TTL and 5-V tolerant IOH = –4 mA 2.4 V
(1)
VOL Low-level output voltage 3.3-V TTL and 5-V tolerant IOL = 4 mA 0.5 V
| VOS | Class-D output offset voltage ±26 mV
VBYPASS PVCC/8 reference for analog section No load 2.2 2.26 2.3 V
3.3-V TTL VI = VIL ±2
IIL Low-level input current µA
5-V tolerant (1) VI = 0 V, DVDD = 3 V ±2
3.3-V TTL VI = VIH ±2
IIH High-level input current µA
5-V tolerant VI = 5.5 V, DVDD = 3 V ±20
Normal mode 43 65 80
Power down 2 8 16
IDD Input supply current Supply voltage (DVDD, AVDD) mA
(PDNZ = LOW)
Reset (RESET = LOW) 11 23 33
ICC Quiescent supply current No load 14 33 57 mA
ICC(RESET) Quiescent supply current in reset mode No load 58 176 µA
ICC(PDNZ) Quiescent supply current in power down mode No load 58 176 µA
PSRR DC power-supply rejection ratio PVCC = 17.5 V to 18.5 V 60 dB
Drain-source on-state resistance, high-side VCC = 18 V , IO = 500 mA, 240
TJ = 25°C
RDS(on) Low-side 240 mΩ
Total 480 850
Turnon time (SE mode) (Set Reg 0x1A bit 7 to 1) C(BYPASS) = 1 µF, 500
tON Time required for the ms
Turnon time (BTL mode) (Set Reg 0x1A bit 7 to 0) 30
C(BYPASS) to reach its final
Turnoff time (SE mode) (Set Reg 0X1A bit 7 to 1) value 500
tOFF ms
Turnoff time (BTL mode) (Set Reg 0X1A bit 7 to 0) 30
(1) 5-V tolerant pins are PDN, RESET, MUTE, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDA, SCL, and HPSEL.
tw(H) tw(L) tr tf
SCL
tsu1 th1
SDA
T0027-01
SCL
th2 t(buf)
tsu2 tsu3
SDA
Start Stop
Condition Condition
T0028-01
VALID
td(I2C_ready)
PDN
tw
VALID
tw(ER)
BKND_ERR
tp(valid_low)
T0031-04
(1) Stepsize = 4 LRCLKs (for 32–48 kHz sample rate); 8 LRCLKs (for 88.2–96 kHz sample rate); 16 LRCLKs (for 176.4–192 kHz sample
rate)
MUTE
td(VOL) td(VOL)
50-50
Duty Cycle
T0032-03
(1) Defined by rate setting. See the Volume Configuration Register section.
Figure 8 and Figure 9 show functionality when bit 4 in HP configuration register is set to DISABLE line output from HP_PWM outputs. If
bit 4 is not set, than the HP PWM outputs are not disabled when HPSEL is brought low.
HPSEL
Spkr Volume
td(VOL)
HP Volume
td(VOL)
t(SW)
VALID
T0267-01
HPSEL
HP Volume
td(VOL)
Spkr Volume
td(VOL)
t(SW)
VALID
T0268-01
P = 2.5 W P=5W
0.1 0.1
0.01 0.01
P = 0.5 W P=1W
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz
G001 G002
TOTAL HARMONIC DISTORTION + NOISE (BTL) TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs vs
FREQUENCY OUTPUT POWER
10 10
THD+N − Total Harmonic Distortion + Noise − %
VCC = 24 V VCC = 12 V
RL = 8 Ω RL = 8 Ω
1 P = 10 W 1
f = 10 kHz
P=5W f = 1 kHz
0.1 0.1
0.01 0.01
P=1W
f = 20 Hz
0.001 0.001
20 100 1k 10k 20k 0.01 0.1 1 10 40
f − Frequency − Hz PO − Output Power − W
G003 G004
TOTAL HARMONIC DISTORTION + NOISE (BTL) TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs vs
OUTPUT POWER OUTPUT POWER
10 10
THD+N − Total Harmonic Distortion + Noise − %
1 1
f = 10 kHz f = 10 kHz
f = 1 kHz f = 1 kHz
0.1 0.1
0.01 0.01
f = 20 Hz f = 20 Hz
0.001 0.001
0.01 0.1 1 10 40 0.01 0.1 1 10 40
PO − Output Power − W PO − Output Power − W
G005 G006
90 RL = 8 Ω
2.5 VCC = 18 V
80
ICC − Supply Current − A
70 VCC = 24 V
VCC = 18 V 2.0 VCC = 12 V
Efficiency − %
60 VCC = 12 V
50 1.5
40
1.0
30
20 VCC = 24 V
0.5
10 RL = 8 Ω
0 0.0
0 5 10 15 20 25 30 0 5 10 15 20 25 30 35 40
PO − Output Power (Per Channel) − W PO − Total Output Power − W
G007 G008
RL = 8 Ω −10
35
−20
30
−30
PO − Output Power − W
25 THD+N = 10%
−40
PSRR − dB
20 −50
−60
15 THD+N = 1%
−70
10
−80
5
−90
0 −100
10 12 14 16 18 20 22 24 26 10 12 14 16 18 20 22 24 26
VCC − Supply Voltage − V PVCC − V
G009 G010
−76 −50
−77 −60
Right to Left
−78 −70
A-Wtd Noise − dBV
Crosstalk − dB
−81 −100
−82 −110
−83 −120
−84 −130 RL = 8 Ω
VCC = 12 V
−85 −140
10 12 14 16 18 20 22 24 26 20 100 1k 10k 20k
PVCC − V f − Frequency − Hz
G011 G012
CROSSTALK CROSSTALK
vs vs
FREQUENCY FREQUENCY
−40 −40
−50 −50
−60 −60
Right to Left Right to Left
−70 −70
Crosstalk − dB
Crosstalk − dB
−80 −80 Left to Right
Left to Right
−90 −90
−100 −100
−110 −110
−120 −120
−130 RL = 8 Ω −130 RL = 8 Ω
VCC = 18 V VCC = 24 V
−140 −140
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz
G013 G014
f = 1 kHz
RL = 4 Ω RL = 4 Ω
1 1
VCC = 12 V
VCC = 12 V
0.1 0.1
VCC = 24 V
VCC = 24 V
0.01 0.01
VCC = 18 V VCC = 18 V
0.001 0.001
20 100 1k 10k 20k 0.01 0.1 1 10 40
f − Frequency − Hz PO − Output Power − W
G015 G016
90 RL = 4 Ω
VCC = 18 V
80
1.5
VCC = 24 V
60
VCC = 12 V
50 1.0
40 VCC = 24 V
30
0.5
20
10 RL = 4 Ω
0 0.0
0 5 10 15 20 25 0 5 10 15 20 25 30 35 40
PO − Output Power (Per Channel) − W PO − Total Output Power − W
G017 G018
OUTPUT POWER
vs
SUPPLY VOLTAGE
20
18 RL = 4 Ω
16
14
PO − Output Power − W
12 THD+N = 10%
10
8
THD+N = 1%
6
0
10 12 14 16 18 20 22 24 26
VCC − Supply Voltage − V
G019
Figure 28.
DETAILED DESCRIPTION
POWER SUPPLY
The digital portion of the chip requires 3.3 V, and the power stages can work from 10 V to 26 V.
PWM Section
The TAS5706 DAP device uses noise-shaping and sophisticated error correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper that
has >100-dB SNR performance from 20 Hz to 20 kHz. The PWM section accepts 24-bit PCM data from the DAP
and outputs four PWM audio output channels. TAS5706 PWM section output supports bridge-tied loads.
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz. Individual channel de-emphasis filters for 32-, 44.1-, and 48-kHz are included and
can be enabled and disabled.
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
LF Noise Out_A
1 7 0x11
Vol1 Shaper LF–
BQ
AD/BD
drc1_ coeff
DRC1
DRC2
6
Figure 29. TAS5706 DAP Data Flow Diagram With I2C Registers
HPL
6
HPR
23
TAS5706
www.ti.com
SLOS550A – DECEMBER 2007 – REVISED DECEMBER 2007
I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
2
2-Channel I S (Philips Format) Stereo Input
32 Clks 32 Clks
SCLK SCLK
23 22 9 8 5 4 1 0 23 22 9 8 5 4 1 0
20-Bit Mode
19 18 5 4 1 0 19 18 5 4 1 0
16-Bit Mode
15 14 1 0 15 14 1 0
T0034-01
2
2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)
24 Clks 24 Clks
SCLK SCLK
23 22 17 16 9 8 5 4 3 2 1 0 23 22 17 16 9 8 5 4 3 2 1
20-Bit Mode
19 18 13 12 5 4 1 0 19 18 13 12 5 4 1 0
16-Bit Mode
15 14 9 8 1 0 15 14 9 8 1 0
T0092-01
2
2-Channel I S (Philips Format) Stereo Input
16 Clks 16 Clks
SCLK SCLK
15 14 13 12 11 10 9 8 5 4 3 2 1 0 15 14 13 12 11 10 9 8 5 4 3 2 1
T0266-01
Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
2-Channel Left-Justified Stereo Input
32 Clks 32 Clks
LRCLK
SCLK SCLK
23 22 9 8 5 4 1 0 23 22 9 8 5 4 1 0
20-Bit Mode
19 18 5 4 1 0 19 18 5 4 1 0
16-Bit Mode
15 14 1 0 15 14 1 0
T0034-02
24 Clks 24 Clks
LRCLK
SCLK SCLK
23 22 21 17 16 9 8 5 4 1 0 23 22 21 17 16 9 8 5 4 1 0
20-Bit Mode
19 18 17 13 12 5 4 1 0 19 18 17 13 12 5 4 1 0
16-Bit Mode
15 14 13 9 8 1 0 15 14 13 9 8 1 0
T0092-02
16 Clks 16 Clks
LRCLK
SCLK SCLK
15 14 13 12 11 10 9 8 5 4 3 2 1 0 15 14 13 12 11 10 9 8 5 4 3 2 1 0
T0266-02
Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks
unused leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks 32 Clks
LRCLK
SCLK SCLK
23 22 19 18 15 14 1 0 23 22 19 18 15 14 1 0
20-Bit Mode
19 18 15 14 1 0 19 18 15 14 1 0
16-Bit Mode
15 14 1 0 15 14 1 0
T0034-03
24 Clks 24 Clks
LRCLK
SCLK SCLK
23 22 19 18 15 14 6 5 2 1 0 23 22 19 18 15 14 6 5 2 1 0
20-Bit Mode
19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0
16-Bit Mode
15 14 6 5 2 1 0 15 14 6 5 2 1 0
T0092-03
The TAS5706 DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read operations.
This is a slave only device that does not support a multimaster bus environment or wait state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation
(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SCL
Start Stop
T0035-01
2
Figure 39. Typical I C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 39.
The 7-bit address for TAS5706 is 0011 011 (0x36).
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5706
also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for
that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the
data for all 16 subaddresses is successfully received by the TAS5706. For I2C sequential write transactions, the
subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or
start is transmitted, determines how many subaddresses are written. As was true for random addressing,
sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to
the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted;
only the incomplete data is discarded.
Single-Byte Write
As shown in Figure 40, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I2C device
address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the
address byte or bytes corresponding to the TAS5706 internal memory address being accessed. After receiving
the address byte, the TAS5706 again responds with an acknowledge bit. Next, the master device transmits the
data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5706 again
responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the
single-byte data write transfer.
Start
Condition Acknowledge Acknowledge Acknowledge
2 Stop
I C Device Address and Subaddress Data Byte
Read/Write Bit Condition
T0036-01
Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 41. After receiving each data byte, the
TAS5706 responds with an acknowledge bit.
Start
Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge
2 Stop
I C Device Address and Subaddress First Data Byte Other Data Bytes Last Data Byte
Read/Write Bit Condition
T0036-02
Single-Byte Read
As shown in Figure 42, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5706 address
and the read/write bit, TAS5706 responds with an acknowledge bit. In addition, after sending the internal memory
address byte or bytes, the master device transmits another start condition followed by the TAS5706 address and
the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the
address and the read/write bit, the TAS5706 again responds with an acknowledge bit. Next, the TAS5706
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer.
Repeat Start
Condition
Start Not
Condition Acknowledge Acknowledge Acknowledge Acknowledge
2 2
I C Device Address and Subaddress I C Device Address and Data Byte Stop
Read/Write Bit Read/Write Bit Condition
T0036-03
Multiple-Byte Read
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TAS5706 to the master device as shown in Figure 43. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start Not
Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge
2 2
I C Device Address and Subaddress I C Device Address and First Data Byte Other Data Bytes Last Data Byte Stop
Read/Write Bit Read/Write Bit Condition
T0036-04
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• One DRC for left/right and one DRC for subwoofer
• Each DRC has adjustable threshold, offset, and compression levels
• Programmable energy, attack, and decay time constants
• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Attack
Audio Input Energy Compression and
DRC Coefficient
Filter Control Decay
Filters
a, w T, K, O aa, wa / ad, wd
S
a –1
w
Z
B0265-01
Loudness Function
The TAS5706 provides a direct form I biquad for loudness on the subwoofer channel. The first biquad is
contained in a gain-compensation circuit that maintains the overall system gain at 1 or less to prevent clipping at
loud volume settings. This gain compensation is shown in Figure 46
1 if Vol £ 1/G
0 if Vol ³ 1/G + 1/Scale
1 - Scale (Vol - 1/G) otherwise
From To
Input Output
Mux Loudness Mux
Volume Biquad (0x23) Biquad (0x24)
Gain = G
B0273-01
Table 1. Loudness Table Example for Gain = 4, 1/G = 0.25, Scale = 1.33
Volume 0.125 0.25 0.375 0.5 0.625 0.75 0.875 1 1.125 1.25 1.375 1.5 1.625 1.75 1.875 2
Biquad path 1 1 0.833 0.666 0.5 0.333 0.166 0 0 0 0 0 0 0 0 0
Direct path 0 0 0.166 0.333 0.5 0.666 0.833 1 1 1 1 1 1 1 1 1
Total gain 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
The biquads are implemented in a direct form-I architecture. The direct form-I structure provides a separate delay
element and mixer (gain coefficient) for each node in the biquad filter.
The five 26-bit (3.23) coefficients for the biquad are programmable via the I2C interface.
The following steps are involved in using a loudness biquad with the volume compensation feature:
1. Program the biquad with a loudness filter.
2. Program 0x26 (1/G) and 0x28 (scale).
3. Enable volume compensation in register 0x0E.
b0
b1 a1
–1 –1
z z
b2 a2
–1 –1
z z
M0012-02
BANK SWITCHING
The TAS5706 uses an approach called bank switching together with automatic sample-rate detection. All
processing features that must be changed for different sample rates are stored internally in the TAS5706. The
TAS5706 has three full banks storing information, one for 32 kHz, one for 44.1/48 kHz, and one for all other data
rates. Combined with the clock-rate autodetection feature, bank switching allows the TAS5706 to detect
automatically a change in the input sample rate and switch to the appropriate bank without any MCU
intervention.
The TAS5706 supports three banks of coefficients to be updated during the initialization. One bank is for 32 kHz
, a second bank is for 44.1/48 kHz, and a third bank is for all other sample rates. An external controller updates
the three banks (see the I2C register mapping table for bankable locations) during the initialization sequence.
If the autobank switch is enabled (register 0x50, bits 2:0) , then the TAS5706 automatically swaps the
coefficients for subsequent sample rate changes, avoiding the need for any external controller intervention for a
sample rate change.
By default, bits 2:0 have the value 000; that means the bank switch is disabled. In that state, any update to
locations 0x29–0x3F go into the DAP. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the
system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any
subsequent write to locations 0x29-0x3F updates the coefficient banks stored outside the DAP. After updating all
the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes
the system state to automatic bank update. In automatic bank update, the TAS5706 automatically swaps banks
based on the sample rate.
In the headphone mode, speaker equalization and DRC are disabled, and they are restored upon returning to the
speaker mode.
Command sequences for initialization can be summarized as follows:
1. Enable factory trim for internal oscillator: Write to register 0x1B with a value 0x00.
2. Update coefficients: Coefficients can be loaded into DAP RAM using the manual bank mode.
OR
Use automatic bank mode.
a. Enable bank-1 mode: Write to register 0x50 with 0x01. Load the 32-kHz coefficients. TI ALE
can generate coefficients.
b. Enable bank-2 mode: Write to register 0x50 with 0x02. Load the 48-kHz coefficients.
c. Enable bank-3 mode: Write to register 0x50 with 0x03. Load the other coefficients.
d. Enable automatic bank switching by writing to register 0x50 with 0x04.
3. Bring the system out of all-channel shutdown: Write 0 to bit 6 of register 0x05.
4. Issue master volume: Write to register 0x07 with the volume value (0 db = 0x30).
APPLICATION INFORMATION
For the TAS5706 controller, the gain is the programmed digital gain multiplied by a scaling factor, called the
maximum modulation level. The maximum modulation level is derived from the modulation limit programmed in
the controller, which limits duty cycle to a set number of percent above 0% and below 100%. Setting the
modulation limit to 97.7% (default) limits the duty cycle between 2.3% and 97.7%.
Controller gain = digital gain × maximum modulation level × (modulation level/digital FFS)
Digital FFS = digital input fraction of full scale
Modulation limit = 97.7%
Maximum modulation level = 2 × modulation limit – 1 = 0.954
The output signal level of the TAS5706 can now be calculated.
VRMS = digital FFS × digital gain × maximum modulation level × 13
With the modulation limit set at the default level of 97.7%, this becomes:
VRMS = digital FFS × digital gain × 12.4 (Single-ended)
VRMS = digital FFS × digital gain × 24.8 (BTL)
Example: Input = –20 dbFS; volume = 0 dB; biquads = ALL PASS; modulation index = 97.7%; mode = BTL
Output VRMS = 24.8 × 0.1 × 1 = 2.48 V
Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must
clear the register (write zeroes) and then read them to determine if there are any persistent errors.
Bit D3 defines which volume register is used to control the volume of the HP_PWMx outputs when in headphone
mode. When set to 0, the HP volume register (0x0C) controls the volume of the headphone outputs when in
headphone mode. When bit D3 is set to 1, the channel volume registers (0x08–0x0B, 0x0D) are used for all
modes (line out, headphone, speaker).
Bits D2–D1 define the output modes. The default is speaker mode with the headphone mode selectable via the
external HPSEL terminal. The device can also be forced into headphone mode by asserting bit D1 (all other
PWM channels are muted). Asserting bit D2 puts the device into a pseudo-line-out mode where the HP_PWMx
and all other PWM channels are active. Bit D3 must also be asserted in this mode, and the HP_PWMx volume is
controlled with the main speaker output volume controls via registers 0x08–0x0B and 0x0D..
1 1 1 1 1 1 1 0 –100 dB
(1)
1 1 1 1 1 1 1 1 MUTE (default for master volume); 50% duty cycle at output – SOFT MUTE
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 – – – – – – – Reserved
– 1 0 0 – – – – Reserved
– 1 0 1 – – – – Reserved
– 1 1 0 – – – – Ground (0) to channel 5
– 1 1 1 – – – – Ch6 (BTL–) to channel 5—BTL pair to channel 6
(2)
– – – – 0 – – – Channel 6 AD mode
– – – – 1 – – – Channel 6 BD mode
– – – – – 0 0 0 SDIN1-L to channel 6
– – – – – 0 0 1 SDIN1-R to channel 6
(2)
– – – – – 0 1 0 SDIN2-L to channel 6
– – – – – 0 1 1 SDIN2-R to channel 6
– – – – – 1 0 0 Reserved
– – – – – 1 0 1 Reserved
(2)
– – – – – 1 1 0 Ground (0) to channel 6
– – – – – 1 1 1 Reserved
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
(1)
– – – – – – – 1 Enable data from input multiplexer 1 to downmix block
– – – – – – – 0 Disable data from input multiplexer 1 to downmix block
(1)
– – – – – – 1 – Enable data from input multiplexer 2 to downmix block
– – – – – – 0 – Disable data from input multiplexer 2 to downmix block
(1)
0 0 0 0 0 0 – – Reserved
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
X X X X – – – – BCD frequency (10s kHz)
– – – – X X X X BCD frequency (1s kHz)
(1)
0 0 0 0 0 0 0 0 Default value
OR
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
X X X X X X X X Binary frequency
(1)
0 0 0 0 0 0 0 0 Default value
Bits D30–D25: Selects which PWM channel is output to HPL_PWM and HPR_PWM
Bits D23–D20: Selects which PWM channel is output to OUT_A
Bits D19–D16: Selects which PWM channel is output to OUT_B
Bits D15–D12: Selects which PWM channel is output to OUT_C
Bits D11–D08: Selects which PWM channel is output to OUT_D
Bits D07–D04: Selects which PWM channel is output to SUB_PWM–
Bits D03–D00: Selects which PWM channel is output to SUB_PWM+
Note that channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, …, channel 6 = 0x05.
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 – – – Multiplex channel 1 to SUB_PWM–
0 0 0 1 – – – – Multiplex channel 2 to SUB_PWM–
0 0 1 0 – – – – Multiplex channel 3 to SUB_PWM–
0 0 1 1 – – – – Multiplex channel 4 to SUB_PWM–
(2)
0 1 0 0 – – – – Multiplex channel 5 to SUB_PWM–
0 1 0 1 – – – – Multiplex channel 6 to SUB_PWM–
– – – – 0 0 0 0 Multiplex channel 1 to SUB_PWM+
– – – – 0 0 0 1 Multiplex channel 2 to SUB_PWM+
– – – – 0 0 1 0 Multiplex channel 3 to SUB_PWM+
– – – – 0 0 1 1 Multiplex channel 4 to SUB_PWM+
– – – – 0 1 0 0 Multiplex channel 5 to SUB_PWM+
(2)
– – – – 0 1 0 1 Multiplex channel 6 to SUB_PWM+
www.ti.com 29-Apr-2009
PACKAGING INFORMATION
Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
TAS5706PAP NRND HTQFP PAP 64 160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TAS5706PAPG4 NRND HTQFP PAP 64 160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TAS5706PAPR NRND HTQFP PAP 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TAS5706PAPRG4 NRND HTQFP PAP 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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to Customer on an annual basis.
Addendum-Page 1
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