cc2541 PDF

CC2541
www.ti.com SWRS110D – JANUARY 2012 – REVISED JUNE 2013
2.4-GHz Bluetooth™ low energy and Proprietary System-on-Chip

Check for Samples: CC2541
1FEATURES
23 • RF – High-Performance and Low-Power 8051
– 2.4-GHz Bluetooth low energy Compliant Microcontroller Core With Code Prefetch
and Proprietary RF System-on-Chip – In-System-Programmable Flash, 128- or
– Supports 250-kbps, 500-kbps, 1-Mbps, 2- 256-KB
Mbps Data Rates – 8-KB RAM With Retention in All Power
– Excellent Link Budget, Enabling Long- Modes
Range Applications Without External Front – Hardware Debug Support
End – Extensive Baseband Automation, Including
– Programmable Output Power up to 0 dBm Auto-Acknowledgment and Address
– Excellent Receiver Sensitivity (–94 dBm at Decoding
1 Mbps), Selectivity, and Blocking – Retention of All Relevant Registers in All
Performance Power Modes
– Suitable for Systems Targeting Compliance • Peripherals
With Worldwide Radio Frequency – Powerful Five-Channel DMA
Regulations: ETSI EN 300 328 and EN 300 – General-Purpose Timers (One 16-Bit, Two
440 Class 2 (Europe), FCC CFR47 Part 15 8-Bit)
(US), and ARIB STD-T66 (Japan)
– IR Generation Circuitry
• Layout
– 32-kHz Sleep Timer With Capture
– Few External Components
– Accurate Digital RSSI Support
– Reference Design Provided
– Battery Monitor and Temperature Sensor
– 6-mm × 6-mm QFN-40 Package
– 12-Bit ADC With Eight Channels and
– Pin-Compatible With CC2540 (When Not Configurable Resolution
Using USB or I2C)
– AES Security Coprocessor
• Low Power
– Two Powerful USARTs With Support for
– Active-Mode RX Down to: 17.9 mA Several Serial Protocols
– Active-Mode TX (0 dBm): 18.2 mA – 23 General-Purpose I/O Pins
– Power Mode 1 (4-µs Wake-Up): 270 µA (21 × 4 mA, 2 × 20 mA)
– Power Mode 2 (Sleep Timer On): 1 µA – I2C interface
– Power Mode 3 (External Interrupts): 0.5 µA – 2 I/O Pins Have LED Driving Capabilities
– Wide Supply-Voltage Range (2 V–3.6 V) – Watchdog Timer
• TPS62730 Compatible Low Power in Active – Integrated High-Performance Comparator
Mode
• Development Tools
– RX Down to: 14.7 mA (3-V supply)
– CC2541 Evaluation Module Kit
– TX (0 dBm): 14.3 mA (3-V supply) (CC2541EMK)
White space
– CC2541 Mini Development Kit (CC2541DK-
White space
MINI)
White space
White space – SmartRF™ Software
White space – IAR Embedded Workbench™ Available
White space
•
1
Microcontroller
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 Bluetooth is a trademark of Bluetooth SIG, Inc..
3 ZigBee is a registered trademark of ZigBee Alliance.
PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CC2541
SWRS110D – JANUARY 2012 – REVISED JUNE 2013 www.ti.com
SOFTWARE FEATURES CC2541 WITH TPS62730

• Bluetooth v4.0 Compliant Protocol Stack for • TPS62730 is a 2-MHz Step-Down Converter
Single-Mode BLE Solution With Bypass Mode
– Complete Power-Optimized Stack, • Extends Battery Lifetime by up to 20%
Including Controller and Host • Reduced Current in All Active Modes
– GAP – Central, Peripheral, Observer, or • 30-nA Bypass Mode Current to Support Low-
Broadcaster (Including Combination Power Modes
Roles) • RF Performance Unchanged
– ATT / GATT – Client and Server • Small Package Allows for Small Solution Size
– SMP – AES-128 Encryption and • CC2541 Controllable
Decryption
– L2CAP DESCRIPTION
– Sample Applications and Profiles The CC2541 is a power-optimized true system-on-
– Generic Applications for GAP Central chip (SoC) solution for both Bluetooth low energy and
and Peripheral Roles proprietary 2.4-GHz applications. It enables robust
network nodes to be built with low total bill-of-material
– Proximity, Accelerometer, Simple Keys, costs. The CC2541 combines the excellent
and Battery GATT Services performance of a leading RF transceiver with an
– More Applications Supported in BLE industry-standard enhanced 8051 MCU, in-system
Software Stack programmable flash memory, 8-KB RAM, and many
– Multiple Configuration Options other powerful supporting features and peripherals.
The CC2541 is highly suited for systems where
– Single-Chip Configuration, Allowing ultralow power consumption is required. This is
Applications to Run on CC2541 specified by various operating modes. Short transition
– Network Processor Interface for times between operating modes further enable low
Applications Running on an External power consumption.
Microcontroller The CC2541 is pin-compatible with the CC2540 in
– BTool – Windows PC Application for the 6-mm × 6-mm QFN40 package, if the USB is not
Evaluation, Development, and Test used on the CC2540 and the I2C/extra I/O is not used
on the CC2541. Compared to the CC2540, the
APPLICATIONS CC2541 provides lower RF current consumption. The
CC2541 does not have the USB interface of the
• 2.4-GHz Bluetooth low energy Systems CC2540, and provides lower maximum output power
• Proprietary 2.4-GHz Systems in TX mode. The CC2541 also adds a HW I2C
• Human-Interface Devices (Keyboard, Mouse, interface.
Remote Control) The CC2541 is pin-compatible with the CC2533
• Sports and Leisure Equipment RF4CE-optimized IEEE 802.15.4 SoC.
• Mobile Phone Accessories The CC2541 comes in two different versions:
• Consumer Electronics CC2541F128/F256, with 128 KB and 256 KB of flash
memory, respectively.
For the CC2541 block diagram, see Figure 1.
2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: CC2541

CC2541
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ON-CHIP VOLTAGE VDD (2 V–3.6 V)

REGULATOR DCOUPL
RESET_N RESET WATCHDOG TIMER
POWER-ON RESET
XOSC_Q2 32-MHZ BROWN OUT
XOSC_Q1 CRYSTAL OSC
SFR bus
CLOCK MUX and
CALIBRATION SLEEP TIMER
P2_4 32.768-kHz
CRYSTAL OSC
P2_3
P2_2 POWER MGT. CONTROLLER
DEBUG HIGH SPEED 32-kHz
P2_1 INTERFACE RC-OSC RC-OSC
P2_0
PDATA
P1_7 RAM SRAM
XRAM
P1_6 8051 CPU
P1_5
CORE IRAM MEMORY
P1_4 SFR
ARBITRATOR
FLASH FLASH
P1_3
P1_2 UNIFIED
DMA
P1_1
P1_0 IRQ FLASH CTRL
CTRL
P0_7
P0_6 ANALOG COMPARATOR FIFOCTRL 1-KB SRAM
I/O CONTROLLER
P0_5 OP-
Radio Arbiter
P0_4
AES RADIO
P0_3 REGISTERS
ENCRYPTION
P0_2 and
P0_1 DS ADC DECRYPTION Link Layer Engine
P0_0 AUDIO / DC
SYNTH
DEMODULATOR MODULATOR
SFR bus
SDA 2
I C
SCL
USART 0
SYNTHESIZER
FREQUENCY
USART 1
RECEIVE TRANSMIT
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
TIMER 3 (8-bit)
RF_P RF_N
TIMER 4 (8-bit) DIGITAL
ANALOG
MIXED
Figure 1. Block Diagram
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 3

CC2541
ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage All supply pins must have the same voltage –0.3 3.9 V
Voltage on any digital pin –0.3 VDD + 0.3 ≤ 3.9 V
Input RF level 10 dBm
Storage temperature range –40 125 °C
All pins, excluding pins 25 and 26, according to human-body
2 kV
model, JEDEC STD 22, method A114
All pins, according to human-body model, JEDEC STD 22,
ESD (2) 1 kV
method A114
According to charged-device model, JEDEC STD 22, method
500 V
C101
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) CAUTION: ESD sesnsitive device. Precautions should be used when handling the device in order to prevent permanent damage.
RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Operating ambient temperature range, TA –40 85 °C
Operating supply voltage 2 3.6 V
ELECTRICAL CHARACTERISTICS
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V,
1 Mbps, GFSK, 250-kHz deviation, Bluetooth low energy mode, and 0.1% BER
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RX mode, standard mode, no peripherals active, low MCU
17.9
activity
RX mode, high-gain mode, no peripherals active, low MCU
20.2
activity
mA
TX mode, –20 dBm output power, no peripherals active, low
16.8
MCU activity
TX mode, 0 dBm output power, no peripherals active, low
18.2
MCU activity
Icore Core current consumption Power mode 1. Digital regulator on; 16-MHz RCOSC and 32-
MHz crystal oscillator off; 32.768-kHz XOSC, POR, BOD and 270
sleep timer active; RAM and register retention
Power mode 2. Digital regulator off; 16-MHz RCOSC and 32-
µA
MHz crystal oscillator off; 32.768-kHz XOSC, POR, and sleep 1
timer active; RAM and register retention
Power mode 3. Digital regulator off; no clocks; POR active;
0.5
RAM and register retention
Low MCU activity: 32-MHz XOSC running. No radio or
6.7 mA
peripherals. Limited flash access, no RAM access.
Timer 1. Timer running, 32-MHz XOSC used 90
Timer 2. Timer running, 32-MHz XOSC used 90
Peripheral current consumption Timer 3. Timer running, 32-MHz XOSC used 60 μA
Iperi (Adds to core current Icore for each
peripheral unit activated) Timer 4. Timer running, 32-MHz XOSC used 70
Sleep timer, including 32.753-kHz RCOSC 0.6
ADC, when converting 1.2 mA

CC2541
GENERAL CHARACTERISTICS
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V
WAKE-UP AND TIMING
Digital regulator on, 16-MHz RCOSC and 32-MHz crystal
Power mode 1 → Active 4 μs
oscillator off. Start-up of 16-MHz RCOSC
Digital regulator off, 16-MHz RCOSC and 32-MHz crystal
Power mode 2 or 3 → Active 120 μs
oscillator off. Start-up of regulator and 16-MHz RCOSC
Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC,
500 μs
Active → TX or RX with 32-MHz XOSC OFF
With 32-MHz XOSC initially on 180 μs
Proprietary auto mode 130
RX/TX turnaround μs
BLE mode 150
RADIO PART
RF frequency range Programmable in 1-MHz steps 2379 2496 MHz
2 Mbps, GFSK, 500-kHz deviation
Data rate and modulation format 1 Mbps, GFSK, 160-kHz deviation
500 kbps, MSK
250 kbps, GFSK, 160-kHz deviation
250 kbps, MSK
RF RECEIVE SECTION
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V, fc = 2440 MHz
2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER
Receiver sensitivity –90 dBm
Saturation BER < 0.1% –1 dBm
Co-channel rejection Wanted signal at –67 dBm –9 dB
±2 MHz offset, 0.1% BER, wanted signal –67 dBm –2
In-band blocking rejection ±4 MHz offset, 0.1% BER, wanted signal –67 dBm 36 dB
±6 MHz or greater offset, 0.1% BER, wanted signal –67 dBm 41
Including both initial tolerance and drift. Sensitivity better than –67dBm,
Frequency error tolerance (1) –300 300 kHz
250 byte payload. BER 0.1%
Symbol rate error Maximum packet length. Sensitivity better than–67dBm, 250 byte
–120 120 ppm
tolerance (2) payload. BER 0.1%
Saturation BER < 0.1% –7 dBm
Co-channel rejection Wanted signal at –67 dBm –12 dB
In-band blocking rejection ±4 MHz offset, 0.1% BER, wanted signal –67 dBm 34 dB
±6 MHz or greater offset, 0.1% BER, wanted signal –67 dBm 39
Including both initial tolerance and drift. Sensitivity better than –67 dBm,
Symbol rate error Maximum packet length. Sensitivity better than –67 dBm, 250 byte
–120 120 ppm
(1) Difference between center frequency of the received RF signal and local oscillator frequency
(2) Difference between incoming symbol rate and the internally generated symbol rate

CC2541
RF RECEIVE SECTION (continued)

1 Mbps, GFSK, 250-kHz Deviation, Bluetooth low energy Mode, 0.1% BER
High-gain mode –94
Receiver sensitivity (3) (4) dBm
Standard mode –88
Saturation (4) BER < 0.1% 5 dBm
(4)
Co-channel rejection Wanted signal –67 dBm –6 dB
±2 MHz offset, 0.1% BER, wanted signal –67 dBm 26
In-band blocking rejection (4) dB
±3 MHz offset, 0.1% BER, wanted signal –67 dBm 34
>6 MHz offset, 0.1% BER, wanted signal –67 dBm 33
Minimum interferer level < 2 GHz (Wanted signal –67 dBm) –21
Out-of-band blocking
Minimum interferer level [2 GHz, 3 GHz] (Wanted signal –67 dBm) –25 dBm
rejection (4)
Minimum interferer level > 3 GHz (Wanted signal –67 dBm) –7
Intermodulation (4) Minimum interferer level –36 dBm
Including both initial tolerance and drift. Sensitivity better than -67dBm,
Symbol rate error Maximum packet length. Sensitivity better than –67 dBm, 250 byte
–80 80 ppm
Receiver sensitivity (7) –91 dBm
Saturation BER < 0.1% 0 dBm
Co-channel rejection Wanted signal 10 dB above sensitivity level –9 dB
±1-MHz offset, 0.1% BER, wanted signal –67 dBm 2
In-band blocking rejection dB
±3-MHz offset, 0.1% BER, wanted signal -–67 dBm 27
>6-MHz offset, 0.1% BER, wanted signal –67 dBm 32
(5) Including both initial tolerance and drift. Sensitivity better than –67 dBm,
Frequency error tolerance –200 200 kHz
250-byte payload. BER 0.1%
Symbol rate error Maximum packet length. Sensitivity better than –67 dBm, 250-byte
–80 80 ppm
500 kbps, MSK, 0.1% BER
Receiver sensitivity (7) –99 dBm
Co-channel rejection Wanted signal –67 dBm –5 dB
In-band blocking rejection ±2-MHz offset, 0.1% BER, wanted signal –67 dBm 27 dB
Maximum packet length. Sensitivity better than –67 dBm, 250-byte
Symbol rate error tolerance –80 80 ppm
payload. BER 0.1%
(3) The receiver sensitivity setting is programmable using a TI BLE stack vendor-specific API command. The default value is standard
mode.
(4) Results based on standard-gain mode.
(7) Results based on high-gain mode.

CC2541
RF RECEIVE SECTION (continued)

250 kbps, GFSK, 160 kHz Deviation, 0.1% BER
(8)
Co-channel rejection Wanted signal -67 dBm –3 dB
Symbol rate error Maximum packet length. Sensitivity better than –67 dBm, 250-byte
–80 80 ppm
250 kbps, MSK, 0.1% BER
(11)
Co-channel rejection Wanted signal -67 dBm –5 dB
Maximum packet length. Sensitivity better than –67 dBm, 250-byte
Symbol rate error tolerance –80 80 ppm
payload. BER 0.1%
ALL RATES/FORMATS
Spurious emission in RX.
f < 1 GHz –67 dBm
Conducted measurement
Spurious emission in RX.
f > 1 GHz –57 dBm
Conducted measurement
(8) Results based on standard-gain mode.

(11) Results based on high-gain mode.

CC2541
RF TRANSMIT SECTION
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz
Delivered to a single-ended 50-Ω load through a balun using
0
maximum recommended output power setting
Output power dBm
Delivered to a single-ended 50-Ω load through a balun using
–23
minimum recommended output power setting
Programmable output power Delivered to a single-ended 50-Ω load through a balun using 23 dB
range minimum recommended output power setting
f < 1 GHz –52 dBm
Spurious emission conducted f > 1 GHz –48 dBm
measurement
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
Differential impedance as seen from the RF port (RF_P and RF_N)
Optimum load impedance 70 +j30 Ω
toward the antenna
Designs with antenna connectors that require conducted ETSI compliance at 64 MHz should insert an LC
resonator in front of the antenna connector. Use a 1.6-nH inductor in parallel with a 1.8-pF capacitor. Connect
both from the signal trace to a good RF ground.
CURRENT CONSUMPTION WITH TPS62730

Measured on Texas Instruments CC2541 TPA62730 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz,
1 Mbsp, GFSK, 250-kHz deviation, Bluetooth™ low energy Mode, 1% BER (1)
RX mode, standard mode, no peripherals active, low MCU activity, MCU
14.7
at 1 MHz
RX mode, high-gain mode, no peripherals active, low MCU activity,
16.7
MCU at 1 MHz
Current consumption mA
TX mode, –20 dBm output power, no peripherals active, low MCU activity, 13.1
MCU at 1 MHz
TX mode, 0 dBm output power, no peripherals active, low MCU activity,
14.3
MCU at 1 MHz
(1) 0.1% BER maps to 30.8% PER
32-MHz CRYSTAL OSCILLATOR

Crystal frequency 32 MHz
Crystal frequency accuracy
–40 40 ppm
requirement (1)
ESR Equivalent series resistance 6 60 Ω
C0 Crystal shunt capacitance 1 7 pF
CL Crystal load capacitance 10 16 pF
Start-up time 0.25 ms
The crystal oscillator must be in power down for a guard
time before it is used again. This requirement is valid for
Power-down guard time 3 ms
all modes of operation. The need for power-down guard
time can vary with crystal type and load.
(1) Including aging and temperature dependency, as specified by [1]

CC2541
32.768-kHz CRYSTAL OSCILLATOR

Crystal frequency 32.768 kHz
Crystal frequency accuracy requirement (1) –40 40 ppm
ESR Equivalent series resistance 40 130 kΩ
C0 Crystal shunt capacitance 0.9 2 pF
CL Crystal load capacitance 12 16 pF
Start-up time 0.4 s
(1) Including aging and temperature dependency, as specified by [1]
32-kHz RC OSCILLATOR
Measured on Texas Instruments CC2541 EM reference design with TA = 25°C and VDD = 3 V.
Calibrated frequency (1) 32.753 kHz
Frequency accuracy after calibration ±0.2%
Temperature coefficient (2) 0.4 %/°C
Supply-voltage coefficient (3) 3 %/V
Calibration time (4) 2 ms
(1) The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.
(2) Frequency drift when temperature changes after calibration
(3) Frequency drift when supply voltage changes after calibration
(4) When the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC32K_CALDIS is set to 0.
16-MHz RC OSCILLATOR
(1)
Frequency 16 MHz
Uncalibrated frequency accuracy ±18%
Calibrated frequency accuracy ±0.6%
Start-up time 10 μs
(2)
Initial calibration time 50 μs
(1) The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.
(2) When the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC_PD is set to 0.

CC2541
RSSI CHARACTERISTICS
2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER and 2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER
Reduced gain by AGC algorithm 64
Useful RSSI range (1) dB
High gain by AGC algorithm 64
Reduced gain by AGC algorithm 79
RSSI offset (1) dBm
High gain by AGC algorithm 99
Absolute uncalibrated accuracy (1) ±6 dB
Step size (LSB value) 1 dB
All Other Rates/Formats
Standard mode 64
Useful RSSI range (1) dB
High-gain mode 64
Standard mode 98
RSSI offset (1) dBm
High-gain mode 107
Absolute uncalibrated accuracy (1) ±3 dB
Step size (LSB value) 1 dB
(1) Assuming CC2541 EM reference design. Other RF designs give an offset from the reported value.
FREQUENCY SYNTHESIZER CHARACTERISTICS

Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz
At ±1-MHz offset from carrier –109
Phase noise, unmodulated carrier At ±3-MHz offset from carrier –112 dBc/Hz
At ±5-MHz offset from carrier –119
ANALOG TEMPERATURE SENSOR

Output 1480 12-bit
Temperature coefficient 4.5 / 1°C
Voltage coefficient Measured using integrated ADC, internal band-gap voltage 1 0.1 V
Initial accuracy without calibration reference, and maximum resolution ±10 °C
Accuracy using 1-point calibration ±5 °C
Current consumption when enabled 0.5 mA
COMPARATOR CHARACTERISTICS
TA = 25°C, VDD = 3 V. All measurement results are obtained using the CC2541 reference designs, post-calibration.
Common-mode maximum voltage VDD V
Common-mode minimum voltage –0.3
Input offset voltage 1 mV
Offset vs temperature 16 µV/°C
Offset vs operating voltage 4 mV/V
Supply current 230 nA
Hysteresis 0.15 mV

CC2541
ADC CHARACTERISTICS
TA = 25°C and VDD = 3 V
Input voltage VDD is voltage on AVDD5 pin 0 VDD V
External reference voltage VDD is voltage on AVDD5 pin 0 VDD V
External reference voltage differential VDD is voltage on AVDD5 pin 0 VDD V
Input resistance, signal Simulated using 4-MHz clock speed 197 kΩ
Full-scale signal (1) Peak-to-peak, defines 0 dBFS 2.97 V
Single-ended input, 7-bit setting 5.7
Differential input, 7-bit setting 6.5
ENOB (1) Effective number of bits bits
Differential input, 10-bit setting 10
10-bit setting, clocked by RCOSC 9.7
12-bit setting, clocked by RCOSC 10.9
Useful power bandwidth 7-bit setting, both single and differential 0–20 kHz
Single ended input, 12-bit setting, –6 dBFS (1) –75.2
THD Total harmonic distortion dB
Differential input, 12-bit setting, –6 dBFS (1) –86.6
Single-ended input, 12-bit setting (1) 70.2
Differential input, 12-bit setting (1) 79.3
Signal to nonharmonic ratio (1)
dB
Single-ended input, 12-bit setting, –6 dBFS 78.8
Differential input, 12-bit setting, –6 dBFS (1) 88.9
Differential input, 12-bit setting, 1-kHz sine
CMRR Common-mode rejection ratio >84 dB
(0 dBFS), limited by ADC resolution
Single ended input, 12-bit setting, 1-kHz sine
Crosstalk >84 dB
(0 dBFS), limited by ADC resolution
Offset Midscale –3 mV
Gain error 0.68%
12-bit setting, mean (1) 0.05
DNL Differential nonlinearity (1)
LSB
12-bit setting, maximum 0.9
12-bit setting, mean (1) 4.6
12-bit setting, maximum (1) 13.3
INL Integral nonlinearity LSB
12-bit setting, mean, clocked by RCOSC 10
12-bit setting, max, clocked by RCOSC 29
Single ended input, 7-bit setting (1) 35.4
SINAD Single ended input, 12-bit setting (1) 66.6
Signal-to-noise-and-distortion dB
(–THD+N) Differential input, 7-bit setting (1) 40.7
7-bit setting 20
9-bit setting 36
Conversion time μs
10-bit setting 68
12-bit setting 132
(1) Measured with 300-Hz sine-wave input and VDD as reference.

CC2541
ADC CHARACTERISTICS (continued)

TA = 25°C and VDD = 3 V
Power consumption 1.2 mA
Internal reference VDD coefficient 4 mV/V
Internal reference temperature
0.4 mV/10°C
coefficient
Internal reference voltage 1.24 V
CONTROL INPUT AC CHARACTERISTICS

TA = –40°C to 85°C, VDD = 2 V to 3.6 V
System clock, fSYSCLK The undivided system clock is 32 MHz when crystal oscillator is used.
The undivided system clock is 16 MHz when calibrated 16-MHz RC 16 32 MHz
tSYSCLK = 1/ fSYSCLK oscillator is used.
See item 1, Figure 2. This is the shortest pulse that is recognized as
a complete reset pin request. Note that shorter pulses may be
RESET_N low duration 1 µs
recognized but do not lead to complete reset of all modules within the
chip.
See item 2, Figure 2.This is the shortest pulse that is recognized as
Interrupt pulse duration 20 ns
an interrupt request.
RESET_N
1 2
Px.n
T0299-01
Figure 2. Control Input AC Characteristics

CC2541
SPI AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
Master, RX and TX 250
t1 SCK period ns
Slave, RX and TX 250
SCK duty cycle Master 50%
Master 63
t2 SSN low to SCK ns
Slave 63
Master 63
t3 SCK to SSN high ns
Slave 63
t4 MOSI early out Master, load = 10 pF 7 ns
t5 MOSI late out Master, load = 10 pF 10 ns
t6 MISO setup Master 90 ns
t7 MISO hold Master 10 ns
SCK duty cycle Slave 50% ns
t10 MOSI setup Slave 35 ns
t11 MOSI hold Slave 10 ns
t9 MISO late out Slave, load = 10 pF 95 ns
Master, TX only 8
Master, RX and TX 4
Operating frequency MHz
Slave, RX only 8
Slave, RX and TX 4
SCK
t2 t3
SSN
t4 t5
MOSI D0 X D1
t6 t7
MISO X D0 X
T0478-01
Figure 3. SPI Master AC Characteristics

CC2541
SCK
t2 t3
SSN
t8 t9
MISO D0 X D1
t10 t11
MOSI X D0 X
T0479-01
Figure 4. SPI Slave AC Characteristics
DEBUG INTERFACE AC CHARACTERISTICS

TA = –40°C to 85°C, VDD = 2 V to 3.6 V
fclk_dbg Debug clock frequency (see Figure 5) 12 MHz
t1 Allowed high pulse on clock (see Figure 5) 35 ns
t2 Allowed low pulse on clock (see Figure 5) 35 ns
EXT_RESET_N low to first falling edge on debug clock (see
t3 167 ns
Figure 7)
t4 Falling edge on clock to EXT_RESET_N high (see Figure 7) 83 ns
t5 EXT_RESET_N high to first debug command (see Figure 7) 83 ns
t6 Debug data setup (see Figure 6) 2 ns
t7 Debug data hold (see Figure 6) 4 ns
t8 Clock-to-data delay (see Figure 6) Load = 10 pF 30 ns
Time
DEBUG_ CLK
P2_2
t1 t2
1/fclk_dbg
T0436-01
Figure 5. Debug Clock – Basic Timing

CC2541
Time
DEBUG_ CLK
P2_2
RESET_N
t3 t4 t5
T0437-01
Figure 6. Debug Enable Timing
Time
DEBUG_ CLK
P2_2
DEBUG_DATA
(to CC2541)
P2_1
DEBUG_DATA
(from CC2541)
P2_1
t6 t7 t8
Figure 7. Data Setup and Hold Timing
TIMER INPUTS AC CHARACTERISTICS

TA = –40°C to 85°C, VDD = 2 V to 3.6 V
Synchronizers determine the shortest input pulse that can be
Input capture pulse duration recognized. The synchronizers operate at the current system 1.5 tSYSCLK
clock rate (16 MHz or 32 MHz).

CC2541
DC CHARACTERISTICS
TA = 25°C, VDD = 3 V
Logic-0 input voltage 0.5 V
Logic-1 input voltage 2.4 V
Logic-0 input current Input equals 0 V –50 50 nA
Logic-1 input current Input equals VDD –50 50 nA
I/O-pin pullup and pulldown resistors 20 kΩ
Logic-0 output voltage, 4- mA pins Output load 4 mA 0.5 V
Logic-1 output voltage, 4-mA pins Output load 4 mA 2.5 V
Logic-0 output voltage, 20- mA pins Output load 20 mA 0.5 V
Logic-1 output voltage, 20-mA pins Output load 20 mA 2.5 V
DEVICE INFORMATION
PIN DESCRIPTIONS
The CC2541 pinout is shown in Figure 8 and a short description of the pins follows.
CC2541
RHA Package
(Top View) P2_3 / OSC32K_Q2
P2_4 / OSC32K_Q1
DCOUPL
DVDD1
AVDD6
P1_6
P1_7
P2_0
P2_1
P2_2
40 39 38 37 36 35 34 33 32 31
GND 1 30 R_BIAS
SCL 2 29 AVDD4
SDA 3 28 AVDD1
NC 4 27 AVDD2
P1_5 5
GND 26 RF_N
P1_4 6 Ground Pad 25 RF_P
P1_3 7 24 AVDD3
P1_2 8 23 XOSC_Q2
P1_1 9 22 XOSC_Q1
DVDD2 10 21 AVDD5
11 12 13 14 15 16 17 18 19 20
P0_1
RESET_N
P0_2
P1_0
P0_4
P0_0
P0_7
P0_6
P0_3
P0_5
NOTE: The exposed ground pad must be connected to a solid ground plane, as this is the ground connection for the chip.
Figure 8. Pinout Top View

CC2541
PIN DESCRIPTIONS
PIN NAME PIN PIN TYPE DESCRIPTION
AVDD1 28 Power (analog) 2-V–3.6-V analog power-supply connection
DCOUPL 40 Power (digital) 1.8-V digital power-supply decoupling. Do not use for supplying external circuits.
DVDD1 39 Power (digital) 2-V–3.6-V digital power-supply connection
DVDD2 10 Power (digital) 2-V–3.6-V digital power-supply connection
GND 1 Ground pin Connect to GND
GND — Ground The ground pad must be connected to a solid ground plane.
NC 4 Unused pins Not connected
P0_0 19 Digital I/O Port 0.0
P1_0 11 Digital I/O Port 1.0 – 20-mA drive capability
P1_1 9 Digital I/O Port 1.1 – 20-mA drive capability
P2_1/DD 35 Digital I/O Port 2.1 / debug data
P2_2/DC 34 Digital I/O Port 2.2 / debug clock
P2_3/ 33 Digital I/O, Analog I/O Port 2.3/32.768 kHz XOSC
OSC32K_Q2
P2_4/ 32 Digital I/O, Analog I/O Port 2.4/32.768 kHz XOSC
OSC32K_Q1
RBIAS 30 Analog I/O External precision bias resistor for reference current
RESET_N 20 Digital input Reset, active-low
RF_N 26 RF I/O Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF_P 25 RF I/O Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
SCL 2 I2C clock or digital I/O Can be used as I2C clock pin or digital I/O. Leave floating if not used. If grounded
disable pull up
SDA 3 I2C clock or digital I/O Can be used as I2C data pin or digital I/O. Leave floating if not used. If grounded
disable pull up
XOSC_Q1 22 Analog I/O 32-MHz crystal oscillator pin 1 or external clock input
XOSC_Q2 23 Analog I/O 32-MHz crystal oscillator pin 2

CC2541
BLOCK DIAGRAM
A block diagram of the CC2541 is shown in Figure 9. The modules can be roughly divided into one of three
categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given.
ON-CHIP VOLTAGE VDD (2 V–3.6 V)

REGULATOR DCOUPL
RESET_N RESET WATCHDOG TIMER
POWER-ON RESET
XOSC_Q2 32-MHZ BROWN OUT
XOSC_Q1 CRYSTAL OSC
SFR bus
CLOCK MUX and
CALIBRATION SLEEP TIMER
P2_4 32.768-kHz
CRYSTAL OSC
P2_3
P2_2 POWER MGT. CONTROLLER
DEBUG HIGH SPEED 32-kHz
P2_1 INTERFACE RC-OSC RC-OSC
P2_0
PDATA
P1_7 RAM SRAM
XRAM
P1_6 8051 CPU
P1_5
CORE IRAM MEMORY
P1_4 SFR
ARBITRATOR
FLASH FLASH
P1_3
P1_2 UNIFIED
DMA
P1_1
P1_0 IRQ FLASH CTRL
CTRL
P0_7
P0_6 ANALOG COMPARATOR FIFOCTRL 1-KB SRAM
I/O CONTROLLER
P0_5 OP-
Radio Arbiter
P0_4
AES RADIO
P0_3 REGISTERS
ENCRYPTION
P0_2 and
P0_1 DS ADC DECRYPTION Link Layer Engine
P0_0 AUDIO / DC
SYNTH
DEMODULATOR MODULATOR
SFR bus
SDA 2
I C
SCL
USART 0
SYNTHESIZER
FREQUENCY
USART 1
RECEIVE TRANSMIT
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
TIMER 3 (8-bit)
RF_P RF_N
TIMER 4 (8-bit) DIGITAL
ANALOG
MIXED
Figure 9. CC2541 Block Diagram

CC2541
BLOCK DESCRIPTIONS
A block diagram of the CC2541 is shown in Figure 9. The modules can be roughly divided into one of three
categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given.
CPU and Memory

The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses (SFR,
DATA, and CODE/XDATA), a debug interface, and an 18-input extended interrupt unit.
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, access
of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It is
responsible for performing arbitration and sequencing between simultaneous memory accesses to the same
physical memory.
The SFR bus is drawn conceptually in Figure 9 as a common bus that connects all hardware peripherals to the
memory arbiter. The SFR bus in the block diagram also provides access to the radio registers in the radio
register bank, even though these are indeed mapped into XDATA memory space.
The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The SRAM is
an ultralow-power SRAM that retains its contents even when the digital part is powered off (power mode 2 and
mode 3).
The 128/256 KB flash block provides in-circuit programmable non-volatile program memory for the device, and
maps into the CODE and XDATA memory spaces.
Peripherals
Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewise
programming. See User Guide for details on the flash controller.
A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA memory
space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing
mode, source and destination pointers, and transfer count) is configured with DMA descriptors that can be
located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers,
ADC interface, etc.) can be used with the DMA controller for efficient operation by performing data transfers
between a single SFR or XREG address and flash/SRAM.
Each CC2541 contains a unique 48-bit IEEE address that can be used as the public device address for a
Bluetooth device. Designers are free to use this address, or provide their own, as described in the Bluetooth
specfication.
The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of which
is associated with one of four interrupt priorities. I/O and sleep timer interrupt requests are serviced even if the
device is in a sleep mode (power modes 1 and 2) by bringing the CC2541 back to the active mode.
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.
Through this debug interface, it is possible to erase or program the entire flash memory, control which oscillators
are enabled, stop and start execution of the user program, execute instructions on the 8051 core, set code
breakpoints, and single-step through instructions in the code. Using these techniques, it is possible to perform in-
circuit debugging and external flash programming elegantly.
The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral
modules control certain pins or whether they are under software control, and if so, whether each pin is configured
as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connects
to the I/O pins can choose between two different I/O pin locations to ensure flexibility in various applications.
The sleep timer is an ultralow-power timer that can either use an external 32.768-kHz crystal oscillator or an
internal 32.753-kHz RC oscillator. The sleep timer runs continuously in all operating modes except power mode
3. Typical applications of this timer are as a real-time counter or as a wake-up timer to get out of power mode 1
or mode 2.
A built-in watchdog timer allows the CC2541 to reset itself if the firmware hangs. When enabled by software,
the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out.
CC2541
Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period
value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of
the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It
can also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with the
output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction.
Timer 2 is a 40-bit timer. It has a 16-bit counter with a configurable timer period and a 24-bit overflow counter
that can be used to keep track of the number of periods that have transpired. A 40-bit capture register is also
used to record the exact time at which a start-of-frame delimiter is received/transmitted or the exact time at which
transmission ends. There are two 16-bit output compare registers and two 24-bit overflow compare registers that
can be used to give exact timing for start of RX or TX to the radio or general interrupts.
Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,
an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter
channels can be used as PWM output.
USART 0 and USART 1 are each configurable as either an SPI master/slave or a UART. They provide double
buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplex
applications. Each USART has its own high-precision baud-rate generator, thus leaving the ordinary timers free
for other uses. When configured as SPI slaves, the USARTs sample the input signal using SCK directly instead
of using some oversampling scheme, and are thus well-suited for high data rates.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware
support for CCM.
The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30-kHz to 4-kHz,
respectively. DC and audio conversions with up to eight input channels (I/O controller pins) are possible. The
inputs can be selected as single-ended or differential. The reference voltage can be internal, AVDD, or a single-
ended or differential external signal. The ADC also has a temperature-sensor input channel. The ADC can
automate the process of periodic sampling or conversion over a sequence of channels.
The I2C module provides a digital peripheral connection with two pins and supports both master and slave
operation. I2C support is compliant with the NXP I2C specification version 2.1 and supports standard mode (up to
100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit device addressing modes are supported, as well as
master and slave modes.
The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an analog
signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator
output is connected to the I/O controller interrupt detector and can be treated by the MCU as a regular I/O pin
interrupt.

CC2541
TYPICAL CHARACTERISTICS
RX CURRENT TX CURRENT
vs vs
TEMPERATURE TEMPERATURE
19 19.5
1 Mbps GFSK 250 kHz TX Power Setting = 0 dBm
Standard Gain Setting VCC = 3 V
18.5 Input = −70 dBm 19
VCC = 3 V
Current (mA)
Current (mA)
18 18.5
17.5 18
17 17.5
16.5 17
−40 −20 0 20 40 60 80 −40 −20 0 20 40 60 80
Temperature (°C) G001
Figure 10. Figure 11.
RX SENSITIVITY TX POWER
vs vs
TEMPERATURE TEMPERATURE
−84 4.0
Standard Gain Setting VCC = 3 V
VCC = 3 V
−86 2.0
Level (dBm)
Level (dBm)
−88 0.0
−90 −2.0
−92 −4.0
−40 −20 0 20 40 60 80 −40 −20 0 20 40 60 80
RX CURRENT TX CURRENT
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
20 20
19.5 Standard Gain Setting 19.5 TA = 25°C
Input = −70 dBm
19 TA = 25°C 19
Current (mA)
Current (mA)
18.5 18.5
18 18
17.5 17.5
17 17
16.5 16.5
16 16
2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Voltage (V) G005
Voltage (V) G006

CC2541
TYPICAL CHARACTERISTICS (continued)

vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
−84 4
Standard Gain Setting TA = 25°C
TA = 25°C
−86 2
Level (dBm)
Level (dBm)
−88 0
−90 −2
−92 −4
2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Voltage (V) G007
Voltage (V) G008
vs vs
FREQUENCY FREQUENCY
−84 4
Standard Gain Setting TA = 25°C
TA = 25°C VCC = 3 V
−86 VCC = 3 V 2
Level (dBm)
Level (dBm)
−88 0
−90 −2
−92 −4
2400 2410 2420 2430 2440 2450 2460 2470 2480 2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz) G009
Frequency (MHz) G010
Table 1. Output Power (1) (2)

TXPOWER Setting Typical Output Power (dBm)
0xE1 0
0xD1 –2
0xC1 –4
0xB1 –6
0xA1 –8
0x91 –10
0x81 –12
0x71 –14
0x61 –16
0x51 –18
0x41 –20
0x31 –23
(1) Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz. See SWRU191 for
recommended register settings.
(2) 1 Mbsp, GFSK, 250-kHz deviation, Bluetooth™ low energy mode, 1% BER

CC2541
Table 2. Output Power and Current Consumption

Typical Current Consumption Typical Current Consumption
Typical Output Power (dBm)
(mA) (1) With TPS62730 (mA) (2)
0 18.2 14.3
–20 16.8 13.1
(1) Measured on Texas Instruments CC2541 EM reference design with TA = 25°C, VDD = 3 V and fc =
2440 MHz. See SWRU191 for recommended register settings.
(2) Measured on Texas Instruments CC2541 TPS62730 EM reference design with TA = 25°C, VDD = 3 V
and fc = 2440 MHz. See SWRU191 for recommended register settings.
TYPICAL CURRENT SAVINGS WHEN USING TPS62730

Current Consumption TX 0 dBm Current Consumption RX SG
0 CLKCONMOD 0xBF
25 40 25 40
DC/DC OFF DC/DC OFF
DC/DC ON 35 DC/DC ON 35
20 Current Savings 20 Current Savings

30 30
Current Savings (%)

Current Savings (%)
25 25
Current (mA)
Current (mA)
15 15
20 20
10 10
15 15
10 10
5 5
5 5
0 0 0 0
2.1 2.4 2.7 3 3.3 3.6 2.1 2.4 2.7 3 3.3 3.6
Supply (V) Supply (V)
Figure 20. Current Savings in TX at Room Figure 21. Current Savings in RX at Room
Temperature Temperature
The application note (SWRA365) has information regarding the CC2541 and TPS62730 combo board and the
current savings that can be achieved using the combo board.

CC2541
APPLICATION INFORMATION
Few external components are required for the operation of the CC2541. A typical application circuit is shown in
Figure 22.
(1)
32-kHz Crystal
C331
2-V to 3.6-V Power Supply
C401
XTAL2
C321
AVDD6 31
P2_4/XOSC32K_Q1 32
P2_3/XOSC32K_Q2 33
P2_0 36
P2_2 34
P2_1 35
DVDD1 39
P1_6 38
P1_7 37
DCOUPL 40
R301
RBIAS 30
1 GND
AVDD4 29 Antenna
2 SCL
(50 W)
AVDD1 28
3 SDA
AVDD2 27
4 NC
RF_N 26
5 P1_5 CC2541
RF_P 25
6 P1_4
DIE ATTACH PAD AVDD3 24
7 P1_3
XOSC_Q2 23
8 P1_2
XOSC_Q1 22
9 P1_1
AVDD5 21
20 RESET_N
10 DVDD2
11 P1_0
12 P0_7
13 P0_6
14 P0_5
15 P0_4
16 P0_3
17 P0_2
18 P0_1
19 P0_0
XTAL1
Power Supply Decoupling Capacitors are Not Shown C221 C231

Digital I/O Not Connected
(1) 32-kHz crystal is mandatory when running the BLE protocol stack in low-power modes, except if the link layer is in
the standby state (Vol. 6 Part B Section 1.1 in [1]).
NOTE: Different antenna alternatives will be provided as reference designs.
Figure 22. CC2541 Application Circuit
Table 3. Overview of External Components (Excluding Supply Decoupling Capacitors)

Component Description Value
C401 Decoupling capacitor for the internal 1.8-V digital voltage regulator 1 µF
R301 Precision resistor ±1%, used for internal biasing 56 kΩ
Input/Output Matching
When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The
balun can be implemented using low-cost discrete inductors and capacitors. See reference design, CC2541EM,
for recommended balun.

CC2541
Crystal
An external 32-MHz crystal, XTAL1, with two loading capacitors (C221 and C231) is used for the 32-MHz crystal
oscillator. See 32-MHz CRYSTAL OSCILLATOR for details. The load capacitance seen by the 32-MHz crystal is
given by:
1
CL = + Cparasitic
1 1
+
C221 C231 (1)
XTAL2 is an optional 32.768-kHz crystal, with two loading capacitors (C321 and C331) used for the 32.768-kHz
crystal oscillator. The 32.768-kHz crystal oscillator is used in applications where both very low sleep-current
consumption and accurate wake-up times are needed. The load capacitance seen by the 32.768-kHz crystal is
given by:
1
CL = + Cparasitic
1 1
+
C321 C331 (2)
A series resistor may be used to comply with the ESR requirement.
On-Chip 1.8-V Voltage Regulator Decoupling

The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor
(C401) for stable operation.
Power-Supply Decoupling and Filtering

Proper power-supply decoupling must be used for optimum performance. The placement and size of the
decoupling capacitors and the power supply filtering are very important to achieve the best performance in an
application. TI provides a compact reference design that should be followed very closely.
References
1. Bluetooth® Core Technical Specification document, version 4.0

http://www.bluetooth.com/SiteCollectionDocuments/Core_V40.zip
2. CC253x System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee® Applications/CC2541 System-on-
Chip Solution for 2.4-GHz Bluetooth low energy Applications (SWRU191)
3. Current Savings in CC254x Using the TPS62730 (SWRA365).
Additional Information
Texas Instruments offers a wide selection of cost-effective, low-power RF solutions for proprietary and standard-
based wireless applications for use in industrial and consumer applications. Our selection includes RF
transceivers, RF transmitters, RF front ends, and System-on-Chips as well as various software solutions for the
sub-1- and 2.4-GHz frequency bands.
In addition, Texas Instruments provides a large selection of support collateral such as development tools,
technical documentation, reference designs, application expertise, customer support, third-party and university
programs.
The Low-Power RF E2E Online Community provides technical support forums, videos and blogs, and the chance
to interact with fellow engineers from all over the world.
With a broad selection of product solutions, end application possibilities, and a range of technical support, Texas
Instruments offers the broadest low-power RF portfolio. We make RF easy!
The following subsections point to where to find more information.

CC2541
Texas Instruments Low-Power RF Web Site

• Forums, videos, and blogs
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Join us today at www.ti.com/lprf-forum.
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Spacer
REVISION HISTORY
Changes from Original (January 2012) to Revision A Page
• Changed data sheet status from Product Preview to Production Data ................................................................................ 1
Changes from Revision A (February 2012) to Revision B Page
• Changed the Temperature coefficient Unit value From: mV/°C To: / 0.1°C ....................................................................... 10
• Changed Figure 22 text From: Optional 32-kHz Crystal To: 32-kHz Crystal ..................................................................... 24
Changes from Revision B (August 2012) to Revision C Page
• Changed the "Internal reference voltage" TYP value From 1.15 V To: 1.24 V .................................................................. 12
• Changed pin XOSC_Q1 Pin Type From Analog O To: Analog I/O, and changed the Pin Description .............................. 17
• Changed pin XOSC_Q2 Pin Type From Analog O To: Analog I/O .................................................................................... 17
Changes from Revision C (November 2012) to Revision D Page
• Changed the RF TRANSMIT SECTION, Output power TYP value From: –20 To: –23 ....................................................... 8
• Changed the RF TRANSMIT SECTION, Programmable output power range TYP value From: 20 To: 23 ........................ 8
• Added row 0x31 to Table 1 ................................................................................................................................................. 22

PACKAGE OPTION ADDENDUM
www.ti.com 25-Jul-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
CC2541F128RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC2541
& no Sb/Br) F128
CC2541F128RHAT ACTIVE VQFN RHA 40 250 Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC2541
& no Sb/Br) F128
CC2541F256RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC2541
& no Sb/Br) F256
CC2541F256RHAT ACTIVE VQFN RHA 40 250 Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC2541
& no Sb/Br) F256
HPA01215RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 CC2541
& no Sb/Br) F128
HPA01216RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 CC2541
& no Sb/Br) F256
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jul-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CC2541 :
• Automotive: CC2541-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
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CC2541

www.ti.com SWRS110D – JANUARY 2012 – REVISED JUNE 2013

2.4-GHz Bluetooth™ low energy and Proprietary System-on-Chip

SOFTWARE FEATURES CC2541 WITH TPS62730

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Product Folder Links: CC2541

ON-CHIP VOLTAGE VDD (2 V–3.6 V)

Figure 1. Block Diagram

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ABSOLUTE MAXIMUM RATINGS (1)

RECOMMENDED OPERATING CONDITIONS

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Product Folder Links: CC2541

Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 5

RF RECEIVE SECTION (continued)

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Product Folder Links: CC2541

RF RECEIVE SECTION (continued)

(8) Results based on standard-gain mode.

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CURRENT CONSUMPTION WITH TPS62730

(1) 0.1% BER maps to 30.8% PER

32-MHz CRYSTAL OSCILLATOR

(1) Including aging and temperature dependency, as specified by [1]

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Product Folder Links: CC2541

32.768-kHz CRYSTAL OSCILLATOR

(1) Including aging and temperature dependency, as specified by [1]

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FREQUENCY SYNTHESIZER CHARACTERISTICS

ANALOG TEMPERATURE SENSOR

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Product Folder Links: CC2541

(1) Measured with 300-Hz sine-wave input and VDD as reference.

ADC CHARACTERISTICS (continued)

CONTROL INPUT AC CHARACTERISTICS

Figure 2. Control Input AC Characteristics

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Figure 3. SPI Master AC Characteristics

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Figure 4. SPI Slave AC Characteristics

DEBUG INTERFACE AC CHARACTERISTICS

Figure 5. Debug Clock – Basic Timing

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Product Folder Links: CC2541

Figure 6. Debug Enable Timing

Figure 7. Data Setup and Hold Timing

TIMER INPUTS AC CHARACTERISTICS

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Figure 8. Pinout Top View

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Product Folder Links: CC2541

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ON-CHIP VOLTAGE VDD (2 V–3.6 V)

Figure 9. CC2541 Block Diagram

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