H

Isolated 15-bit A/D Converter

Technical Data

HCPL-7860
HCPL-0870, -7870

Features
• 12-bit Linearity • Fast 3 µs Over-Range • Offset Calibration
• 700 ns Conversion Time Detection • -40 °C to +85 °C Operating
(Pre-Trigger Mode 2) • Serial I/O (SPI®, QSPI® and Temperature Range
• 5 Conversion Modes for Microwire® Compatible) • 15 kV/µs Isolation Transient
Resolution/Speed Trade-Off; • ± 200 mV Input Range with Immunity
12-bit Effective Resolution Single 5 V Supply • Regulatory Approvals; UL,
with 18 µs Signal Delay • 1% Internal Reference CSA, VDE
(14-bit with 94 µs) Voltage Matching

DIGITAL CURRENT SENSOR

+ +
ISOLATION
BOUNDARY MICRO-CONTROLLER

OUTPUT
DATA
HP7860

HPx870
YYWW

YYWW

INPUT
CURRENT

ISOLATED DIGITAL
MODULATOR INTERFACE IC

Hewlett-Packard’s Isolated A/D Converter delivers the reliability, small size, superior
isolation and over-temperature performance motor drive designers need to accurately
measure current at half the price of traditional solutions.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.

SPI and QSPI are trademarks of Motorola Corp.

Microwire is a trademark of National Semiconductor Inc.

1-260 5965-5255E
Digital Current Sensing shunt resistance, any range of than 1 µs, the fast over-range
Circuit current can be monitored, from detector for quickly detecting
As shown in Figure 1, using the less than 1 A to more than 100 A. short circuits, different conversion
Isolated 2-chip A/D converter to modes giving various resolution/
sense current can be as simple as Even better performance can be speed trade-offs, offset calibra-
connecting a current-sensing achieved by fully utilizing the tion mode to eliminate initial
resistor, or shunt, to the input more advanced features of the offset from measurements, and
and reading output data through Isolated A/D converter, such as an adjustable threshold detector
the 3-wire serial output interface. the pre-trigger circuit which can for detecting non-short circuit
By choosing the appropriate reduce conversion time to less overload conditions.

NON-ISOLATED
+5V

ISOLATED CCLK VDD

+5V
CLAT CHAN
+ VDD1 VDD2 CDAT SCLK
INPUT 3-WIRE
CURRENT R VIN+ MCLK MCLK1 SDAT SERIAL
SHUNT
0.02 C1 INTERFACE
VIN- MDAT MDAT1 CS
0.1 µF
GND1 GND2 C2 MCLK2 THR1 +
0.1 µF C3
MDAT2 OVR1 10 µF
HCPL-7860
GND RESET

HCPL-x870

Figure 1: Typical Application Circuit.

Product Overview low-bandwidth analog input into that is compatible with SPI®,
a high-speed one-bit data stream QSPI®, and Microwire® proto-
Description
by means of a sigma-delta (∑∆) cols, allowing direct connection
The HCPL-7860 Isolated Modu- to a microcontroller. The Digital
oversampling modulator. This
lator and the HCPL-x870 Digital Interface IC is available in two
modulation provides for high
Interface IC together form an package styles: the HCPL-7870 is
noise margins and excellent
isolated programmable two-chip in a 16-pin DIP package and the
immunity against isolation-mode
analog-to-digital converter. The HCPL-0870 is in a 300-mil wide
transients. The modulator data
isolated modulator allows direct SO-16 surface-mount package.
and on-chip sampling clock are
measurement of motor phase Features of the Digital Interface
encoded and transmitted across
currents in power inverters while IC include five different conver-
the isolation boundary where they
the digital interface IC can be sion modes, three different pre-
are recovered and decoded into
programmed to optimize the trigger modes, offset calibration,
separate high-speed clock and
conversion speed and resolution fast over-range detection, and
data channels.
trade-off. adjustable threshold detection.
The Digital Interface IC converts Programmable features are con-
In operation, the HCPL-7860 figured via the Serial Configura-
the single-bit data stream from
Isolated Modulator (optocoupler tion port. A second multiplexed
the Isolated Modulator into
with 3750 VRMS dielectric with- input is available to allow
fifteen-bit output words and
stand voltage rating) converts a measurements with a second
provides a serial output interface

1-261
 isolated modulator without HCPL-x870 Digital Interface IC
additional hardware. Because the Feature Channel #1 Channel #2
two inputs are multiplexed, only
Conversion Mode ✓ ✓
one conversion at a time can be
made and not all features are Offset Calibration ✓ ✓
available for the second channel. Pre-Trigger Mode ✓
The available features for both Over-Range Detection ✓
channels are shown in the table Adjustable Threshold Detection ✓
at right.

Functional Diagrams
ISOLATION
BOUNDARY
CCLK 1 16 VDD
CONFIG.
CLAT 2 INTER- 15 CHAN
CON-
VDD1 1 8 VDD2 FACE
CDAT 3 VERSION 14 SCLK
INTER-
MCLK1 4 FACE 13 SDAT
VIN+ 2 SIGMA- 7 MCLK CH1
DELTA DECODE MDAT1 5 12 CS
MOD./
VIN– 3 ENCODE 6 MDAT MCLK2 6 THRES- 11 THR1
HOLD
MDAT2 7 CH2 DETECT 10 OVR1
GND1 4 5 GND2 &
SHIELD GND 8 RESET 9 RESET

HCPL-7860 Isolated Modulator HCPL-x870 Digital Interface IC

Pin Description, Isolated Modulator

Symbol Description Symbol Description
VDD1 Supply voltage input (4.5 V to 5.5 V) VDD2 Supply voltage input (4.5 V to 5.5 V)
VIN+ Positive input (± 200 mV MCLK Clock output (10 MHz typical)
recommended)
VIN– Negative input MDAT Serial data output
(normally connected to GND1)
GND1 Input ground GND2 Output ground

1-262
Pin Description, Digital Interface IC
Symbol Description Symbol Description
CCLK Clock input for the Serial Configuration VDD Supply voltage (4.5 V to 5.5 V).
Interface (SCI). Serial Configuration
data is clocked in on the rising edge
of CCLK.
CLAT Latch input for the Serial Configuration CHAN Channel select input. The input level on
Interface (SCI). The last 8 data bits CHAN determines which channel of
clocked in on CDAT by CCLK are data is used during the next conversion
latched into the appropriate cycle. An input low selects channel 1,
configuration register on the rising a high selects channel 2.
edge of CLAT.
CDAT Data input for the Serial Configuration SCLK Serial clock input. Serial data is clocked
Interface (SCI). Serial configuration out of SDAT on the falling edge of SCLK.
data is clocked in MSB first.
MCLK1 Channel 1 Isolated Modulator clock SDAT Serial data output. SDAT changes from
input. Input Data on MDAT1 is clocked high impedance to a logic low output
in on the rising edge of MCLK1. at the start of a conversion cycle.
SDAT then goes high to indicate that
data is ready to be clocked out. SDAT
returns to a high-impedance state after
all data has been clocked out and CS
has been brought high.
MDAT1 Channel 1 Isolated Modulator data CS Conversion start input. Conversion
input. begins on the falling edge of CS. CS
should remain low during the entire
conversion cycle and then be brought
high to conclude the cycle.
MCLK2 Channel 2 Isolated Modulator clock THR1 Continuous, programmable-threshold
input. Input Data on MDAT2 is clocked detection for channel 1 input data. A
in on the rising edge of MCLK2. high level output on THR1 indicates
that the magnitude of the channel 1
input signal is beyond a user
programmable threshold level between
160 mV and 310 mV. This signal
continuously monitors channel 1
independent of the channel select
(CHAN) signal.
MDAT2 Channel 2 Isolated Modulator data OVR1 High speed continuous over-range
input. detection for channel 1 input data. A
high level output on OVR1 indicates
that the magnitude of the channel 1
input is beyond full-scale. This signal
continuously monitors channel 1
independent of the CHAN signal.
GND Digital ground. RESET Master reset input. A logic high input
for at least 100 ns asynchronously
resets all configuration registers to
their default values and zeroes the
Offset Calibration registers.

1-263
 Isolated A/D Converter Performance

Electrical Specifications
Unless otherwise noted, all specifications are at VIN+ = -200 mV to +200 mV and VIN- = 0 V; all Typical
specifications are at TA = 25°C and VDD1 = VDD2 = VDD = 5 V; all Minimum/Maximum specifications are at
TA = -40°C to +85°C, VDD1 = VDD2 = VDD = 4.5 to 5.5 V.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
STATIC CONVERTER CHARACTERISTICS
Resolution 15 bits 1
Integral Nonlinearity INL 6 30 LSB 3 2
0.025 0.14 % 4
Differential Nonlinearity DNL 1 LSB 3
Uncalibrated Input Offset VOS -1 1 2.5 mV VIN+ = 0 V 5
Offset Drift vs. Temperature dVOS/dTA 4 µV/ °C 4
Offset drift vs. VDD1 dVOS/dVDD1 0.7 mV/V
Internal Reference Voltage VREF 326 mV
Absolute Reference Voltage -4 4 % 6 5
Tolerance
Reference Voltage -1 1 % TA = 25°C.
Matching See Note 5
VREF Drift vs. Temperature dVREF /dTA 190 ppm/°C
VREF Drift vs. VDD1 dVREF /dVDD1 0.9 %
Full Scale Input Range -VREF +VREF mV 6
Recommended Input -200 +200
Voltage Range
DYNAMIC CONVERTER CHARACTERISTICS
(Digital Interface IC is set to Conversion Mode 3.)
Signal-to-Noise Ratio SNR 62 73 dB VIN+ = 35 Hz, 2,9
Total Harmonic Distortion THD -67 400 mVpk-pk
Signal-to-(Noise SND 66 (141 mVrms) sine
+ Distortion) wave.
Effective Number of Bits ENOB 10 12 bits 8 7
Conversion Time tC2 0.7 1.0 µs Pre-Trigger Mode 2 7, 8
tC1 18 22 Pre-Trigger Mode 1 14
tC0 37 44 Pre-Trigger Mode 0
Signal Delay tDSIG 18 22 10 9
Over-Range Detect Time tOVR1 2.0 2.7 4.2 VIN+ = 0 to 400 mV 12 10
Threshold Detect Time tTHR1 10 step waveform 11
Signal Bandwidth BW 18 22 kHz 11 12
Isolation Transient CMR 15 20 kV/µs VISO = 1 kV 13
Immunity

1-264
Notes: equation ENOB = (SNR-1.76)/6.02 and should be used for determining
1. Resolution is defined as the total and represents the resolution of an phase margins in closed-loop applica-
number of output bits. The useable ideal, quantization-noise limited A/D tions. The signal delay is determined
accuracy of any A/D converter is a converter with the same SNR. by the frequency of the modulator
function of its linearity and signal-to- 8. Conversion time is defined as the clock and which Conversion Mode is
noise ratio, rather than how many time from when the convert start selected, and is independent of the
total bits it has. signal CS is brought low to when selected Pre-Trigger Mode and,
2. Integral nonlinearity is defined as SDAT goes high, indicating that therefore, conversion time.
one-half the peak-to-peak deviation output data is ready to be clocked 10. The minimum and maximum over-
of the best-fit line through the out. This can be as small as a few range detection time is determined by
transfer curve for VIN+ = -200 mV to cycles of the isolated modulator clock the frequency of the channel 1 iso-
+200 mV, expressed either as the and is determined by the frequency of lated modulator clock.
number of LSBs or as a percent of the isolated modulator clock and the 11. The minimum and maximum thresh-
measured input range (400 mV). selected Conversion and Pre-Trigger old detection time is determined by
3. Differential nonlinearity is defined as modes. For determining the true the user-defined configuration of the
the deviation of the actual difference signal delay characteristics of the A/D adjustable threshold detection circuit
from the ideal difference between converter for closed-loop phase and the frequency of the channel 1
midpoints of successive output margin calculations, the signal delay isolated modulator clock. See the
codes, expressed in LSBs. specification should be used. Applications Information section for
4. Data sheet value is the average 9. Signal delay is defined as the effec- further detail. The specified times
magnitude of the difference in offset tive delay of the input signal through apply for the default configuration.
voltage from TA = 25°C to the Isolated A/D converter. It can be 12. The signal bandwidth is the frequency
TA = -40°C, expressed in microvolts measured by applying a -200 mV to at which the magnitude of the output
per °C. ± 200 mV step at the input of modu- signal has decreased 3 dB below its
5. All units within each HCPL-7860 lator and adjusting the relative delay low-frequency value. The signal
standard packaging increment (either of the convert start signal CS so that bandwidth is determined by the fre-
50 per tube or 1000 per reel) have an the output of the converter is at mid- quency of the modulator clock and
Absolute Reference Voltage tolerance scale. The signal delay is the elapsed the selected Conversion Mode.
of ± 1%. An Absolute Reference time from when the step signal is 13. The isolation transient immunity (also
Voltage tolerance of ± 4% is applied at the input to when output known as Common-Mode Rejection)
guaranteed between standard data is ready at the end of the conver- specifies the minimum rate-of-rise of
packaging increments. sion cycle. The signal delay is the an isolation-mode signal applied
6. Beyond the full-scale input range the most important specification for across the isolation boundary beyond
output is either all zeroes or all ones. determining the true signal delay which the modulator clock or data
7. The effective number of bits (or characteristics of the A/D converter signals are corrupted.
effective resolution) is defined by the

75.0 16 0.08

VDD1 = 4.5 V 14 VDD1 = 4.5 V 0.07 VDD1 = 4.5 V

74.5 VDD1 = 5.0 V VDD1 = 5.0 V VDD1 = 5.0 V
VDD1 = 5.5 V 12 VDD1 = 5.5 V 0.06 VDD1 = 5.5 V
10 0.05
INL – LSB

74.0
INL – %
SNR

8 0.04
73.5 6 0.03

4 0.02
73.0
2 0.01
72.5 0 0
-40 -20 0 20 40 60 85 -40 -20 0 20 40 60 85 -40 -20 0 20 40 60 85
TEMPERATURE – °C TEMPERATURE – °C TEMPERATURE – °C

Figure 2. SNR vs. Temperature. Figure 3. INL (Bits) vs. Temperature. Figure 4. INL (%) vs. Temperature.

1-265
 400 2.5 200
PRE-TRIGGER
300 180
2.0 VDD1 = 4.5 V MODE 0
VDD1 = 4.5 V 160

CONVERSION TIME – µs
200 VDD1 = 5.0 V PRE-TRIGGER
OFFSET CHANGE – µV

VDD1 = 5.0 V 1.5 MODE 1

VDD1 = 5.5 V 140

VREF CHANGE – %
100 VDD1 = 5.5 V
PRE-TRIGGER
0 1.0 120 MODE 2
-100 0.5 100
-200 80
0
-300 60
-0.5
-400 40
-500 -1.0 20
-600 -1.5 0
-40 -20 0 20 40 60 85 -40 -20 0 20 40 60 85 1 2 3 4 5
TEMPERATURE – °C TEMPERATURE – °C CONVERSION MODE #

Figure 5. Offset Change vs. Figure 6. VREF Change vs. Figure 7. Conversion Time vs.
Temperature. Temperature. Conversion Mode.

14 85 100
EFFECTIVE RESOLUTION (# BITS)

90
13 80
80

SIGNAL DELAY – µs
75 70
12
70 60
SNR

11 50
65
40
10
60 30
20
9 55
10
8 50 0
1 2 3 4 5 1 2 3 4 5 1 2 3 4 5
CONVERSION MODE # CONVERSION MODE # CONVERSION MODE #

Figure 8. Effective Resolution vs. Figure 9. SNR vs. Conversion Mode. Figure 10. Signal Delay vs.
Conversion Mode. Conversion Mode.

100
90
SIGNAL BANDWIDTH – kHz

80 VIN+ (200 mV/DIV.)

70
OVR1 (200 mV/DIV.)
60
50 THR1
(2 V/DIV.)
40
30
20
10
0
1 2 3 4 5
2 µs/DIV.
CONVERSION MODE #

Figure 11. Signal Bandwidth vs. Figure 12. Over-Range and Threshold
Conversion Mode. Detect Times.

1-266
Isolated Modulator
Ordering Information
Specify Part Number followed by Option Number (if desired).

Example:

HCPL-7860#XXX
No Option = Standard DIP package, 50 per tube.
300 = Gull Wing Surface Mount Option, 50 per tube.
500 = Tape and Reel Packaging Option, 1000 per reel.

Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor.

Package Outline Drawings

8-pin DIP Package

9.40 (0.370)
9.90 (0.390)

8 7 6 5 REFERENCE VOLTAGE
TYPE NUMBER 0.18 (0.007)
MATCHING SUFFIX*
6.10 (0.240) 0.33 (0.013)
HP 7860X DATE CODE
6.60 (0.260)
YYWW 7.36 (0.290)
7.88 (0.310) 5° TYP.

PIN ONE 1 2 3 4

1.78 (0.070) MAX.

1.19 (0.047) MAX.

4.70 (0.185) MAX. PIN DIAGRAM

1 VDD1 VDD2 8
PIN ONE
0.51 (0.020) MIN.
2 VIN+ MCLK 7
2.92 (0.115) MIN.

3 VIN– MDAT 6
0.76 (0.030) 0.65 (0.025) MAX.
1.24 (0.049) 4 GND1 GND2 5
2.28 (0.090)
2.80 (0.110)

DIMENSIONS IN MILLIMETERS AND (INCHES).

*ALL UNITS WITHIN EACH HCPL-7860 STANDARD PACKAGING INCREMENT (EITHER 50 PER TUBE OR 1000 PER REEL)
HAVE A COMMON MARKING SUFFIX TO REPRESENT AN ABSOLUTE REFERENCE VOLTAGE TOLERANCE OF ± 1%.
AN ABSOLUTE REFERENCE VOLTAGE TOLERANCE OF ± 4% IS GUARANTEED BETWEEN STANDARD PACKAGING
INCREMENTS.

1-267
8-pin DIP Gull Wing Surface Mount Option 300

PIN LOCATION (FOR REFERENCE ONLY)

9.65 ± 0.25 1.02 (0.040)
(0.380 ± 0.010) 1.19 (0.047)

8 7 6 5
4.83 TYP.
(0.190)
6.350 ± 0.25
(0.250 ± 0.010) 9.65 ± 0.25
(0.380 ± 0.010)

1 2 3 4
MOLDED
0.380 (0.015)
1.19 (0.047) 0.635 (0.025)
1.78 (0.070)

1.780 9.65 ± 0.25

(0.070) (0.380 ± 0.010)
1.19 MAX.
(0.047) 7.62 ± 0.25
MAX. (0.300 ± 0.010)
0.255 (0.075)
4.19 MAX. 0.010 (0.003)
(0.165)

1.080 ± 0.320 0.635 ± 0.25

(0.043 ± 0.013) (0.025 ± 0.010)
0.51 ± 0.130
2.540 (0.020 ± 0.005) 12° NOM.
(0.100)
BSC

DIMENSIONS IN MILLIMETERS (INCHES).

TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 LEAD COPLANARITY
xx.xxx = 0.005 MAXIMUM: 0.102 (0.004)

Package Characteristics
Unless otherwise noted, all specifications are at TA = +25°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions Note
Input-Output Momentary VISO 3750 Vrms RH ≤ 50%, t = 1 min. 14,15
Withstand Voltage
(See note ** below)
Resistance (Input - Output) RI-O 1012 1013 Ω VI-O = 500 Vdc 15
1011 TA = 100°C
Capacitance CI-O 0.7 pF f = 1 MHz
(Input - Output)
Input IC Junction-to-Case θjci 96 °C/W Thermocouple located at
Thermal Resistance center underside of
Output IC Junction-to-Case θjco 114 °C/W package
Thermal Resistance
** The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or HP Application Note
1074, Optocoupler Input-Output Endurance Voltage.

1-268
Maximum Solder Reflow Thermal Profile

260
240
∆T = 145°C, 1°C/SEC
220
∆T = 115°C, 0.3°C/SEC
200
TEMPERATURE – °C

180
160
140
120
100
80
∆T = 100°C, 1.5°C/SEC
60
40
20
0
0 1 2 3 4 5 6 7 8 9 10 11 12
TIME – MINUTES

(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)

Regulatory Information
The HCPL-7860 (isolated modulator) has been approved by the following organizations:

UL VDE (Pending) CSA

Recognized under UL 1577, Approved under VDE 0884/06.92 Approved under CSA Component
Component Recognition with VIORM = 848 VPEAK. Acceptance Notice #5, File CA
Program, File E55361. 88324.

VDE 0884 Insulation Characteristics

Description Symbol Characteristic Unit
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 Vrms I - IV
for rated mains voltage ≤ 600 Vrms I - III
Climatic Classification 40/85/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 848 V PEAK
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 VPR 1590 V PEAK
sec, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, VPR 1273 V PEAK
Partial Discharge < 5 pC
Highest Allowable Overvoltage
(Transient Overvoltage tini = 10 sec) VIOTM 6000 V PEAK
Safety-Limiting Values–Maximum Values Allowed in the
Event of a Failure, also see Figure 13.
Case Temperature TS 175 °C
Input Power IS, INPUT 80 mW
Output Power PS, OUTPUT 250 mW
Insulation Resistance at TSI, VIO = 500 V RS ≥ 109 Ω
*Refer to the optocoupler section of the Optoelectronics Designer's Catalog, under Product Safety Regulations section, (VDE 0884)
for a detailed description of Method a and Method b partial discharge test profiles.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.

1-269
 300

250
PSi, OUTPUT
PSi – POWER – mW

200
PSi, INPUT

150
MAX. OPERATING
TEMP. IS 100 °C
100

50

0
0 50 100 150 200
TA – TEMPERATURE – °C

Figure 13. Dependence of Safety-

Limiting Values on Temperature.

Insulation and Safety Related Specifications

Parameter Symbol Value Units Conditions
Minimum External Air Gap L(I01) 7.4 mm Measured from input terminals to output
(Clearance) terminals, shortest distance through air.
Minimum External Tracking L(I02) 8.0 mm Measured from input terminals to output
(Creepage) terminals, shortest distance path along body
Minimum Internal Plastic Gap 0.5 mm Insulation thickness between emitter and
(Internal Clearance) detector; also known as distance through
insulation.
Tracking Resistance CTI 175 Volts DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking Index)
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.

Absolute Maximum Ratings

Parameter Symbol Min. Max. Units Note
Storage Temperature TS -55 125 °C
Ambient Operating Temperature TA -40 +85 °C
Supply Voltages VDD1, VDD2 0 5.5 Volts
Steady-State Input Voltage VIN+, VIN- -2.0 VDD1 + 0.5 Volts 16
Two Second Transient Input Voltage -6.0
Output Voltages MCLK, MDAT -0.5 VDD2 +0.5 Volts
Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane 17
Solder Reflow Temperature Profile See Maximum Solder Reflow Thermal Profile section

Recommended Operating Conditions

Parameter Symbol Min. Max. Units Note
Ambient Operating Temperature TA -40 +85 °C
Supply Voltages VDD1, VDD2 4.5 5.5 V
Input Voltage VIN+, VIN- -200 +200 mV 16

1-270
Electrical Specifications, Isolated Modulator
Unless otherwise noted, all specifications are at VIN+ = 0 V and VIN- = 0 V, all Typical specifications are at
TA = 25°C and VDD1 = VDD2 = 5 V, and all Minimum and Maximum specifications apply over the following
ranges: TA = -40°C to +85°C, VDD1 = 4.5 to 5.5 V and VDD2 = 4.5 to 5.5 V.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Average Input Bias Current IIN -1.0 µA 14 18
Average Input Resistance RIN 270 kΩ
Input DC Common-Mode CMRRIN 55 dB 19
Rejection Ratio
Output Logic High Voltage VOH 3.9 4.9 V IOUT = -100 µA
Output Logic Low Voltage VOL 0.3 0.6 V IOUT = 1.6 mA
Output Short Circuit Current |IOSC| 10 mA VOUT = VDD2 or GND2 20
Input Supply Current IDD1 9.5 15 mA VIN+ = -350 mV 15
Output Supply Current IDD2 8.8 15 mA to +350 mV 16
Output Clock Frequency fCLK 9 11 14 MHz 17
Data Hold Time tHDDAT 15 ns 21
Notes:
14. In accordance with UL1577, for devices with minimum VISO specified at 3750 Vrms, each isolated modulator (optocoupler) is
proof-tested by applying an insulation test voltage greater than 4500 Vrms for one second (leakage current detection limit
II-O < 5 µa). This test is performed before the Method b, 100% production test for partial discharge shown in VDE 0884
Insulation Characteristics Table.
15. This is a two-terminal measurement: pins 1-4 are shorted together and pins 5-8 are shorted together.
16. If VIN- (pin 3) is brought above VDD1 - 2 V with respect to GND1 an internal optical-coupling test mode may be activated. This test
mode is not intended for customer use.
17. HP recommends the use of non-chlorinated solder fluxes.
18. Because of the switched-capacitor nature of the isolated modulator, time averaged values are shown.
19. CMRRIN is defined as the ratio of the gain for differential inputs applied between VIN+ and VIN- to the gain for common-mode
inputs applied to both VIN+ and VIN- with respect to input ground GND1.
20. Short-circuit current is the amount of output current generated when either output is shorted to VDD2 or GND2. Use under these
conditions is not recommended.
21. Data hold time is amount of time that the data output MDAT will stay stable following the rising edge of output clock MCLK.

1-271
 1 10.5
-40 °C
0 25 °C
-1 10.0 85 °C

-2
-3

IDD1 – mA
9.5
IIN – mA

-4
-5 9.0
-6
-7 8.5
-8
-9 8.0
-6 -4 -2 0 2 4 6 -400 -200 0 200 400
VIN – V VIN – mV

Figure 14. IIN vs. VIN. Figure 15. IDD1 vs. VIN.

9.4 11.05

9.2
CLOCK FREQUENCY – MHz

11.00
9.0
10.95
IDD2 – mA

8.8

8.6 10.90

8.4
-40 °C 10.85 VDD1 = 4.5 V
8.2 25 °C VDD1 = 5.0 V
85 °C VDD1 = 5.5 V
8.0 10.80
-400 -200 0 200 400 -40 -20 0 20 40 60 85

VIN – mV TEMPERATURE – °C

Figure 16. IDD2 vs. VIN. Figure 17. Clock Frequency vs. Temperature.

1-272
Digital Interface IC
Ordering Information
Specify Part Number followed by Option Number (if desired).

Example

HCPL-7870 Standard 16-pin DIP package, 25 per tube.

HCPL-0870#XXX
No Option = Standard 16-pin SO package, 47 per tube.
500 = Tape and Reel Packaging Option, 1000 per reel.

Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor.

Package Outline Drawings

Standard 16-pin DIP Package

16 15 14 13 12 11 10 9

R 0.030 x 0.030 DP TYPE NUMBER

HP 7870 DATE CODE

YYWW

1 2 3 4 5 6 7 8

0.310 ± 0.010
(OUTER TO OUTER)
0.754
0.258
7°
7°

0.060
0.150 ± 0.010
0.130
0.060

0.260
0.130 ± 0.010
0.010 ± 0.002

0.018 ± 0.003
0.060 0.310/0.380
(CENTER TO CENTER)
0.100 ± 0.010

DIMENSIONS IN INCHES.
TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = ± 0.01
xx.xxx = ± 0.002

1-273
Standard 16-pin SO Package

∅ 1.27 (0.050)
TOP VIEW BOTTOM VIEW x 0.075 (0.003)
PIN NO. 1 IDENTIFIER DEPTH
1.90 1.90
∅ 1.27 (0.050) x 0.075 (0.003) DEPTH (0.075)
(2x) EJECTOR PIN
(0.075)
0.33 x 45° SHINY SURFACE SHINY SURFACE
(0.013 x 45°) 16 15 14 13 12 11 10 9

7.544 ± 0.05 HP 0870 10.00–10.65

(0.297 ± 0.002) (0.394–0.419) TH XX
YYWW (TIP TO TIP)

1.27 1 2 3 4 5 6 7 8
(0.050)
1.27 (0.050)

SIDE VIEW R 0.18 (R 0.007) END VIEW

1.27 BSC 0.33–0.51 ALL CORNERS
1.016 ± 0.025 (0.050 BSC) (0.013–0.020) AND EDGES
(0.040 ± 0.001)
0.10–0.30
7° (0.004–0.0118)
PARTING
2.286 LINE
(0.090)
0.01 (0.004)
A
SEATING PLANE
0.23–0.32
10.21 ± 0.10 (0.0091–0.0125)
(0.402 ± 0.002) 2.386–2.586
(0.094–0.1018)
1.016 REF.
(0.040)

DIMENSIONS IN MILLIMETERS (INCHES).

TOLERANCES 0° – 8°
(UNLESS OTHERWISE SPECIFIED): xx.xx = ± 0.010
xx.xxx = ± 0.002
0.40 – 1.27 DETAIL A
(0.016 – 0.050)

1-274
Maximum Solder Reflow Thermal Profile
260
240
∆T = 145°C, 1°C/SEC
220
∆T = 115°C, 0.3°C/SEC
200
TEMPERATURE – °C

180
160
140
120
100
80
∆T = 100°C, 1.5°C/SEC
60
40
20
0
0 1 2 3 4 5 6 7 8 9 10 11 12
TIME – MINUTES

(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)

Absolute Maximum Ratings

Parameter Symbol Min. Max. Units Note
Storage Temperature TS -55 +125 °C
Ambient Operating Temperature TA -40 +85 °C
Supply Voltage VDD 0 5.5 V
Input Voltage All Inputs -0.5 VDD + 0.5 V
Output Voltage All Outputs -0.5 VDD + 0.5 V
Lead Solder Temperature 260°C for 10 seconds, 1.6 mm below seating plane 17
Solder Reflow Temperature Profile See Reflow Thermal Profile
Note:
17. HP recommends the use of non-chlorinated solder fluxes.

Recommended Operating Conditions

Parameter Symbol Min. Max. Units Note
Ambient Operating Temperature TA -40 +85 °C
Supply Voltage VDD 4.5 5.5 V
Input Voltage All Inputs 0 VDD V

1-275
Electrical Specifications, Digital Interface IC
Unless otherwise noted, all Typical specifications are at TA = 25°C and VDD = 5 V, and all Minimum and
Maximum specifications apply over the following ranges: TA = -40°C to +85°C and VDD = 4.5 to 5.5 V.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Supply Current IDD 20 35 mA fCLK = 10 MHz
DC Input Current IIN 0.001 10 µA
Input Logic Low Voltage VIL 0.8 V
Input Logic High Voltage VIH 2.0 V
Output Logic Low Voltage VOL 0.15 0.4 V IOUT = 4 mA
Output Logic High Voltage VOH 4.3 5.0 V IOUT = -400 µA
Clock Frequency (CCLK, fCLK 20 MHz
MCLK and SCLK)
Clock Period (CCLK, tPER 50 ns 18,
MCLK and SCLK) 19
Clock High Level Pulse tPWH 20 ns
Width (CCLK, MCLK
and SCLK)
Clock Low Level Pulse tPWL 20
Width (CCLK, MCLK
and SCLK)
Setup Time from DAT to tSUCLK 10 18
Rising Edge of CLK
(CDAT, CCLK, MDAT
and MCLK)
DAT Hold Time after tHDCLK 10
Rising Edge of CLK
(CDAT, CCLK, MDAT
and MCLK)
Setup Time from Falling tSUCL1 20
Edge of CLAT to First
Rising Edge of CCLK
Setup Time from Last tSUCL2 20
Rising Edge of CCLK
to Rising Edge of CLAT
Delay Time from Falling tDSDAT 15 19
Edge of SCLK to SDAT
Setup Time from Data tSUS 200
Ready to First Falling
Edge of SCLK
Setup Time from CHAN tSUCHS 20
to falling edge of CS
Reset High Level Pulse tPWR 100
Width

1-276
 tSUCL1 tSUCL2

CLAT

CDAT B7 B6 B5 B4 B3 B2 B1 B0

tHDCLK
tSUCLK

tPWH

CCLK

tPER
tPWL

Figure 18. Serial Configuration Interface Timing.

CHAN

tSUCHS

CS

SDAT B14 B13 B12 B11 B10 B1 B0

tDSDAT
tPWH

SCLK 1 2 3 4 5 6 15 16

tPER
tPWL
tSUS
tC

Figure 19. Conversion Timing.

1-277
Applications The primary functions of the effective sampling time or reduce
Information HCPL-x870 Digital Interface IC conversion time to less than 1 µs,
are to derive a multi-bit output a fast over-range detection circuit
Product Description signal by averaging the single-bit that rapidly indicates when the
The HCPL-7860 Isolated Modula- modulator data, as well as to magnitude of the input signal is
tor (optocoupler) uses sigma- provide a direct microcontroller beyond full-scale, an adjustable
delta modulation to convert an interface. The effective resolution threshold detection circuit that
analog input signal into a high- of the multi-bit output signal is a indicates when the magnitude of
speed (10 MHz) single-bit digital function of the length of time the input signal is above a user-
data stream; the time average of (measured in modulator clock adjustable threshold level, an
the modulator’s single-bit data is cycles) over which the average is offset calibration circuit, and a
directly proportional to the input taken; averaging over longer second multiplexed input that
signal. The isolated modulator’s periods of time results in higher allows a second Isolated
other main function is to provide resolution. The Digital Interface Modulator to be used with a
galvanic isolation between the IC can be configured for five single Digital Interface IC.
analog input and the digital conversion modes which have
output. An internal voltage different combinations of speed The digital output format of the
reference determines the full- and resolution to achieve the Isolated A/D Converter is 15 bits
scale analog input range of the desired level of performance. of unsigned binary data. The
modulator (approximately input full-scale range and code
± 320 mV); an input range of Other functions of the HCPL- assignment is shown in Table 1
± 200 mV is recommended to x870 Digital Interface IC include below. Although the output con-
achieve optimal performance. a Phase Locked Loop based pre- tains 15 bits of data, the effective
trigger circuit that can either give resolution is lower and is deter-
more precise control of the mined by selected conversion
mode as shown in Table 2 below.
Table 1. Input Full-Scale Range and Code Assignment.
Analog Input Voltage Input Digital Output
Full Scale Range 640 mV 32768 LSBs
Minimum Step Size 20 µV 1 LSB
+Full Scale +320 mV 111111111111111
Zero 0 mV 100000000000000
-Full Scale -320 mV 000000000000000

Table 2. Isolated A/D Converter Typical Performance Characteristics.

Signal-to- Effective Conversion Time (µs) Signal
Signal
Conversion Noise Ratio Resolution Pre-Trigger Mode Delay Bandwidth
Mode (dB) (bits) 0 1 2 (µs) (kHz)
1 83 13.5 188 94 94 3.4
2 79 12.8 95 47 47 6.9
3 73 11.9 37 18 0.7 18 22
4 66 10.7 19 10 10 45
5 53 8.5 10 5 5 90
Note: Bold italic type indicates Default values.

1-278
Digital Interface impedance state after a few sion cycle. A logic low level
Timing cycles of the Isolated Modulator’s selects channel one, a high level
clock. selects channel 2. CHAN should
Power Up/Reset not be changed during a conver-
At power up, the digital interface The amount of time between the sion cycle. The state of the CHAN
IC should be reset either falling edge of CS and the rising signal has no effect on the
manually, by bringing the RESET edge of SDAT depends on which behavior of either the over-range
pin (pin 9) high for at least conversion and pre-trigger modes detection circuit (OVR1) or the
100 ns, or automatically by are selected; it can be as low as adjustable threshold detection
connecting a 10 µF capacitor 0.7 µs when using pre-trigger circuit (THR1). Both OVR1 and
between the RESET pin and VDD mode 2, as explained in the THR1 continuously monitor
(pin 16). The RESET pin operates Digital Interface Configuration channel 1 independent of the
asynchronously and places the IC section. CHAN signal. CHAN also does not
in its default configuration, as affect the behavior of the pre-
specified in the Digital Interface Serial Configuration trigger circuit, which is tied to
Configuration section. Timing the conversion timing of channel
The HCPL-x870 Digital Interface 1, as explained in the Digital
Conversion Timing IC is programmed using the Interface Configuration section.
Figure 19 illustrates the timing Serial Configuration Interface
for one complete conversion (SCI) which consists of the clock
cycle. A conversion cycle is (CCLK), data (CDAT), and Digital Interface
initiated on the falling edge of the enable/latch (CLAT) signals.
convert start signal (CS); CS
Configuration
Figure 18 illustrates the timing
should be held low during the for the serial configuration inter-
Configuration Registers
entire conversion cycle. When CS face. To send a byte of configura- The Digital Interface IC contains
is brought low, the serial output tion data to the HCPL-x870, first four 6-bit configuration registers
data line (SDAT) changes from a bring CLAT low. Then clock in that control its behavior. The two
high-impedance to the low state, the eight bits of the configuration LSBs of any byte clocked into the
indicating that the converter is byte (MSB first) using CDAT and serial configuration port (CDAT,
busy. A rising edge on SDAT the rising edge of CCLK. After the CCLK, CLAT) are used as address
indicates that data is ready to be last bit has been clocked in, bits to determine which register
clocked out. The output data is bringing CLAT high again will the data will be loaded into.
clocked out on the negative edges latch the data into the appropri- Registers 0 and 1 (with address
of the serial clock pulses (SCLK), ate configuration register inside bits 00 and 01) specify the
MSB first. A total of 16 pulses is the interface IC. If more than conversion and offset calibration
needed to clock out all of the data. eight bits are clocked in before modes of channels 1 and 2,
After the last clock pulse, CS CLAT is brought high, only the register 2 (address bits 10)
should be brought high again, last eight bits will be used. Refer specifies the behavior of the
causing SDAT to return to a high- to the Digital Interface Configura- adjustable threshold circuit, and
impedance state, completing the tion section to determine appro- register 3 (address bits 11)
conversion cycle. If the external priate configuration data. If the specifies which pre-trigger mode
circuit uses the positive edges of default configuration of the to use for channel 1. These
SCLK to clock in the data, then a digital interface IC is acceptable, registers are illustrated in Table 3
total of sixteen bits is clocked in, then CCLK, CDIN and CLAT may below, with default values
the first bit is always high be connected to either VDD or indicated in bold italic type. Note
(indicating that data is ready) GND. that there are several reserved
followed by 15 data bits. If fewer bits which should always be set
than 16 cycles of SCLK are input Channel Select Timing low and that the configuration
before CS is brought high, the registers should not be changed
The channel select signal (CHAN)
conversion cycle will terminate during a conversion cycle.
determines which input channel
and SDAT will go to the high- will be used for the next conver-

1-279
Table 3. Register Configuration.
Configuration Data Bits Address Bits
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Channel 1 Conversion Mode Channel 1 Reserved
Offset Cal
0
High High Low Low Low Low Low Low
Channel 2 Conversion Mode Channel 2 Reserved
Offset Cal
1
High High Low Low Low Low Low High
Threshold Threshold Level
Detection Time
2
High Low Low Low Low Low High Low
Pre-Trigger Mode Reserved
3
Low Low Low Low Low Low High High
Note: Bold italic type indicates default values. Reserved bits should be set low.

Conversion Mode determine the conversion mode a summary of how performance

The conversion mode determines for the appropriate channel. The changes as a function of conver-
the speed/resolution trade-off for bit settings for choosing a partic- sion mode setting. Combinations
the Isolated A/D converter. The ular conversion mode are shown of data bits not specified in Table
four MSBs of registers 0 and 1 in Table 4 below. See Table 2 for 4 below are not recommended.

Table 4. Conversion Mode Configuration.

Conversion Configuration Data Bits
Mode Bit 7 Bit 6 Bit 5 Bit 4
1 Low High Low High
2 Low Low High High
3 High High High Low
4 High High Low Low
5 High Low High Low
Note: Bold italic type indicates default values.

1-280
Pre-Trigger Mode ately following the convert start periodic. If the signal is not
The pre-trigger mode refers to command. The weighting func- periodic and pre-trigger mode 1
the operation of a PLL-based tion increases for half of the con- or 2 is selected, then the pre-
circuit that affects the sampling version cycle and then decreases trigger circuit will not function
behavior and conversion time of back to zero, at which time the properly.
the A/D converter when channel 1 data ready signal is given,
is selected. The PLL pre-trigger completing the conversion cycle. An important distinction should
circuit has two modes of opera- The analog signal is effectively be made concerning the differ-
tion; the first mode allows more sampled at the peak of the ence between conversion time
precise control of the time at weighting function, half-way and signal delay. As can be seen
which the analog input voltage is through the conversion cycle. in Figure 20, the amount of time
effectively sampled, while the This is the default mode. from the peak of the weighting
second mode essentially function (when the input signal is
eliminates the time between when If the convert start signal is being sampled) to when output
the external convert start periodic (i.e., at a fixed fre- data is ready is the same for all
command is given and when out- quency) and the PLL pre-trigger three modes. This is the actual
put data is available (reducing it circuit is enabled (pre-trigger delay of the analog signal through
to less than 1 µs). A brief modes 1 or 2), either the peak of the A/D converter and is indepen-
description of how the A/D con- the weighting function or the end dent of the “conversion time,”
verter works with the pre-trigger of the conversion cycle can be which is simply the time between
circuit disabled will help explain aligned to the external convert the convert start signal and the
how the pre-trigger circuit affects start command, as shown in data ready signal. Because signal
operation when it is enabled. Figure 20. The Digital Interface delay is the true measure of how
IC can therefore synchronize the much phase shift the A/D
With the pre-trigger circuit is conversion cycle so that either converter adds to the signal, it
disabled (pre-trigger mode 0), the beginning, the middle, or the should be used when making
Figure 20 illustrates the relation- end of the conversion is aligned calculations of phase margin and
ship between the convert start with the external convert start loop stability in feedback
command, the weighting function command, depending on whether systems.
used to average the modulator pre-trigger mode 0, 1, or 2 is
data, and the data ready signal. selected, respectively. The only There are different reasons for
The weighted averaging of the requirement is that the convert using each of the pre-trigger
modulator data begins immedi- start signal for channel 1 be modes. If the signal is not

WEIGHTING
FUNCTION

CONVERT START – CS

DATA READY – SDAT

A) PRE-TRIGGER MODE 0 B) PRE-TRIGGER MODE 1 C) PRE-TRIGGER MODE 2

Figure 20. Pre-Trigger Modes 0, 1, and 2.

1-281
periodic, then the pre-trigger The pre-trigger circuit functions start signals are periodic while
circuit should be disabled by only with channel 1; the circuit channel 1 is selected, then the
selecting pre-trigger mode 0. If ignores any convert start signals pre-trigger circuit will function
the most time-accurate sampling while channel 2 is selected with properly.
of the input signal is desired, the CHAN input. This allows
then mode 1 should be selected. conversions on channel 2 to be The three different pre-trigger
If the shortest possible conver- performed between conversions modes are selected using bits 6
sion time is desired, then mode 2 on channel 1 without affecting and 7 of register 3, as shown in
should be selected. the operation of the pre-trigger Table 5 below.
circuit. As long as the convert

Table 5. Pre-Trigger Mode Configuration.

Configuration Data Bits
Pre-Trigger Mode Bit 7 Bit 6
0 Low Low
1 Low High
2 High Don’t Care
Note: Bold italic type indicates default values.

Offset Calibration the selected channel (register 5. Send another configuration

The offset calibration circuit can 0 for channel 1, register 1 for byte to the appropriate regis-
be used to separately calibrate channel 2). Bit 3 of the ter for the selected channel,
the offsets of both channels 1 and configuration byte should be setting bit 3 low to disable
2. The offset calibration circuit set high to enable offset calibration mode and setting
contains a separate offset register calibration mode and bits 4 bits 4 through 7 to select the
for each channel. After an offset through 7 should be set to desired conversion mode for
calibration sequence, the offset select conversion mode 1 to subsequent conversions on
registers will contain a value achieve the highest resolution that channel.
equal to the measured offset, measurement of the offset.
which will then be subtracted 4. Perform one complete conver- To calibrate both channels,
from all subsequent conversions. sion cycle by bringing CS low perform the above sequence for
A hardware reset (bringing the until SDAT goes high, indicat- each channel. The offset
RESET pin high for at least ing completion of the conver- calibration sequence can be
100 ns) is required to reset the sion cycle. Because bit 3 of the performed as often as needed.
offset calibration registers to configuration has been set The table below summarizes how
zero. high, the uncalibrated output to turn the offset calibration
data from the conversion will mode on or off using bit 3 of
The following sequence is be stored in the appropriate configuration registers 0 and 1.
recommended for performing an offset calibration register and
offset calibration: will be subtracted from all Table 6. Offset Calibration
1. Select the appropriate channel subsequent conversions on Configuration.
using the CHAN pin (low = that channel. If multiple Configuration
conversion cycles are Offset
channel 1, high = channel 2). Data Bits
performed while the offset Calibration
2. Force zero volts at the input of Mode Bit 3
the selected isolated calibration mode is enabled,
the uncalibrated data from the Off Low
modulator.
last conversion cycle will be On High
3. Send a configuration data byte
stored in the offset calibration
to the appropriate register for Note: Bold italic type indicates default
register. values.

1-282
Over-Range Detection Adjustable Threshold are programmable using bits 2
The over-range detection circuit Detection through 7 of configuration
allows fast detection of when the The adjustable threshold detector register 2, as shown in Tables 7
magnitude of the input signal on causes the THR1 output to go and 8 below.
channel 1 is near or beyond full high when the magnitude of the
scale, causing the OVR1 output to input signal on channel 1 exceeds As with the over-range detector,
go high. This circuit can be very a user-defined threshold level. the adjustable threshold detector
useful in current-sensing applica- The threshold level can be set to continuously monitors channel 1
tions for quickly detecting when a one of 16 different values independent of which channel is
short-circuit occurs. The over- between approximately 160 mV selected with the CHAN signal.
range detection circuit works by and 310 mV. The adjustable This allows continuous monitor-
detecting when the modulator threshold detector uses a smaller ing of channel 1 for faults while
output data has not changed state version of the main conversion converting Channel 2.
for at least 25 clock cycles in a circuit in combination with a
row, indicating that the input digital comparator to detect when
signal is near or beyond full- the magnitude of the input signal
Table 7. Threshold
scale, positive or negative. on channel 1 is beyond the
Detection Configuration.
Typical response time to over- defined threshold level. As with
range signals is less than 3 µs. the main conversion circuit, there Threshold Configuration
is a trade-off between speed and Detection Data Bits
The over-range circuit actually resolution with the threshold Time Bit 7 Bit 6
begins to indicate an over-range detector; selecting faster detec- 2 - 6 µs Low Low
condition when the magnitude of tion times exhibit more noise as 3 - 10 µs Low High
the input signal exceeds approxi- the signal passes through the
5 - 20 µs High Low
mately 250 mV; it starts to threshold, while slower detection
times offer lower noise. Both the 10 - 35 µs High High
generate periodic short pulses on
OVR1 which get longer and more detection time and threshold level Note: Bold italic type indicates default
frequent as the input signal values.
approaches full scale. The OVR1
output stays high continuously
Table 8. Threshold Level Configuration.
when the input is beyond full Configuration Data Bits
scale. Threshold Level Bit 5 Bit 4 Bit 3 Bit 2
± 160 mV Low Low Low Low
The over-range detection circuit
± 170 mV Low Low Low High
continuously monitors channel 1
independent of which channel is ± 180 mV High Low
selected with the CHAN signal. ± 190 mV High
This allows continuous monitor- ± 200 mV High Low Low
ing of channel 1 for faults while ± 210 mV High
converting an input signal on ± 220 mV High Low
channel 2.
± 230 mV High
± 240 mV High Low Low Low
± 250 mV High
± 260 mV High Low
± 270 mV High
± 280 mV High Low Low
± 290 mV High
± 300 mV High Low
± 310 mV High
Note: Bold italic type indicates default values.

1-283
Analog Interfacing drive circuit. If a dedicated capacitor (C2) is also recom-
Power Supplies and supply is required, in many cases mended at the input due to the
Bypassing it is possible to add an additional switched-capacitor nature of the
The recommended application winding on an existing trans- input circuit. The input bypass
circuit is shown in Figure 21. A former. Otherwise, some sort of capacitor also forms part of the
floating power supply (which in simple isolated supply can be anti-aliasing filter, which is
many applications could be the used, such as a line powered recommended to prevent high-
same supply that is used to drive transformer or a high-frequency frequency noise from aliasing
the high-side power transistor) is DC-DC converter. down to lower frequencies and
regulated to 5 V using a simple interfering with the input signal.
zener diode (D1); the value of An inexpensive 78L05 three-
resistor R1 should be chosen to terminal regulator can also be PC Board Layout
supply sufficient current from the used to reduce the floating supply The design of the printed circuit
existing floating supply. The voltage to 5 V. To help attenuate board (PCB) should follow good
voltage from the current sensing high-frequency power supply layout practices, such as keeping
resistor or shunt (Rsense) is noise or ripple, a resistor or bypass capacitors close to the
applied to the input of the HCPL- inductor can be used in series supply pins, keeping output
7860 (U2) through an RC anti- with the input of the regulator to signals away from input signals,
aliasing filter (R2 and C2). And form a low-pass filter with the the use of ground and power
finally, the output clock and data regulator’s input bypass planes, etc. In addition, the layout
of the isolated modulator are capacitor. of the PCB can also affect the
connected to the digital interface isolation transient immunity
IC. Although the application As shown in Figure 21, 0.1 µF (CMR) of the isolated modulator,
circuit is relatively simple, a few bypass capacitors (C1 and C3) due primarily to stray capacitive
recommendations should be should be located as close as coupling between the input and
followed to ensure optimal possible to the input and output the output circuits. To obtain
performance. power-supply pins of the isolated optimal CMR performance, the
modulator (U2). The bypass layout of the PC board should
The power supply for the isolated capacitors are required because minimize any stray coupling by
modulator is most often obtained of the high-speed digital nature of maintaining the maximum
from the same supply used to the signals inside the isolated possible distance between the
power the power transistor gate modulator. A 0.01 µF bypass input and output sides of the
circuit and ensuring
FLOATING
POSITIVE
SUPPLY +5V
HV+

GATE DRIVE
CIRCUIT

R1

CCLK VDD
D1 C1
0.1 µF CLAT CHAN
5.1 V
VDD1 VDD2 CDAT SCLK
R2 39 Ω
VIN+ MCLK MCLK1 SDAT

MOTOR VIN- MDAT MDAT1 CS

+ - MCLK2 THR1
GND1 GND2 C3
RSENSE C2 0.1 µF
0.01 µF MDAT2 OVR1
HCPL-7860
GND RESET
TO
HCPL-X870 CONTROL
CIRCUIT
HV-

Figure 21. Recommended Application Circuit.

1-284
that any ground or power plane maximum value of the shunt is temperature coefficient (tempco)
on the PC board does not pass determined by the current being of the shunt can introduce
directly below or extend much measured and the maximum nonlinearity due to the signal
wider than the body of the recommended input voltage of dependent temperature rise of the
isolated modulator. the isolated modulator. The shunt. The effect increases as the
maximum shunt resistance can be shunt-to-ambient thermal
Shunt Resistors calculated by taking the maxi- resistance increases. This effect
The current-sensing shunt mum recommended input voltage can be minimized either by
resistor should have low and dividing by the peak current reducing the thermal resistance
resistance (to minimize power that the shunt should see during of the shunt or by using a shunt
dissipation), low inductance (to normal operation. For example, if with a lower tempco. Lowering
minimize di/dt induced voltage a motor will have a maximum the thermal resistance can be
spikes which could adversely RMS current of 10 A and can accomplished by repositioning
affect operation), and reasonable experience up to 50% overloads the shunt on the PC board, by
tolerance (to maintain overall during normal operation, then the using larger PC board traces to
circuit accuracy). Choosing a peak current is 21.1 A carry away more heat, or by
particular value for the shunt is (=10x1.414x1.5). Assuming a using a heat sink.
usually a compromise between maximum input voltage of
minimizing power dissipation and 200 mV, the maximum value of For a two-terminal shunt, as the
maximizing accuracy. Smaller shunt resistance in this case value of shunt resistance
shunt resistances decrease power would be about 10 mΩ. decreases, the resistance of the
dissipation, while larger shunt leads becomes a significant
resistances can improve circuit The maximum average power percentage of the total shunt
accuracy by utilizing the full dissipation in the shunt can also resistance. This has two primary
input range of the isolated be easily calculated by multiply- effects on shunt accuracy. First,
modulator. ing the shunt resistance times the the effective resistance of the
square of the maximum RMS shunt can become dependent on
The first step in selecting a shunt current, which is about 1 W in factors such as how long the
is determining how much current the previous example. leads are, how they are bent, how
the shunt will be sensing. The far they are inserted into the
graph in Figure 22 shows the If the power dissipation in the board, and how far solder wicks
RMS current in each phase of a shunt is too high, the resistance up the lead during assembly
three-phase induction motor as a of the shunt can be decreased (these issues will be discussed in
function of average motor output below the maximum value to more detail shortly). Second, the
power (in horsepower, hp) and decrease power dissipation. The leads are typically made from a
motor drive supply voltage. The minimum value of the shunt is material such as copper, which
limited by precision and accuracy has a much higher tempco than
MOTOR OUTPUT POWER – HORSEPOWER

40
requirements of the design. As the material from which the
440 the shunt value is reduced, the resistive element itself is made,
35 380
220 output voltage across the shunt is resulting in a higher tempco for
30 120 also reduced, which means that the shunt overall.
25 the offset and noise, which are
20 fixed, become a larger percentage Both of these effects are elimi-
15
of the signal amplitude. The nated when a four-terminal shunt
selected value of the shunt will is used. A four-terminal shunt has
10
fall somewhere between the two additional terminals that are
5 minimum and maximum values, Kelvin-connected directly across
0 depending on the particular the resistive element itself; these
0 5 10 15 20 25 30 35
requirements of a specific design. two terminals are used to monitor
MOTOR PHASE CURRENT – A (rms)
the voltage across the resistive
Figure 22. Motor Output Horsepower
When sensing currents large element while the other two
vs. Motor Phase Current and Supply enough to cause significant terminals are used to carry the
Voltage. heating of the shunt, the load current. Because of the
Kelvin connection, any voltage
1-285
drops across the leads carrying a tightly twisted pair of wires can wires or PC board traces to
the load current should have no accomplish the same thing. connect the isolated modulator
impact on the measured voltage. circuit to the shunt resistor. By
Also, multiple layers of the PC referencing the input circuit to
Several four-terminal shunts from board can be used to increase the negative side of the sense
Isotek (Isabellenhütte) suitable current carrying capacity. resistor, any load current induced
for sensing currents in motor Numerous plated-through vias noise transients on the shunt are
drives up to 71 Arms (71 hp or should surround each non-Kelvin seen as a common-mode signal
53 kW) are shown in Table 9; the terminal of the shunt to help and will not interfere with the
maximum current and motor distribute the current between the current-sense signal. This is
power range for each of the PBV- layers of the PC board. The PC important because the large load
series shunts are indicated. For board should use 2 or 4 oz. currents flowing through the
shunt resistances from 50 mΩ copper for the layers, resulting in motor drive, along with the
down to 10 mΩ, the maximum a current carrying capacity in parasitic inductances inherent in
current is limited by the input excess of 20 A. Making the the wiring of the circuit, can
voltage range of the isolated current carrying traces on the PC generate both noise spikes and
modulator. For the 5 mΩ and board fairly large can also offsets that are relatively large
2 mΩ shunts, a heat sink may be improve the shunt’s power compared to the small voltages
required due to the increased dissipation capability by acting as that are being measured across
power dissipation at higher a heat sink. Liberal use of vias the current shunt.
currents. where the load current enters and
exits the PC board is also If the same power supply is used
When laying out a PC board for recommended. both for the gate drive circuit and
the shunts, a couple of points for the current sensing circuit, it
should be kept in mind. The Shunt Connections is very important that the connec-
Kelvin connections to the shunt The recommended method for tion from GND1 of the isolated
should be brought together under connecting the isolated modula- modulator to the sense resistor
the body of the shunt and then tor to the shunt resistor is shown be the only return path for
run very close to each other to in Figure 21. VIN+ (pin 2 of the supply current to the gate drive
the input of the isolated modula- HPCL-7860) is connected to the power supply in order to
tor; this minimizes the loop area positive terminal of the shunt eliminate potential ground loop
of the connection and reduces the resistor, while VIN- (pin 3) is problems. The only direct con-
possibility of stray magnetic shorted to GND1 (pin 4), with the nection between the isolated
fields from interfering with the power-supply return path func- modulator circuit and the gate
measured signal. If the shunt is tioning as the sense line to the drive circuit should be the
not located on the same PC board negative terminal of the current positive power supply line.
as the isolated modulator circuit, shunt. This allows a single pair of

Table 9. Isotek (Isabellenhütte) Four-Terminal Shunt Summary.

Shunt Maximum Motor Power Range
Shunt Resistor Resistance Tol. RMS Current 120 Vac-440 Vac
Part Number mΩ % A hp kW
PBV-R050-0.5 50 0.5 3 0.8-3 0.6-2
PBV-R020-0.5 20 0.5 7 2-7 1.4-5
PBV-R010-0.5 10 0.5 14 4-14 3-10
PBV-R005-0.5 5 0.5 25 [28] 7-25 [8-28] 5-19 [6-21]
PBV-R002-0.5 2 0.5 39 [71] 11-39 [19-71] 8-29 [14-53]
Note: Values in brackets are with a heatsink for the shunt.

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In some applications, however, The 39 Ω resistor in series with Voltage Sensing
supply currents flowing through the input lead (R2) forms a low- The HCPL-7860 Isolated Modula-
the power-supply return path may pass anti-aliasing filter with the tor can also be used to isolate
cause offset or noise problems. In 0.01 µF input bypass capacitor signals with amplitudes larger
this case, better performance (C2) with a 400 kHz bandwidth. than its recommended input
may be obtained by connecting The resistor performs another range with the use of a resistive
VIN+ and VIN- directly across the important function as well; it voltage divider at its input. The
shunt resistor with two conduc- dampens any ringing which might only restrictions are that the
tors, and connecting GND1 to the be present in the circuit formed impedance of the divider be
shunt resistor with a third by the shunt, the input bypass relatively small (less than 1 kΩ)
conductor for the power-supply capacitor, and the inductance of so that the input resistance
return path, as shown in Figure wires or traces connecting the (280 kΩ) and input bias current
23. When connected this way, two. Undamped ringing of the (1 µA) do not affect the accuracy
both input pins should be input circuit near the input of the measurement. An input
bypassed. To minimize electro- sampling frequency can alias into bypass capacitor is still required,
magnetic interference of the the baseband producing what although the 39 Ω series damping
sense signal, all of the conductors might appear to be noise at the resistor is not (the resistance of
(whether two or three are used) output of the device. the voltage divider provides the
connecting the isolated modula- same function). The low-pass
tor to the sense resistor should be filter formed by the divider
either twisted pair wire or closely resistance and the input bypass
spaced traces on a PC board. capacitor may limit the achievable
bandwidth. To obtain higher
bandwidth, the input bypass
capacitor (C2) can be reduced,
but it should not be reduced
FLOATING much below 1000 pF to maintain
POSITIVE
SUPPLY adequate input bypassing of the
HV+
isolated modulator.
GATE DRIVE
CIRCUIT

R1

D1
5.1 V C1
0.1 µF
R2a 39 Ω
VDD1 VDD2
R2b 39 Ω VIN+ MCLK

MOTOR VIN- MDAT

+ -
GND1 GND2
RSENSE C2a C2b
0.01 µF 0.01 µF HCPL-7860

HV-

Figure 23. Schematic for Three Conductor Shunt Connection.

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