MAX2550

EVALUATION KIT AVAILABLE
MAX2550
Band I, V, and VIII WCDMA Femtocell
Transceiver with GSM Monitoring
General Description Benefits and Features
The MAX2550 is a complete single-chip RF-to-bits and S Single-Chip Femtocell Radio Transceiver
bits-to-RF radio transceiver. This device is in compliance
S WCDMA/HSPA+ Band I, V, and VIII Operation
with the 3GPP TS25.104 femtocell standard for Band I, V,
and VIII. It is equipped with multiple receive inputs and S TS25.104 Standard Compliant
transmit outputs for low band, high band, and macro-cell
S Multiple LNA Inputs for WCDMA, PCS, and GSM
monitoring (Table 1).
Macrocell Monitoring
This fully integrated transceiver facilitates compact radio
designs for dongle and standalone femtocell products by S High Level of Integration
minimizing external component count. Maxim’s MAX-PHY  On-Chip Fractional-N Frequency Synthesizers
serial interface is used to drastically reduce IC pin count, for LO Generation
while worldwide field-proven architecture accelerates  No Tx SAW Filters Required
time to product deployment.  Integrated PA Drivers for Lower-Cost Power
The device features unparalleled receive blocker perfor- Amplifier Designs
mance and the industry’s lowest noise figure for higher  12-Bit AFC DAC to Control TCXO
data rates and range. Low-power operational modes are  On-Chip Temperature Sensor
available to minimize power consumption. The transmit-
 Three General-Purpose Outputs
ter is designed to deliver EVM far exceeding the stand-
 Reference Clock with Selectable CMOS and Low
ard requirement at 0dBm.
Swing Output
The MAX2550–MAX2553 is a family of pin-compatible
 PLL Lock-Detect Output Through GPO3
transceivers that cover all major WCDMA and cdma2000®
bands. All parts are controlled by a 4-wire interface. S Optimized Receiver Performance
The MAX2550 is packaged in a compact 7mm x 7mm  Exceptional Receive Sensitivity
TQFN and specified over the -40NC to +85NC extended  High Dynamic Range Sigma-Delta ADCs Allow
temperature range. A complete radio reference design is Simple AGC Implementation with Switched Gain
available to facilitate custom designs. States
Functional Diagrams
Applications S Optimized Transmitter Performance
 Factory Calibrated for Gain, Carrier Leakage,
WCDMA Band I, V, and VIII Femtocells and Sideband Suppression
 10-Bit Gain Control Resolution for Better Power
Ordering Information and Simplified Block Diagram appear Accuracy
at end of data sheet.  60dB Gain Control Range
S Loopback Operating Mode from Tx Baseband
For related parts and recommended products to use with this part,
refer to www.maxim-ic.com/MAX2550.related. Input to Rx Baseband Output
S MAX-PHY Serial Digital Interface
S SPI Read/Write Functionality
S Operation Controlled by 4-Wire Serial Interface
S Low-Cost, 7mm x 7mm TQFN Package
Pin Configurations appear at end of data sheet.

Functional Diagrams continued at end of data sheet.
cdma2000 is a registered service mark of
UCSP is a trademark of Maxim Integrated Products, Inc.
Telecommunications Industry Association.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-6397; Rev 0; 7/12
MAX2550
ABSOLUTE MAXIMUM RATINGS
VCC_ to GND_.......................................................-0.3V to +3.9V Junction Temperature......................................................+150NC
RXIN_, MIXIN_, LNAOUT_ to GND_......................-0.3V to +1.2V Operating Temperature Range........................... -40NC to +85NC
All Pins except VCC_ to GND_.................-0.3V to (VCC_ + 0.3V) Storage Temperature Range............................. -65NC to +150NC
AC Input Signals..........................................................1.0V Peak Lead Temperature (soldering, 10s).................................+300NC
Digital Input Current......................................................... Q10mA Soldering Temperature (reflow).......................................+260NC
Maximum VSWR Without Damage.......................................... 8:1
Continuous Power Dissipation (TA = +70NC)
TQFN Multilayer Board
(derate 40mW/NC above +70NC)......................................3.2W
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)

TQFN
Junction-to-Ambient Thermal Resistance (BJA)...........25NC/W Junction-to-Case Thermal Resistance (BJC)......................1NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
DC ELECTRICAL CHARACTERISTICS
(VCC_ = 3.0V to 3.6V, TA = -40 to +85NC, 50I system, fREFIN = 19.2MHz, typical values are at VCC_ = 3.3V, TA = +25NC, unless
otherwise noted. Register settings as defined in tables following the specification tables.) (Note 2)
SPEC NO. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC1a Supply Voltage VCC_ 3.0 3.3 3.6 V
DC19a Full-duplex high band 298 390
DC19b Full-duplex low band 300 390
DC20 RXIN2 monitor 78 105
DC21 Operating Supply Current RXIN4 monitor 78 105
ICC_ mA
DC22 WCDMA RXIN5 monitor 72 95
DC23 Tx only 236 315
DC24 Idle Rx 43
DC25 Idle Tx 40
Operating Supply Current
DC3 ICC_ AFC DAC and SPI only 175 1000 FA
AFC-Only Mode
Operating Supply Current REFOUT = 500Ω || 22pF,
DC5 ICC_ 5.3 7.5 mA
Reference Buffer Mode all else = off
Operating Supply Current
DC6 ICC_ All functions off 14 1000 FA
Sleep Mode
DC11 Digital Input Logic-High 1.3 V
DC12 Digital Input Logic-Low 0.4 V
Input Current for Digital
DC13 10 |FA|
Control Pins
DC16 GPO Sink Current VOUT = 0.35V, DOUT_DRV = 01 1.0 1.8 mA
VOUT = VCC_ - 0.3V,
DC17 GPO Source Current 1.0 1.9 mA
DOUT_DRV = 01
Maxim Integrated 2
MAX2550
AC ELECTRICAL CHARACTERISTICS
(MAX2550 EV kit, TA = -40NC to +85NC, registers set as described in Tables 20–51, VCC_ = 3.0V to 3.6V, fREFIN = 19.2MHz, all sensi-
tivity levels and blocker levels are antenna referred. Typical values are at VCC_ = 3.3V, TA = +25NC and mid-band, unless otherwise
noted. Tx specifications are referred to the input pin of the chip.) (Note 2)
Band I Duplexer Specifications

(Diplexer between antenna and duplexer loss: 0.3dB (applies to all Rx modes).)
Antenna—Uplink Port (Applies to Uplink WCDMA Rx Mode on RXIN1)

Uplink 1870 to 1980 to 2020 to 2300 to 2500 to 4500 to
BAND (MHz) 1 to 1870
1920 to 1980 1920 2020 2200 2500 4500 12750
ATTENUATION Attenuation Minimum Attenuation
(dB) 2 32 12 12 37 27 12 7
Rx SAW FILTER RESPONSE
BAND (MHz) Out of band
ATTENUATION Required minimum attenuation relative to in-band
(dB) 25
Band I Uplink WCDMA Rx Mode on RXIN1 (Full Duplex)

SPEC NO. PARAMETER CONDITIONS MIN TYP MAX UNITS
WCDMA FDD Band I uplink (lowest to highest
Wb1fu-0 Frequency Band 1922.4 1977.6 MHz
channel center frequency)
Tx on at -27dBm, LNA gain mid gain, PGA gain
register set to 9, assumed SNDR > -17.5dB at
sensitivity, using UL reference measurement
Sensitivity
channel (12.2kbps) as specified in A.2 3GPP
Wb1fu-1 3GPP TS25.104 -116 -107 dBm
25.104, tested by measurement of SNDR at
Section 7.2.1
output on CW input signal at -90dBm, SNDR
at MAX-PHY filter output established with FFT,
LNA linearity set to high
Tx on at -27dBm, LNA gain high, PGA gain
Sensitivity with LNA in channel (12.2kbps) as specified in A.2 3GPP
Wb1fu-1a -119 -107 dBm
High-Gain Mode 25.104, tested by measurement of SNDR at
at MAX-PHY filter output established with FFT,
LNA linearity set to high
PIN = -20dBm, LNA gain low, PGA gain register
Wb1fu-3 High-Level EVM WCDMA 4.5 %
set to 1
Maxim Integrated 3
MAX2550
AC ELECTRICAL CHARACTERISTICS (continued)
Band I Uplink WCDMA Rx Mode on RXIN1 (Full Duplex) (continued)

Tx on -27dBm, LNA gain high, PGA gain

sensitivity, inferring signals at front-end input
Sensitivity with
-28dBm, at 5MHz offset and -5MHz offset and
Adjacent Channel
modulated as in 3GPP. Using UL reference
Wb1fu-4 Interference -109 -101 dBm
measurement channel (12.2kbps) as specified
3GPPP TS25.104 Section
in A.2 3GPP 25.104. Production tested by
7.4.1
measurement if SNDR at output on CW input
signal at -90dBm. SNDR at MAX-PHY filter
output established with FFT.
Tx on -27dBm, LNA gain high, PGA gain

sensitivity, inferring signals at front-end input
Sensitivity with -30dBm, at 10MHz offset and -5MHz offset and
In-Band Blocking modulated as in 3GPPP. Using UL reference
Wb1fu-5 Interference measurement channel (12.2kbps) as specified -117 -101 dBm
3GPPP TS25.104 Section in A.2 3GPP 25.104. Production tested by
7.5.1 measurement if SNDR at output on CW input
signal at -90dBm test only worst case in
production. SNDR at MAX-PHY filter output
established with FFT.
Front-end assumed response as above, Tx on
at -27dBm, LNA high gain, PGA gain register
set to 6, assumed SNDR > -17.5dB at
Sensitivity with sensitivity, interfering signal at front-end input
Out-of-Band Blocking -15dBm CW, 1MHz to 1900MHz and 2000MHz
Wb1fu-6 Interference to 12750MHz using UL reference measurement -112 -101 dBm
3GPP TS25.104 Section channel (12.2kbps) as specified in A.2 3GPP
7.5.1 25.104, tested by measurement of SNDR at
at MAX-PHY filter output established with FFT
(Note 3)
Maxim Integrated 4
MAX2550
Band I Uplink WCDMA Rx Mode on RXIN1 (Full Duplex) (continued)

Tx on at -27dBm; LNA gain high; PGA gain
register set to 6; assumed SNDR > -17.5dB at
sensitivity; interfering signals at front-end input
Sensitivity with -38dBm, at 10MHz offset (CW) and 20MHz
Intermodulation Interference offset (modulated) as in 3GPP; using UL
Wb1fu-8 -118 -101 dBm
3GPP TS25.104 Section reference measurement channel (12.2kbps) as
7.6.1 specified in A.2 3GPP 25.104; tested by
measurement of SNDR at output on CW input
signal at -90dBm; SNDR at MAX-PHY filter
output established with FFT (Note 3)
30MHz to 1GHz, measured in 100kHz BW -100 -60
Spurious Emissions 1GHz to 12.75GHz, measured in 1MHz BW,
Out-of-Band with the exception of frequencies between
Wb1fu-10 dBm
3GPP TS25.104 12.5MHz below the first carrier frequency and -75 -50
Section 7.7.1 12.5MHz above the last carrier frequency used
by the BS (Note 3)
Spurious Emissions
in Receive Bands Front-end assumed response as above,
Wb1fu-11 -95 -80 dBm
3GPP TS25.104 1920MHz to 1980MHz (Note 3)
Section 7.9.2
LNA high gain; PGA gain register set to 6;

tested on CW input signal at -90dBm;
Conversion Gain calculated by subtracting the FE input signal
Wb1fu-12 21 30 36 dB
High LNA Gain in dBm from the ADC output signal in dBFS at
digital filter outputs, includes digital gain to the
16-bit output
LNA mid gain; PGA gain register set to 9;

Wb1fu-13 21 30 36 dB
Mid LNA Gain in dBm from the ADC output signal in dBFS at
16-bit output
LNA gain low; PGA gain register set to 1;
Wb1fu-14 -13 -7 -3.5 dB
Low LNA Gain in dBm from the ADC output signal in dBFS at
16-bit output
Maxim Integrated 5
MAX2550
Antenna—Downlink Port (Applies to Downlink WCDMA Rx Mode on RXIN5)

Downlink 2025 to 2050 to 2185 to 2230 to 2255 to
2110 to 2170 2050 2095 2230 2255 12750
ATTENTUATION Attenuation Minimum Attenuation
(dB) 2 15 10 0 0 10 15
Band I Downlink WCDMA Rx Mode on RXIN5 (Monitor)

Wb1fd-0 Frequency Band 2112.4 2167.6 MHz
LNA gain high, PGA gain register set to 11,
assumed SNDR > -7dB at sensitivity, using UL
reference measurement channel, (12.2kbps) as
Sensitivity
specified in C.3.1 3GPP 25.101, tested by
Wb1fd-1 3GPP TS25.101 -110 dBm
Section 7.3.1
signal at -90dBm, SNDR at MAX-PHY filter
output established with FFT, LNA linearity set to
high
LNA gain high; PGA gain register set to 11;

assumed SNDR > -7dB at sensitivity; interfering
signals at front-end input -52dBm, at 5MHz
Sensitivity with Adjacent
offset and -5MHz offset and modulated as in
Channel Interference
Wb1fd-4 3GPP; using UL reference measurement channel -110 dBm
3GPP TS25.101
(12.2kbps) as specified in C.3.1 3GPP 25.101;
Section 7.5.1
production tested by measurement of SNDR at
output on CW input signal at -90dBm; SNDR at
MAX-PHY filter output established with FFT
LNA gain medium, PGA gain register set to 6;

tested SNDR at output; interfering signals at
Sensitivity with Adjacent front-end input -25dBm, at 5MHz offset and
Channel Interference -5MHz offset and modulated as in 3GPP; using
Wb1fd-4a 3GPP TS25.101 UL reference measurement channel (12.2kbps) -94 dBm
Section 7.5.1 as specified in C.3.1 3GPP 25.101; production
CASE 2 tested by measurement of SNDR at output on
CW input signal at -69dBm; SNDR at MAX-PHY
filter output established with FFT
Maxim Integrated 6
MAX2550
Band I Downlink WCDMA Rx Mode on RXIN5 (Monitor) (continued)

LNA gain high, PGA gain register set to 11;
Sensitivity with signals at front-end input -46dBm, at 10MHz
Intermodulation offset (CW) and 20MHz offset (modulated ) as in
Wb1fd-8 Interference 3GPP; using UL reference measurement channel -110 dBm
3GPP TS25.101 (12.2kbps) as specified in C.3.1 3GPP 25.101;
Section 7.8.1 production tested by measurement of SNDR at
Spurious Emissions
Out-of-Band 30MHz to 12750MHz in 100kHz bandwidth
Wb1fd-10 -80 -60 dBm
3GPP TS25.101 (Note 3)
Section 7.9.1
Spurious Emissions
Front-end assumed response as above,
in Receive Bands
Wb1fd-11 1920MHz to 1980MHz and 2110MHz to -95 -80 dBm
3GPP TS25.101
2170MHz (Note 3)
section 7.9.2
tested on CW input signal at -90dBm; calculated
Conversion Gain
Wb1fd-12 by subtracting the FE input signal in dBm from 33 44 49 dB
High LNA Gain
the ADC output signal in dBFS at digital filter
outputs, includes digital gain to the 16-bit output
LNA gain low; PGA gain register set to 0; tested

on CW input signal at -20dBm; calculated by
Conversion Gain
Wb1fd-13 subtracting the FE input signal in dBm from the -22 -13 -7.5 dB
Low LNA Gain
ADC output signal in dBFS at digital filter
Maxim Integrated 7
MAX2550
DCS Band Rx Mode on RXIN2

Assumed External Front-End Filtering Characteristics Between Antenna and LNA
In-Band Out of Band (a) Out of Band (b) Out of Band (c) Out of Band (d)
BAND (MHz)
1805 to 1880 0.1 to 1705 1705 to 1785 1920 to 1980 1980 to 4000
(dB) 3.5 27.5 15.5 15.5 27.5
DCS Band Rx Mode on RXIN2

At pin RXIN2, 200KHz channel raster, lowest to
dcs -0 RF Frequency 1805.2 1879.8 MHz
highest channel center frequency
assumed SNDR > 7dB at sensitivity; using static
Sensitivity
E-TCH/F as specified in 3GPP TS 100.910;
dcs-1 3GPP TS100.910 -108 dBm
Section 6.2

production tested on CW input signal at
Conversion Gain -102dBm; calculated by subtracting the FE input
dcs-2 40 46 dB
High LNA Gain signal in dBm from the output signal in dBFS
at digital filter outputs, includes digital gain to
the16-bit output
EGSM/WCDMA Band Rx Mode on RXIN4

External Front-End Filtering Characteristics EGSM
In-Band Out of Band Out of Band Out of Band Out of Band (d)
925 to 960 (a) 0.1 to 905 (b) N/A (c) N/A 980 to 12750
(dB) 3.5 19.5 24.5 N/A N/A 24.5
Assumed External Front-End Filtering Characteristics Between Antenna and LNA:

(WCDMA on RXIN4)
Downlink 1 to
BAND (MHz) 824 to 849 914 to 3000 3000 to 6000
869 to 894 804
Attenuation Minimum Attenuation
ATTENUATION (dB)
3 37 51 35 20
Maxim Integrated 8
MAX2550
EGSM/WCDMA Band Rx Mode on RXIN4

At pin RXIN4, 200KHz channel raster, EGSM
G900 -0 RF Frequency 925.2 959.8 MHz
lowest to highest channel center frequency
assumed SNDR > 7dB at sensitivity; using static
Sensitivity
E-TCH/F as specified in 3GPP TS 100.910;
G900-1 3GPP TS100.910 -110 dBm
Section 6.2

production tested on CW input signal at
Conversion Gain -102dBm; calculated by subtracting the FE input
G900-2 43 50 dB
High LNA Gain signal in dBm from the output signal in dBFS
at digital filter outputs, includes digital gain to
the16-bit output
Band V Duplexer Specifications

Uplink
BAND (MHz) 1 to 804 869 to 894 894 to 2500 2500 to 3000 3000 to 6000
824 to 849
ATTENUATION (dB)
2 32 43 32 22 15
BAND (MHz) Out-of-Band
Required minimum attenuation relative to in-band
ATTENUATION (dB)
25
Maxim Integrated 9
MAX2550
Band V Uplink WCDMA Rx Mode on RXIN3 (Full Duplex)

WCDMA FDD Band V uplink (lowest to highest
Sensitivity
Wb5fu-1 3GPP TS25.104 -116 -107 dBm
Section 7.2.1
output on CW input signal at -90dBm, SNDR at
MAX-PHY filter output established with FFT, LNA
linearity set to high
Wb5fu-2 -119 -107 dBm
PIN = -20 dBm, LNA gain low, PGA gain register
set to 1
Tx on at -27dBm; LNA gain high; PGA gain register

set to 3; assumed SNDR > -17.5dB at sensitivity;
interfering signals at front-end input -28dBm, at
5MHz offset and -5MHz offset and modulated as in
Wb5fu-4 3GPP; using UL reference measurement channel -108 dBm
3GPP TS25.104 Section
(12.2kbps) as specified in A.2 3GPP 25.104; tested
7.4.1
by measurement of SNDR at output on CW input
signal at -90dBm; SNDR at MAX-PHY filter output
established with FFT

sensitivity; interfering signal at front-end input
Sensitivity with In-Band
-30dBm at min, 10MHz offset modulated as in
Blocking Interference
3GPP; using UL reference measurement channel
Wb5fu-5 3GPP TS25.104 Section -117 -101 dBm
(12.2kbps) as specified in A.2 3GPP 25.104;
7.5.1
tested by measurement of SNDR at output on CW
input signal at -90dBm; (test only worst case in
production); SNDR at MAX-PHY filter output
established with FFT (Note 3)
Maxim Integrated 10
MAX2550
Band V Uplink WCDMA Rx Mode on RXIN3 (Full Duplex) (continued)

Front-end assumed response as above; Tx on at
-27dBm; LNA gain high; PGA gain register set
to 6; assumed SNDR > -17.5dB at sensitivity;
interfering signal at Front-end input -15dBm CW;
Sensitivity with
1MHz to 804MHz and 869MHz to 12750MHz with
Out-of-Band Blocking
1 MHz steps; no exceptions allowed; (test only
Wb5fu-6 Interference -111 dBm
worst case in production); using UL reference
measurement channel (12.2kbps) as specified
7.5.1
in A.2 3GPP 25.104; tested by measurement of
SNDR at output on CW input signal at -90dBm;
SNDR at MAX-PHY filter output established with
FFT
Sensitivity with
-38dBm, at 10MHz offset (CW) and 20MHz offset
Intermodulation
(modulated) as in 3GPP; using UL
reference measurement channel (12.2kbps) as
specified in A.2 3GPP 25.104; tested by
7.6.1
Spurious Emissions 1GHz to 12.75GHz, measured in 1MHz BW, with
Out-of-Band the exception of frequencies between 12.5MHz
Wb5fu-8 dBm
3GPP TS25.104 below the first carrier frequency and 12.5MHz -86 -50
Section 7.7.1 above the last carrier frequency used by the BS
(Note 3)
LNA high gain; PGA gain register set to 6; tested
Conversion Gain
Wb5fu-10 subtracting the FE input signal in dBm from the 22 29.5 35 dB
High LNA Gain
ADC output signal in dBFS at digital filter outputs,
includes digital gain to the 16-bit output
LNA mid gain; PGA gain register set to 9; tested
Conversion Gain
Wb5fu-11 subtracting the FE input signal in dBm from the 22 29 35 dB
Mid LNA Gain
Maxim Integrated 11
MAX2550
Band V Uplink WCDMA Rx Mode on RXIN3 (Full Duplex) (continued)

Conversion Gain
Wb5fu-12 subtracting the FE input signal in dBm from the -17.5 -10.5 -6 dB
Low LNA Gain

Downlink
BAND (MHz) 1 to 804 824 to 849 914 to 3000 3000 to 6000
869 to 894
ATTENUATION (dB)
3 37 51 35 20
Band V Downlink WCDMA Rx Mode on RXIN4 (Monitor)

Sensitivity reference measurement channel (12.2kbps) as
Wb5fd-1 3GPP TS25.101 specified in C.3.1 3GPP 25.101, tested by -111.5 -104.7 dBm
Section 7.3.1 measurement of SNDR at output on CW input
signal at -90dBm, SNDR at MAX-PHY filter output
established with FFT, LNA linearity set to high
Wb5fd-4 3GPP; using UL reference measurement channel -111 -101 dBm
3GPP TS25.101
Section 7.5.1
tested by measurement of SNDR at output on
Spurious Emissions
30MHz to 1000MHz, 100kHz bandwidth -100 -60
Out-of-Band
Wb5fd-9 dBm
3GPP TS25.101
1000MHz to 12750MHz, 1MHz bandwidth -98 -50
Section 7.9.1 (Note 3)
Maxim Integrated 12
MAX2550
Band V Downlink WCDMA Rx Mode on RXIN4 (Monitor) (continued)

Spurious Emissions
in Receive Bands Front-end assumed response as above, 824MHz
Wb5fd-10 -95 -80 dBm
3GPP TS25.101 to 849MHz and 869MHz to 894MHz (Note 3)
Section 7.9.2

Conversion Gain
Wb5fd-11 by subtracting the FE input signal in dBm from 40 45 48.5 dB
High LNA Gain

Conversion Gain
Wb5fd-12 subtracting the FE input signal in dBm from the -18 -14 -10 dB
Low LNA Gain
outputs, includes digital gain to the16-bit output
Band VIII Duplexer Specifications

Uplink
BAND (MHz) 1 to 870 925 to 960 960 to 2500 2500 to 3000 3000 to 6000
880 to 915
ATTENUATION (dB)
2 32 43 32 22 15
BAND (MHz) Out-of-band
Required minimum attenuation relative to in-band
ATTENUATION (dB)
25
Maxim Integrated 13
MAX2550
Band VIII Uplink WCDMA Rx Mode on RXIN3 (Full Duplex)

WCDMA FDD Band V uplink (lowest to highest
Sensitivity
Wb8fu-1 3GPP TS25.104 -116 -107 dBm
Section 7.2.1
linearity set to high (Note 3)
Wb8fu-2 -120 -107 dBm
PIN = -20dBm, LNA gain low, PGA gain register
set to 1
Tx on at -27dBm; LNA gain high; PGA gain register

set to 3; assumed SNDR > -17.5dB at sensitivity;
interfering signals at front-end input -28dBm, at
5MHz offset and -5MHz offset and modulated as in
Wb8fu-4 3GPP; using UL reference measurement channel -107 -101 dBm
(12.2kbps) as specified in A.2 3GPP 25.104; tested
7.4.1
by measurement of SNDR at output on CW input

Sensitivity with In-Band
-30dBm at min, 10MHz offset modulated as in
Blocking Interference
3GPP; using UL reference measurement channel
Wb8fu-5 3GPP TS25.104 Section -118 -101 dBm
7.5.1
input signal at -90dBm; (test only worst case in
production); SNDR at MAX-PHY filter output
Maxim Integrated 14
MAX2550
Band VIII Uplink WCDMA Rx Mode on RXIN3 (Full Duplex) (continued)

Front-end assumed response as above; Tx on at
-27dBm; LNA gain high; PGA gain register set to
6; assumed SNDR > -17.5dB at
Sensitivity with
-15dBm CW; 1MHz to 804MHz and 869MHz
Out-of-Band Blocking
to 12750MHz with 1 MHz steps; no exceptions
allowed; (test only worst case in production);
using UL reference measurement channel
7.5.1
input signal at -90dBm; SNDR at MAX-PHY filter
output established with FFT (Note 3)
Sensitivity with
-38dBm, at 10MHz offset (CW) and 20MHz offset
Intermodulation
(modulated) as in 3GPP; using UL
specified in A.2 3GPP 25.104; tested by
7.6.1
Spurious Emissions 1GHz to 12.75GHz, measured in 1MHz BW, with
Out-of-Band the exception of frequencies between 12.5MHz
Wb8fu-8 dBm
3GPP TS25.104 below the first carrier frequency and 12.5MHz -78 -50
Section 7.7.1 above the last carrier frequency used by the BS
(Note 3)
LNA high gain; PGA gain register set to 6; tested
Conversion Gain
Wb8fu-10 subtracting the FE input signal in dBm from the 23 30 35 dB
High LNA Gain
LNA mid gain; PGA gain register set to 9; tested
Conversion Gain
Wb8fu-11 subtracting the FE input signal in dBm from the 22 29.5 35 dB
Mid LNA Gain
Maxim Integrated 15
MAX2550
Band VIII Uplink WCDMA Rx Mode on RXIN3 (Full Duplex) (continued)

Conversion Gain
Wb8fu-12 subtracting the FE input signal in dBm from the -16 -9 -5 dB
Low LNA Gain

Downlink
BAND (MHz) 1 to 804 880 to 915 914 to 3000 3000 to 6000
925 to 960
ATTENUATION (dB)
3 37 51 35 20
Band VIII Downlink WCDMA Rx Mode on RXIN4 (Monitor)


Sensitivity specified in C.3.1 3GPP 25.101, tested by
Wb8fd-1 3GPP TS25.101 measurement of SNDR at output on CW input -111.5 -104.7 dBm
Section 7.3.1 signal at -90dBm, SNDR at MAX-PHY filter output
established with FFT, LNA linearity set to high,
specified data is for a manual built fcLGA using
2.7pF filter caps

Wb8fd-4 3GPP; using UL reference measurement channel -111 -101 dBm
3GPP TS25.101
Section 7.5.1
tested by measurement of SNDR at output on
Maxim Integrated 16
MAX2550
Band VIII Downlink WCDMA Rx Mode on RXIN4 (Monitor) (continued)

Spurious Emissions
30MHz to 1000MHz, 100kHz bandwidth -100 -60
Out-of-Band
Wb8fd-9 dBm
3GPP TS25.101
1000MHz to 12750MHz, 1MHz bandwidth -90 -50
Section 7.9.1 (Note 3)
Spurious Emissions
in Receive Bands Front-end assumed response as above, 925MHz
Wb8fd-10 -100 -80 dBm
3GPP TS25.101 to 960MHz and 880MHz to 915MHz (Note 3)
Section 7.9.2

Conversion Gain
Wb8fd-11 by subtracting the FE input signal in dBm from 40 44.5 49 dB
High LNA Gain

Conversion Gain
Wb8fd-12 subtracting the FE input signal in dBm from the -17.5 -12 -8.5 dB
Low LNA Gain
outputs, includes digital gain to the16-bit output
Maxim Integrated 17
MAX2550
Tx MODE AC ELECTRICAL CHARACTERISTICS
(MAX2550 EV kit, TA = -40NC to +85NC, WCDMA downlink TM1 16 channels with -14dBFs peak level into sigma-delta modulator inside
baseband chip (see the Baseband Input Level section), registers set as described in Tables 20–51, VCC_ = 3.0V to 3.6V, fREFIN =
19.2MHz, typical values are at TA = +25NC, VCC_ = 3.3V, and mid-band, unless otherwise noted. Tx specifications are referred to the
input pin of the chip.) (Note 2)

Center of the WCDMA signal, Band I output
W1 2112.4 2167.6 MHz
(TXOUTH)
RF Frequency Range
W1a Band V and VIII output Band V 867.4 891.6
MHz
W1b (TXOUTL) Band VIII 927.4 957.6
W2 Linear Output Power TX_GAIN = 1023 0 dBm
Adjacent Channel Power Offset frequency = Q5MHz in 3.84MHz BW,
W3 -55 dBc
Ratio POUT = 0dBm
Alternate Channel Power Offset frequency = Q10MHz in 3.84MHz BW,
W4 -70 dBc
Ratio POUT = 0dBm
Noise measured at -80MHz offset in 3.84MHz
W5 -149 -142 dBm/Hz
BW, then convert to per Hz, Band I output
Rx Band Noise Power,
POUT ≤ 0dBm (Note 3) Noise measured at -45MHz offset in 3.84MHz
W5a BW, then convert to per Hz, Band V and VIII -145 -140 dBm/Hz
output
W6 EVM POUT = 0dBm 4 %
W6a RCDE TM6, 8 channels at 0dBm -28 dB
W7 Minimum Output Power TX_GAIN = 0 -61 -45 dBm
Output Power Deviation
TX_GAIN = 1023, high band -1.5 +0.4 +2
W8 from TA = +25NC to -40NC dB
(Note 3) Low band -0.5 +1.5 +3.5
Output Power Deviation
TX_GAIN = 1023, high band -3 -0.8 0
W9 from TA = +25NC to +85NC dB
(Note 3) Low band -3.5 -1.6 0
Five calibration points over the power control
range to create four linear regions, any linearly
Power Control Step Size
W10 interpolated 1dB TX_GAIN step over the ±0.25 dB
Accuracy
specified power range (W2 and W7) produces
1dB output power step within this error range.
Five calibration points over the power control

range to create four linear regions, any linearly
Power Control Step Size
W11 interpolated 10dB TX_GAIN step over the ±0.75 dB
Accuracy
specified power range (W2 and W7) produces
10dB output power step within this error range.
Maxim Integrated 18
MAX2550
AC ELECTRICAL CHARACTERISTICS: General
tivity levels and blocker levels are antenna referred, typical values are at TA = +25NC, VCC_ = 3.3V, unless otherwise noted.) (Note 2)

REFERENCE FREQUENCY INPUT
R1 Input Level Test condition 125 600 mVP-P
Reference divider set to divide-by-2 for
R2 Input Frequency 13 19.2 40 MHz
frequencies higher than 26MHz
REFERENCE FREQUENCY OUTPUT
RO1a REFOUT Output Level, AC 500I || 22pF load, REFOUT_LV_CMOS_SEL = 1 110 320 500 mVP-P
RO1b REFOUT Output Level, DC 0.8 V
RO2 REFOUT Output Amplitude 500I || 22pF load, REFOUT_LV_CMOS_SEL = 0 2.25 2.7 VP-P
REFOUT Output
RO4 Matches REFIN frequency (FREF) 13 19.2 40 MHz
Frequency
Rx DIGITAL LOW-VOLTAGE DIFFERENTIAL SIGNALING OUTPUT INTERFACE
Output Bit Rate on Each I
LV0 Test condition 153.6 Mbps
and Q
LV1 Output Common Mode 1.2 V
Output Differential Swing
LV3 120I differential output load (Note 3) 100 140 220 mVPEAK
on Load (Note 3)
Differential Output
LV4 670 I
Resistance
Tx BASEBAND INTERFACE
Input Bit Rate, on Each I
Bb1 Test condition 153.6 Mbps
and Q
Common Mode Input
Bb8 1.25 V
Voltage
Bb9 Differential Input Swing 112 140 500 mVP-P
Bb10 Differential Input Bit TXINDACZI = 1 55 100 140
I
Bb11 Resistance (Note 3) Bit TXINDACZI = 0 140 220 340
Rx RF PLL
Valid RF Main Division
RS1 62 147
Ratio Range
Valid Main Fractional
RS3 Divider Programming 20-bit resolution 00000 FFFFF hex
Value
Charge-Pump Current
RS5 Using 800FA setting 0.5 0.82 1.0 mA
Gain
RS6a RXVCO, high band 38 127 216
VCO Tuning Gain MHz/V
RS6b RXVCO, low band 21 65 111
RS9 PLL Settling Time 50kHz loop bandwidth 200 Fs
Maxim Integrated 19
MAX2550
AC ELECTRICAL CHARACTERISTICS: General (continued)
tivity levels and blocker levels are antenna referred, typical values are at TA = +25NC, VCC_ = 3.3V, unless otherwise noted.) (Note 2)

Tx RF PLL
Valid RF Main Division
TS2 66 153
Ratio Range
Valid Reference Division
TS3 Division ratios are 1 or 2 1 2
Ratios
Valid Main Fractional
TS4 Divider Programming 20-bit resolution 00000 FFFFF hex
Value
TS5 Charge-Pump Current CP 800FA 0.5 0.82 1.0 mA
TS9 PLL Settling Time 50kHz loop bandwidth 200 Fs
DAC1 Resolution Monotonicity is production tested 12 Bits
AFC DAC
DAC3 Output-Voltage High Load > 200kI to GND, AFCDAC = all 1 2.55 2.68 V
DAC4 Output-Voltage Low Load > 200kI to VCC_, AFCDAC = all 0 0.37 0.45 V
Any code within 0.5V to 2.5V output level, 100Hz

DAC5 Output Noise 6 FV/rtHz
to 20kHz
DAC6 Settling Time Step from 0.6V to 2V, settling to Q10mV Fs
DIGITAL TEMPERATURE SENSOR
T1 TA = -40NC 5
Output Code vs.
T2 TA = +25NC 17
Temperature N/code
T3 TA = +85NC 27
T5 Code Slope TA = -20NC to +70NC 5
ISOLATION
Between any RXIN_ pins, with one of the two
M1 RXIN_ Pin-to-Pin Isolation 30 dB
ports disabled
M2 TXOUT_ to RXIN_ Isolation Between any TXOUT and RXIN_, with both ports on 60 dB
Note 2: Production tested at TA = +25NC. Cold and hot are guaranteed by design and characterization.
Note 3: Guaranteed by design and characterization.
Maxim Integrated 20
MAX2550
General Comments Additional Information
The specifications in the following pages calculate sensi-
MAX-PHY tivity with a specified front-end loss from a measured sig-
MAX-PHY is Maxim’s solution for the digital interface nal-to-noise and distortion ratio (SNDR) and an assumed
system between the radio IC and the baseband/DSP. It is minimum output SNDRSENS needed for demodulation at
a multimode, software programmable, digital signal post- sensitivity. The sensitivity values can be related to noise
processing engine that processes the data out of the figure by the formula:
radio IC and produces the digital filtered outputs for use Noise Figure of MAX2550 (dB) = Sensitivity (dBm) -
in the DSP. It enables multimode operation of the radio Front-End Loss (dB) - SNDRSENS (dB) + 174dBm/Hz -
through software control. Maxim offers an evaluation kit 10 x LOG(bandwidth in Hz)
for the MAX2550 along with an FPGA-based MAX-PHY Low-noise amplifier (LNA) and programmable-gain
evaluation platform. The FPGA includes the recommend- amplifier (PGA) gain are set according to the Conditions
ed digital channel-selection filters. The Verilog code for column in the Electrical Characteristics table. The output
these filters is also available for integration into the DSP. SNDR is measured using MAX-PHY and the bandwidth of
Contact Maxim for further information. the measurement is defined by the digital filters in MAX-
PHY. DC at the output is excluded from the SNDR meas-
urement. SNDR is calculated using an FFT of the output
bytes with a typical FFT length of 214 output samples.
Typical Operating Characteristics

(MAX2550 EV kit and MAX-PHY FPGA evaluation platform, TA = +25NC, unless otherwise noted. Registers set as described in
Tables 20 and 21, VCC_ = 3.3V, fREFIN = 19.2MHz, all sensitivity levels and blocker levels are antenna referred.)
SLEEP MODE SUPPLY CURRENT AFC-ONLY MODE SUPPLY CURRENT REFERENCE BUFFER MODE
vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE
17 0.190 5.8
MAX2550 toc01
MAX2550 toc02
MAX2550 toc03
16 0.185 5.6
TA = +25°C TA = +85°C
15
TA = -40°C 0.180 TA = +25°C 5.4
TA = -40°C
14
ICC (mA)
ICC (mA)
ICC (µA)
TA = +85°C
0.175 5.2
13
TA = +85°C TA = +25°C
0.170 TA = -40°C 5.0
12
11 0.165 4.8
10 0.160 4.6
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6
VCC (V) VCC (V) VCC (V)
Maxim Integrated 21
MAX2550
Typical Operating Characteristics (continued)
FULL DUPLEX MODE, BAND1 RX1 ONLY MODE, BAND 1 RX1 IDLE MODE, BAND1
SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE
0.305 95 49
MAX2550 toc05
MAX2550 toc06
MAX2550 toc04
94 TA = +85°C
48
TA = +85°C
0.300 93 47
92
46
0.295
91 TA = +85°C
45
ICC (mA)
ICC (mA)
ICC (mA)
90
0.290 44
TA = +25°C 89
43 TA = +25°C
88 TA = +25°C
0.285 TA = -40°C
87 42
86 41
0.280 TA = -40°C
85 TA = -40°C 40
0.275 84 39
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6
FULL-DUPLEX MODE, BAND5 RX3 ONLY MODE, BAND 5 RX3 IDLE MODE, BAND5
0.295 83 40
MAX2550 toc08
MAX2550 toc09
MAX2550 toc07
TA = +25°C TA = +85°C
82 35
0.290
30 TA = +85°C
TA = +85°C 81
TA = +25°C TA = +25°C
25 TA = -40°C
0.285 80
ICC (mA)
ICC (mA)
ICC (A)
20
79
0.280 TA = -40°C TA = -40°C 15
78
10
0.275
77 5
0.270 76 0
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Maxim Integrated 22
MAX2550
FULL-DUPLEX MODE, BAND8 RX3 ONLY MODE, BAND8 RX3 IDLE MODE, BAND8
0.320 94 49
MAX2550 toc11
MAX2550 toc12
MAX2550 toc10
TA = +25°C 93 48 TA = +25°C
TA = +85°C
0.315
92 47
91 TA = +25°C 46 TA = +85°C
0.310
TA = +85°C 90 45
ICC (mA)
ICC (mA)
ICC (A)
0.305 89 44
88 TA = -40°C 43 TA = -40°C
0.300 TA = -40°C
87 42
86 41
0.295
85 40
0.290 84 39
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6
RX4 MONITOR MODE, BAND5 RX4 MONITOR MODE, BAND8 RX5 MONITOR MODE, BAND1
74 84 77
MAX2550 toc13
MAX2550 toc15
MAX2550 toc14
TA = +85°C TA = +85°C
73 TA = +85°C 76
82
72 75
TA = +25°C TA = +25°C
71 74 TA = +25°C
80
70 73
ICC (mA)
ICC (mA)
ICC (mA)
69 78 72
68 TA = -40°C TA = -40°C 71 TA = -40°C
76
67 70
66 69
74
65 68
64 72 67
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Maxim Integrated 23
MAX2550
RX2 MONITOR MODE, DCS RX4 MONITOR MODE, GSM BAND1 UPLINK Rx
SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE SENSITIVITY vs. FREQUENCY
88 84 -116
MAX2550 toc16
MAX2550 toc17
MAX2550 toc18
TA = +85°C
86 82 -117
84 TA = +25°C TA = +85°C -118
SENSITIVITY (dBm)
TA = +25°C 80
82
ICC (mA)
ICC (mA)
-119
78
80 TA = -40°C -120
TA = -40°C
76
78 -121
76 74 -122
TA = -40°C TA = +25°C TA = +85°C
74 72 -123
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 1910 1920 1930 1940 1950 1960 1970 1980 1990
VCC (V) VCC (V) FREQUENCY (MHz)
BAND5 UPLINK Rx BAND8 UPLINK Rx BAND5 DOWNLINK Rx

SENSITIVITY vs. FREQUENCY SENSITIVITY vs. FREQUENCY SENSITIVITY vs. FREQUENCY
-117 -116.5 -110.5
MAX2550 toc19
MAX2550 toc21
MAX2550 toc20
TA = -40°C
-117.0
-118 TA = +25°C
-117.5 TA = +85°C -111.0
-119 -118.0
SENSITIVITY (dBm)
SENSITIVITY (dBm)
SENSITIVITY (dBm)
-118.5 -111.5
-120
-119.0
-121
-119.5 -112.0
-122 -120.0
-120.5 -112.5
-123
-121.0
TA = -40°C TA = +25°C TA = +85°C TA = -40°C TA = +25°C TA = +85°C
-124 -121.5 -113.0
820 825 830 835 840 845 850 875 880 885 890 895 900 905 910 915 920 865 870 875 880 885 890 895
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
Maxim Integrated 24
MAX2550
BAND1 DOWNLINK Rx DCS Rx

BAND8 DOWNLINK Rx SENSITIVITY
SENSITIVITY vs. FREQUENCY SENSITIVITY vs. FREQUENCY
-109.5
MAX2550 toc22
-109.0 -106.5
MAX2550 toc23
MAX2550 toc24
TA = -40°C
-109.5 TA = +25°C -107.0
-110.0
TA = +85°C
-107.5
-110.0
SENSITIVITY (dBm)
SENSITIVITY (dBm)
SENSITIVITY (dBm)
-110.5 -108.0
-110.5
-108.5
-111.0 -111.0
-109.0
-111.5
-111.5 -109.5
-112.0 -110.0
TA = -40°C TA = +25°C TA = +85°C
-112.0 TA = -40°C TA = +25°C TA = +85°C
920 925 930 935 940 945 950 955 960 965 -112.5 -110.5
2100 2110 2120 2130 2140 2150 2160 2170 2180 1800 1820 1840 1860 1880 1900
FREQUENCY (MHz)
FREQUENCY (MHz) FREQUENCY (MHz)
GSM Rx Rx BAND1 Rx BAND5

SENSITIVITY vs. FREQUENCY EVM vs. FREQUENCY EVM vs. FREQUENCY
-108.0 10 10
MAX2550 toc26
MAX2550 toc27
MAX2550 toc25
TA = +85°C
9
TA = +25°C
-108.5 8 TA = +85°C 8
7
SENSITIVITY (dBm)
-109.0 TA = +25°C
6 6 TA = +85°C
TA = +25°C
EVM (%)
EVM (%)
-109.5 TA = -40°C 5
4 4
-110.0
3
2 2 TA = -40°C
-110.5
1
TA = -40°C
-111.0 0 0
920 925 930 935 940 945 950 955 960 965 2100 2110 2120 2130 2140 2150 2160 2170 2180 820 825 830 835 840 845 850
Maxim Integrated 25
MAX2550
Rx BAND8
EVM vs. FREQUENCY RX1 GAIN vs. FREQUENCY RX1 GAIN vs. FREQUENCY
10 32.0 31.0
MAX2550 toc29
MAX2550 toc30
MAX2550 toc28
TA = +85°C LNA GAIN = HIGH TA = +85°C

9 30.8
31.8 PGA = 6
8 TA = +85°C 30.6
TA = +25°C TA = -40°C TA = +25°C
31.6 30.4
7
6 30.2
GAIN (dB)
GAIN (dB)
31.4
EVM (%)
5 30.0
31.2
4 TA = -40°C 29.8
TA = -40°C
3 31.0 29.6
2 29.4
30.8 TA = +25°C LNA GAIN = MID
1 29.2
PGA = 9
0 30.6 29.0
875 880 885 890 895 900 905 910 915 920 1910 1920 1930 1940 1950 1960 1970 1980 1990 1910 1920 1930 1940 1950 1960 1970 1980 1990
RX1 GAIN vs. FREQUENCY RX2 GAIN vs. FREQUENCY RX3 BAND 5 GAIN vs. FREQUENCY
-6.5 48.4 33.0
MAX2550 toc32
MAX2550 toc31
MAX2550 toc33
LNA GAIN = LOW LNA GAIN = HIGH TA = -40°C
PGA = 1 48.3 TA = +85°C PGA = 11
-6.6 TA = +85°C 32.8 TA = +25°C
48.2
TA = +25°C
-6.7 32.6 TA = +85°C
48.1
TA = -40°C
GAIN (dB)
GAIN (dB)
GAIN (dB)
TA = +25°C
-6.8 48.0 32.4
47.9
-6.9 32.2
47.8
-7.0 32.0
47.7 LNA = HIGH
TA = -40°C PGA = 6
-7.1 47.6 31.8
1910 1920 1930 1940 1950 1960 1970 1980 1990 1800 1810 1820 1830 1840 1850 1860 1870 1880 1890 820 825 830 835 840 845 850
Maxim Integrated 26
MAX2550
RX3 BAND5 GAIN vs. FREQUENCY RX3 BAND5 GAIN vs. FREQUENCY RX3 BAND8 GAIN vs. FREQUENCY
30.8 -7.0 30.9
MAX2550 toc36
MAX2550 toc34
MAX2550 toc35
TA = -40°C LNA GAIN = LOW LNA GAIN = HIGH
-7.2 PGA = 1 TA = -40°C PGA = 6
30.6 TA = +25°C 30.8
-7.4
30.4 -7.6 30.7
TA = +85°C
-7.8
GAIN (dB)
GAIN (dB)
GAIN (dB)
30.2 30.6 TA = +25°C

-8.0 TA = +25°C
30.0 30.5
-8.2
29.8 -8.4 30.4

TA = +85°C
-8.6
29.6 LNA GAIN = MID TA = +85°C 30.3
-8.8 TA = -40°C
PGA = 9
29.4 -9.0 30.2
820 825 830 835 840 845 850 820 825 830 835 840 845 850 875 880 885 890 900 905 910 915 920
RX3 BAND8 GAIN vs. FREQUENCY RX3 BAND8 GAIN vs. FREQUENCY RX4 BAND5 GAIN vs. FREQUENCY
29.8 -6.6 45.2
MAX2550 toc39
MAX2550 toc37
MAX2550 toc38
LNA GAIN = MID LNA = HIGH, PGA = 11

29.7 PGA = 9 45.1
-6.8
TA = -40°C 45.0
29.6 TA = -40°C
-7.0
TA = +85°C 44.9
29.5
GAIN (dB)
GAIN (dB)
GAIN (dB)
-7.2 44.8
29.4 TA = +25°C
TA = +25°C 44.7
-7.4 TA = +25°C
29.3
44.6
-7.6
29.2 44.5
-7.8 LNA GAIN = LOW
29.1 44.4 TA = +85°C
TA = -40°C PGA = 1
TA = +85°C
29.0 -8.0 44.3
875 880 885 890 900 905 910 915 920 875 880 885 890 900 905 910 915 920 865 870 875 880 885 890 895
Maxim Integrated 27
MAX2550
RX4 BAND 5 GAIN vs. FREQUENCY RX4 BAND8 GAIN vs. FREQUENCY RX4 BAND8 GAIN vs. FREQUENCY
-13.3 44.8 -11.8
MAX2550 toc40
MAX2550 toc41
MAX2550 toc42
LNA = LOW LNA GAIN = HIGH, LNA GAIN = LOW TA = +25°C
-13.4 PGA = 0 PGA = 11 -11.9 TA = +85°C
44.7 PGA = 0
-13.5 TA = +25°C
-12.0
-13.6 44.6
-13.7 TA = +85°C -12.1

GAIN (dB)
GAIN (dB)
GAIN (dB)
44.5 TA = -40°C
TA = -40°C
-13.8 -12.2
44.4
-13.9 TA = +25°C -12.3
-14.0 TA = -40°C
44.3
-12.4
-14.1
44.2 -12.5
-14.2 TA = +85°C
-14.3 44.1 -12.6
865 870 875 880 885 890 895 920 925 930 935 940 945 950 955 960 920 925 930 935 940 945 950 955 960 965
RX5 GAIN vs. FREQUENCY RX5 GAIN vs. FREQUENCY RXIN1 PIN S-PARAMETER
45.3 -11.2 0.1
MAX2550 toc43
MAX2550 toc44
MAX2550 toc45
LNA = LOW
45.2
-11.4 PGA = 0
0
45.1 TA = -40°C
-11.6 REAL
45.0
-0.1
S-PARAMETER
44.9 TA = -40°C
GAIN (dB)
GAIN (dB)
-11.8
44.8 -0.2
-12.0
44.7
TA = +85°C -0.3
44.6 TA = +25°C -12.2 IMAGINARY
44.5 TA = +85°C
-12.4 -0.4
LNA = HIGH
44.4 TA = +25°C
PGA = 11
44.3 -12.6 -0.5
2100 2110 2120 2130 2140 2150 2160 2170 2180 2100 2110 2120 2130 2140 2150 2160 2170 2180 1860 1900 1940 1980 2020
FREQUENCY (MHz) FREQUENCY (MHz) 1880 1920 1960 2000 2040
FREQUENCY (MHz)
Maxim Integrated 28
MAX2550
RXIN2 PIN S-PARAMETER RXIN3 PIN S-PARAMETER RXIN4 PIN S-PARAMETER

0 0.10 0.2
MAX2550 toc47
MAX2550 toc48
MAX2550 toc46
0.05 0.1
-0.1
0 0
REAL REAL REAL
-0.2 -0.05 -0.1
S-PARAMETER
S-PARAMETER
S-PARAMETER
-0.10 -0.2
-0.3
-0.15 -0.3
-0.4 -0.20 IMAGINARY -0.4

IMAGINARY IMAGINARY
-0.25 -0.5
-0.5
-0.30 -0.6
-0.6 -0.35 -0.7

1740 1780 1820 1860 1900 1940 850 860 870 880 890 900 910 920 930 940 900 910 920 930 940 950 960 970 980 990
1760 1800 1840 1880 1920 FREQUENCY (MHz) FREQUENCY (MHz)
FREQUENCY (MHz)
WCDMA FILTER RESPONSE

RXIN5 PIN S-PARAMETER Rx GAIN vs. PGA GAIN CODE vs. OFFSET FREQUENCY
0 0 0
MAX2550 toc51
MAX2550 toc50
MAX2550 toc49
-5
-0.1 -5
-10
GAIN FROM MAX GAIN (dB)
-0.2 -15 -10

ATTENUATION (dB)
S-PARAMETER
-20
-0.3 -15
REAL -25
-0.4 -30 -20
IMAGINARY
-0.5 -35 -25
-40
-0.6 RXBB-I -30
-45
RXBB-Q
-0.7 -50 -35
2060 2100 2140 2180 2220 0 2 4 6 8 10 12 14 0.1 1 10 100
2080 2120 2160 2200 PGA GAIN CODE OFFSET FREQUENCY (MHz)
FREQUENCY (MHz)
Maxim Integrated 29
MAX2550
GSM FILTER RESPONSE Tx ONLY MODEBAND1 Tx ONLY MODE BAND5

vs. OFFSET FREQUENCY SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE
0 0.224 0.235
MAX2550 toc54
MAX2550 toc53
MAX2550 toc52
0.222 TA = +85°C
-10
0.220 0.230 TA = +25°C
-20
0.218
ATTENUATION (dB)
-30 0.216 0.225
ICC (A)
ICC (A)
-40 0.214
TA = +85°C
0.212 TA = +25°C 0.220
-50
TA = -40°C
0.210
-60 TA = -40°C
0.208 0.215
-70 0.206
-80 0.204 0.210

10 100 1k 10k 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6
OFFSET FREQUENCY (kHz) VCC (V) VCC (V)
Tx ONLY MODE BAND8 Tx IDLE MODE BAND1 Tx IDLE MODE BAND5

0.245 0.045 0.045
MAX2550 toc55
MAX2550 toc56
MAX2550 toc57
TA = +85°C TA = +85°C
0.040 0.040
TA = +25°C
0.240 0.035 0.035
0.030 TA = +25°C 0.030
0.235 TA = +25°C
0.025 TA = -40°C 0.025
ICC (A)
ICC (A)
ICC (A)
TA = -40°C
TA = +85°C
0.020 0.020
0.230
TA = -40°C 0.015 0.015
0.225 0.010 0.010
0.005 0.005
0.220 0 0
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Maxim Integrated 30
MAX2550
Tx IDLE MODE BAND8 Tx BAND1 MAXIMUM OUTPUT Tx BAND5 MAXIMUM OUTPUT

SUPPLY CURRENT vs. SUPPLY VOLTAGE POWER vs. FREQUENCY POWER vs. FREQUENCY
0.06 5.0 6
MAX2550 toc58
MAX2550 toc60
MAX2550 toc59
TA = +85°C 4.5
0.05 5
4.0
TA = -40°C
3.5 TA = +25°C
0.04 4
TA = +25°C 3.0 TA = -40°C
PO (dBm)
PO (dBm)
ICC (A)
0.03 TA = -40°C 2.5 3

TA = +85°C
2.0
0.02 2 TA = +25°C
1.5
TA = +85°C
1.0
0.01 1
0.5
0 0 0
3.0 3.1 3.2 3.3 3.4 3.5 3.6 2100 2110 2120 2130 2140 2150 2160 2170 2180 855 860 865 870 875 880 885 890 895 900
VCC (V) FREQUENCY (MHz) FREQUENCY (MHz)
Tx BAND8 MAXIMUM OUTPUT Tx OUTPUT POWER LOW BAND Tx OUTPUT POWER AND
POWER vs. FREQUENCY vs. GAIN SETTINGS, HIGH BAND OUTPUT POWER ERROR vs. GAIN SETTINGS
MAX2550 toc62 MAX2550 toc63
8 10 4 10 4
MAX2550 toc61
TA = +25°C TA = +25°C
7 0 PO ERROR 3 0 PO ERROR 3
TA = +85°C TA = +85°C
6 -10 TA = -40°C 2 -10 TA = -40°C 2
TA = -40°C
TA = +85°C
PO ERROR (dB)
PO ERROR (dB)
5 -20 1 -20 TA = +85°C 1
PO (dBm)
PO (dBm)
PO (dBm)
4 -30 0 -30 0
TA = +25°C TA = +85°C
3 -40 -1 -40 -1
2 -50 PO ERROR -2 -50 -2

PO ERROR
TA = -40°C
PO ERROR PO ERROR TA = -40°C
1 -60 -3 -60 -3
TA = +25°C TA = +25°C
0 -70 -4 -70 -4
925 930 935 940 945 950 955 960 0 256 512 768 1024 0 256 512 768 1024
FREQUENCY (MHz) Tx GAIN SETTINGS Tx GAIN SETTINGS
Maxim Integrated 31
MAX2550
HIGH BAND Tx GAIN STEP LOW BAND Tx GAIN STEP

vs. GAIN SETTINGS vs. GAIN SETTINGS BAND1 Tx EVM vs. OUTPUT POWER
0.20 0.20 8
MAX2550 toc66
MAX2550 toc64
MAX2550 toc65
7
0.15 0.15
6 2110MHz, 2170MHz
0.10 0.10 TA = -40°C
GAIN STEP (dB)
GAIN STEP (dB)
Tx EVM (%)
0.05 0.05 4
3
0 0 2110MHz, 2170MHz
TA = +25°C 2 TA = +85°C
TA = -40°C TA = +25°C
-0.05 -0.05 TA = -40°C 2110MHz, 2170MHz
TA = +85°C 1
TA = +85°C TA = +25°C
-0.10 -0.10 0
0 256 512 768 1024 0 256 512 768 1024 -60 -40 -20 0 20
Tx GAIN SETTINGS Tx GAIN SETTINGS PO (dBm)
BAND5 Tx EVM vs. OUTPUT POWER BAND8 Tx EVM vs. OUTPUT POWER Tx TM6 RCDE, BAND1
8 8 -20
MAX2550 toc67
MAX2550 toc69
MAX2550 toc68
7 860MHz, 895MHz -21

7
TA = -40°C 927MHz, 957MHz -22
6 6 2110MHz, 2170MHz
TA = -40°C -23 TA = -40°C
5 860MHz, 895MHz 927MHz, 957MHz
5
Tx EVM (%)
Tx EVM (dB)
-24
Tx EVM (%)
TA = +85°C TA = +85°C
2110MHz, 2170MHz
4 4 -25
TA = +85°C
3 -26
3
-27
2 2
-28
860MHz, 895MHz 927MHz, 957MHz
1 TA = +25°C 1 2110MHz, 2170MHz
TA = +25°C -29
TA = +25°C
0 0 -30
-70 -50 -30 -10 10 -70 -50 -30 -10 10 -60 -40 -20 0 20
PO (dBm) PO (dBm) PO (dBm)
Maxim Integrated 32
MAX2550
Tx TM6 RCDE, BAND5 Tx OUTPUT SPECTRUM, HIGH BAND Tx OUTPUT SPECTRUM, LOW BAND
-20 -10 -10
MAX2550 toc70
MAX2550 toc71
MAX2550 toc72
-21 -20 2.5MHz/div -20 2.5MHz /div
-22 -30 -30

-23 -40 -40
1AVG 1AVG
POWER (dBm)
POWER (dBm)
Tx EVM (dB)
-24 -50 -50

860MHz, 894MHz 860MHz, 894MHz
-25 -60 -60
TA = -40°C TA = +85°C
-26 -70 -70
-27 -80 -80
-28 -90 -90
-29 860MHz, 894MHz -100 -100
TA = +25°C
-30 -110 -110
-60 -40 -20 0 20 2.1275 2.1400 2.1450 865.0 877.5 890.0
PO (dBm) FREQUENCY (GHz) FREQUENCY (GHz)
BAND1 ADJACENT CHANNEL POWER BAND5 ADJACENT CHANNEL POWER BAND8 ADJACENT CHANNEL POWER
RATIO AT 0dBM vs. FREQUENCY RATIO AT 0dBM vs. FREQUENCY RATIO AT 0dBM vs. FREQUENCY
-50 -50 -50
MAX2550 toc73
MAX2550 toc74
MAX2550 toc75
-52 -52 -52
-54 -54 -54
-56 -56 -56
-58 -58 -58
ACP (dBc)
ACP (dBc)
ACP (dBc)
-60 -60 -60

TA = +25°C, ACPL TA = +25°C, ACPL TA = +25°C, ACPL
-62 -62 -62
TA = +25°C, ACPR TA = +25°C, ACPR TA = +25°C, ACPR
-64 TA = -40°C, ACPL -64 TA = -40°C, ACPL -64 TA = -40°C, ACPL
-66 TA = -40°C, ACPR -66 TA = -40°C, ACPR -66 TA = -40°C, ACPR
TA = +85°C, ACPL TA = +85°C, ACPL TA = +85°C, ACPL
-68 TA = +85°C, ACPR -68 TA = +85°C, ACPR -68 TA = +85°C, ACPR
-70 -70 -70
2100 2110 2120 2130 2140 2150 2160 2170 2180 850 860 870 880 890 900 920 930 940 950 960
Maxim Integrated 33
MAX2550
BAND1 ALTERNATE CHANNEL POWER BAND5 ALTERNATE CHANNEL POWER BAND8 ALTERNATE CHANNEL POWER
RATIO AT 0dBM vs. FREQUENCY RATIO AT 0dBM vs. FREQUENCY RATIO AT 0dBM vs. FREQUENCY
-60 -60 -60
MAX2550 toc76
MAX2550 toc77
MAX2550 toc78
-65 -65 -65
-70 -70 -70
-75 -75 -75

ALT1 (dBc)
ALT1 (dBc)
ALT1 (dBc)
-80 -80 -80
TA = +25°C, ALT1I TA = +25°C, ALT1I TA = +25°C, ALT1I
-85 TA = +25°C, ALT1U -85 TA = +25°C, ALT1U -85 TA = +25°C, ALT1U
TA = -40°C, ALT1I TA = -40°C, ALT1I TA = -40°C, ALT1I
-90 -90 -90
TA = -40°C, ALT1U TA = -40°C, ALT1U TA = -40°C, ALT1U
-95 TA = +85°C, ALT1I -95 TA = +85°C, ALT1I -95 TA = +85°C, ALT1I
TA = +85°C, ALT1U TA = +85°C, ALT1U TA = +85°C, ALT1U
-100 -100 -100
2100 2110 2120 2130 2140 2150 2160 2170 2180 850 860 870 880 890 900 920 930 940 950 960
Tx OUTPUT SPECTRUM, BAND1 Tx OUTPUT SPECTRUM, BAND5 Tx OUTPUT SPECTRUM, BAND8

-10 10 -10
MAX2550 toc79
MAX2550 toc80
MAX2550 toc81
-20 D2 [T1] -37.51dB 0 -20 MARKER1 [T1] -13.54dBm
6.412660256GHz 934.294871795MHz
-30 D3 [T1] -38.13dB -10 -30 D2 [T1] -31.22dB
-40 4.289262821GHz -20 -40 2.845352564GHz
2
D4 [T1] -43.52dB 3 D3 [T1] -34.26dB
3 2 SWP 59 OF 100
POWER (dBm)
POWER (dBm)
POWER (dBm)
-50 2.123397436GHz -30 -50 1.868589744GHz

4 4
-60 -40 -60
-70 -50 -70
-80 -50 -80
-90 -70 -90
-100 -80 -100
-110 -90 -110
0 13.25 26.50 0 13.25 26.50 0 13.25 26.50
FREQUENCY (GHz) FREQUENCY (GHz) FREQUENCY (GHz)
Maxim Integrated 34
MAX2550
TXOUTH S-PARAMETER, HIGH BAND TXOUTL S-PARAMETER, LOW BAND Tx LOWPASS FILTER REJECTION
0.05 0.5 10
MAX2550 toc82
MAX2550 toc83
MAX2550 toc84
TA = +25°C
0 0.4 TA = +85°C
0
TA = -40°C
-0.05 0.3
-10
0.2 REAL
S-PARAMETER
S-PARAMETER
-0.10
GAIN (dB)
0.1 -20
-0.15 REAL
0 -30
-0.20
-0.1
-40
-0.25 -0.2
IMAGINARY
-0.30 IMAGINARY -50
-0.3
-0.35 -0.4 -60
2180 2185 2190 2195 2200 800 850 900 950 1000 0 2000 4000 6000 8000 10,000
LO FREQUENCY AND GAIN LO FREQUENCY AND GAIN

LO FREQUENCY AND GAIN vs. CHARGE-PUMP VOLTAGE vs. CHARGE-PUMP VOLTAGE
vs. CHARGE-PUMP VOLTAGE REG3[20:19] OR REG28[15:14] = 10, WITH REG3[20:19] OR REG28[15:14] = 10,
REG3[20:19] OR REG28[15:14] = 01 AND REG3[22:21] OR REG28[17:16] = 00 AND REG3[22:21] OR REG28[15:14] = 01
MAX2550 toc86
1.00
MAX2550 toc85
2.2 250 2.2
MAX2550 toc87
250
KLO,
140 KLO,
TA = +85°C FLO,
KLO, FLO, 2.1 TA = +85°C
0.95 TA = +25°C 200 2.1
TA = +25°C TA = +25°C 120 FLO, 200
FLO,
TA = +25°C
LO FREQUENCY (GHz)
FLO, TA = -40°C
LO FREQUENCY (GHz)
FLO,
LO GAIN (MHz/ V)
2.0
LO GAIN (MHz/V)
0.90 TA = -40°C FLO, 100 2.0

150 TA = -40°C
150
KLO (MHz/ V)
FLO (GHz)
TA = +85°C KLO, FLO,

KLO, 80 1.9
0.85 KLO, TA = +25°C TA = +85°C 1.9 FLO,
TA = +85°C KLO, TA = +85°C
TA = -40°C 60 100 100
TA = +25°C
0.80 1.8 1.8
KLO,
40 TA = -40°C KLO,
50 TA = -40°C 50
0.75 1.7 1.7
20
0.70 0 1.6 0 1.6 0

0 1 2 3 4 0 1 2 3 4 0 1 2 3 4
VCPOUT (V) VCPOUT (V) VCPOUT (V)
Maxim Integrated 35
MAX2550
LO FREQUENCY AND GAIN

vs. CHARGE-PUMP VOLTAGE TURN-ON FREQUENCY SETTLING,
REG3[20:19] OR REG28[15:1] = 11 LOW BAND
2.4 160
KLO,
TA = +85°C FLO,
2.3 140
TA = +25°C
FLO,
FREQUENCY (10kHz/div)
LO FREQUENCY (GHz)
TA = -40°C
LO GAIN (MHz/ V)
2.2 120
KLO, FLO,
2.1 TA = -40°C 100
TA = +85°C
2.0 KLO, 80
TA = +25°C
1.9 60
1.8 40
0 1 2 3 4 TIME (20µs/div)
VCPOUT (V)
TURN-ON FREQUENCY SETTLING, CHANNEL-SWITCH FREQUENCY SETTLING,

HIGH BAND LOW BAND
FREQUENCY (10kHz /div)
TIME (20µs/div) TIME (20µs/div)
Maxim Integrated 36
MAX2550
LO PHASE NOISE INTEGRATED PHASE NOISE

CHANNEL-SWITCH FREQUENCY SETTLING,
vs. FREQUENCY OFFSET HIGH BAND vs. TEMPERATURE, HIGH BAND
HIGH BAND
MAX2550 toc92 -60 -37.0
MAX2550 toc93
MAX2550 toc94
2110MHz
2110MHz TA = -40°C -37.5
-70 2110MHz TA = +25°C
INTEGRATED PHASE NOISE (dBc)

2110MHz TA = +85°C -38.0
-80
PHASE NOISE (dBc/Hz)
-38.5
-90
-39.0
-100 2170MHz
-39.5
-110
-40.0
-120
2170MHz TA = -40°C -40.5
2170MHz TA = +25°C
-130 -41.0
2170MHz TA = +85°C
-140 -41.5
0.1 1 10 100 1k 10k -40 -15 10 35 60 85
TIME (20µs/div)
FREQUENCY OFFSET (kHz) TEMPERATURE (°C)
LO PHASE NOISE INTEGRATED PHASE NOISE, GAIN FROM TXOUTH TO OTHER

vs. FREQUENCY OFFSET LOW BAND LOW BAND RF PORTS vs. FREQUENCY
-60 -46.0 0
MAX2550 toc97
MAX2550 toc95
MAX2550 toc96
820MHz TA = -40°C
-70 820MHz TA = +25°C -46.2 -10
820MHz
INTEGRATED PHASE NOISE (dBc)
820MHz TA = +85°C -46.4 TXOUTL

-80 960MHz TA = -40°C -20
PHASE NOISE (dBc/Hz)
960MHz TA = +25°C -46.6

-90 -30 RXIN1~5
960MHz TA = +85°C
GAIN (dB)
-46.8
-100 -40
-47.0
-110 -50
-47.2
-120 960MHz -60
-47.4
-130 -47.6 -70
-140 -47.8 -80

0.1 1 10 100 1k 10k -40 -15 10 35 60 85 0 1000 2000 3000 4000 5000 6000
FREQUENCY OFFSET (kHz) TEMPERATURE (°C) FREQUENCY (MHz)
Maxim Integrated 37
MAX2550
GAIN FROM TXOUTL TO OTHER RF PORTS GAIN FROM ALL OTHER RF PORTS GAIN FROM ALL OTHER RF PORTS
vs. FREQUENCY TO RXIN1 vs. FREQUENCY TO RXIN2 vs. FREQUENCY
0 -20 -20
MAX2550 toc98
MAX2550 toc99
MAX2550 toc100
RXIN5 RXIN2 RXIN5 RXIN1 RXIN3
RXIN3
-10
-30 RXIN4 -30 RXIN4
TXOUTH
-20
-40 -40
-30
GAIN (dB)
GAIN (dB)
GAIN (dB)
RXIN1~5
-40 -50 -50
-50
-60 -60
-60
-70 -70
-70
TXOUTL, TXOUTH TXOUTL, TXOUTH
-80 -80 -80
0 1000 2000 3000 4000 5000 6000 0 1000 2000 3000 4000 5000 6000 0 1000 2000 3000 4000 5000 6000
GAIN FROM ALL OTHER RF PORTS TO GAIN FROM ALL OTHER RF PORTS
RXIN3 vs. FREQUENCY TO RXIN4 vs. FREQUENCY
-20 -20
MAX2550 toc101
MAX2550 toc102
RXIN4 RXIN1 RXIN5 RXIN1 RXIN3 RXIN5
RXIN2 RXIN2
-30 -30
-40 -40
GAIN (dB)
GAIN (dB)
-50 -50
-60 -60
-70 -70
TXOUTL, TXOUTH TXOUTL, TXOUTH

-80 -80
0 1000 2000 3000 4000 5000 6000 0 1000 2000 3000 4000 5000 6000
FREQUENCY (MHz) FREQUENCY (MHz)
Maxim Integrated 38
MAX2550
GAIN FROM ALL OTHER RF PORTS AFCDAC OUTPUT VOLTAGE

TO RXIN5 vs. FREQUENCY AND STEP vs. AFCDAC CODE
MAX2550 toc104
-20 3.0 0.7
MAX2550 toc103
RXIN1 RXIN2 RXIN4
-30 RXIN3 2.5 0.6
0.5
-40 2.0
VAFCDAC (V)
STEP (mV)
GAIN (dB)
VSTEP 0.4
-50 1.5
0.3
-60 1.0
0.2
VOUT, TA = +85°C, +25°C, -40°C
-70 0.5 0.1
TXOUTL, TXOUTH
-80 0 0
0 1000 2000 3000 4000 5000 6000 0 1024 2048 3072 4096
FREQUENCY (MHz) AFCDAC[11:0] CODE
TEMPERATURE SENSOR TEMPERATURE SENSOR SWITCHING TEMPERATURE SENSOR CODE

TURN-ON TRANSIENT TRANSIENT FROM CODE 4095 TO 0 vs. TEMPERATURE
35
MAX2550 toc107
CH1: CSB
30
FULL-DUPLEX MODE
25
CH1: CSB
OUTPUT CODE
CH2: AFCOUT 20
CH2: AFCOUT 15
10 IDLE MODE
CH1 1V/div CH1 1V/div 5

CH2 500mV/div CH2 500mV/div
0
1µs/div 1µs/div -40 -15 10 35 60 85
TEMPERATURE (°C)
Maxim Integrated 39
MAX2550
Pin Configuration
GND_RXVCO
BYPASS_RX
VCC_RXVCO
CPOUT_RX
TOP VIEW
VCC_RXPLL
LNAOUTH
LNAOUTL
VCC_MXR
VCC_LNA
MIXINH
MIXINL
DOUT
GPO3
SCLK
42 41 40 39 38 37 36 35 34 33 32 31 30 29
REFEN 43 28 VCC_CLKPLL
RXIN2 44 27 GND_CLKVCO
GND_LNAP 45 26 VCC_CLKVCO
RXIN1 46 25 N.C.
GPO2 47 24 VCC_RXBB
RXIN3 48 23 RXOUTQ-
GND_LNAC 49 22 RXOUTQ+
MAX2550
RXIN4 50 21 RXOUTI-
GND_LNAI 51 20 RXOUTI+
RXIN5 52 19 AFC_OUT
GPO1 53 18 VCC_TXVCO
CS 54 17 GND_TXVCO
VCC_TXRF 55 EP 16 BYPASS_TX
+
VCC_PAD 56 15 REFIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14
REFOUT
TXOUTL
TXOUTH
TXINI+
TXINI-
TXINQ+
TXINQ-
VCC_TXPLL
VCC_REF
GND_TXL
GND_TXH
DIN
VCC_TXBB
CPOUT_TX
TQFN
Pin Description
PIN NAME FUNCTION
1 TXOUTL Low-Band TXRF Output. Internally matched to 50I over the band of operation.
2 GND_TXL Tx Ground. Connect directly to ground plane.
3 TXOUTH High-Band TXRF Output. Internally matched to 50I over the band of operation.
4 GND_TXH High-Band Tx Output Ground. Connect directly to ground plane.
5 DIN Data Input of the 4-Wire Serial Interface
Transmitter Noninverting In-Phase Input. Accepts baseband sigma-delta modulated digital bit
6 TXINI+
streams. Connect directly to the baseband processor.
Transmitter Inverting In-Phase Input. Accepts baseband sigma-delta modulated digital bit streams.
7 TXINI-
Connect directly to the baseband processor.
Maxim Integrated 40
MAX2550
Pin Description (continued)
PIN NAME FUNCTION
Transmitter Noninverting Quadrature Input. Accepts baseband sigma-delta modulated digital bit
8 TXINQ+
Transmitter Inverting Quadrature Input. Accepts baseband sigma-delta modulated digital bit
9 TXINQ-
Baseband Tx Path Supply. Connect to a regulated supply voltage. Bypass each supply to the PCB
10 VCC_TXBB ground plane with a capacitor placed as close as possible to the pin. Do not share ground vias
among multiple bypass capacitors.
Charge-Pump Output for Tx Synthesizer. Also used as the tuning voltage for Tx VCO. Connect to an
11 CPOUT_TX
external loop filter.
Tx Synthesizer Supply. Connect to a regulated supply voltage. Bypass each supply pin to the PCB
12 VCC_TXPLL ground plane with a capacitor placed as close as possible to the pin. Do not share ground vias
Reference Clock Buffer Output. Configurable by the REFEN pin and SPI. See the REFOUT
13 REFOUT
Functionality section for details.
Reference Buffer Supply. Connect to a regulated supply voltage. Bypass each supply pin to the
14 VCC_REF PCB ground plane with a capacitor placed as close as possible to the pin. Do not share ground
vias among multiple bypass capacitors.
15 REFIN Reference Input Pin. Connected to TCXO. Requires a DC-blocking capacitor (1nF).
16 BYPASS_TX Tx VCO Bias Bypass. Bypass to ground with a 470nF capacitor as close as possible.to the pin.
17 GND_TXVCO Tx VCO Ground. Connect to the PCB ground plane with a separate via.
Tx VCO Supply. Connect to a regulated supply voltage. Bypass each supply pin to the PCB ground
18 VCC_TXVCO plane with a capacitor placed as close as possible to the pin. Do not share ground vias among
multiple bypass capacitors.
19 AFC_OUT AFC DAC Output. The DAC is controlled by the register TXLO_AFCDAC (Table 43).
Receiver Noninverting In-Phase Output. Digital sigma-delta modulated LVDS output. Connect
20 RXOUTI+
directly to the baseband processor.
Receiver Inverting In-Phase Output. Digital sigma-delta modulated LVDS output. Connect directly to
21 RXOUTI-
the baseband processor.
Receiver Noninverting Quadrature Output. Digital sigma-delta modulated LVDS output. Connect
22 RXOUTQ+
directly to the baseband processor.
Receiver Inverting Quadrature Output. Digital sigma-delta modulated LVDS output. Connect directly
23 RXOUTQ-
to the baseband processor.
Baseband Rx Path Supply. Regulated Power-Supply Input. Connect to a regulated supply voltage.
24 VCC_RXBB Bypass each supply pin to the PCB ground plane with a capacitor placed as close as possible to
the pin. Do not share ground vias among multiple bypass capacitors.
25 N.C. No Connection. Leave unconnected.
Clock Generation VCO Supply. Connect to a regulated supply voltage. Bypass each supply pin to
26 VCC_CLKVCO the PCB ground plane with a capacitor placed as close as possible to the pin. Do not share ground
vias among multiple bypass capacitors.
Maxim Integrated 41
MAX2550
PIN NAME FUNCTION
Clock Generation Synthesizer Ground. Connect clock generation synthesizer ground to the PCB
27 GND_CLKVCO
ground plane with a separate via.
Clock Generation Synthesizer Supply. Connect to a regulated supply voltage. Bypass each supply
28 VCC_CLKPLL pin to the PCB ground plane with a capacitor placed as close as possible to the pin. Do not share
ground vias among multiple bypass capacitors.
SPI Interface Clock Input. Data is clocked in to the serial data input on the rising edge of SCLK.
29 SCLK
See Figure 4 for details.
Rx Synthesizer Supply. Connect to a regulated supply voltage. Bypass each supply pin to the PCB
30 VCC_RXPLL ground plane with a capacitor placed as close as possible to the pin. Do not share ground vias
Rx Synthesizer Charge-Pump Output. Also used as the tuning voltage for Rx VCO. Connect to an
31 CPOUT_RX
external loop filter.
32 BYPASS_RX Rx VCO Bias Bypass. Bypass to ground with a 470nF capacitor as close as possible to the pin.
33 GND_RXVCO Rx VCO Ground. Connect ground to the PCB ground plane with a separate via.
Rx VCO Supply. Connect to a regulated supply voltage. Bypass each supply pin to the PCB ground
34 VCC_RXVCO plane with a capacitor placed as close as possible to the pin. Do not share ground vias among
35 DOUT SPI Data Output
Rx Mixer Supply. Connect to a regulated supply voltage. Bypass each supply pin to the PCB
36 VCC_MXR ground plane with a capacitor placed as close as possible to the pin. Do not share ground vias
High-Band Rx Mixer Input. RF input to mixer from an external filter (optional). Internally DC-blocked
37 MIXINH
and matched to 50I.
Low-Band Rx Mixer Input. RF input to mixer from an external filter (optional). Internally DC-blocked
38 MININL
and matched to 50I.
General-Purpose Output. Controlled by register 7 (Table 20). GPO3 can also be configure as a PLL
39 GPO3
lock-detect output.
LNA Supply. Connect to a regulated supply voltage. Bypass each supply pin to the PCB ground
40 VCC_LNA plane with a capacitor placed as close as possible to the pin. Do not share ground vias among
Low-Band LNA Output. RF output from LNA 3 to external SAW filter. Internally DC-blocked and
41 LNAOUTL
matched to 50I.
High-Band LNA Output. RF Output from LNA 1 to an external SAW filter. Internally DC-blocked and
42 LNAOUTH
matched to 50I .
Configuration for REFOUT. When REFEN = 0, REFOUT can be configured for CMOS or low-voltage
43 REFEN output by the SPI interface. See the REFOUT Functionality section. When REFEN = 1, REFOUT is
configured as REFIN buffer with CMOS output.
44 RXIN2 Low-Noise Amplifier Input 2. Requires AC-coupling and external matching.
45 GND_LNAP PCS LNA Ground. Connect directly to ground plane.
47 GPO2 General-Purpose Output. Controlled by register 7<3:2>.
Maxim Integrated 42
MAX2550
PIN NAME FUNCTION
49 GND_LNAC Ground for Cellular LNA. Connect directly to the ground plane.
51 GND_LNAI IMT LNA Ground. Connect directly to the ground plane.
53 GPO1 General-Purpose Output. Controlled by register 23<25:24>.
54 CS Serial-Interface Chip Select. See Figure 4.
Tx Upconverter Supply. Connect to a regulated supply voltage. Bypass each supply pin to the PCB
55 VCC_TXRF ground plane with a capacitor placed as close as possible to the pin. Do not share ground vias
PA Driver Supply. Connect to a regulated supply voltage. Bypass each supply pin to the PCB
56 VCC_PAD ground plane with a capacitor placed as close as possible to the pin. Do not share ground vias
— EP Exposed Pad. Connect to a large ground plane to maximize thermal performance.
Detailed Description has high and low gain modes. The gain state of the LNA
in operation is programmed by the LNAGAIN bits in the
Quad RF Inputs RX_GAIN[15:14] register. Each LNA requires an external
The MAX2550 features five independent RF inputs. matching network to optimize system sensitivity. Table 3
RXIN1 and RXIN3 are used for receiving WCDMA Bands provides S11 for each LNA input over the specified band
I, V, VI, and VIII. Bands I, V, VI, and VIII WCDMA/PCS of operation, Table 4 provides S11 of RXIN1 and RXIN3
downlink can be monitored (network listen) by program- LNA output, and Table 5 provides S11 of the mixer input.
ming the part to receive through the RXIN4 and RXIN5 The receiver also features a separate dedicated receive
inputs. RXIN2 can be used to monitor Band III. This path for the 1930MHz to 1995MHz band that enables
allows the base station to monitor surrounding cells to monitoring.
select the best operating conditions (transmit power, The baseband amplifiers has 16 possible gain states with
codes, frequency, capacity, etc.) each LSB providing a gain step of 3dB. The gain state of
the baseband amplifiers is programmed by the PGAGAIN
REFOUT Functionality
bits in the RX_GAIN[11:8] register. The dynamic range of
The MAX2550 features a reference oscillator buffered
the data converters when using the recommended sam-
output that is configurable by the REFEN input and
pling rates is sufficient to allow for minimal switching of
Register 29. REFOUT can be configured as CMOS or
system gain over varying input signal power. Tables 6
as a low-voltage output. Table 2 lists all REFOUT
and 7 provide suggested LNA and PGA settings for vari-
configurations.
ous input signal power ranges. Two possible LNA/PGA
Receiver System Gain Control gain settings are provided for the uplink band. Case 1
The device features programmable-gain LNAs and pro- (Table 6) allows for 3GPP TS25.104 compliance under all
grammable variable-gain baseband amplifiers, allowing conditions while case 2 (Table 7) allows best sensitivity,
the system gain to be entirely controlled by the serial but compromises adjacent channel selectivity and inter-
interface. RX1, RX2, RX3, and RX5 have three possible modulation in high-gain LNA mode.
gain states: high gain, medium gain, and low gain. RX4
Maxim Integrated 43
MAX2550
Table 1. RF Input/Output Frequency Range
PIN FUNCTION FREQUENCY RANGE (MHz)
RXIN1 Band I WCDMA uplink Rx 1920 to 1980
RXIN2 Band III DCS monitor 1805 to 1880
Band V uplink WCDMA/GSM 824 to 849
RXIN3 Band VI WCDMA uplink 830 to 840
Band VIII uplink WCDMA 880 to 915
Band V downlink WCDMA/GSM monitor 865 to 894
RXIN4 Band VI WCDMA monitor 875 to 885
Band VIII downlink WCDMA/GSM monitor 925 to 960
RXIN5 Band I WCDMA monitor 2110 to 2170
Band V WCDMA downlink Tx 865 to 894
TXOUTL Band VI WCDMA downlink Tx 875 to 885
Band VIII WCDMA downlink Tx 925 to 960
TXOUTH Band I WCDMA downlink Tx 2110 to 2170
Table 2. REFOUT Output Configurations

INPUT OUTPUT
REFIN_ENOUT3 REFOUT_LV_CMOS_SEL
REFEN INPUT OUTPUT TYPE
(TXLO_REF<14>) (TXLO_REF<23>)
0 X Off
0 0 CMOS
1
1 Low voltage
1 X X CMOS
Table 3. Typical RXIN1 (High Gain) S11 Parameters (VCC_ = +3.3V, TA = +25°C)
FREQUENCY (MHz) S11 REAL S11 IMAGINARY FREQUENCY (MHz) S11 REAL S11 IMAGINARY
1880 34.3 -40.1 1955 36.0 -39.8
1885 34.4 -40.0 1960 36.1 -39.8
1890 34.6 -40.0 1965 36.2 -39.8
1895 34.7 -40.0 1970 36.3 -39.8
1900 34.8 -39.9 1975 36.4 -39.9
1905 34.9 -39.9 1980 36.5 -39.9
1910 35.0 -39.9 1985 36.6 -39.9
1915 35.1 -39.8 1990 36.6 -39.9
1920 35.3 -39.8 1995 36.7 -40.0
1925 35.4 -39.8 2000 36.8 -40.0
1930 35.5 -39.8 2005 36.9 -40.0
1935 35.6 -39.8 2010 36.9 -40.1
1940 35.7 -39.8 2015 37.0 -40.1
1945 35.8 -39.8 2020 37.1 -40.2
1950 35.9 -39.8
Maxim Integrated 44
MAX2550
Table 4. Typical RXIN3 (High Gain) S11 Table 5. Typical RXIN4 (High Gain) S11
Parameters (VCC_ = +3.3V, TA = +25°C) Parameters (VCC_ = +3.3V, TA = +25°C)
1765 23.4 -38.9 840 22.0 -53.8
1770 23.5 -38.8 845 22.5 -53.6
1775 23.7 -38.6 850 22.9 -53.4
1780 23.8 -38.5 855 23.3 -53.3
1785 23.9 -38.4 860 23.7 -53.2
1790 24.1 -38.3 865 24.1 -53.1
1795 24.2 -38.2 870 24.3 -53.0
1800 24.3 -38.1 875 24.6 -53.0
1805 24.4 -38.0 880 24.8 -52.9
1810 24.6 -37.9 885 24.9 -52.9
1815 24.7 -37.8 890 25.0 -52.8
1820 24.8 -37.7 895 25.1 -52.8
1825 24.9 -37.6 900 25.1 -52.7
1830 25.0 -37.5 905 25.3 -52.3
1835 25.1 -37.4 910 25.6 -52.2
1840 25.2 -37.3 915 25.9 -52.1
1845 25.3 -37.2 920 26.2 -52.0
1850 25.4 -37.1 925 26.4 -52.0
1855 25.5 -37.1 930 26.5 -51.9
1860 25.6 -37.0 935 26.6 -51.9
1865 25.7 -36.9 940 26.7 -51.8
1870 25.8 -36.8 945 26.8 -51.8
1875 25.9 -36.7 950 26.8 -51.7
1880 26.0 -36.6 955 26.8 -51.6
1885 26.1 -36.5 960 26.8 -51.5
1890 26.1 -36.4 965 26.7 -51.4
1895 26.2 -36.3 970 26.6 -51.2
1900 26.3 -36.2 975 26.5 -51.1
1905 26.4 -36.2 980 26.4 -50.9
1910 26.5 -36.1
1915 26.6 -36.0
1920 26.6 -35.9
Maxim Integrated 45
MAX2550
Table 6. Typical RXIN5 (High Gain) S11 Parameters (VCC_ = +3.3V, TA = +25°C)
2070 16.9 -33.3 2150 17.6 -30.2
2075 16.9 -33.1 2155 17.6 -30.0
2080 17.0 -32.9 2160 17.7 -29.8
2085 17.0 -32.7 2165 17.7 -29.6
2090 17.0 -32.5 2170 17.8 -29.5
2095 17.1 -32.3 2175 17.9 -29.3
2100 17.1 -32.2 2180 17.9 -29.1
2105 17.1 -32.0 2185 18.0 -28.9
2110 17.2 -31.8 2190 18.1 -28.7
2115 17.2 -31.6 2195 18.1 -28.5
2120 17.3 -31.4 2200 18.2 -28.3
2125 17.3 -31.2 2205 18.3 -28.2
2130 17.3 -31.0 2210 18.4 -28.0
2135 17.4 -30.8 2070 16.9 -33.3
2140 17.4 -30.6 2075 16.9 -33.1
2145 17.5 -30.4
Table 7. Typical LNAOUTH (High Gain) S11 Parameters (VCC_ = +3.3V, TA = +25°C)
1880 28.2 -5.7 1955 33.0 1.5
1885 28.5 -5.2 1960 33.3 2.0
1890 28.8 -4.7 1965 33.7 2.5
1895 29.1 -4.3 1970 34.1 2.9
1900 29.4 -3.8 1975 34.4 3.4
1905 29.7 -3.3 1980 34.8 3.9
1910 30.0 -2.8 1985 35.2 4.4
1915 30.3 -2.4 1990 35.6 4.9
1920 30.6 -1.9 1995 36.0 5.4
1925 31.0 -1.4 2000 36.4 5.8
1930 31.3 -0.9 2005 36.8 6.3
1935 31.6 -0.4 2010 37.2 6.8
1940 31.9 0.0 2015 37.6 7.3
1945 32.3 0.5 2020 38.0 7.8
1950 32.6 1.0
Maxim Integrated 46
MAX2550
Digital I/Q Receive Interface Baseband Input Level
The baseband output of the device is in the form of a The baseband input is in digital 1-bit sigma-delta convert-
digital I/Q interface. The received signals are sampled ed format. There are internal 1-bit I/Q DACs that restore
by a 1-bit sigma-delta modulator clocked at 153.6MHz the level of the incoming digital signals to a repeatable
for WCDMA and 26MHz for GSMK. The digital bitstream analog level in the device. At a given TX_GAIN value,
out of the converter is transported from the device to the RMS output power level depends on the density of
the baseband processor by a low-voltage differential the bit stream, not the voltage level of the LVDS digital
signaling (LVDS) interface. The output data is single-bit signal. The density of the bit stream, in turn, depends
nonreturn-to-zero (NRZ). The device does not perform on the input level of the sigma-delta converter, which
any encoding of the data and no clock is exchanged resides in the baseband chip. The condition for the AC
between the device and the baseband processor. performance in the EC table calls for -4dBFs peak, which
The device performs limited analog filtering only to mini- means -4dB relative to the full scale of the input of the
mize aliasing; all channel filtering is realized entirely in sigma-delta converter. The sigma-delta converter, coded
the digital domain. The digital filtering removes undesired in Verilog, and implemented on FPGA has 10 bits (9 bits
signals as well as the inherent quantization noise of the + sign) at the input. In this case, the full scale is Q511,
sigma-delta modulator. In addition, the device’s analog and -4dBFs peak means Q322 peak excursion. The RMS
filters include a pole at approximately half the channel level is lower than this number, depending on the peak-
bandwdith that must be equalized by the digital filters. average ratio of the signal. For TM1, the peak-average
is 10.6dB at 0.01%, so the RMS level of the baseband
The differential outputs require a termination resistor at signal is -14.6dBFs, or Q95.
the digital baseband IC inputs. The output current of the
LVDS drivers are programmable by the LVDSI_2X bit in DC Offset
the BB_CLKOUT register to accommodate different ter- While the inherent DC offset at the I/Q outputs is very
mination resistors. Set LVDSI_2X = 1 to set the drive cur- low, it is expected that the baseband processor digitally
rent to nominal for operation with 120I differential loads. removes any DC offset.
Digital Filters/Sigma Delta Modulator
Digital I/Q Transmit Interface
Verilog code is available for implementation of the sigma-
The Tx baseband input of the device is in the form of a
delta modulator and digital filters in the baseband pro-
sigma-delta modulated digital I/Q interface. The digital
cessor. Contact the factory for more information.
bitstream of the baseband processor is transported
to the device by a low-voltage differential signaling Fractional-N Synthesizers
(LVDS) or DDR3 interface. The LVDS signal has a typical The device includes three fractional-N frequency synthe-
common-mode voltage of 1.2V and a differential swing sizers. One synthesizer is used to generate the receive
of 140mVP-P, while DDR3 has a common-mode voltage RF local oscillator (LO), the second is used to generate
of 0.75V and differential of 600mVP-P. For LVDS, the the transmit RF local oscillator, while the third is used to
input data should be in single-bit NRZ format; no clock generate the ADC sampling clock. The loop filter for the
is exchanged between the baseband processor and the ADC sampling clock synthesizer is integrated on-chip.
device. The device recovers the I/Q bitstreams with an RF synthesizers require an external loop filter. All synthe-
on-chip data recovery circuit. The bitstream is converted sizers have 20 bits of fractional resolution.
to an analog signal and filtered prior to upconversion to
an RF signal.
Maxim Integrated 47
MAX2550
LVDS
ANALOG INTERFACE
PREFILTER
I MIXER
1-BIT SIGMA- MATCHED
I CHANNEL 120I DATA SYNC DECIMATION EQUALIZER
DELTA ADC FILTER
PGA
LVDS DEMOD
ANALOG INTERFACE
PREFILTER
Q MIXER
1-BIT SIGMA- DATA SYNC DECIMATION EQUALIZER MATCHED
Q CHANNEL 120I
DELTA ADC FILTER
PGA
FRAC-N DIGITAL
SYNTHESIZER FILTER
MAX2550 CLOCK CLOCK
/K
GENERATOR
19.2MHz
TCXO
DIGITAL BASEBAND IC
Figure 1. Digital Baseband Receiver Interface
I
1-BIT SIGMA-DELTA 10
DIGITAL RRC
DAC CONVERTER
FULL SCALE IS (2(n-1) - 1)

WHERE n = NUMBER OF BITS.
BASEBAND FOR 10 BITS, FULL SCALE IS 511.
MAX2550
dBFs IS dB RELATIVE TO THIS FULL SCALE.
Q
1-BIT SIGMA-DELTA 10
DIGITAL RRC
DAC CONVERTER
THE DENSITY OF 1S AND 0S HERE DETERMINES THE MAX2550

OUTPUT POWER, AND THE DENSITY IS DETERMINED BY THE LEVEL AT
THE INPUT OF THE SIGMA-DELTA CONVERTER.
Figure 2. Baseband Input Example
Maxim Integrated 48
MAX2550
RF Synthesizers multiplying by 220 and rounding to the nearest whole
For the receiver the RF LO frequency is programmed number. Then, convert the result to binary and program
by the RXLO_FRAC [19:0] (Fractional) register and the the bits into the RXLO_FRAC.
RXLO_SYN[7:0] (Integer) register. The synthesizer fre- Fractional-N divider = 0.479166 x 220 = 502442 =
quency is demonstrated by the following example. 0x7AAAA à RXLO_FRAC = 0x7AAAA
Assume:
ADC Clock Synthesizer
fREFIN = fCOMPARISON = 19.2MHz The sampling clock frequency is controlled by the CINT
(BBCLK_SYN[7:0]) and CFRAC (BBCLK_FRAC[19:0])
 RXLO_FRAC  registers. The sampling clock synthesizer does not need
fLO =
fREFIN × RXLO_SYN + ×K
 2 20  to be repeatedly programmed during normal operation.
The sampling clock frequency (fADCCLK) is 153.6MHz in
where: WCDMA mode and 26MHz in GSM mode. The dynamic
K = 1 if RXIN1, RXIN2, RXIN5 range of the converters with this sampling frequency is
sufficient to meet all system specifications with very mini-
K = 0.5 if RXIN3, RXIN4
mal control of the PGA.
For the transmitter the RF LO frequency is programmed
Assume:
by the TXLO_FRAC [19:0] (Fractional) register and the
TXLO_SYN[7:0] (Integer) register. The synthesizer fre- fREFIN = fCOMPARISON = 19.2MHz
quency is demonstrated by the following example. ADC Clock Synthesizer
Assume: Fractional Frequency Correction
fREFIN = fCOMPARISON = 19.2MHz The ADC clock synthesizer uses a 20-bit frequency syn-
thesizer and can be enhanced by a fractional error cor-
rection. Parameters PBYQ_RATUP and PBYQ_RATDN
 TXLO_FRAC 
fLO =
fREFIN ×  TXLO_SYN + × K implement the following function.
 2 20 
fADCCLK = fREFIN x (CINT + (CFRAC + PBYQ_RATUP/
where: (PBYQ_RATUP + PBYQ_RATDN))/220) x K
K = 0.5 for TXOUTL PBYQ_RATUP/(PBYQ_RATUP + PBYQ_RATDN) =
(fADCCLK/fREFIN - CINT) x 220 x K - CFRAC
K = 1 for TXOUTH
where:
Calculate the required divider ratio by dividing the LO
frequency by the reference frequency. K = 8 if WCDMA
K = 48 if GSM/PCS/DCS
fLO x 2 1910MHz PBYQ_RATUP and PBYQ_RATDN should be chosen for
=
Divider = = 99.479166
fCOMPARISON 19.2MHz the best fit.
This feature can be enabled or disabled through EN_
The integer-N divider is equal to the integer portion of the PBYQDIV (REG15<22>). Table 8 shows the PBYQ_
divider ratio, 99 in this example. Convert the integer-N dec- RATUP and PBYQ_RATDN with commonly used crystal
imal value to binary and program into the RXLO_SYN bits. oscillator frequencies.
Integer-N divider = 99 = 0x63 = 0110 0011 à
RXLO_SYN = 0110 0011 Power-Down Modes
The device features multiple power-down modes that can
The fractional-N divider is equal to the fractional portion be controlled by hardware or software. Table 9 describes
of the divider ration, 0.479166 in this example. Convert the various power-down modes.
the fractional portion of the divider to a 20-bit word by
Maxim Integrated 49
MAX2550
Table 8. Typical LNAOUTL (High Gain) S11 Parameters (VCC_ = +3.3V, TA = +25°C)
795 40.1 -4.0 870 52.7 5.3
800 40.8 -3.3 875 53.6 5.8
805 41.6 -2.6 880 54.6 6.3
810 42.3 -1.9 885 55.6 6.7
815 43.1 -1.2 890 56.6 7.2
820 43.9 -0.6 895 57.6 7.6
825 44.7 0.1 900 58.6 8.0
830 45.5 0.7 905 59.7 8.4
835 46.4 1.3 910 60.7 8.8
840 47.2 1.9 915 61.8 9.1
845 48.1 2.5 920 62.9 9.4
850 49.0 3.1 925 64.0 9.7
855 49.9 3.7 930 65.1 10.0
860 50.8 4.2 935 66.3 10.2
865 51.7 4.8
Table 9. Typical MIXINH S11 Parameters (VCC_ = +3.3V, TA = +25°C)

FREQUENCY (MHz) S11 REAL S11 IMAGINARY FREQUENCY (MHz) REAL IMAGINARY
1880 28.55 -31.48 1955 31.31 -32.35
1885 28.77 -31.50 1960 31.45 -32.44
1890 28.98 -31.53 1965 31.59 -32.54
1895 29.19 -31.56 1970 31.72 -32.64
1900 29.39 -31.60 1975 31.84 -32.74
1905 29.59 -31.64 1980 31.96 -32.85
1910 29.79 -31.69 1985 32.07 -32.95
1915 29.98 -31.75 1990 32.18 -33.06
1920 30.16 -31.81 1995 32.28 -33.18
1925 30.34 -31.87 2000 32.37 -33.29
1930 30.52 -31.94 2005 32.46 -33.41
1935 30.69 -32.01 2010 32.54 -33.52
1940 30.85 -32.09 2015 32.61 -33.64
1945 31.01 -32.17 2020 32.68 -33.76
1950 31.16 -32.26
Maxim Integrated 50
MAX2550
Carrier and RF Band Configuration
Sideband Suppression Optimization The device has configurable VCO and LO generation
The device delivers a typical carrier suppression of to support Bands I, V, and VIII forward and reverse link
-40dBc and a sideband suppression of -45dBc without operation. In transmit signal path, LC tank is also config-
any external calibration; however, if greater suppression urable to optimize performance in both bands. Table 10
is required, the device is capable of overriding the fac- shows the key difference in SPI settings.
tory settings and accepting manual calibration from the
baseband processor. General-Purpose Outputs
The device is equipped with three general-purpose out-
puts. GPO3 can also be configured as a PLL lock detect
for the Rx, Tx, or Rx and Tx. See Table 20 for how to
properly configure the general-purpose outputs.
Table 10. Typical MIXINL S11 Parameters (VCC_ = +3.3V, TA = +25°C)

FREQUENCY (MHz) S11 REAL S11 IMAGINARY FREQUENCY (MHz) REAL IMAGINARY
795 25.70 -43.40 870 36.10 -30.90
800 26.10 -42.50 875 37.22 -30.22
805 26.50 -41.60 880 38.39 -29.58
810 27.00 -40.70 885 39.60 -28.97
815 27.50 -39.80 890 40.85 -28.41
820 28.00 -38.90 895 42.14 -27.89
825 28.60 -38.00 900 43.48 -27.42
830 29.20 -37.10 905 44.85 -27.00
835 29.90 -36.30 910 46.27 -26.64
840 30.60 -35.50 915 47.73 -26.35
845 31.40 -34.70 920 49.22 -26.11
850 32.20 -33.90 925 50.75 -25.95
855 33.10 -33.10 930 52.31 -25.87
860 33.97 -32.34 935 53.91 -25.86
865 35.01 -31.60
Maxim Integrated 51
MAX2550
Power-On Reset (POR) 4-Wire Serial Interface
Recommended defaults are not guaranteed upon power- The device includes 32 programmable 26-bit registers.
up and are provided for reference only. All registers must The most significant bit (MSB) is the read/write selection
be written with the proper values no earlier than 100Fs bit (R/W in Figure 4). The next 5 bits are register address
after power-up. Figure 3 displays the time it takes for (A[4:0] in Figure 4). The 26 least significant bits (LSBs)
Tx/Rx PLL lock detect (GPO3) to become active after are register data (D[25:0] in Figure 4). Register data is
power-up and enabling the correct registers for proper loaded through the 4-wire SPI/MICROWIREK-compatible
operation. All reserved registers should only be written serial interface. MSB of data at the DIN pin is shifted in
with default values. first and is framed by CS. When CS is low, input data is
shifted at the rising edge of the clock at the SCLK pin. At
Temperature Sensor
CS rising edge, the 26-bit data bits are latched into the
An on-chip temperature sensor is enabled by program-
register selected by the address bits. See Figure 4. There
ming RX_ENABLE<14> = 1. To trigger temperature sen-
is no power-on SPI register self-reset functionality in the
sor ADC reading, program RX_MISC2<6> from 0 to 1.
device; the user must program all register values after
The ADC acquires the 5-bit logic output in 2Fs; the tem-
power-up. During the read mode, register data selected
perature sensor needs to be on (RX_ENABLE<14> = 1)
by address bits is shifted out to the DOUT pin at the fall-
to maintain the ADC logic output. To read the 5-bit logic
ing edges of the clock.
output through the DOUT pin, apply 4-wire SPI readout
programming sequence to RX_MISC2<11:7>.
CS
SCLK
DIN W/ADDRESS/DATA
INTERNAL
32tSCLK
BUILDING BLOCK
ENABLE BITS 32tSCLK
WCDMA = 200µs
TXPLL
LOCK DETECT
AT GPO3
RXPLL
LOCK DETECT WCDMA = 200µs
AT GPO3
XCVR IS ENABLED XCVR IS READY
Figure 3. POR PLL Lock-Detect Time

MICROWIRE is a trademark of National Semiconductor Corp.
Maxim Integrated 52
MAX2550
Table 11. Typical TXOUTL S11 Parameters (VCC_ = +3.3V, TA = +25°C)
FREQUENCY (MHz) REAL IMAGINARY FREQUENCY (MHz) REAL IMAGINARY
700.0 25.5 63.9 1500.0 9.7 20.1
750.0 52.3 76.8 1550.0 9.6 22.5
800.0 103.7 59.2 1600.0 9.6 24.8
850.0 107.4 -9.9 1650.0 9.6 27.1
900.0 64.8 -32.6 1700.0 9.7 29.4
950.0 39.6 -27.2 1750.0 9.8 31.6
1000.0 27.2 -18.9 1800.0 10.0 33.9
1050.0 20.7 -11.8 1850.0 10.2 36.2
1100.0 16.9 -6.1 1900.0 10.4 38.6
1150.0 14.5 -1.3 1950.0 10.7 41.0
1200.0 12.9 2.7 2000.0 11.0 43.5
1250.0 11.8 6.3 2050.0 11.3 46.0
1300.0 11.1 9.4 2100.0 11.7 48.6
1350.0 10.5 12.3 2150.0 12.2 51.4
1400.0 10.1 15.0 2200.0 12.7 54.2
1450.0 9.9 17.6
Table 12. Typical TXOUTH S11 Parameters (VCC_ = +3.3V, TA = +25°C)

FREQUENCY (MHz) REAL IMAGINARY FREQUENCY (MHz) REAL IMAGINARY
700.0 3.7 21.9 1500.0 41.1 89.9
750.0 3.9 23.9 1550.0 58.2 98.0
800.0 4.2 26.0 1600.0 83.9 101.3
850.0 4.5 28.2 1650.0 117.3 91.2
900.0 4.8 30.5 1700.0 146.2 58.0
950.0 5.2 33.1 1750.0 149.1 10.8
1000.0 5.8 35.8 1800.0 126.3 -24.1
1050.0 6.4 38.9 1850.0 97.4 -38.3
1100.0 7.2 42.2 1900.0 74.0 -39.5
1150.0 8.3 45.8 1950.0 57.4 -35.4
1200.0 9.7 50.0 2000.0 45.8 -29.5
1250.0 11.5 54.6 2050.0 37.8 -23.5
1300.0 14.0 60.0 2100.0 32.0 -17.8
1350.0 17.5 66.1 2150.0 27.8 -12.6
1400.0 22.5 73.2 2200.0 24.7 -7.8
1450.0 29.9 81.2
Maxim Integrated 53
MAX2550
Table 13. PBYQ_RATUP and PBYQ_RATDN Commonly Used Crystal Oscillator
Frequencies
CINT CFRAC PBYQ_RATUP PBYQ_RATDN CINT CFRAC
fREFIN PBYQ_RATUP PBYQ_RATDN
REG15 REG1 REG16 REG16 REG15 REG14
(MHz) REG16<7:0> REG16<15:8>
<7:0> <19:0> <7:0> <15:8> <7:0> <19:0>
STANDARD Integer Fractional Integer Fractional
Fractional LSB Fractional LSB
Reference Divide Divide Fractional LSB Divide Divide Fractional LSB
Dither Down Dither Down
Frequency Ratio Ratio Dither Up (dec) Ratio Ratio Dither Up (hex)
(dec) (hex)
(dec) (dec) (hex) (hex)
13 94 548485 59 6 5E 85E85 3B 6
15.36 80 0 0 0 50 0 0 0
WCDMA 19.2 64 0 0 0 40 0 0 0
20 61 461373 11 14 3D 70A3D B E
26 47 274242 62 3 2F 42F42 3E 3
13 96 0 0 0 60 0 0 0
15.36 81 262144 0 0 51 40000 0 0
GSM 19.2 65 0 0 0 41 0 0 0
20 62 419430 2 3 3E 66666 2 3
26 48 0 0 0 30 0 0 0
Table 14. Power-Down Modes

BLOCKS BIAS AFCDAC CDR DIVIDER
REFEN PIN, CDR ENABLE
OPERATING MODE ENABLE ENABLE ENABLE ENABLE
REG29<14:12> REG24<18>
REG00<18:0> REG20<24> REG30<19> REG16<20>
Sleep 0000 00000 0 0 0 0
AFC Only 0000 00000 0 1 0 0
Reference Buffer Only 1xxx or 0100 00000 0 1 0 0
Idle RX 1xxx or 0x11 00840 1 1 0 0
Idle TX 1xxx or 0x11 01000 1 1 1 1
RXIN1/TXOUTH Full
1xxx or 0x11 79BFF 1 1 1 1
Duplex
RXIN1 Only 1xxx or 0x11 009FF 1 1 0 0
RXIN3/TXOUTL Full
1xxx or 0x11 79BFF 1 1 1 1
Duplex
RXIN3 Only 1xxx or 0x11 009FF 1 1 0 0
RXIN4 Monitor 1xxx or 0x11 009FF 1 1 0 0
RXIN5 Monitor 1xxx or 0x11 009FF 1 1 0 0
TXOUTL Only 1xxx or 0x11 79240 1 1 1 1
TXOUTH Only 1xxx or 0x11 79240 1 1 1 1
RXIN2 1xx or 0x11 009FF 1 1 0 0
Maxim Integrated 54
MAX2550
Table 15. RF Band Configuration
LNA/MIXER
INPUT RF RANGE VCO SELECT VCO ROH BAND VCO DIVIDER RXIN4_HB
SELECT
PIN (MHz) REG03<20:19> REG03<22:21> REG03<18:17> REG06<16>
REG01<5:0>
RXIN1 1920 to 1980 10 01 10 18 X
RXIN3 (Band V) 820 to 849 01 XX 01 01 X
RXIN3 (Band VIII) 880 to 915 10 11 01 01 X
RXIN4 (Band V) 865 to 894 01 00 01 15 0
RXIN4 (Band VIII) 925 to 960 10 01 01 15 1
RXIN5 2110 to 2170 10 00 10 2A X
RXIN2 1805 to 1880 10 11 10 0C X
VCO VCO ROH VCO PAD_ PAD_ TXLO_ UCX_ T_UCX_ T_UCX_
RF
OUTPUT SELECT BAND DIVIDER BAND CTUNE IQ_GAIN CSW RSW BAND_SEL
RANGE
PIN REG28 REG28 REG28 REG19 REG19 REG20 REG21 REG22 REG22
(MHz)
<15:14> <17:16> <13:12> <1:0> <6:2> <19> <5:2> <20:17> <23:22>
TX_OUTL
925 to 960 10 01 01 00 00100 1 1011 XXXX 01
(Band VIII)
TX_OUTL
865 to 894 01 00 01 00 00100 1 1101 XXXX 01
(Band V)
2110 to
TX_OUTH 11 00 10 11 00000 0 0000 0101 11
2170
Maxim Integrated 55
MAX2550
tCSW
CS
tCSO tCSH
tCSS tCS1
SCLK
tCL
tDS tDH
tCH
DIN
R/W A4 A0 D25 D0 DON’T CARE
(SPI WRITE)
DIN
R/W A4 A0 D25 D0 DON’T CARE
(SPI READ)
tD
DOUT
DON’T CARE D25 D0 DON’T CARE
(SPI READ)
Figure 4. SPI Timing
Table 16. SPI Serial Interface Timing

SPEC NO. PARAMETER SYMBOL TYP UNITS
SPI1 SCLK Rising Edge to CS Falling Edge Wait Time tCSO 6 ns
SPI2 Falling Edge of CS to Rising Edge of First SCLK Time tCSS 6 ns
SPI3 DIN to SCLK Setup Time tDS 6 ns
SPI4 DIN to SCLK Hold Time tDH 6 ns
SPI5 SCLK Pulse-Width High tCH 6 ns
SPI6 SCLK Pulse-Width Low tCL 6 ns
SPI7 Last Rising Edge of SCLK to Rising Edge of CS tCSH 6 ns
SPI8 CS High Pulse Width tCSW 50 ns
SPI9 Time Between Rising Edge of CS and the Next Rising Edge of SCLK tCS1 6 ns
SPI10 SCLK Frequency fCLK 40 MHz
SPI11 Rise Time tR 2.5 ns
SPI12 Fall Time tF 2.5 ns
SPI13 SCLK Falling Edge to Valid DOUT tD 12.5 ns
Maxim Integrated 56
MAX2550
Register and Bit Descriptions Recommended defaults are not guaranteed upon power-
(If Applicable) up and are provided for reference only. All registers must
The operating mode of the device is completely con- be written with the proper values no earlier than 10Fs after
trolled by 32 on-chip registers. power-up (once VCC_ is 90% of final value). All reserved
registers should only be written with default values.
Table 17. Brief Register Map

REGISTER NO. REGISTER NAME ADDRESS FUNCTION
0 RX_ENABLE 00000 Enable bits for various internal functions
1 RX_GAIN 00001 Gain control of LNA and PGA
2 Reserved 00010 —
3 RX_LNA 00011 LNA bias, Rx synthesizer configuration
6 RX_LPF 00110 RXLPF configuration
7 GPO_CONFIG 00111 Configuration of GPOs
10 RXLO_FRAC 01010 Receive synthesizer fractional division ratio
11 RXLO_SYN 01011 Configuration of Rx synthesizer
12 BBCLK_OUT 01100 ADC configuration
14 BBCLK_FRAC 01110 ADC clock generator fractional division ratio
15 BBCLK_SYN 01111 Configuration of clock generator synthesizer
16 BBCLK_MISC 10000 Dithering clock generator synthesizer
17 BBCLK_SPARE 10001 Miscellaneous setting for clock generator
18 TX_LPF 10010 LPF settings for Tx path
19 TX_PAD 10011 PA driver settings
20 TX_UPX1 10100 Tx upconverter bias
21 TX_UPX2 10101 Tx upconverter bias adjustment and V2I attenuation
22 TX_UPX3 10110 Tx upconverter DC offset adjustment
23 TX_GAIN1 10111 Tx path gain setting
24 TX_GAIN2 11000 Tx path gain curve adjustment
27 TXLO_FRAC 11011 Transmit synthesizer fractional division ratio
28 TXLO_SYN 11100 Configuration of Tx synthesizer
29 TXLO_REF 11101 Configuring REFOUT and REFIN
30 TXLO_AFCDAC 11110 AFC DAC word
Maxim Integrated 57
0
9
8
7
6
5
4
3
2
1
BIT
TXVGCEN LVDSI LVDSQ ADCCLKEN ADCEN PGAIEN PGAQEN RXLPFEN RXMXREN LNAEN BIT ID
Tx VGC Rx I LVDS Rx Q LVDS ADC Clock Rx I PGA Rx Q PGA Rx LPF Rx Mixer

ADC Enable LNA Enable NAME
Maxim Integrated
Enable Enable Enable Enable Enable Enable Enable Enable
0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable
DEFINITION
1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable
0
0
0
0
0
0
0
0
0
0
BIT
0
1
1
1
1
1
1
1
1
1
BAND1 RX1 ONLY
0
1
1
1
1
1
1
1
1
1
DCS RX2 ONLY
0
1
1
1
1
1
1
1
1
1
BAND V RX3 ONLY
BAND VIII RX3
0
1
1
1
1
1
1
1
1
1
ONLY
0
1
1
1
1
1
1
1
1
1 BAND V RX4 ONLY
BAND VIII RX4
0
1
1
1
1
1
1
1
1
1
ONLY
0
1
1
1
1
1
1
1
1
1
BAND I RX5 ONLY
1
0
0
1
0
0
0
0
0
0
BAND I TXH ONLY

Table 18. RX_ENABLE Register 0 (Address = 00000)
1
0
0
1
0
0
0
0
0
0
BAND V TXL ONLY
BAND VIII TXL
1
0
0
1
0
0
0
0
0
0
ONLY
BAND I RX1/TXH
1
1
1
1
1
1
1
1
1
1
FDD
BAND V RX3/TXL
1
1
1
1
1
1
1
1
1
1
FDD
BAND VIII RX3/TXL
1
1
1
1
1
1
1
1
1
1
FDD
0
0
0
1
0
0
0
0
0
0
BAND I RX IDLE
0
0
0
1
0
0
0
0
0
0
BAND I TX IDLE
0
0
0
0
0
0
0
0
0
0
AFC ONLY
REFERENCE
0
0
0
0
0
0
0
0
0
0
BUFFER
0
0
0
0
0
0
0
0
0
0
SLEEP
MAX2550
58
10
18
17
16
15
14
13
12
11
BIT
UPCXEN TXLOEN TXLPFEN PADEN TSEN BBLBEN TXSYNEN RXSYNEN Reserved BIT ID
Upconverter Tx LO Tx LPF PA Driver Temperature BB Loopback Tx SYN Rx SYN

Reserved NAME
Maxim Integrated
Enable Enable Enable Enable Sensor Enable Enable Enable Enable
0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable 0 = Disable
— DEFINITION
1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable 1 = Enable
0
0
0
0
0
0
0
0
0
BIT
0
0
0
0
0
0
0
1
0
BAND1 RX1 ONLY
0
0
0
0
0
0
0
1
0
DCS RX2 ONLY
0
0
0
0
0
0
0
1
0
BAND V RX3 ONLY
0
0
0
0
0
0
0
1
0
BAND8 RX3 ONLY
0
0
0
0
0
0
0
1
0 BAND5 RX4 ONLY
0
0
0
0
0
0
0
1
0
BAND8 RX4 ONLY
0
0
0
0
0
0
0
1
0
BAND1 RX5 ONLY
1
1
1
1
0
0
1
0
0
BAND1 TXH ONLY
1
1
1
1
0
0
1
0
0
BAND5 TXL ONLY
1
1
1
1
0
0
1
0
0
BAND8 TXL ONLY
BAND1 RX1/TXH
1
1
1
1
0
0
1
1
0
FDD
BAND5 RX3/TXL
1
1
1
1
0
0
1
1
0
Table 18. RX_ENABLE Register 0 (Address = 00000) (continued)
FDD
BAND8 RX3/TXL
1
1
1
1
0
0
1
1
0
FDD
0
0
0
0
0
0
0
1
0
BAND1 RX IDLE
0
0
0
0
0
0
0
1
0
BAND1 TX IDLE
0
0
0
0
0
0
0
0
0
AFC ONLY
REFERENCE
0
0
0
0
0
0
0
0
0
BUFFER
0
0
0
0
0
0
0
0
0
SLEEP
MAX2550
59
MAX2550
Table 18. RX_ENABLE Register 0 (Address = 00000) (continued)
BAND V RX3 ONLY
BAND1 TXH ONLY

BAND1 RX1 ONLY
BAND8 RX3 ONLY
BAND5 RX4 ONLY
BAND8 RX4 ONLY
BAND1 RX5 ONLY
BAND5 TXL ONLY
BAND8 TXL ONLY
BAND1 RX1/TXH
BAND5 RX3/TXL
BAND8 RX3/TXL
BAND1 RX IDLE
BAND1 TX IDLE
DCS RX2 ONLY
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
FDD
FDD
FDD
BIT
BIT
19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
22 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 60
3
8
2
9
7
6
5
4
1
0
11
10
BIT
PGAGAIN MX_SW LNASEL

Reserved BandSel_Mix BIT ID
<3:0> <1:0> <2:0>
LNA
Rx PGA Gain Control Reserved Rx Mixer Input Select Rx Mixer Select NAME
Selection
Maxim Integrated
<3:0> = 0000 = Min gain (default) If BandSel_Mix = 0 If BandSel_Mix = 1 <2:0> = 000 = RXIN1
<3:0> = 0001 = Min gain + 3dB (CELL) (PCS) 0 = CEL mixer <2:0> = 100 = RXIN2
00 = DCS input
… — 11 = None (default) <2:0> = 001 = RXIN3 DEFINITION
01 = PCS input
<3:0> = 1110 = Max gain - 3dB X0 = CELL input 10 = IMT input 1 = PCS mixer <2:0> = 101 = RXIN4
<3:0> = 1111 = Max gain X1 = GSM input 11 = None <2:0> = X10 = RXIN5
3
1
1
1
2
0
0
1
0
0
0
BIT
0
1
0
0
1
0
0
0
1
1
0
BAND1 RX1 ONLY
1
0
0
0
1
0
0
0
0
1
0
DCS RX2 ONLY
0
1
0
0
1
0
0
0
0
0
1
BAND V RX3 ONLY
0
1
0
0
1
0
0
0
0
0
1
BAND8 RX3 ONLY
1
1
0
0
0
1
0
0
1
0
1
BAND5 RX4 ONLY
1
1
0
0
0
1
0
0
1
0
1
BAND8 RX4 ONLY

0
1
1
0
1
0
1
0
1
0
1
0
BAND1 RX5 ONLY

Table 19. RX_GAIN Register 1 (Address = 00001)
0
0
0
0
0
0
0
0
1
1
0
BAND1 TXH ONLY

0
0
0
0
0
0
0
0
0
0
0
1
BAND5 TXL ONLY

0
0
0
0
0
0
0
0
0
0
0
1
BAND8 TXL ONLY
BAND1 RX1/TXH
0
0
1
0
0
1
0
0
0
1
1
0
FDD
BAND5 RX3/TXL
0
0
1
0
0
1
0
0
0
0
0
1
FDD
BAND8 RX3/TXL
0
0
1
0
0
1
0
0
0
0
0
1
FDD
0
0
1
0
0
1
0
0
0
1
1
0
BAND1 RX IDLE
0
0
1
0
0
1
0
0
0
1
1
0
BAND1 TX IDLE
0
0
0
0
0
0
0
0
0
1
1
0
AFC ONLY
REFERENCE
0
0
0
0
0
0
0
0
1
1
0
0
BUFFER
0
0
0
0
0
0
0
0
1
1
0
0
SLEEP
MAX2550
61
22
21
20
19
25
18
16
14
24
17
15
13
23
12
BIT
LNAGAIN Reserved
Reserved BIT ID
<1:0>
LNA GAIN
Reserved Reserved NAME
Control
Maxim Integrated
<1:0> = 00 = Low gain
<1:0> = 01 = Mid gain (not
available
— — DEFINITION
for RXIN4)
<1:0> = 10 = High gain (default)
<1:0> = 11 = Do not use
7
6
5
4
3
9
1
1
1
8
0
0
0
10
BIT
0
0
0
0
0
0
0
0
1
0
0
0
0
0
BAND1 RX1 ONLY
0
0
0
0
0
0
0
0
1
0
0
0
0
0
DCS RX2 ONLY
0
0
0
0
0
0
0
0
1
0
0
0
0
0
BAND V RX3 ONLY
0
0
0
0
0
0
0
0
1
0
0
0
0
0
BAND8 RX3 ONLY
0
0
0
0
0
0
0
0
1
0
0
0
0
0
BAND5 RX4 ONLY
0
0
0
0
0
0
0
0
1
0
0
0
0
0
BAND8 RX4 ONLY
0
0
0
0
0
0
0
0
1
0
0
0
0
0
BAND1 RX5 ONLY
0
0
0
0
0
0
0
0
1
0
0
0
0
0
BAND1 TXH ONLY
0
0
0
0
0
0
0
0
1
0
0
0
0
0
BAND5 TXL ONLY
0
0
0
0
0
0
0
0
1
0
0
0
0
0
BAND8 TXL ONLY

Table 19. RX_GAIN Register 1 (Address = 00001) (continued)
BAND1 RX1/TXH
0
0
0
0
0
0
0
0
1
0
0
0
0
0
FDD
BAND5 RX3/TXL
0
0
0
0
0
0
0
0
1
0
0
0
0
0
FDD
BAND8 RX3/TXL
0
0
0
0
0
0
0
0
1
0
0
0
0
0
FDD
0
0
0
0
0
0
0
0
1
0
0
0
0
0
BAND1 RX IDLE
0
0
0
0
0
0
0
0
1
0
0
0
0
0
BAND1 TX IDLE
0
0
0
0
0
0
0
0
1
0
0
0
0
0
AFC ONLY
REFERENCE
0
0
0
0
0
0
0
0
1
0
0
0
0
0
BUFFER
0
0
0
0
0
0
0
0
1
0
0
0
0
0
SLEEP
MAX2550
62
MAX2550
Table 20. Reserved Register 2 (Address = 00010)
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND1 TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
12 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
13 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23 23 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
24 24 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
25 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 63
MAX2550
Table 21. RX_LNA Register 3 (Address = 00011)
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
—
6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
9 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rx RF PLL Loop
Ena Rx RF oop
RXSYN_RBYP
1 = Not used
0 = WCDMA
Filter ble
Filter Adjust
Rx SYN
11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
14 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
—
15 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
16 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Maxim Integrated 64
25
23
21
19
24
22
20
18
17
BIT
RVCO_DIV2
Reserved RVCOTUNE <1:0> RVCO_SEL <1:0> BIT ID
<1:0>
Rx RF VCO ROH Band

Reserved Rx RF VCO Selection NAME
Maxim Integrated
Selection
<1:0> = 00 = band2
<1:0> = 00 = Disable Rx RF VCO
(IMT) <1:0> = 01 = ROL Prescaler Divide
— <1:0> = 01 = band3 (CELL) Ratio Configuration DEFINITION
<1:0> = 10 = ROH (PCS) <1:0> = 01 = CELL
(PCS)
<1:0> = 11 = Not used <1:0> = 10 = PCS
<1:0> = 11 = Not used
3
2
0
9
7
1
8
6
10
BIT
0
0
0
1
1
1
0
0
0
BAND I RX1 ONLY
0
0
1
1
1
1
1
0
0
DCS RX2 ONLY
0
0
0
0
0
1
1
1
1
BAND V RX3 ONLY
BAND VIII RX3
0
0
1
1
0
1
1
0
1
ONLY
0
0
0
0
0
1
0
1
1
BAND V RX4 ONLY
BAND VIII RX4
0
0
0
1
0
1
1
0
1
ONLY
0
0
0
1
1
1
0
1
0
BAND I RX5 ONLY
0
0
0
1
1
1
0
0
0
BAND I TXH ONLY
0
0
0
0
0
1
0
1
1
BAND V TXL ONLY
BAND VIII TXL
0
0
1
1
0
1
1
0
1
Table 21. RX_LNA Register 3 (Address = 00011) (continued)
ONLY
BAND I RX1/TXH
0
0
0
1
1
1
0
0
0
FDD
BAND V RX3/TXL
0
0
0
0
0
1
1
1
1
FDD
BAND VIII RX3/TXL
0
0
1
1
0
1
1
0
1
FDD
0
0
0
1
1
1
0
0
0
BAND I RX IDLE
0
0
0
1
1
1
0
0
0
BAND I TX IDLE
0
0
0
1
1
1
0
0
0
AFC ONLY
REFERENCE
0
0
0
1
1
1
0
0
0
BUFFER
0
0
0
1
1
1
0
0
0
SLEEP
MAX2550
65
MAX2550
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reserved
Reserved
12 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
—
13 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
18 18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22 22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
23 23 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
24 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 66
MAX2550
BAND V RX3 ONLY
BAND1 TXH ONLY

BAND1 RX1 ONLY
BAND8 RX3 ONLY
BAND5 RX4 ONLY
BAND8 RX4 ONLY
BAND1 RX5 ONLY
BAND5 TXL ONLY
BAND8 TXL ONLY
BAND1 RX1/TXH
BAND5 RX3/TXL
BAND8 RX3/TXL
BAND1 RX IDLE
BAND1 TX IDLE
DCS RX2 ONLY
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
FDD
FDD
FDD
BIT
BIT
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
7 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
12 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
13 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
17 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 67
MAX2550
Table 24. RX_LPF Register 6 (Address = 00110)
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reserved
Reserved
8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
9 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
10 10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
11 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13 13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
14 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
16 16 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0
0 = Normal operation
1 = Bypass Rx LPF
Rx LPF Bypass
LPFBYPASS
17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
20 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
21 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rx LPF Bandwidth
23 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000 = WCDMA
011 = GSM
BBMODE
Select
24 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 68
6
4
5
3
2
1
0
BIT
TS_TRIG GPO3<1:0> GPO2<1:0> GPO3_LD_RD_sel_LSB Reserved BIT ID
Temperature Sensor GPO2 GPO2 Output

GPO3 Output Select Reserved NAME
Select Select
Maxim Integrated
Reading Trigger
GPO3 Output Mux Select LSB

<1:0> = 00 = High-Z <1:0> = 00 = High-Z MSB in REG7<17>
0 = Not trigger reading <1:0> = 01 = High-Z <1:0> = 01 = High-Z 00 = RXPLL LD
— DEFINITION
1 = Trigger reading <1:0> = 10 = Low-Z low <1:0> = 10 = Low-Z low 01 = TXPLL LD
<1:0> = 11 = Low-Z high <1:0> = 11 = Low-Z high 10 = Output selected by GPO3<1:0>
11 = RXPLL LD and TXPLL LD and CLKPLL LD
1
1
0
0
0
0
BIT
0
0
0
1
1
0
0
BAND I RX1 ONLY
0
0
0
1
1
0
0
DCS RX2 ONLY
0
0
0
1
1
0
0
BAND V RX3 ONLY
BAND VIII RX3
0
0
0
1
1
0
0
ONLY
0
0
0
1
1
0
0
BAND V RX4 ONLY
BAND VIII RX4
0
0
0
1
1
0
0
ONLY
0
0
0
1
1
0
0
BAND I RX5 ONLY
0
0
0
1
1
0
0
BAND I TXH ONLY

Table 25. GPO_CONFIG Register 7 (Address = 00111)
0
0
0
1
1
0
0
BAND V TXL ONLY
BAND VIII TXL
0
0
0
1
1
0
0
ONLY
BAND I RX1/TXH
0
0
0
1
1
0
0
FDD
BAND V RX3/TXL
0
0
0
1
1
0
0
FDD
BAND VIII RX3/TXL
0
0
0
1
1
0
0
FDD
0
0
0
1
1
0
0
BAND I RX IDLE
0
0
0
1
1
0
0
BAND I TX IDLE
0
0
0
1
1
0
0
AFC ONLY
REFERENCE
0
0
0
1
1
0
0
BUFFER
0
0
0
1
1
0
0
SLEEP
MAX2550
69
9
8
7
17
16
11
15
10
24
22
20
14
25
23
21
19
18
13
12
BIT
DOUT_DRV
Reserved Reserved GPO3_LD_RD_sel_MSB Reserved BIT ID
<1:0>
Temperature Sensor
Reserved DOUT Drive Strength Reserved Reserved NAME
Output
Maxim Integrated
GPO3 Output Mux Select MSB
LSB in REG7<1>
<1:0> = 00 = 1x
00 = RXPLL LD To be read at DOUT
<1:0> = 01 = 2x
— — 01 = TXPLL LD — pin DEFINITION
<1:0> = 10 = 3x
10 = Output selected by GPO3<0:1> through SPI readback
<1:0> = 11 = 4x
11 = RXPLL LD and TXPLL LD and
CLKPLL LD
4
4
3
3
2
2
3
1
1
1
1
1
2
0
0
0
0
0
0
BIT
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
BAND I RX1 ONLY
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
DCS RX2 ONLY
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
BAND V RX3 ONLY
BAND VIII RX3
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
ONLY
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
BAND V RX4 ONLY
BAND VIII RX4
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
ONLY
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
BAND I RX5 ONLY
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
BAND I TXH ONLY
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
BAND V TXL ONLY
BAND VIII TXL

1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
ONLY
BAND I RX1/TXH
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
FDD
Table 25. GPO_CONFIG Register 7 (Address = 00111) (continued)
BAND V RX3/TXL
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
FDD
BAND VIII RX3/TXL
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
FDD
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
BAND I RX IDLE
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
BAND I TX IDLE
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
AFC ONLY
REFERENCE
1
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
BUFFER
1
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
SLEEP
MAX2550
70
MAX2550
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
12 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
13 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 71
MAX2550
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
12 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
13 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 72
MAX2550
Table 28. RXLO_FRAC Register 10 (Address = 01010)
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
1 1 0 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
2 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
3 3 0 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
Receiver RF Synthesizer Fractional Division Ratio
5 5 0 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
6 6 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
7 7 0 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
See the RF Synthesizers
8 8 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
RFFRAC
9 9 0 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
<19:0>
section
10 10 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
11 11 0 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
12 12 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
13 13 0 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
14 14 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
15 15 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
16 16 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
17 17 0 1 1 1 1 1 1 0 1 1 0 1 1 0 0 0 0 0
18 18 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0
19 19 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1
20 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
21 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
22 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
23 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Maxim Integrated 73
MAX2550
Table 29. RXLO_SYN Register 11 (Address = 01011)
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 1 1 0 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1
Rx RF PLL Integer Divide Ratio
1 0 0 1 1 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0
See the RF Synthesizers
2 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
RINT<7:0>
3 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0
section
4 0 0 1 1 1 1 0 0 0 1 1 0 1 1 0 0 0 0 0
5 0 1 0 0 0 0 1 1 1 0 0 1 0 0 1 1 1 1 1
6 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 = Divide-by-1
1 = Divide-by-2
Rx Reference
Divide Ratio
RRD
8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
11 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rx PLL Charge-Pump Current
18 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Rx RF PLL Charge-Pump
RCPI<2:0>
000 = Not used
19 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
110 = 1200µA
001 = 200µA
011 = 600µA
Current
20 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
23 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
—
24 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
25 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 74
MAX2550
Table 30. BBCLK_OUT Register 12 (Address = 01100)
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
100~111 = Not used
000 = 1 for WCDMA
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
011 = 6 for GSM
Divide Ratio
ADC Clock
001 = Not used

010 = Not used
ADF<2:0>
1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
5 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
6 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RxBB LVDS 2X
Current Enable
0 = 220I load
1 = 100I load
LVDSI_2X
9 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
12 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
17 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
18 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20 10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
21 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Maxim Integrated 75
MAX2550
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reserved
Reserved
12 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
—
13 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
14 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
16 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 76
MAX2550
Table 32. BBCLK_FRAC Register 14 (Address = 01110)
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.36MHz = 40000 (hex)
4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.0MHz = 00000 (hex)
19.2MHz = 00000 (hex)

26.0MHz = 00000 (hex)
5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADC Clock PLL Fractional Divide Ratio
6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
For fREFIN =
7 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GSM:
CFRAC
<19:0>
9 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.36MHz = 00000 (hex)
14 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.0MHz = 85E85 (hex)
19.2MHz = 00000 (hex)

26.0MHz = 42F4s (hex)
15 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
For fREFIN =
17 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WCDMA:
18 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
21 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
22 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Maxim Integrated 77
4
8
3
7
2
9
6
1
5
0
17
16
15
14
13
12
10
11
BIT
Reserved CRD CINT<7:0> BIT ID
Maxim Integrated
ADC Clock PLL
Reserved Reference Divide ADC Clock PLL Integer Divide Ratio NAME
Ratio
WCDMA: GSM:
0 = Divide-by-1 For fREFIN = For fREFIN =
— (default) 13.0MHz = 5E (hex) 13.0MHz = 60 (hex) DEFINITION
1 = Divide-by-2 15.36MHz = 50 (hex) 15.36MHz = 51 (hex)
19.2MHz = 40 (hex) 19.2MHz = 41 (hex)
26.0MHz = 2F (hex) 26.0MHz = 30 (hex)
8
7
6
5
3
4
7
2
3
1
6
1
2
0
0
5
4
0
BIT
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
BAND I RX1 ONLY
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
1 DCS RX2 ONLY
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
BAND V RX3 ONLY
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
BAND VIII RX3 ONLY
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
BAND V RX4 ONLY
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
BAND VIII RX4 ONLY
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
BAND I RX5 ONLY
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
BAND I TXH ONLY
Table 33. BBCLK SYN Register 15 (Address = 01111)
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
BAND V TXL ONLY
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
BAND VIII TXL ONLY
BAND I RX1/TXH
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
FDD
BAND V RX3/TXL
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
FDD
BAND VIII RX3/TXL
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
FDD
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
BAND I RX IDLE
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
BAND I TX IDLE
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
AFC ONLY
REFERENCE
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
BUFFER
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
SLEEP
MAX2550
78
21
20
25
24
23
19
22
18
BIT
EN_
Reserved CINTB Reserved CCPI<2:0> BIT ID
PBYQDIV
Maxim Integrated
ADC Clock PLL ADC Clock PLL
ADC Clock PLL Charge Pump
Reserved Integer/ P/Q Rational Reserved NAME
Current
Fractional Mode Division Enable
ADC Clock 000 = 0FA, do not use

ADC Clock PLL
Integer/Fractional 001 = 25FA
P/Q Rational
Mode 010 = 50FA (fREFIN = 26MHz)
— Division Enable — DEFINITION
0 = Integer mode 011 = 75FA (fREFIN = 19.2MHz
0 = Disabled
1 = Fractional 100 = 100FA (fREFIN = 13MHz)
1 = Enable
mode 111 = 175FA
1
1
0
1
0
0
0
BIT
1
1
0
1
1
0
1
BAND I RX1 ONLY
1
1
0
1
1
0
1
DCS RX2 ONLY
1
1
0
1
1
0
1
BAND V RX3 ONLY
1
1
0
1
1
0
1
BAND VIII RX3 ONLY
1
1
0
1
1
0
1
BAND V RX4 ONLY
1
1
0
1
1
0
1
BAND VIII RX4 ONLY
1
1
0
1
1
0
1
BAND I RX5 ONLY

0
1
1
0
1
1
0
1
0 BAND I TXH ONLY
1
1
0
1
1
0
1
BAND V TXL ONLY

0
1
1
0
1
1
0
1
BAND VIII TXL ONLY
BAND I RX1/TXH
0
1
1
0
1
1
0
1
FDD
Table 33. BBCLK SYN Register 15 (Address = 01111) (continued)
BAND V RX3/TXL
0
1
1
0
1
1
0
1
FDD
BAND VIII RX3/TXL

0
1
1
0
1
1
0
1
FDD
0
1
1
0
1
1
1
BAND I RX IDLE
0
1
1
0
1
1
1
BAND I TX IDLE
0
1
1
0
1
1
1
AFC ONLY
REFERENCE
0
1
1
0
1
1
1
BUFFER
0
1
1
0
1
1
1
SLEEP
MAX2550
79
8
4
7
3
6
2
9
5
1
0
14
13
10
15
12
11
BIT
PBYQ_RATDN<7:0> PBYQ_RATUP<7:0> BIT ID
ADC Clock Fractional LSB Dither Down ADC Clock Fractional LSB Dither Up
NAME
Number of Cycles LSB Is Low Number of Cycles LSB Is High
Maxim Integrated
WCDMA: WCDMA:
DC Clock GSM: GSM:
For fREFIN = For fREFIN =
Fractional LSB For fREFIN = For fREFIN =
13.0MHz = 06 (hex) 13.0MHz = 3B (hex)
Dither Down. 13.0MHz = 00 (hex) 13.0MHz = 00 (hex)
15.36MHz = 00 (hex) 15.36MHz = 00 (hex) DEFINITION
Number of 15.36MHz = 00 (hex) 15.36MHz = 00 (hex)
19.2MHz = 00 (hex) 19.2MHz = 00 (hex)
cycles LSB is 19.2MHz = 00 (hex) 19.2MHz = 00 (hex)
20.0MHz = 0E (hex) 20.0MHz = 0B (hex)
low. 26.0MHz = 00 (hex) 26.0MHz = 00 (hex)
26.0MHz = 03 (hex) 26.0MHz = 3E (hex)
7
3
5
2
6
2
7
4
1
5
1
6
3
0
4
0
BIT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BAND I RX1 ONLY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DCS RX2 ONLY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BAND V RX3 ONLY
BAND VIII RX3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ONLY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BAND V RX4 ONLY
BAND VIII RX4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ONLY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BAND I RX5 ONLY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BAND I TXH ONLY

Table 34. BBCLK_MISC Register 16 (Address = 10000)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BAND V TXL ONLY
BAND VIII TXL

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ONLY
BAND I RX1/TXH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FDD
BAND V RX3/TXL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FDD
BAND VIII RX3/TXL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FDD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BAND I RX IDLE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BAND I TX IDLE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AFC ONLY
REFERENCE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BUFFER
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SLEEP
MAX2550
80
25
20
24
19
23
18
22
21
17
16
BIT
CDR_DIV2_
Reserved Reserved BIT ID
EN
CLK VCO to
Reserved CDR Divide- Reserved NAME
Maxim Integrated
by-2 Enable
CLK VCO to
CDR Divide-
— by-2 Enable — DEFINITION
0 = Disable
1 = Enable
4
3
3
2
2
1
1
0
0
0
BIT
0
0
1
0
1
0
0
0
0
0
BAND I RX1 ONLY
0
0
1
0
1
0
0
0
0
0
DCS RX2 ONLY
0
0
1
0
1
0
0
0
0
0
BAND V RX3 ONLY
BAND VIII RX3
0
0
1
0
1
0
0
0
0
0
ONLY
0
0
1
0
1
0
0
0
0
0
BAND V RX4 ONLY
BAND VIII RX4
0
0
1
0
1
0
0
0
0
0
ONLY
0
0
1
0
1
0
0
0
0
0
BAND I RX5 ONLY
0
0
1
0
1
0
0
0
1
0
BAND I TXH ONLY
0
0
1
0
1
0
0
0
1
0
BAND V TXL ONLY
BAND VIII TXL
0
0
1
0
1
0
0
0
1
0
ONLY
BAND I RX1/TXH
0
0
1
0
1
0
0
0
1
0
FDD
BAND V RX3/TXL
Table 34. BBCLK_MISC Register 16 (Address = 10000) (continued)
0
0
1
0
1
0
0
0
1
0
FDD
BAND VIII RX3/TXL
0
0
1
0
1
0
0
0
1
0
FDD
0
0
1
0
1
0
0
0
0
0
0 BAND I RX IDLE
0
1
0
1
0
0
0
0
0
BAND I TX IDLE
0
0
1
0
1
0
0
0
0
0
AFC ONLY
REFERENCE
0
0
1
0
1
0
0
0
0
0
BUFFER
0
0
1
0
1
0
0
0
0
0
SLEEP
MAX2550
81
MAX2550
Table 35. BBCLK_SPARE Register 17 (Address = 10001)
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL

DEFINITION
REFERENCE
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
9 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
12 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
13 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Die ID Readout Select
0 = Read register value

Affect REG17<25:19>
DIE_ID_sel
1 = Read die ID
18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Die ID Readout Bits at
20 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DIE_ID<6:0>
21 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DOUT pin
22 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DIE_ID<2:0>
23 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001 = 1Z
010 = 2Z
011 = 3Z
24 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 82
5
4
8
3
7
2
9
6
1
0
10
BIT
TXLPFMD TXLPFB
BBLB Reserved BIT ID
<1:0> <2:0>
TXLPF
Baseband TXLPF Operating Mode TXLPF Bandwidth Reserved NAME
Maxim Integrated
Loopback
<1:0> = 00 = Shut down 000 = Do not use
0 = Enable
<1:0> = 01 = LPF bypass 001 = WCDMA
loopback
<1:0> = 10 = Do not use 010 = Do not use — DEFINITION
1 = Normal
<1:0> = 11 = Normal operation 011 = Do not use
operation
(WCDMA 100~111 = Do not use
4
3
2
2
1
1
1
0
0
0
0
BIT
0
1
0
1
1
0
0
1
1
1
0
BAND I RX1 ONLY
0
1
0
1
1
0
0
1
1
1
0
DCS RX2 ONLY
0
1
0
1
1
0
0
1
1
1
0
BAND V RX3 ONLY
BAND VIII RX3
0
1
0
1
1
0
0
1
1
1
0
ONLY
0
1
0
1
1
0
0
1
1
1
0
BAND V RX4 ONLY
BAND VIII RX4
0
1
0
1
1
0
0
1
1
1
0
ONLY
0
1
0
1
1
0
0
1
1
1
0
BAND I RX5 ONLY

Table 36. TX_LPF Register 18 (Address = 10010)
0
1
0
1
1
0
0
1
1
0
1
BAND I TXH ONLY
0
1
0
1
1
0
0
1
1
0
1
BAND V TXL ONLY
BAND VIII TXL

0
1
0
1
1
0
0
1
1
0
1
ONLY
BAND I RX1/TXH
0
1
0
1
1
0
0
1
1
0
1
FDD
BAND V RX3/TXL
0
1
0
1
1
0
0
1
1
0
1
FDD
BAND VIII RX3/TXL
0
1
0
1
1
0
0
1
1
0
1
FDD
0
1
0
1
1
0
0
1
1
0
1
BAND I RX IDLE
0
1
0
1
1
0
0
1
1
0
1
BAND I TX IDLE
0
1
0
1
1
0
0
1
1
0
1
AFC ONLY
REFERENCE
0
1
0
1
1
0
0
1
1
0
1
BUFFER
0
1
0
1
1
0
0
1
1
0
1
SLEEP
MAX2550
83
MAX2550
Table 36. TX_LPF Register 18 (Address = 10010) (continued)
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
13 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
14 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
16 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
17 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reserved
Reserved
18 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
21 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
23 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TXINDACF
Bandwidth
1 = 15MHz
Bandwidth
Tx DAC
Select
25 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Tx DAC
Maxim Integrated 84
MAX2550
Table 37. TX_PAD Register 19 (Address = 10011)
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
<1:0> = 01 = Do not use
<1:0> = 11 = Do not use
0 0 1 1 0 0 1 1 1 1 0 0 1 0 0 1 1 1 1 1
Frequency Band
<1:0> = 00 = CELL
PAD_BAND
<1:0> = 10 = PCS
PA Driver
<2:0>
1 1 1 1 0 0 1 1 1 1 0 0 1 0 0 1 1 1 1 1
2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Frequency Select
PA Driver Center
CELL = 00100
PCS = 10001
PAD_CTUNE
3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
<4:0>
4 2 0 0 1 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0
5 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
11 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
14 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reserved
Reserved
16 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
—
17 10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
18 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 85
MAX2550
Table 38. TX_UPX1 Register 20 (Address = 10100)
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reserved
Reserved
9 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
13 13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
14 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
16 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
17 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TXLO IQ Phase
0 = PCS bands
1 = CELL band
Adjust Slope
TXLO_IQ_
GAIN
19 0 0 0 1 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0
20 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reserved
Reserved
21 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
22 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Master Bias
0 = Disable
1 = Enable
BIAS_EN
Enable
24 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
Reserved
Reserved
25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
Maxim Integrated 86
MAX2550
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 0 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
UCX Tank Frequency
UCX_CSW
3 1 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0
Adjust
<3:0>
1101 = CELL
0000 = PCS
4 2 0 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0
5 3 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
13 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
15 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
—
16 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
21 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Maxim Integrated 87
MAX2550
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
7 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
9 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
11 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
12 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 17 1 1 0 0 1 1 1 1 0 0 1 0 0 1 1 1 1 1
18 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19 19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
20 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
<1:0> = 01 = CELL band
<1:0> = 00 = Do not use
<1:0> = 10 = Do not use

<1:0> = 11 = PCS band
T_UCX_BAND_SEL
22 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Upconverter
Band Select
<1:0>
23 1 1 1 0 0 1 1 1 1 0 0 1 0 0 1 1 1 1 1
<1:0> = 00 = Do not use
<1:0> = 10 = Do not use

<1:0> = 11 = Do not use
<1:0> = 01 = WCDMA
UCX_V2I_MODE_F
Upconverter V2I
24 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bandwidth
<1:0>
25 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 88
MAX2550
Table 41. TX_GAIN1 Register 23 (Address = 10111)
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX5 ONLY
BAND1 RX1 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3FF (hex) = Maximum gain
000 (hex) = Minimum gain
TX_GAIN
Tx Gain
4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
<9:0>
5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
7 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
9 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
12 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reserved
Reserved
16 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
17 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
22 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Low-Z high
Low-Z low
GPO1 Output Select
24 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
High-Z
High-Z
GPO1<1:0>
=
=
=
=
00
01
10
11
=
=
=
=
25 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
<1:0>
<1:0>
<1:0>
<1:0>
Maxim Integrated 89
0
7
6
1
8
2
9
3
12
10
11
BIT
TXINDACI
TXINDACZI Reserved BIT ID
<5:0>
TXBB Differential
TXBB DAC Bias Current Reserved NAME
Maxim Integrated
Input Impedance
0 = 220I TXBB DAC Bias Current

— DEFINITION
1 = 100I 010100 = WCDMA
0
0
5
0
1
1
2
2
3
3
4
4
5
BIT
1
0
0
0
0
1
1
0
0
0
1
0
0
BAND I RX1 ONLY
1
0
0
0
0
1
1
0
0
0
1
0
0
DCS RX2 ONLY
1
0
0
0
0
1
1
0
0
0
1
0
0
BAND V RX3 ONLY
BAND VIII RX3
1
0
0
0
0
1
1
0
0
0
1
0
0
ONLY
1
0
0
0
0
1
1
0
0
0
1
0
0
BAND V RX4 ONLY
BAND VIII RX4
1
0
0
0
0
1
1
0
0
0
1
0
0
ONLY
1
0
0
0
0
1
1
0
0
0
1
0
0
BAND I RX5 ONLY
1
0
0
0
0
1
1
0
0
0
1
0
BAND I TXH ONLY
Table 42. TX_GAIN2 Register 24 (Address = 11000)
1
0
0
0
0
1
1
0
0
0
1
0
BAND V TXL ONLY
BAND VIII TXL
1
0
0
0
0
1
1
0
0
0
1
0
ONLY
BAND I RX1/TXH
1
0
0
0
0
1
1
0
0
0
1
0
FDD
BAND V RX3/TXL
1
0
0
0
0
1
1
0
0
0
1
0
FDD
BAND VIII RX3/TXL
1
0
0
0
0
1
1
0
0
0
1
0
FDD
1
0
0
0
0
1
1
0
0
0
1
0
BAND I RX IDLE
1
0
0
0
0
1
1
0
0
0
1
0
BAND I TX IDLE
0
1
0
0
0
0
1
1
0
0
0
1
0
AFC ONLY
REFERENCE
0
1
0
0
0
0
1
1
0
0
0
1
0
BUFFER
0
1
0
0
0
0
1
1
0
0
0
1
0
SLEEP
MAX2550
90
13
20
19
14
15
16
17
24 21
18
25 23 22 BIT
TXBB_LVDS_
Reserved Reserved CDR_EN Reserved BIT ID
DDR3
TXBB Input
Reserved Reserved CDR Enable Reserved NAME
Maxim Integrated
LVDS/DDR3 Select
TXBB Input LVDS/DDR3 Select CDR Enable

— 0 = LVDS — 0 = Disable — DEFINITION
1 = DDR3 1 = Enable
0
0
0
1
1
4
3 2 1 0 0 BIT
1
0
0
1
0
0
0 0 0 0 0 BAND I RX1 ONLY
1
0
0
1
0
0
0 0 0 0 0 DCS RX2 ONLY
1
0
0
1
0
0
0 0 0 0 0 BAND V RX3 ONLY
BAND VIII RX3
1
0
0
1
0
0
0 0 0 0 0
ONLY
1
0
0
1
0
0
0 0 0 0 0 BAND V RX4 ONLY
BAND VIII RX4
1
0
0
1
0
0
0 0 0 0 0
ONLY
1
0
0
1
0
0
0 0 0 0 0 BAND I RX5 ONLY
1
1
0
1
0
0
0 0 0 0 0 BAND I TXH ONLY
1
1
0
1
0
0 0 0 0 0 BAND V TXL ONLY
BAND VIII TXL
1
1
0
1
0
0 0 0 0 0
ONLY
BAND I RX1/TXH
1
1
0
1
0
0 0 0 0 0
FDD
Table 42. TX_GAIN2 Register 24 (Address = 11000) (continued)
BAND V RX3/TXL
1
1
0
1
0
0 0 0 0 0
FDD
BAND VIII RX3/TXL
1
1
0
1
0
0 0 0 0 0
FDD
1
0
0
1
0
0 0 0 0 0 BAND I RX IDLE
1
0
0
1
0
0 0 0 0 0 BAND I TX IDLE
1
0
0
1
0
0 0 0 0 0 AFC ONLY
REFERENCE
1
0
0
1
0
0 0 0 0 0
BUFFER
1
0
0
1
0
0 0 0 0 0 SLEEP
MAX2550
91
MAX2550
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
12 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
13 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 92
MAX2550
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
7 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
12 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
13 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19 19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
20 20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
21 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 93
MAX2550
Table 45. TXLO_FRAC Register 27 (Address = 11011)
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 1
1 1 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
2 2 1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 1
3 3 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
4 4 1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 1
5 5 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
6 6 1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 1
Tx RF PLL Fractional Divide Ratio
AAAAB (hex) = CELL band
7 7 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
36AAB (hex) = PCS band
8 8 1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 1
9 9 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
<19:0>
TFRAC
10 10 1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 1
11 11 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
12 12 1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 1
13 13 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
14 14 1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 1
15 15 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
16 16 1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 1
17 17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
18 18 1 1 0 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1
19 19 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0
20 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
21 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
22 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
23 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Maxim Integrated 94
5
0
9
6
1
7
2
8
3
12
13
10
11
BIT
TVCO_DIV2
Reserved TRD TINT<7:0> BIT ID
<1:0>
Tx RF VCO Prescaler Divide Tx Reference
Reserved Tx RF PLL Integer Divide Ratio NAME
Ratio Configuration Divide Ratio
Maxim Integrated
<1:0> = 01 = CELL 0 = Divide-by-1 5B (hex) = CELL
— DEFINITION
<1:0> = 10 = PCS 1 = Divide-by-2 66 (hex) = PCS
0
0
0
5
0
1
1
6
1
2
7
2
4
BIT
0
1
0
1
1
1
1
1
1
1
0
1
0
BAND I RX1 ONLY
0
1
0
1
1
1
1
1
1
1
0
1
0
DCS RX2 ONLY
1
1
0
0
1
0
1
1
1
1
0
0
1
BAND V RX3 ONLY
BAND VIII RX3
1
1
0
1
1
0
1
1
0
1
0
0
0
ONLY
0
1
1
0
0
1
1
1
1
1
0
0
1
BAND V RX4 ONLY
BAND VIII RX4
0
1
1
0
1
1
1
1
1
0
0
0
0
ONLY
0
1
1
0
1
1
1
1
1
1
0
1
0
BAND I RX5 ONLY
0
1
1
0
1
1
1
1
1
1
0
1
0
BAND I TXH ONLY
Table 46. TXLO_SYN Register 28 (Address = 11100)
1
1
1
0
0
1
0
1
1
1
0
0
BAND V TXL ONLY
BAND VIII TXL
1
1
1
0
1
1
0
1
1
0
0
0
ONLY
BAND I RX1/TXH
0
1
1
0
1
1
1
1
1
1
0
1
FDD
BAND V RX3/TXL
1
1
1
0
0
1
0
1
1
1
0
0
FDD
BAND VIII RX3/TXL
1
1
1
0
1
1
0
1
1
0
0
0
FDD
0
1
1
0
1
1
1
1
1
1
0
1
BAND I RX IDLE
0
1
1
0
1
1
1
1
1
1
0
1
BAND I TX IDLE
0
1
1
0
1
1
1
1
1
1
0
1
AFC ONLY
REFERENCE
0
1
1
0
1
1
1
1
1
1
0
1
BUFFER
0
1
1
0
1
1
1
1
1
1
0
1
SLEEP
MAX2550
95
14
25
22
19
17
15
23
20
18
16
24
21
BIT
TVCO_SEL
Reserved TCPI<2:0> Reserved BIT ID
<1:0>
Tx RF PLL Charge
Reserved Reserved Tx RF VCO Selection NAME
Pump Current
Maxim Integrated
000 = 0FA,
001 = 200FA <1:0> = 00 = Disable
... <1:0> = 01 = ROL
— — DEFINITION
100 = 800FA <1:0> = 10 = ROH
... <1:0> = 11 = Not used
110 = 1200FA
0
0
0
0
4
1
1
1
1
2
2
3
BIT
1
0
0
1
0
0
0
0
1
1
1
1
BAND I RX1 ONLY
1
0
0
1
0
0
0
0
1
1
1
1
DCS RX2 ONLY
1
0
0
1
0
0
0
0
0
1
1
1
BAND V RX3 ONLY
BAND VIII RX3
1
0
1
0
0
0
0
0
1
1
1
1
ONLY
1
0
0
1
0
0
0
0
1
1
1
1
BAND V RX4 ONLY
BAND VIII RX4
1
1
0
0
1
0
0
0
0
1
1
1
ONLY
1
1
0
0
1
0
0
0
0
1
1
1
BAND I RX5 ONLY
1
1
0
0
1
0
0
0
0
1
1
1
BAND I TXH ONLY
1
1
0
0
1
0
0
0
0
0
1
1
BAND V TXL ONLY
BAND VIII TXL
1
1
0
1
0
0
0
0
0
1
1
1
ONLY
BAND I RX1/TXH
1
1
0
0
1
0
0
0
0
1
1
1
FDD
Table 46. TXLO_SYN Register 28 (Address = 11100) (continued)
BAND V RX3/TXL
1
1
0
0
1
0
0
0
0
0
1
1
FDD
BAND VIII RX3/TXL
1
1
0
1
0
0
0
0
0
1
1
1
FDD
1
1
0
0
1
0
0
0
0
1
1
1
BAND I RX IDLE
1
1
0
0
1
0
0
0
0
1
1
1
BAND I TX IDLE
1
1
0
0
1
0
0
0
0
1
1
1
AFC ONLY
REFERENCE
1
1
0
0
1
0
0
0
0
1
1
1
BUFFER
1
1
0
0
1
0
0
0
0
1
1
1
SLEEP
MAX2550
96
5
9
4
8
3
7
2
6
1
0
11
10
13
12
BIT
REFIN_ENOUT2 REFIN_ENOUT1 Reserved BIT ID
Reference Tx PLL Reference Rx PLL

Reserved NAME
Output Enable Output Enable
Maxim Integrated
Reference for Tx Reference for Rx
PLL Enable PLL Enable
— DEFINITION
0 = Disable 0 = Disable
1 = Enable 1 = Enable
9
4
8
3
7
2
6
1
0
0
5
0
11
10
BIT
0
0
1
0
1
0
0
1
0
1
1
1
0
1
BAND I RX1 ONLY
0
0
1
0
1
0
0
1
0
1
1
1
0
1
DCS RX2 ONLY
0
0
1
0
1
0
0
1
0
1
1
1
0
1
BAND V RX3 ONLY
BAND VIII RX3
0
0
1
0
1
0
0
1
0
1
1
1
0
1
ONLY
0
0
1
0
1
0
0
1
0
1
1
1
0
1
BAND V RX4 ONLY
BAND VIII RX4
0
0
1
0
1
0
0
1
0
1
1
1
0
1
ONLY
0
0
1
0
1
0
0
1
0
1
1
1
0
1
BAND I RX5 ONLY
0
0
1
0
1
0
0
1
0
1
1
1
0
1
BAND I TXH ONLY

Table 47. TXLO_REF Register 29 (Address = 11101)
0
0
1
0
1
0
0
1
0
1
1
1
0
1
BAND V TXL ONLY
BAND VIII TXL
0
0
1
0
1
0
0
1
0
1
1
1
0
1
ONLY
BAND I RX1/TXH
0
0
1
0
1
0
0
1
0
1
1
1
0
1
FDD
BAND V RX3/TXL
0
0
1
0
1
0
0
1
0
1
1
1
0
1
FDD
BAND VIII RX3/TXL
0
0
1
0
1
0
0
1
0
1
1
1
0
1
FDD
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0 BAND I RX IDLE
1
0
1
0
0
1
0
1
1
1
0
1
0 BAND I TX IDLE
0
1
0
1
0
0
1
0
1
0
0
0
1
AFC ONLY
REFERENCE
0
1
0
1
0
0
1
0
1
0
0
0
1
BUFFER
0
1
0
1
0
0
1
0
1
0
0
0
1
SLEEP
MAX2550
97
18
21
23
17
20
24
22
16
15
25
19
14
BIT
REFOUT_LV_ REFOUT_
Reserved Reserved REFIN_ENOUT3 BIT ID
CMOS_SEL DRV<1:0>
REFOUT Output
Reserved REFOUT Buffer Drive Strength Reserved REFOUT Enable NAME
Driver Select
Maxim Integrated
REFOUT Drive Strength
00 = 1x REFOUT Enable
0 = CMOS
— 01 = 2x — 0 = Disable DEFINITION
1 = Low voltage
10 = 3x 1 = Enable
11 = 4x
3
2
1
1
1
4
0
0
0
0
0
BIT
1
0
1
0
0
0
0
0
1
0
1
BAND I RX1 ONLY
1
0
1
0
0
0
0
0
1
0
1
DCS RX2 ONLY
1
0
1
0
0
0
0
0
1
0
1
BAND V RX3 ONLY
BAND VIII RX3
1
0
1
0
0
0
0
0
1
0
1
ONLY
1
0
1
0
0
0
0
0
1
0
1
BAND V RX4 ONLY
BAND VIII RX4
1
0
1
0
0
0
0
0
1
0
1
ONLY
1
0
1
0
0
0
0
0
1
0
1
BAND I RX5 ONLY
1
0
1
0
0
0
0
0
1
0
1
BAND I TXH ONLY
1
0
1
0
0
0
0
0
1
0
1
BAND V TXL ONLY
1 BAND VIII TXL

0
1
0
0
0
0
0
1
0
1
ONLY
BAND I RX1/TXH
1
0
1
0
0
0
0
1
0
1
0
FDD
Table 47. TXLO_REF Register 29 (Address = 11101) (continued)
BAND V RX3/TXL
1
0
1
0
0
0
0
1
0
1
0
FDD
BAND VIII RX3/TXL
1
0
1
0
0
0
0
1
0
1
0
FDD
1
0
1
0
0
0
0
1
0
1
0
BAND I RX IDLE
0
1
0
0
0
0
1
0
1
0
1
BAND I TX IDLE
0
1
0
0
0
0
1
0
0
0
1
AFC ONLY
REFERENCE
0
1
0
0
0
0
1
0
1
0
1
BUFFER
0
1
0
0
0
0
1
0
0
0
1
SLEEP
MAX2550
98
MAX2550
Table 48. TXLO_AFCDAC Register 30 (Address = 11110)
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
NAME
BIT ID
ONLY
ONLY
ONLY
80BIT
FDD
FDD
FDD
BIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VAFCOUT = 0.4 + (2.5 - 0.4) x AFCDAC/212
2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AFCDAC Output Voltage
4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AFCDAC
5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
<11:0>
6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
800 (hex)
10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
15 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
16 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AFCDAC_EN
AFCDAC
0 = Disable
1 = Enable
Enable
19 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
22 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
23 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 99
MAX2550
BAND V RX3 ONLY
BAND V RX4 ONLY
BAND V TXL ONLY
BAND VIII RX3/TXL

BAND I TXH ONLY
BAND I RX1 ONLY
BAND I RX5 ONLY
BAND V RX3/TXL
BAND I RX1/TXH
BAND I RX IDLE
BAND I TX IDLE
DCS RX2 ONLY
BAND VIII RX3
BAND VIII RX4
BAND VIII TXL
REFERENCE
DEFINITION
AFC ONLY
BUFFER
SLEEP
BIT ID
ONLY
ONLY
ONLY
FDD
FDD
FDD
BIT
BIT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Reserved
12 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
—
13 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
18 18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19 19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
20 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
21 21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
22 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Maxim Integrated 100

MAX2550
Applications Information on all high-frequency traces. The exposed pad must be
soldered evenly to the board’s ground plane for proper
Layout Considerations operation. Use abundant ground vias between RF traces
The EV kit and reference design serve as a guide for to minimize undesired coupling. Bypass each VCC_ pin
PCB layout. Keep RF signal lines as short as possible to to ground with capacitors placed as close as possible
minimize losses and radiation. Use controlled impedance to the pin.
Simplified Block Diagram
OPTIONAL FILTERS
LNAOUTL MIXINL LNAOUTH MIXINH

3RD-PARTY BROADBAND
RXIN4
MAX2550
1 2
ADC
DECIMATION Rx
MULTIMODE ADC
FILTER PROCESSING
RXIN1 Q 2
ADC
RXIN5 /2, /4
FRAC-N R/W
SPI SPI
PLL
RXIN2
FRAC-N GPO3
PA PA PLL (LOCK DETECT
TXOUTH /2, /4 WCDMA
1930MHz I DATA
TO 1995MHz 1 2 CD MOD
DAC
TX I
Tx
TXOUTL PROCESSING
Q Q DATA
865MHz 2 CD MOD
DAC
TO 894MHz TX Q
Ordering Information Package Information

For the latest package outline information and land patterns
TEMP PIN-
PART BAND (footprints), go to www.maxim-ic.com/packages. Note that a
RANGE PACKAGE
“+”, “#”, or “-” in the package code indicates RoHS status only.
I, V, and -40NC to Package drawings may show a different suffix character, but
MAX2550ETN+ 56 TQFN-EP*
VIII +85NC the drawing pertains to the package regardless of RoHS status.
+Denotes a lead(Pb)-free/RoHS-compliant package. PACKAGE PACKAGE OUTLINE LAND
*EP = Exposed pad. TYPE CODE NO. PATTERN NO.
56 TQFN-EP T5677+2 21-0144 90-0043
Maxim Integrated 101

MAX2550
Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 7/12 Initial release —
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 102
© Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.

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EVALUATION KIT AVAILABLE

Pin Configurations appear at end of data sheet.

PACKAGE THERMAL CHARACTERISTICS (Note 1)

SPEC NO. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Band I Duplexer Specifications

Antenna—Uplink Port (Applies to Uplink WCDMA Rx Mode on RXIN1)

Band I Uplink WCDMA Rx Mode on RXIN1 (Full Duplex)

Band I Uplink WCDMA Rx Mode on RXIN1 (Full Duplex) (continued)

Tx on -27dBm, LNA gain high, PGA gain

Tx on -27dBm, LNA gain high, PGA gain

Band I Uplink WCDMA Rx Mode on RXIN1 (Full Duplex) (continued)

LNA high gain; PGA gain register set to 6;

LNA mid gain; PGA gain register set to 9;

Antenna—Downlink Port (Applies to Downlink WCDMA Rx Mode on RXIN5)

Band I Downlink WCDMA Rx Mode on RXIN5 (Monitor)

LNA gain high; PGA gain register set to 11;

LNA gain medium, PGA gain register set to 6;

Band I Downlink WCDMA Rx Mode on RXIN5 (Monitor) (continued)

LNA gain low; PGA gain register set to 0; tested

DCS Band Rx Mode on RXIN2

DCS Band Rx Mode on RXIN2

LNA gain high, PGA gain register set to 12;

EGSM/WCDMA Band Rx Mode on RXIN4

Assumed External Front-End Filtering Characteristics Between Antenna and LNA:

EGSM/WCDMA Band Rx Mode on RXIN4

LNA gain high, PGA gain register set to 12;

Band V Duplexer Specifications

Antenna—Uplink Port (Applies to Uplink WCDMA Rx Mode on RXIN3)

Band V Uplink WCDMA Rx Mode on RXIN3 (Full Duplex)

Tx on at -27dBm; LNA gain high; PGA gain register

Tx on at -27dBm; LNA gain high; PGA gain

Band V Uplink WCDMA Rx Mode on RXIN3 (Full Duplex) (continued)

Band V Uplink WCDMA Rx Mode on RXIN3 (Full Duplex) (continued)

Antenna—Downlink Port (Applies to Downlink WCDMA Rx Mode on RXIN4)

Band V Downlink WCDMA Rx Mode on RXIN4 (Monitor)

Band V Downlink WCDMA Rx Mode on RXIN4 (Monitor) (continued)

LNA gain high; PGA gain register set to 11;

LNA gain low; PGA gain register set to 0; tested

Band VIII Duplexer Specifications

Antenna—Uplink Port (Applies to Uplink WCDMA Rx Mode on RXIN3)

Band VIII Uplink WCDMA Rx Mode on RXIN3 (Full Duplex)

Tx on at -27dBm; LNA gain high; PGA gain register

Tx on at -27dBm; LNA gain high; PGA gain

Band VIII Uplink WCDMA Rx Mode on RXIN3 (Full Duplex) (continued)

Band VIII Uplink WCDMA Rx Mode on RXIN3 (Full Duplex) (continued)

Antenna—Downlink Port (Applies to Downlink WCDMA Rx Mode on RXIN4)

Band VIII Downlink WCDMA Rx Mode on RXIN4 (Monitor)

LNA gain high, PGA gain register set to 11,

LNA gain high; PGA gain register set to 11;

Band VIII Downlink WCDMA Rx Mode on RXIN4 (Monitor) (continued)

LNA gain high; PGA gain register set to 11;

LNA gain low; PGA gain register set to 0; tested

SPEC NO. PARAMETER CONDITIONS MIN TYP MAX UNITS

Five calibration points over the power control

SPEC NO. PARAMETER CONDITIONS MIN TYP MAX UNITS

SPEC NO. PARAMETER CONDITIONS MIN TYP MAX UNITS

Any code within 0.5V to 2.5V output level, 100Hz

Typical Operating Characteristics

84 TA = +25°C TA = +85°C -118

BAND5 UPLINK Rx BAND8 UPLINK Rx BAND5 DOWNLINK Rx

BAND1 DOWNLINK Rx DCS Rx

GSM Rx Rx BAND1 Rx BAND5

TA = +85°C LNA GAIN = HIGH TA = +85°C

30.2 30.6 TA = +25°C