AMC1306x Small, High-Precision, Reinforced Isolated Delta-Sigma Modulators With High CMTI

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AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

SBAS734C – MARCH 2017 – REVISED JANAURY 2020
AMC1306x Small, High-Precision,

Reinforced Isolated Delta-Sigma Modulators With High CMTI
1 Features 3 Description
1• Pin-compatible family optimized for shunt-resistor- The AMC1306 is a precision, delta-sigma (ΔΣ)
based current measurements: modulator with the output separated from the input
circuitry by a capacitive double isolation barrier that is
– ±50-mV or ±250-mV input voltage ranges highly resistant to magnetic interference. This barrier
– Manchester coded or uncoded bitstream is certified to provide reinforced isolation of up to
options 7000 VPEAK according to the DIN VDE V 0884-11 and
• Excellent DC performance: UL1577 standards. Used in conjunction with isolated
power supplies, this isolated modulator separates
– Offset error: ±50 µV or ±100 µV (max) parts of the system that operate on different common-
– Offset drift: 1 µV/°C (max) mode voltage levels and protects lower-voltage parts
– Gain error: ±0.2% (max) from damage.
– Gain drift: ±40 ppm/°C (max) The input of the AMC1306 is optimized for direct
• Transient immunity: 100 kV/µs (typ) connection to shunt resistors or other low voltage-
level signal sources. The unique low input voltage
• System-level diagnostic features range of the ±50-mV device allows significant
• Safety-related certifications: reduction of the power dissipation through the shunt
– 7000-VPEAK reinforced isolation per DIN VDE V and supports excellent ac and dc performance. The
0884-11: 2017-01 output bitstream of the AMC1306 is Manchester
coded (AMC1306Ex) or uncoded (AMC1306Mx),
– 5000-VRMS isolation for 1 minute per UL1577 depending on the derivate. By using an integrated
– CAN/CSA no. 5A-component acceptance digital filter (such as those in the TMS320F2807x or
service notice and IEC 62368-1 end equipment TMS320F2837x microcontroller families) to decimate
standard the bitstream, the device can achieve 16 bits of
• Fully specified over the extended industrial resolution with a dynamic range of 85 dB at a data
rate of 78 kSPS.
temperature range: –40°C to +125°C
The bitstream output of the Manchester coded
2 Applications AMC1306Ex versions support single-wire data and
clock transfer without having to consider the setup
• Shunt-resistor-based current sensing and isolated and hold time requirements of the receiving device.
voltage measurements in:
– Industrial motor drives Device Information(1)
– Photovoltaic inverters PART NUMBER PACKAGE BODY SIZE (NOM)
– Uninterruptible power supplies AMC1306x SOIC (8) 5.85 mm × 7.50 mm

(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Floating
Power Supply
HV+
AMC1306Mx
3.3 V or 5.0 V
AVDD DVDD 3.0 V, 3.3 V, or 5.0 V
Reinforced Isolation
AGND DGND TMS320F28x7x

RSHUNT Optional
To Load AINN DOUT SD-Dx
Optional Optional
AINP CLKIN SD-Cx
PWMx
HV-
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SBAS734C – MARCH 2017 – REVISED JANAURY 2020 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.1 Overview ................................................................. 21
2 Applications ........................................................... 1 8.2 Functional Block Diagram ....................................... 21
3 Description ............................................................. 1 8.3 Feature Description................................................. 22
8.4 Device Functional Modes........................................ 26
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 4 9 Application and Implementation ........................ 27
9.1 Application Information............................................ 27
6 Pin Configuration and Functions ......................... 4
9.2 Typical Applications ................................................ 28
7 Specifications......................................................... 5
10 Power Supply Recommendations ..................... 33
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5 11 Layout................................................................... 34
11.1 Layout Guidelines ................................................. 34
7.3 Recommended Operating Conditions....................... 5
11.2 Layout Example .................................................... 34
7.4 Thermal Information .................................................. 5
7.5 Power Ratings........................................................... 5 12 Device and Documentation Support ................. 35
7.6 Insulation Specifications............................................ 6 12.1 Device Support...................................................... 35
7.7 Safety-Related Certifications..................................... 7 12.2 Documentation Support ........................................ 35
7.8 Safety Limiting Values .............................................. 7 12.3 Related Links ........................................................ 35
7.9 Electrical Characteristics: AMC1306x05 ................... 8 12.4 Receiving Notification of Documentation Updates 35
7.10 Electrical Characteristics: AMC1306x25 ............... 10 12.5 Community Resources.......................................... 35
7.11 Switching Characteristics ...................................... 12 12.6 Trademarks ........................................................... 35
7.12 Insulation Characteristics Curves ......................... 13 12.7 Electrostatic Discharge Caution ............................ 35
7.13 Typical Characteristics .......................................... 14 12.8 Glossary ................................................................ 36
8 Detailed Description ............................................ 21 13 Mechanical, Packaging, and Orderable
Information ........................................................... 36
4 Revision History
Changes from Revision B (June 2018) to Revision C Page
• Changed Safety-related certifications bullet in Features section: changed VDE certification revision from DIN V VDE
V 0884-10 (VDE V 0884-11) to DIN VDE V 0884-11 and changed IEC 60950-1, and IEC 60065 to IEC 62368-1 .............. 1
• Changed DIN V VDE V to DIN VDE V in Description section................................................................................................ 1
• Changed CLR and CPG values from ≥ 9 mm to ≥ 8.5 mm in Insulation Specifications table ............................................... 6
• Changed Insulation Specifications table header row from DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01 to DIN
VDE V 0884-11: 2017-01 ....................................................................................................................................................... 6
• Changed VDE certification details in Safety-Related Certifications table............................................................................... 7
• Changed Safety Limiting Values table format as per current standard.................................................................................. 7
• Changed free air to ambient in condition statement of Switching Characteristics table ...................................................... 12
• Changed 6.05 dB to 6.02 dB in Equation 3.......................................................................................................................... 27
• Changed input common-mode voltage from 2 V to 1.9 V for consistency with Input Bias Current vs Common-Mode
Input Voltage figure in What To Do and What Not To Do section........................................................................................ 32
• Changed VINx to AINx in Layout Guidelines section ........................................................................................................... 34
• Changed Recommended Layout of the AMC1306x figure to include connection to the shunt resistor and input filter
components .......................................................................................................................................................................... 34
Changes from Revision A (July 2017) to Revision B Page
• Changed Reinforced Isolation Capacitor Lifetime Projection figure .................................................................................... 13
2 Submit Documentation Feedback Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25

www.ti.com SBAS734C – MARCH 2017 – REVISED JANAURY 2020
Changes from Original (March 2017) to Revision A Page
• Released AMC1306E05 and AMC1306M05 to production .................................................................................................... 1

• Added ±50 µV to first DC Performance sub-bullet to reflect the AMC1306x05 devices ........................................................ 1
• Changed standard deviation from 0884-10 to 0884-11 in first Safety-Related Certifications sub-bullet................................ 1
• Changed VPEAK from 8000 to 7000 and standard deviation from 0884-10 to 0884-11 in first paragraph of Description
section ................................................................................................................................................................................... 1
• Deleted Status column from Device Comparison Table......................................................................................................... 4
• Changed standard deviation from 0884-10 to 0884-11 in DIN V VDE V 0884-11 section of Insulation Specifications table 6
• Changed standard deviation from 0884-10 to 0884-11 in Safety-Related Certifications table .............................................. 7
• Changed prevent to minimize in condition statement of Safety Limiting Values table........................................................... 7
• Added Electrical Characteristics: AMC1306x05 table ........................................................................................................... 8
• Changed test conditions of Analog Inputs test conditions from (AINP – AINN) / 2 to AGND to (AINP + AINN) / 2 to
AGND to include all possible conditions............................................................................................................................... 10
• Changed IIB test condition from Inputs shorted to AGND to AINP = AINN = AGND, IIB = IIBP + IIBN .................................... 10
• Added AINP = AINN = AGND to EO parameter test conditions .......................................................................................... 10
• Changed minus sign to plus or minus sign in typical specification of EG parameter ........................................................... 10
• Changed 10% to 90% to 90% to 10% in test conditions of tf parameter ............................................................................ 12
• Added AMC1306x05 devices to Typical Characteristics section ........................................................................................ 14
Copyright © 2017–2020, Texas Instruments Incorporated Submit Documentation Feedback 3

5 Device Comparison Table
DIFFERENTIAL INPUT
PART NUMBER INPUT VOLTAGE RANGE DIGITAL OUTPUT INTERFACE
RESISTANCE
AMC1306E05 ±50 mV 4.9 kΩ Manchester coded CMOS
AMC1306E25 ±250 mV 22 kΩ Manchester coded CMOS
AMC1306M05 ±50 mV 4.9 kΩ Uncoded CMOS
AMC1306M25 ±250 mV 22 kΩ Uncoded CMOS
6 Pin Configuration and Functions
DWV Package
8-Pin SOIC
Top View
AVDD 1 8 DVDD
AINP 2 7 CLKIN
AINN 3 6 DOUT
AGND 4 5 DGND
Not to scale
Pin Functions
PIN
I/O
NO. NAME DESCRIPTION
Analog (high-side) power supply, 3.0 V to 5.5 V.
1 AVDD —
See the Power Supply Recommendations section for decoupling recommendations.
2 AINP I Noninverting analog input
3 AINN I Inverting analog input
4 AGND — Analog (high-side) ground reference
5 DGND — Digital (controller-side) ground reference
6 DOUT O Modulator data output. This pin is a Manchester coded output for AMC1306Ex derivates.
7 CLKIN I Modulator clock input: 5 MHz to 21 MHz (5-V operation) with internal pulldown resistor (typical value: 1.5 MΩ)
Digital (controller-side) power supply, 2.7 V to 5.5 V.
8 DVDD —
See the Power Supply Recommendations section for decoupling recommendations.

7 Specifications
7.1 Absolute Maximum Ratings (1)
MIN MAX UNIT
Supply voltage AVDD to AGND or DVDD to DGND –0.3 6.5 V
Analog input voltage at AINP, AINN AGND – 6 AVDD + 0.5 V
Digital input or output voltage at CLKIN or DOUT DGND – 0.5 DVDD + 0.5 V
Input current to any pin except supply pins –10 10 mA
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD Analog (high-side) supply voltage (AVDD to AGND) 3.0 5.0 5.5 V
DVDD Digital (controller-side) supply voltage (DVDD to DGND) 2.7 3.3 5.5 V
TA Operating ambient temperature –40 125 °C
7.4 Thermal Information

AMC1306x
(1)
THERMAL METRIC DWV (SOIC) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 112.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 47.6 °C/W
RθJB Junction-to-board thermal resistance 60.0 °C/W
ψJT Junction-to-top characterization parameter 23.1 °C/W
ψJB Junction-to-board characterization parameter 60.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Maximum power dissipation AMC1306Ex, AVDD = DVDD = 5.5 V 91.85
PD mW
(both sides) AMC1306Mx, AVDD = DVDD = 5.5 V 86.90
Maximum power dissipation
PD1 AVDD = 5.5 V 53.90 mW
(high-side supply)
Maximum power dissipation AMC1306Ex, DVDD = 5.5 V 37.95
PD2 mW
(low-side supply) AMC1306Mx, DVDD = 5.5 V 33.00

7.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance (1) Shortest pin-to-pin distance through air ≥ 8.5 mm
CPG External creepage (1) Shortest pin-to-pin distance across the package surface ≥ 8.5 mm
Minimum internal gap (internal clearance) of the double insulation
DTI Distance through insulation ≥ 0.021 mm
(2 × 0.0105 mm)
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V
Material group According to IEC 60664-1 I
Rated mains voltage ≤ 300 VRMS I-IV
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 VRMS I-IV
Rated mains voltage ≤ 1000 VRMS I-III
DIN VDE V 0884-11: 2017-01 (2)
Maximum repetitive peak isolation
VIORM At ac voltage (bipolar) 2121 VPK
voltage
Maximum-rated isolation working At ac voltage (sine wave) 1500 VRMS
VIOWM
voltage At dc voltage 2121 VDC
VTEST = VIOTM, t = 60 s (qualification test) 7000
VIOTM Maximum transient isolation voltage VPK
VTEST = 1.2 × VIOTM, t = 1 s (100% production test) 8400
Test method per IEC 60065, 1.2/50-μs waveform,
VIOSM Maximum surge isolation voltage (3) 8000 VPK
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
Method a, after input/output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s, ≤5
Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s
Method a, after environmental tests subgroup 1,
qpd Apparent charge (4) Vini = VIOTM, tini = 60 s, ≤5 pC
Method b1, at routine test (100% production) and preconditioning
(type test), Vini = VIOTM, tini = 1 s, ≤5
CIO Barrier capacitance, input to output (5) VIO = 0.5 VPP at 1 MHz ~1 pF
VIO = 500 V at TA = 25°C > 1012
RIO Insulation resistance, input to output (5) VIO = 500 V at 100°C ≤ TA ≤ 125°C > 1011 Ω
VIO = 500 V at TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL1577
VTEST = VISO = 5000 VRMS or 7000 VDC, t = 60 s (qualification),
VISO Withstand isolation voltage 5000 VRMS
VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test)
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves and ribs on the PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.

7.7 Safety-Related Certifications

VDE UL
Certified according to DIN VDE V 0884-11: 2017-01, DIN EN Recognized under 1577 component recognition and
62368-1: 2016-05, EN 62368-1: 2014, and IEC 62368-1: 2014 CSA component acceptance NO 5 programs
Reinforced insulation Single protection
File number: DIN 40040142 File number: E181974
7.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
RθJA = 112.2°C/W, AVDD = DVDD = 5.5 V,
202.5
TJ = 150°C, TA = 25°C
IS Safety input, output, or supply current mA
RθJA = 112.2°C/W, AVDD = DVDD = 3.6 V,
309.4
TJ = 150°C, TA = 25°C
PS Safety input, output, or total power RθJA = 112.2°C/W, TJ = 150°C, TA = 25°C 1114 (1) mW
TS Maximum safety temperature 150 °C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × AVDDmax + IS × AVDDmax, where AVDDmax is the maximum high-side supply voltage and DVDDmax is the maximum controller-
side supply voltage.

7.9 Electrical Characteristics: AMC1306x05

minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,
AINP = –50 mV to 50 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are
at TA = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
ANALOG INPUTS
VClipping Differential input voltage before clipping output VIN = AINP – AINN ±64 mV
FSR Specified linear differential full-scale VIN = AINP – AINN –50 50 mV
Absolute common-mode input voltage (1) (AINP + AINN) / 2 to AGND –2 AVDD V
VCM Operating common-mode input voltage (AINP + AINN) / 2 to AGND –0.032 AVDD – 2.1 V
VCMov Common-mode overvoltage detection level (2) (AINP + AINN) / 2 to AGND AVDD - 2 V
CIN Single-ended input capacitance AINN = AGND 4 pF
CIND Differential input capacitance 2 pF
IIB Input bias current AINP = AINN = AGND, IIB = IIBP + IIBN –97 –72 –57 μA
RIN Single-ended input resistance AINN = AGND 4.75 kΩ
RIND Differential input resistance 4.9 kΩ
IIO Input offset current ±10 nA
CMTI Common-mode transient immunity 50 100 kV/μs
AINP = AINN, fIN = 0 Hz,
–99
VCM min ≤ VIN ≤ VCM max
CMRR Common-mode rejection ratio dB
AINP = AINN, fIN from 0.1 Hz to 50 kHz,
–98
BW Input bandwidth (3) 800 kHz
DC ACCURACY
DNL Differential nonlinearity Resolution: 16 bits –0.99 0.99 LSB
Resolution: 16 bits, 4.5 V ≤ AVDD ≤ 5.5 V –4 ±1 4
INL Integral nonlinearity (4) LSB
Resolution: 16 bits, 3.0 V ≤ AVDD ≤ 3.6 V –5 ±1.5 5
EO Offset error Initial, at 25°C, AINP = AINN = AGND –50 ±2.5 50 µV
TCEO Offset error thermal drift (5) –1 ±0.25 1 μV/°C
EG Gain error Initial, at 25°C –0.2% ±0.005% 0.2%
TCEG Gain error thermal drift (6) –40 ±20 40 ppm/°C
AINP = AINN = AGND,
–108
3.0 V ≤ AVDD ≤ 5.5 V, at dc
PSRR Power-supply rejection ratio AINP = AINN = AGND, dB
3.0 V ≤ AVDD ≤ 5.5 V, –107
10 kHz, 100-mV ripple
AC ACCURACY
SNR Signal-to-noise ratio fIN = 1 kHz 78 82.5 dB
SINAD Signal-to-noise + distortion fIN = 1 kHz 77.5 82.3 dB
4.5 V ≤ AVDD ≤ 5.5 V,
–98 –84
5 MHz ≤ fCLKIN ≤ 21 MHz, fIN = 1 kHz
THD Total harmonic distortion dB
3.0 V ≤ AVDD ≤ 3.6 V,
–93 –83
SFDR Spurious-free dynamic range fIN = 1 kHz 83 100 dB
(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal
operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.
(2) The common-mode overvoltage detection level has a typical hysteresis of 90 mV.
(3) This is the –3-dB, second-order roll-off frequency of the integrated differential input amplifier to consider for the antialiasing filter design.
(4) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as a number of LSBs or as a percent of the specified linear full-scale range (FSR).
(5) Offset error drift is calculated using the box method, as described by the following equation:
value MAX value MIN
TCE O
TempRange
(6) Gain error drift is calculated using the box method, as described by the following equation:
§ value MAX value MIN ·
TCE G ( ppm ) ¨¨ ¸¸ u 10 6
© value u TempRange ¹

Electrical Characteristics: AMC1306x05 (continued)

AINP = –50 mV to 50 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are
at TA = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
DIGITAL INPUTS/OUTPUTS
CMOS Logic With Schmitt-Trigger
IIN Input current DGND ≤ VIN ≤ DVDD 0 7 µA
CIN Input capacitance 4 pF
VIH High-level input voltage 0.7 × DVDD DVDD + 0.3 V
VIL Low-level input voltage –0.3 0.3 × DVDD V
CLOAD Output load capacitance 30 pF
IOH = –20 µA DVDD – 0.1
VOH High-level output voltage V
IOH = –4 mA DVDD – 0.4
IOL = 20 µA 0.1
VOL Low-level output voltage V
IOL = 4 mA 0.4
POWER SUPPLY
AVDD High-side supply voltage 3.0 5.0 5.5 V
3.0 V ≤ AVDD ≤ 3.6 V 6.3 8.5
IAVDD High-side supply current mA
4.5 V ≤ AVDD ≤ 5.5 V 7.2 9.8
DVDD Controller-side supply voltage 2.7 3.3 5.5 V
AMC1306Ex, 2.7 V ≤ DVDD ≤ 3.6 V,
4.1 5.5
CLOAD = 15 pF
AMC1306Mx, 2.7 V ≤ DVDD ≤ 3.6 V,
3.3 4.8
CLOAD = 15 pF
IDVDD Controller-side supply current mA
AMC1306Ex, 4.5 V ≤ DVDD ≤ 5.5 V,
5.0 6.9
CLOAD = 15 pF
AMC1306Mx, 4.5 V ≤ DVDD ≤ 5.5 V,
3.9 6.0
CLOAD = 15 pF

7.10 Electrical Characteristics: AMC1306x25

AINP = –250 mV to 250 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications
are at TA = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
ANALOG INPUTS
VClipping Differential input voltage before clipping output AINP – AINN ±320 mV
FSR Specified linear differential full-scale AINP – AINN –250 250 mV
Absolute common-mode input voltage (1) (AINP + AINN) / 2 to AGND –2 AVDD V
VCM Operating common-mode input voltage (AINP + AINN) / 2 to AGND –0.16 AVDD – 2.1 V
VCMov Common-mode overvoltage detection level (2) (AINP + AINN) / 2 to AGND AVDD – 2 V
CIN Single-ended input capacitance AINN = AGND 2 pF
CIND Differential input capacitance 1 pF
IIB Input bias current AINP = AINN = AGND, IIB = IIBP + IIBN –82 –60 –48 µA
RIN Single-ended input resistance AINN = AGND 19 kΩ
RIND Differential input resistance 22 kΩ
IIO Input offset current ±5 nA
CMTI Common-mode transient immunity 50 100 kV/µs
AINP = AINN, fIN = 0 Hz,
–95
CMRR Common-mode rejection ratio dB
AINP = AINN, fIN from 0.1 Hz to 50 kHz,
–95
BW Input bandwidth (3) 900 kHz
DC ACCURACY
DNL Differential nonlinearity Resolution: 16 bits –0.99 0.99 LSB
INL Integral nonlinearity (4) Resolution: 16 bits –4 ±1 4 LSB
EO Offset error Initial, at 25°C, AINP = AINN = AGND –100 ±4.5 100 µV
(5)
TCEO Offset error thermal drift –1 ±0.15 1 µV/°C
EG Gain error Initial, at 25°C –0.2% ±0.005% 0.2%
TCEG Gain error thermal drift (6) –40 ±20 40 ppm/°C
AINP = AINN = AGND,
–103
3.0 V ≤ AVDD ≤ 5.5 V, at dc
PSRR Power-supply rejection ratio AINP = AINN = AGND, dB
3.0 V ≤ AVDD ≤ 5.5 V, –92
10 kHz, 100-mV ripple
AC ACCURACY
SNR Signal-to-noise ratio fIN = 1 kHz 82 86 dB
SINAD Signal-to-noise + distortion fIN = 1 kHz 81.9 85.7 dB
4.5 V ≤ AVDD ≤ 5.5 V,
–98 –86
THD Total harmonic distortion dB
3.0 V ≤ AVDD ≤ 3.6 V,
–93 –85
SFDR Spurious-free dynamic range fIN = 1 kHz 83 100 dB
(1) Steady-state voltage supported by the device in case of a system failure; see the specified common-mode input voltage VCM for normal
operation. Adhere to the analog input voltage range as specified in the Absolute Maximum Ratings table.
(2) The common-mode overvoltage detection level has a typical hysteresis of 90 mV.
(3) This parameter is the –3-dB, second-order, roll-off frequency of the integrated differential input amplifier to consider for antialiasing filter
designs.
(4) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
value MAX value MIN
TCE O
(5) Offset error drift is calculated using the box method, as described by the following equation: TempRange .
§ value MAX value MIN ·
TCE G ( ppm ) ¨¨ ¸¸ u 10
6
(6) Gain error drift is calculated using the box method, as described by the following equation: © value u TempRange ¹ .

Electrical Characteristics: AMC1306x25 (continued)

AINP = –250 mV to 250 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications
are at TA = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
DIGITAL INPUTS/OUTPUTS
CMOS Logic with Schmitt-trigger
IIN Input current DGND ≤ VIN ≤ DVDD 0 7 μA
CIN Input capacitance 4 pF
VIH High-level input voltage 0.7 × DVDD DVDD + 0.3 V
VIL Low-level input voltage –0.3 0.3 × DVDD V
CLOAD Output load capacitance fCLKIN = 20 MHz 30 pF
IOH = –20 µA DVDD – 0.1
VOH High-level output voltage V
IOH = –4 mA DVDD – 0.4
IOL = 20 µA 0.1
VOL Low-level output voltage V
IOL = 4 mA 0.4
POWER SUPPLY
AVDD High-side supply voltage 3.0 5.0 5.5 V
3.0 V ≤ AVDD ≤ 3.6 V 6.3 8.5
IAVDD High-side supply current mA
4.5 V ≤ AVDD ≤ 5.5 V 7.2 9.8
DVDD Controller-side supply voltage 2.7 3.3 5.5 V
AMC1306Ex, 2.7 V ≤ DVDD ≤ 3.6 V,
4.1 5.5
CLOAD = 15 pF
AMC1306Mx, 2.7 V ≤ DVDD ≤ 3.6 V,
3.3 4.8
CLOAD = 15 pF
IDVDD Controller-side supply current mA
AMC1306Ex, 4.5 V ≤ DVDD ≤ 5.5 V,
5.0 6.9
CLOAD = 15 pF
AMC1306Mx, 4.5 V ≤ DVDD ≤ 5.5 V,
3.9 6.0
CLOAD = 15 pF

7.11 Switching Characteristics

4.5 V ≤ AVDD ≤ 5.5 V 5 21
fCLKIN CLKIN clock frequency MHz
3.0 V ≤ AVDD ≤ 5.5 V 5 20
4.5 V ≤ AVDD ≤ 5.5 V 47.6 200
tCLKIN CLKIN clock period ns
3.0 V ≤ AVDD ≤ 5.5 V 50 200
tHIGH CLKIN clock high time 20 25 120 ns
tLOW CLKIN clock low time 20 25 120 ns
DOUT hold time after rising edge AMC1306Mx (1),
tH 3.5 ns
of CLKIN CLOAD = 15 pF
Rising edge of CLKIN to DOUT
tD AMC1306Mx (1), CLOAD = 15 pF 15 ns
valid delay
10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V,
0.8 3.5
CLOAD = 15 pF
tr DOUT rise time ns
10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V,
1.8 3.9
CLOAD = 15 pF
90% to 10%, 2.7 V ≤ DVDD ≤ 3.6 V,
0.8 3.5
CLOAD = 15 pF
tf DOUT fall time ns
90% to 10%, 4.5 V ≤ DVDD ≤ 5.5 V,
1.8 3.9
CLOAD = 15 pF
DVDD at 2.7 V (min) to DOUT valid with CLKIN
tISTART Interface startup time 32 32
AVDD ≥ 3.0 V cycles
AVDD step to 3.0 V with DVDD ≥ 2.7 V,
tASTART Analog startup time 0.5 ms
0.1% settling
(1) The output of the Manchester encoded versions of the AMC1306Ex can change with every edge of CLKIN with a typical delay of 6 ns;
see the Manchester Coding Feature section for additional details.
tCLKIN tHIGH
CLKIN
tLOW
tH tD tr / tf
DOUT
Figure 1. Digital Interface Timing
AVDD
DVDD
tASTART
CLKIN
...
Bitream not valid

DOUT Test Pattern Valid bitstream
(analog settling)
tISTART
Figure 2. Device Startup Timing

7.12 Insulation Characteristics Curves
500 1200
AVDD = DVDD = 3.6 V 1100
AVDD = DVDD = 5.5 V
1000
400
900
800
300 700
PS (mW)
IS (mA)
600
200 500
400
300
100
200
100
0 0
0 50 100 150 200 0 50 100 150 200
TA (°C) D001
TA (°C) D002
Figure 3. Thermal Derating Curve for Safety-Limiting Figure 4. Thermal Derating Curve for Safety-Limiting
Current per VDE Power per VDE
1.E+11 Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
1.E+10 TDDB Line (<1 PPM Fail Rate)
87.5%
1.E+9
1.E+8
Time to Fail (s)
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
20%
1.E+2
1.E+1
500 1500 2500 3500 4500 5500 6500 7500 8500 9500
Stress Voltage (VRMS)
TA up to 150°C, stress-voltage frequency = 60 Hz,
isolation working voltage = 1500 VRMS, operating lifetime = 135 years
Figure 5. Reinforced Isolation Capacitor Lifetime Projection

7.13 Typical Characteristics

at AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1306x05) or –250 mV to 250 mV (AMC1306x25),
AINN = AGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256 (unless otherwise noted)
4 3.3
3.5 3.25
3.2
3
3.15
VCMov (V)
2.5
VCM (V)
3.1
2
3.05
1.5
3
1 2.95
0.5 2.9
3 3.5 4 4.5 5 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125
AVDD (V) D003
Temperature (qC) D004
Figure 6. Maximum Operating Common-Mode Input Voltage Figure 7. Common-Mode Overvoltage Detection Level vs
vs High-Side Supply Voltage Temperature
60 0
AMC1306x25
40 AMC1306x05
-20
20
-40
CMRR (dB)
0
IIB (PA)
-60
-20
-80
-40
-60 -100
AMC1306x25
AMC1306x05
-80 -120
-0.5 0 0.5 1 1.5 2 2.5 3 3.5 0.1 1 10 100 1000
VCM (V) D005
fIN (kHz) D006
Figure 8. Input Bias Current vs Figure 9. Common-Mode Rejection Ratio vs

Common-Mode Input Voltage Input Signal Frequency
4 100
AMC1306x AMC1306x25
3.5 AMC1306x05, AVDD = 3.3 V 75 AMC1306x05
3 50
2.5 25
INL (|LSB|)
EO (µV)
2 0
1.5 -25
1 -50
0.5 -75
0 -100
-40 -25 -10 5 20 35 50 65 80 95 110 125 3 3.5 4 4.5 5 5.5
Temperature (°C) D008
AVDD (V) D009
Figure 10. Integral Nonlinearity vs Temperature Figure 11. Offset Error vs High-Side Supply Voltage

Typical Characteristics (continued)

100 100
AMC1306x25
80 80 AMC1306x05
60 60
40 40
20 20
EO (PV)
EO (µV)
0 0
-20 -20
-40 -40
-60 Device 1 -60
-80 Device 2 -80
Device 3
-100 -100
-40 -25 -10 5 20 35 50 65 80 95 110 125 5 9 13 17 21
fCLKIN (MHz) D011
Figure 12. Offset Error vs Temperature Figure 13. Offset Error vs Clock Frequency
0.25 0.3
0.2
0.2
0.15
0.1
0.1
0.05
EG (%)
EG (%)
0 0
-0.05
-0.1
-0.1
-0.15
-0.2
-0.2
-0.25 -0.3
3 3.5 4 4.5 5 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125
AVDD (V) D012
Figure 14. Gain Error vs High-Side Supply Voltage Figure 15. Gain Error vs Temperature
0.3 0
AMC1306x25
AMC1306x05
0.2 -20
0.1 -40
PSRR (dB)
EG (%)
0 -60
-0.1 -80
-0.2 -100
-0.3 -120
5 9 13 17 21 0.1 0.2 0.5 1 2 3 4 5 7 10 2030 50 100 200 500 1000
fCLKIN (MHz) D014
Ripple Frequency (kHz) D015
Figure 16. Gain Error vs Clock Frequency Figure 17. Power-Supply Rejection Ratio vs
Ripple Frequency


90 90
AMC1306x25, SNR AMC1306x25, SNR
89 AMC1306x25, SINAD 89 AMC1306x25, SINAD
88 AMC1306x05, SNR 88 AMC1306x05, SNR
AMC1306x05, SINAD AMC1306x05, SINAD
SNR and SINAD (dB)
SNR and SINAD (dB)

87 87
86 86
85 85
84 84
83 83
82 82
81 81
80 80
3 3.5 4 4.5 5 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125
AVDD (V) D016
Figure 18. Signal-to-Noise Ratio and Signal-to-Noise + Figure 19. Signal-to-Noise Ratio and Signal-to-Noise +
Distortion vs High-Side Supply Voltage Distortion vs Temperature
90 88
AMC1306x25, SNR
89 AMC1306x25, SINAD 86
88 AMC1306x05, SNR
AMC1306x05, SINAD 84
SNR and SINAD (dB)
SNR and SINAD (dB)
87
82
86
80
85
78
84
76
83
74 AMC1306x25, SNR
82 AMC1306x25, SINAD
81 72 AMC1306x05, SNR
AMC1306x05, SINAD
80 70
5 9 13 17 21 0.1 1 10 100
fCLKIN (MHz) D018
fIN (kHz) D019
Distortion vs Clock Frequency Distortion vs Input Signal Frequency
100 95
AMC1306x25, SNR AMC1306x05, SNR
95 AMC1306x25, SINAD 90 AMC1306x05, SINAD
90 85
SNR and SINAD (dB)
SNR and SINAD (dB)
85 80
80 75
75 70
70 65
65 60
60 55
55 50
50 45
0 50 100 150 200 250 300 350 400 450 500 0 10 20 30 40 50 60 70 80 90 100
VIN (mVpp) D020
VIN (mVpp) D042
Distortion vs Input Signal Amplitude Distortion vs Input Signal Amplitude


-86 -86
-88 -88
-90 -90
-92 -92
-94 -94
THD (dB)
THD (dB)
-96 -96
-98 -98
-100 -100
-102 -102
-104 -104
-106 -106
-108 -108
-110 -110
4.5 4.75 5 5.25 5.5 3 3.5 4 4.5 5 5.5
AVDD (V) D021
AVDD (V) D039
fCLKIN = 21 MHz fCLKIN = 20 MHz
Figure 24. Total Harmonic Distortion vs Figure 25. Total Harmonic Distortion vs
High-Side Supply Voltage (5 V, nom) High-Side Supply Voltage (3.3 V, nom)
-86 -86
-88 -88
-90 -90
-92 -92
-94 -94
THD (dB)
THD (dB)
-96 -96
-98 -98
-100 -100
-102 -102
-104 -104
-106 -106
-108 -108
-110 -110
-40 -25 -10 5 20 35 50 65 80 95 110 125 5 9 13 17 21
fCLKIN (MHz) D023
Figure 26. Total Harmonic Distortion vs Temperature Figure 27. Total Harmonic Distortion vs Clock Frequency
-85 -70
-75
-90
-80
-95 -85
-90
THD (dB)
THD (dB)
-100
-95
-105
-100
-110 -105
-110
-115
-115
-120 -120
0.1 1 10 0 50 100 150 200 250 300 350 400 450 500
fIN (kHz) D024
VIN (mVpp) D025
AMC1306x25
Figure 28. Total Harmonic Distortion vs Figure 29. Total Harmonic Distortion vs
Input Signal Frequency Input Signal Amplitude


-65 118
-70 114
-75 110
-80
106
SFDR (dB)
-85
THD (dB)
102
-90
98
-95
94
-100
-105 90
-110 86
-115 82
0 10 20 30 40 50 60 70 80 90 100 3 3.5 4 4.5 5 5.5
VIN (mVpp) D043
AVDD (V) D026
AMC1306x05
Figure 30. Total Harmonic Distortion vs Figure 31. Spurious-Free Dynamic Range vs
Input Signal Amplitude High-Side Supply Voltage
118 118
114 114
110 110
106 106
SFDR (dB)
SFDR (dB)
102 102
98 98
94 94
90 90
86 86
82 82
-40 -25 -10 5 20 35 50 65 80 95 110 125 5 9 13 17 21
fCLKIN (MHz) D028
Figure 32. Spurious-Free Dynamic Range vs Temperature Figure 33. Spurious-Free Dynamic Range vs
Clock Frequency
118 125
114 120
110 115
110
106
SFDR (dB)
SFDR (dB)
105
102
100
98
95
94
90
90 85
86 80
82 75
0.1 1 10 0 50 100 150 200 250 300 350 400 450 500
fIN (kHz) D029
VIN (mVpp) D030
AMC1306x25
Figure 34. Spurious-Free Dynamic Range vs Figure 35. Spurious-Free Dynamic Range vs
Input Signal Frequency Input Signal Amplitude


120 0
115 -20
110
-40
105
Magnitude (dB)
-60
SFDR (dB)
100
95 -80
90 -100
85
-120
80
75 -140
70 -160
0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40
VIN (mVpp) D046
Frequency (kHz) D044
AMC1306x05 AMC1306x05, 4096-point FFT, VIN = 100 mVPP
Figure 36. Spurious-Free Dynamic Range vs Figure 37. Frequency Spectrum with 1-kHz Input Signal
Input Signal Amplitude
0 0
-20 -20
-40 -40
Magnitude (dB)
Magnitude (dB)
-60 -60
-80 -80
-100 -100
-120 -120
-140 -140
-160 -160
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
AMC1306x05, 4096-point FFT, VIN = 100 mVPP AMC1306x25, 4096-point FFT, VIN = 500 mVPP
Figure 38. Frequency Spectrum with 10-kHz Input Signal Figure 39. Frequency Spectrum with 1-kHz Input Signal
0 10
9.5
-20
9
-40 8.5
8
Magnitude (dB)
-60
IAVDD (mA)
7.5
-80 7
6.5
-100
6
-120 5.5
5
-140
4.5
-160 4
0 5 10 15 20 25 30 35 40 3 3.5 4 4.5 5 5.5
AVDD (V) D033
AMC1306x25, 4096-point FFT, VIN = 500 mVPP
Figure 40. Frequency Spectrum with 10-kHz Input Signal Figure 41. High-Side Supply Current vs
High-Side Supply Voltage


10 10
9.5 9.5
9 9
8.5 8.5
8 8
IAVDD (mA)
IAVDD (mA)
7.5 7.5
7 7
6.5 6.5
6 6
5.5 5.5
5 5
4.5 4.5
4 4
-40 -25 -10 5 20 35 50 65 80 95 110 125 5 9 13 17 21
Clock Frequency (MHz) D035
Figure 42. High-Side Supply Current vs Temperature Figure 43. High-Side Supply Current vs Clock Frequency
8 8
7.5 AMC1306Mx 7.5 AMC1306Mx, DVDD = 3.3 V
AMC1306Ex AMC1306Mx, DVDD = 5 V
7 7 AMC1306Ex, DVDD = 3.3 V
6.5 6.5 AMC1306Ex, DVDD = 5 V
6 6
IDVDD (mA)
IDVDD (mA)
5.5 5.5
5 5
4.5 4.5
4 4
3.5 3.5
3 3
2.5 2.5
2 2
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125
DVDD (V) D036
Figure 44. Controller-Side Supply Current vs Figure 45. Controller-Side Supply Current vs Temperature
Controller-Side Supply Voltage
8
7.5 AMC1306Mx, DVDD = 3.3 V
AMC1306Mx, DVDD = 5 V
7 AMC1306Ex, DVDD = 3.3 V
6.5 AMC1306Ex, DVDD = 5 V
6
IDVDD (mA)
5.5
5
4.5
4
3.5
3
2.5
2
5 9 13 17 21
fCLKIN (MHz) D038
Figure 46. Controller-Side Supply Current vs

Clock Frequency

8 Detailed Description
8.1 Overview
The differential analog input (comprised of input signals AINP and AINN) of the AMC1306 is a fully-differential
amplifier feeding the switched-capacitor input of a second-order, delta-sigma (ΔΣ) modulator stage that digitizes
the input signal into a 1-bit output stream. The isolated data output DOUT of the converter provides a stream of
digital ones and zeros that is synchronous to the externally-provided clock source at the CLKIN pin with a
frequency in the range of 5 MHz to 21 MHz. The time average of this serial bitstream output is proportional to the
analog input voltage.
The Functional Block Diagram section shows a detailed block diagram of the AMC1306. The analog input range
is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. The silicon-
dioxide (SiO2) based capacitive isolation barrier supports a high level of magnetic field immunity as described in
the ISO72x Digital Isolator Magnetic-Field Immunity application report, available for download at www.ti.com. The
external clock input simplifies the synchronization of multiple current-sensing channels on the system level. The
extended frequency range of up to 21 MHz supports higher performance levels compared to the other solutions
available on the market.
8.2 Functional Block Diagram
AVDD DVDD
Reinforced
AMC1306x Isolation
Barrier
AINP
Manchester Coding
(AMC1306Ex Only)
Receiver
û Modulator DOUT
AINN
Receiver
Interface
Band-Gap
CLKIN
Reference
VCM, AVDD
Diagnostic
AGND DGND

8.3 Feature Description

8.3.1 Analog Input
The AMC1306 incorporates front-end circuitry that contains a differential amplifier and a sampling stage, followed
by a ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of 4 for
devices with a specified input voltage range of ±250 mV (this value is for the AMC1306x25), or to a factor of 20
in devices with a ±50-mV input voltage range (for the AMC1306x05), resulting in a differential input impedance of
4.9 kΩ (for the AMC1306x05) or 22 kΩ (for the AMC1306x25). For reduced offset and offset drift, the differential
amplifier is chopper-stabilized with the switching frequency set at fCLKIN / 32. The switching frequency generates
a spur as shown in Figure 47.
0
-20
-40
Magnitude (dB)
-60
-80
-100
-120
-140
-160
0.1 1 10 100 1000 10000
sinc3 filter, OSR = 2, fCLKIN = 20 MHz, fIN = 1 kHz
Figure 47. Quantization Noise Shaping
Consider the input impedance of the AMC1306 in designs with high-impedance signal sources that can cause
degradation of gain and offset specifications. The importance of this effect, however, depends on the desired
system performance. Additionally, the input bias current caused by the internal common-mode voltage at the
output of the differential amplifier is dependent on the actual amplitude of the input signal; see the Isolated
Voltage Sensing section for more details on reducing these effects.
There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the
range AGND – 6 V to AVDD + 0.5 V, the input current must be limited to 10 mA because the device input
electrostatic discharge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are
ensured only when the differential analog input voltage remains within the specified linear full-scale range (FSR),
that is ±250 mV (for the AMC1306x25) or ±50 mV (for the AMC1306x05), and within the specified input common-
mode range.

Feature Description (continued)

8.3.2 Modulator
The modulator implemented in the AMC1306 is a second-order, switched-capacitor, feed-forward ΔΣ modulator,
such as the one conceptualized in Figure 48. The analog input voltage VIN and the output V5 of the 1-bit digital-
to-analog converter (DAC) are differentiated, providing an analog voltage V1 at the input of the first integrator
stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage
V3 that is differentiated with the input signal VIN and the output of the first integrator V2. Depending on the polarity
of the resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the
next clock pulse by changing the associated analog output voltage V5, causing the integrators to progress in the
opposite direction and forcing the value of the integrator output to track the average value of the input.
fCLKIN
V1 V2 V3 V4
VIN Integrator 1 Integrator 2
CMP
0V
V5
DAC
Figure 48. Block Diagram of a Second-Order Modulator
The modulator shifts the quantization noise to high frequencies, as shown in Figure 48. Therefore, use a low-
pass digital filter at the output of the device to increase the overall performance. This filter is also used to convert
from the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's
microcontroller families TMS320F2807x and TMS320F2837x offer a suitable programmable, hardwired filter
structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC1306 family. Also,
SD24_B converters on the MSP430F677x microcontrollers offer a path to directly access the integrated sinc-
filters for a simple system-level solution for multichannel, isolated current sensing. An additional option is to use a
suitable application-specific device, such as the AMC1210 (a four-channel digital sinc-filter). Alternatively, a field-
programmable gate array (FPGA) can be used to implement the filter.


8.3.3 Isolation Channel Signal Transmission
The AMC1306 device uses an on-off keying (OOK) modulation scheme to transmit the modulator output
bitstream across the capacitive SiO2-based isolation barrier. The transmitter modulates the bitstream at TX IN in
Figure 49 with an internally-generated, 480-MHz carrier across the isolation barrier to represent a digital one and
sends a no signal to represent the digital zero. The receiver demodulates the signal after advanced signal
conditioning and produces the output. The symmetrical design of each isolation channel improves the CMTI
performance and reduces the radiated emissions caused by the high-frequency carrier. The block diagram of an
isolation channel integrated in the AMC1306 is shown in Figure 49.
Transmitter Receiver
OOK
Modulation
SiO2-Based
TX IN Capacitive
TX Signal RX Signal Envelope
Reinforced RX OUT
Conditioning Conditioning Detection
Isolation
Barrier
Oscillator
Figure 49. Block Diagram of an Isolation Channel
Figure 50 shows the concept of the on-off keying scheme.
TX IN
Carrier Signal Across

the Isolation Barrier
RX OUT
Figure 50. OOK-Based Modulation Scheme


8.3.4 Digital Output
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A
differential input of 250 mV (for the AMC1306x25) or 50 mV (for the AMC1306x05) produces a stream of ones
and zeros that are high 89.06% of the time. With 16 bits of resolution, that percentage ideally corresponds to the
code 58368. A differential input of –250 mV (–50 mV for the AMC1306x05) produces a stream of ones and zeros
that are high 10.94% of the time and ideally results in code 7168 with 16-bit resolution. These input voltages are
also the specified linear ranges of the different AMC1306 versions with performance as specified in this
document. If the input voltage value exceeds these ranges, the output of the modulator shows nonlinear behavior
when the quantization noise increases. The output of the modulator clips with a stream of only zeros with an
input less than or equal to –320 mV (–64 mV for the AMC1306x05) or with a stream of only ones with an input
greater than or equal to 320 mV (64 mV for the AMC1306x05). In this case, however, the AMC1306 generates a
single 1 (if the input is at negative full-scale) or 0 every 128 clock cycles to indicate proper device function (see
the Fail-Safe Output section for more details). The input voltage versus the output modulator signal is shown in
Figure 51.
Modulator Output
+FS (Analog Input)
-FS (Analog Input)
Analog Input
Figure 51. Analog Input versus the AMC1306 Modulator Output
The density of ones in the output bitstream for any input voltage value (with the exception of a full-scale input
signal, as described in the Output Behavior in Case of a Full-Scale Input section) can be calculated using
Equation 1:
VIN VClipping
2 u VClipping (1)
The AMC1306 system clock is provided externally at the CLKIN pin. For more details, see the Switching
Characteristics table and the Manchester Coding Feature section.
8.3.5 Manchester Coding Feature

The AMC1306Ex offers the IEEE 802.3-compliant Manchester coding feature that generates at least one
transition per bit to support clock signal recovery from the bitstream. A Manchester coded bitstream is free of dc
components. The Manchester coding combines the clock and data information using exclusive or (XOR) logical
operation and results in a bitstream as shown in Figure 52. The duty cycle of the Manchester encoded bitstream
depends on the duty cycle of the input clock CLKIN.
Clock
Uncoded
Bitstream
1 0 1 0 1 1 1 0 0 1 1 0 0 0 1
Machester
Coded
Bitstream
Figure 52. Manchester Coded Output of the AMC1306Ex

8.4 Device Functional Modes

8.4.1 Fail-Safe Output
In the case of a missing high-side supply voltage AVDD, the output of a ΔΣ modulator is not defined and can
cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable.
Therefore, the AMC1306 implements a fail-safe output function that ensures that the output DOUT of the device
offers a steady-state bitstream of logic 0's in case of a missing AVDD, as shown in Figure 53.
Additionally, if the common-mode voltage of the input reaches or exceeds the specified common-mode
overvoltage detection level VCMov as defined in the Electrical Characteristics table, the AMC1306 offers a steady-
state bitstream of logic 1's at the output DOUT, as also shown in Figure 53.
tASTART
tISTART
CLKIN
...
AVDD AVDD GOOD Missing AVDD AVDD GOOD
VCM VCM < VCMov VCM • 9CMov VCM < VCMov
DOUT Valid Bit Stream 1 0 Test Pattern 1 Bit Stream Not Valid Valid Bit Stream
Figure 53. Fail-Safe Output of the AMC1306
8.4.2 Output Behavior in Case of a Full-Scale Input

If a full-scale input signal is applied to the AMC1306 (that is, VIN ≥ VClipping), the device generates a single one or
zero every 128 bits at DOUT, depending on the actual polarity of the signal being sensed, as shown in Figure 54.
In this way, differentiating between a missing AVDD and a full-scale input signal is possible on the system level.
CLKIN
... ...
DOUT VIN ” ±320 mV (AMC1306x05: ±64 mV)

... ...
... ...
DOUT VIN • 320 mV (AMC1306x05: 64 mV)
127 CLKIN Cycles 127 CLKIN Cycles
Figure 54. Overrange Output of the AMC1306

9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

9.1.1 Digital Filter Usage
The modulator generates a bitstream that is processed by a digital filter to obtain a digital word similar to a
conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, built with minimal effort
and hardware, is a sinc3-type filter, as shown in Equation 2:
3
§ 1 z OSR ·
H z ¨¨ 1
¸¸
© 1 z ¹ (2)
This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-
order modulator. All the characterization in this document is also done with a sinc3 filter with an oversampling
ratio (OSR) of 256 and an output word width of 16 bits.
The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators.
Figure 55 shows the ENOB of the AMC1306 with different oversampling ratios. In this document, this number is
calculated from the SINAD by using Equation 3:
SINAD = 1.76 dB + 6.02 dB × ENOB (3)
16
14
12
10
ENOB (bits)
4
sinc3
2 sinc2
sinc1
0
1 10 100 1000
OSR D040
Figure 55. Measured Effective Number of Bits versus Oversampling Ratio
An example code for implementing a sinc3 filter in an FPGA is discussed in the Combining the ADS1202 with an
FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available for
download at www.ti.com.

9.2 Typical Applications

9.2.1 Frequency Inverter Application
Isolated ΔΣ modulators are being widely used in frequency inverter designs because of their high ac and dc
performance. Frequency inverters are critical parts of industrial motor drives, photovoltaic inverters (string and
central inverters), uninterruptible power supplies (UPS), electrical and hybrid electrical vehicles, and other
industrial applications.
Figure 56 shows a simplified schematics of the AMC1306Mx in a typical frequency inverter application as used in
industrial motor drives with shunt resistors (RSHUNT) used for current sensing. Depending on the system design,
either all three or only two motor phase currents are sensed.
The Manchester coded bitstream output of the AMC1306Ex minimizes the wiring efforts of the connection
between the power board and the control board; see Figure 57. This bitstream output also allows the clock to be
generated locally on the power board without the having to adjust the propagation delay time of each DOUT
connection to fulfill the setup and hold time requirements of the microcontroller.
In both examples, an additional fourth AMC1306 is used to support isolated voltage sensing of the dc link. This
high voltage is reduced using a high-impedance resistive divider and is sensed by the device across a smaller
resistor. The value of this resistor can degrade the performance of the measurement, as described in the Isolated
Voltage Sensing section.
Motor
DC link
RSHUNT L1
RSHUNT L3
RSHUNT
L2
AMC1306Mx
3.3 V AVDD DVDD 3.3 V
AINP CLKIN
AINN DOUT
AMC1306Mx
3.3 V AVDD DVDD 3.3 V SD-D1
SD-C1
AINP CLKIN
AINN DOUT SD-D2
SD-C2
AGND DGND
AMC1306Mx
SD-D3
SD-C3
AINP CLKIN
SD-D4
AINN DOUT
SD-C4
AGND DGND
AMC1306Mx
CDCLVC1104 PWMx
AINP CLKIN
AINN DOUT
AGND DGND
Power Board Control Board
Figure 56. The AMC1306Mx in a Frequency Inverter Application

Typical Applications (continued)

Motor
DC link
RSHUNT L1
RSHUNT L3
RSHUNT
L2
AMC1306Ex
AINP CLKIN
AINN DOUT
AMC1306Ex
AINP CLKIN
AINN DOUT
SD-D1
AGND DGND SD-D2
AMC1306Ex
SD-D3
3.3 V AVDD DVDD 3.3 V SD-D4
AINP CLKIN
AINN DOUT
AGND DGND
AMC1306Ex
AINP CLKIN
AINN DOUT
AGND DGND Clock Source
Power Board Control Board
Figure 57. The AMC1306Ex in a Frequency Inverter Application
9.2.1.1 Design Requirements

Table 1 lists the parameters for the typical application in the Frequency Inverter Application section.
Table 1. Design Requirements

PARAMETER VALUE
High-side supply voltage 3.3 V or 5 V
Low-side supply voltage 3.3 V or 5 V
Voltage drop across the shunt for a linear response ±250 mV (maximum)

9.2.1.2 Detailed Design Procedure

The high-side power supply (AVDD) for the AMC1306 device is derived from the power supply of the upper gate
driver. Further details are provided in the Power Supply Recommendations section.
The floating ground reference (AGND) is derived from one of the ends of the shunt resistor that is connected to
the negative input of the AMC1306 (AINN). If a four-pin shunt is used, the inputs of the device are connected to
the inner leads and AGND is connected to one of the outer shunt leads.
Use Ohm's Law to calculate the voltage drop across the shunt resistor (VSHUNT) for the desired measured
current: VSHUNT = I × RSHUNT.
Consider the following two restrictions to choose the proper value of the shunt resistor RSHUNT:
• The voltage drop caused by the nominal current range must not exceed the recommended differential input
voltage range: VSHUNT ≤ ±250 mV
• The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes
a clipping output: |VSHUNT| ≤ |VClipping|
The typically recommended RC filter in front of a ΔΣ modulator to improve signal-to-noise performance of the
signal path is not required for the AMC1306. By design, the input bandwidth of the analog front-end of the device
is limited as specified in the Electrical Characteristics table.
For modulator output bitstream filtering, a device from TI's TMS320F2807x family of low-cost microcontrollers
(MCUs) or TMS320F2837x family of dual-core MCUs is recommended. These families support up to eight
channels of dedicated hardwired filter structures that significantly simplify system level design by offering two
filtering paths per channel: one providing high accuracy results for the control loop and one fast response path
for overcurrent detection.
9.2.1.3 Application Curve

In motor control applications, a very fast response time for overcurrent detection is required. The time for fully
settling the filter in case of a step-signal at the input of the modulator depends on the filter order; that is, a sinc3
filter requires three data updates for full settling (with fDATA = fCLK / OSR). Therefore, for overcurrent protection,
filter types other than sinc3 can be a better choice; an alternative is the sinc2 filter. Figure 58 compares the
settling times of different filter orders.
The delay time of the sinc filter with a continuous signal is half of the settling time.
16
14
12
10
ENOB (Bits)
4
sinc1
2 sinc2
sinc3
0
0 2 4 6 8 10 12 14 16 18 20
Settling Time (µs) D041
Figure 58. Measured Effective Number of Bits versus Settling Time

9.2.2 Isolated Voltage Sensing

The AMC1306 is optimized for usage in current-sensing applications using low-impedance shunts. However, the
device can also be used in isolated voltage-sensing applications if the affect of the (usually higher) impedance of
the resistor used in this case is considered.
High Voltage
Potential
3.3 V
or 5 V
R1
AVDD
R2
R4 R5
AINP
IIB
200 NŸ
R3 RIND û Modulator
AINN
R3' R4' R5'
AGND
VCM = 1.9 V
AGND
Figure 59. Using the AMC1306 for Isolated Voltage Sensing
9.2.2.1 Design Requirements

Figure 59 shows a simplified circuit typically used in high-voltage-sensing applications. The high impedance
resistors (R1 and R2) are used as voltage dividers and dominate the current value definition. The resistance of
the sensing resistor R3 is chosen to meet the input voltage range of the AMC1306. This resistor and the
differential input impedance of the device (the AMC1306x25 is 22 kΩ, the AMC1306x05 is 4.9 kΩ) also create a
voltage divider that results in an additional gain error. With the assumption of R1, R2, and RIN having a
considerably higher value than R3, the resulting total gain error can be estimated using Equation 4, with EG
being the gain error of the AMC1306.
R3
EGtot = EG +
RIN (4)
This gain error can be easily minimized during the initial system-level gain calibration procedure.
9.2.2.2 Detailed Design Procedure

As indicated in Figure 59, the output of the integrated differential amplifier is internally biased to a common-mode
voltage of 1.9 V. This voltage results in a bias current IIB through the resistive network R4 and R5 (or R4' and
R5') used for setting the gain of the amplifier. The value range of this current is specified in the Electrical
Characteristics table. This bias current generates additional offset error that depends on the value of the resistor
R3. The initial system offset calibration does not minimize this effect because the value of the bias current
depends on the actual common-mode amplitude of the input signal (as illustrated in Figure 60). Therefore, in
systems with high accuracy requirements, a series resistor is recommended to be used at the negative input
(AINN) of the AMC1306 with a value equal to the shunt resistor R3 (that is, R3' = R3 in Figure 59) to eliminate
the effect of the bias current.

This additional series resistor (R3') influences the gain error of the circuit. The effect can be calculated using
Equation 5 with R5 = R5' = 50 kΩ and R4 = R4' = 2.5 kΩ (for the AMC1306x05) or 12.5 kΩ (for the
AMC1306x25).
§ R4 ·
E G (%) ¨ 1 R4' R3' ¸ u 100%
© ¹ (5)
9.2.2.3 Application Curve

Figure 60 shows the dependency of the input bias current on the common-mode voltage at the input of the
AMC1306.
60
40
20
0
IIB (PA)
-20
-40
-60 AMC1306x25
AMC1306x05
-80
-0.5 0 0.5 1 1.5 2 2.5 3 3.5
VCM (V) D005
Figure 60. Input Bias Current vs Common-Mode Input Voltage
9.2.3 What To Do and What Not To Do

Do not leave the inputs of the AMC1306 unconnected (floating) when the device is powered up. If both modulator
inputs are left floating, the input bias current drives these inputs to the output common-mode of the analog front-
end of approximately 1.9 V. If that voltage is above the specified input common-mode range, the front gain
diminishes and the modulator outputs a bitstream resembling a zero input differential voltage.

10 Power Supply Recommendations

In a typical frequency-inverter application, the high-side power supply (AVDD) for the device is directly derived
from the floating power supply of the upper gate driver. For lowest system-level cost, a Zener diode can be used
to limit the voltage to 5 V or 3.3 V (±10%). Alternatively a low-cost low-drop regulator (LDO), for example the
LM317-N, can be used to adjust the supply voltage level and minimize noise on the power-supply node. A low-
ESR decoupling capacitor of 0.1 µF is recommended for filtering this power-supply path. Place this capacitor (C2
in Figure 61) as close as possible to the AVDD pin of the AMC1306 for best performance. If better filtering is
required, an additional 10-µF capacitor can be used.
The floating ground reference (AGND) is derived from the end of the shunt resistor that is connected to the
negative input (AINN) of the device. If a four-pin shunt is used, the device inputs are connected to the inner leads
and AGND is connected to one of the outer leads of the shunt.
For decoupling of the digital power supply on the controller side, a 0.1-µF capacitor is recommended to be
placed as close to the DVDD pin of the AMC1306 as possible, followed by an additional capacitor in the range of
1 µF to 10 µF.
Floating
Power Supply
HV+ 20 V
R1 AMC1306Mx
Gate Driver 800 3.0 V,
5.1 V
AVDD DVDD 3.3 V,
or 5.0 V
Reinforced Isolation
Z1 C1 C2 C4 C5
1N751A 10 F 0.1 F 0.1 F 2.2 F
AGND DGND
RSHUNT
To Load AINN DOUT SD-Dx
AINP CLKIN SD-Cx
Gate Driver PWMx
TMS320F2837x
HV-
Figure 61. Decoupling the AMC1306

11 Layout
11.1 Layout Guidelines

A layout recommendation showing the critical placement of the decoupling capacitors (as close as possible to the
AMC1306) and placement of the other components required by the device is shown in Figure 62. For best
performance, place the shunt resistor close to the AINP and AINN inputs of the AMC1306 and keep the layout of
both connections symmetrical.
11.2 Layout Example

Clearance area,
to be kept free of any
conductive materials.
2.2 µF 0.1 µF 0.1 µF 2.2 µF
SMD SMD SMD SMD

To Floating 0603 0603 0603 0603
Power AVDD 1 16 DVDD
Supply
SMD
Shunt Resistor
RFLT From Clock

0603 AINP CLKIN
CFLT Source
AMC1306x
SMD
0603 To Digital
SMD
RFLT AINN DOUT Filter
0603
(MCU)
AGND DGND
LEGEND
Copper Pour and Traces
High-Side Area
Controller-Side Area
Via to Ground Plane
Via to Supply Plane
Figure 62. Recommended Layout of the AMC1306x

12 Device and Documentation Support
12.1 Device Support

12.1.1 Device Nomenclature
12.1.1.1 Isolation Glossary

See the Isolation Glossary
12.2 Documentation Support

12.2.1 Related Documentation
For related documentation see the following:
• AMC1210 Quad Digital Filter for 2nd-Order Delta-Sigma Modulator
• MSP430F677x Polyphase Metering SoCs
• TMS320F2807x Piccolo™ Microcontrollers
• TMS320F2837xD Dual-Core Delfino™ Microcontrollers
• ISO72x Digital Isolator Magnetic-Field Immunity
• Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications
• CDCLVC11xx 3.3-V and 2.5-V LVCMOS High-Performance Clock Buffer Family
12.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
AMC1306E05 Click here Click here Click here Click here Click here
AMC1306E25 Click here Click here Click here Click here Click here
AMC1306M05 Click here Click here Click here Click here Click here
AMC1306M25 Click here Click here Click here Click here Click here
12.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
AMC1306E05DWV ACTIVE SOIC DWV 8 64 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 1306E05
& no Sb/Br)
AMC1306E05DWVR ACTIVE SOIC DWV 8 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 1306E05
& no Sb/Br)
AMC1306E25DWV ACTIVE SOIC DWV 8 64 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 1306E25
& no Sb/Br)
AMC1306E25DWVR ACTIVE SOIC DWV 8 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 1306E25
& no Sb/Br)
AMC1306M05DWV ACTIVE SOIC DWV 8 64 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 1306M05
& no Sb/Br)
AMC1306M05DWVR ACTIVE SOIC DWV 8 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 1306M05
& no Sb/Br)
AMC1306M25DWV ACTIVE SOIC DWV 8 64 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 1306M25
& no Sb/Br)
AMC1306M25DWVR ACTIVE SOIC DWV 8 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 1306M25
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jan-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AMC1306E05DWVR SOIC DWV 8 1000 330.0 16.4 12.05 6.15 3.3 16.0 16.0 Q1
AMC1306E25DWVR SOIC DWV 8 1000 330.0 16.4 12.05 6.15 3.3 16.0 16.0 Q1
AMC1306M05DWVR SOIC DWV 8 1000 330.0 16.4 12.05 6.15 3.3 16.0 16.0 Q1
AMC1306M25DWVR SOIC DWV 8 1000 330.0 16.4 12.05 6.15 3.3 16.0 16.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jan-2020
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
AMC1306E05DWVR SOIC DWV 8 1000 350.0 350.0 43.0
AMC1306E25DWVR SOIC DWV 8 1000 350.0 350.0 43.0
AMC1306M05DWVR SOIC DWV 8 1000 350.0 350.0 43.0
AMC1306M25DWVR SOIC DWV 8 1000 350.0 350.0 43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DWV0008A SCALE 2.000

SOIC - 2.8 mm max height
SOIC
SEATING PLANE
11.5 0.25
PIN 1 ID TYP 0.1 C
AREA
6X 1.27
8
1
5.95 2X
5.75 3.81
NOTE 3
4
5
0.51
8X
0.31
7.6 0.25 C A B
A B 2.8 MAX
7.4
NOTE 4
0.33
TYP
0.13
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5 DETAIL A
(2) TYPICAL
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A SOIC - 2.8 mm max height

SOIC
8X (1.8) SEE DETAILS

SYMM
8X (0.6) SYMM
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE

9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
SOLDER MASK SOLDER MASK METAL

METAL
OPENING OPENING
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A SOIC - 2.8 mm max height

SOIC
8X (1.8) SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated

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AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

AMC1306x Small, High-Precision,

– Uninterruptible power supplies AMC1306x SOIC (8) 5.85 mm × 7.50 mm

AGND DGND TMS320F28x7x

Changes from Revision A (July 2017) to Revision B Page

• Changed Reinforced Isolation Capacitor Lifetime Projection figure .................................................................................... 13

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Changes from Original (March 2017) to Revision A Page

• Released AMC1306E05 and AMC1306M05 to production .................................................................................................... 1

Copyright © 2017–2020, Texas Instruments Incorporated Submit Documentation Feedback 3

5 Device Comparison Table

6 Pin Configuration and Functions

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Product Folder Links: AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Power Ratings

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7.6 Insulation Specifications

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Product Folder Links: AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25

7.7 Safety-Related Certifications

7.8 Safety Limiting Values

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7.9 Electrical Characteristics: AMC1306x05

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Electrical Characteristics: AMC1306x05 (continued)

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7.10 Electrical Characteristics: AMC1306x25

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Electrical Characteristics: AMC1306x25 (continued)

Copyright © 2017–2020, Texas Instruments Incorporated Submit Documentation Feedback 11

7.11 Switching Characteristics

Figure 1. Digital Interface Timing

Bitream not valid

Figure 2. Device Startup Timing

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Product Folder Links: AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25

7.12 Insulation Characteristics Curves

Figure 5. Reinforced Isolation Capacitor Lifetime Projection

Copyright © 2017–2020, Texas Instruments Incorporated Submit Documentation Feedback 13

7.13 Typical Characteristics

Figure 8. Input Bias Current vs Figure 9. Common-Mode Rejection Ratio vs

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Typical Characteristics (continued)

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Typical Characteristics (continued)

SNR and SINAD (dB)

SNR and SINAD (dB)

SNR and SINAD (dB)

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