Lab # 4
Lab # 4
Lab # 4
Objective:
Introduction to I2C Protocol. Configuration of I2C registers for communication.
Apparatus:
i. PIC 16F877A
ii. Resistor (1 kΩ)
iii. I2C Debugger
Softwares:
i. MPLABX IDE
ii. XC8 compiler
iii. Proteus.
Theory:
1) I2C Communication:
I²C (Inter-Integrated Circuit), is a multi-master, multi-slave, packet switched, single-ended, serial
computer bus invented in 1982 by Philips. The I2C bus is a bi-directional two-wire serial bus that provides
a communication link between integrated circuits. It is a synchronous protocol that allows a master device
to initiate communication with a slave device. Data is exchanged one bit at a time.
The two wires, or lines are called Serial Clock (or SCL) and Serial Data (or SDA). The SCL line is the
clock signal line, generated by the master which synchronize the data transfer between the devices on the
I2C bus. The other line is the SDA line which carries the data.
Both the lines are “open-drain” which means that pull up resistors needs to be attached to them so that
the lines are high because the devices on the I2C bus are active low. Commonly used values for the resistors
are from 2k for higher speeds at about 400 kbps, to 10k for lower speed at about 100 kbps. The I2C mode
fully implements all master and slave functions and provides interrupts on Start and Stop bits in hardware
to determine a free bus (multi-master function). It supports 7-bit and 10-bit addressing and can connect up
to 127 devices with only two wires. The user must configure these pins as inputs or outputs.
a) Master:
A device on the I2C bus which starts the communication.
b) Slave:
A device which is being addressed by Master.
2) Protocol:
The data signal is transferred in sequences of 8-bits. So, after a special start condition occurs comes the
first 8-bits sequence which indicates the address of the slave to which the data is being sent. The device
addressing sequence starts with the most significant bit (MSB) first and ends with the least significant bit
(LSB) and it’s actually composed of 7 bits because the 8th bit is used for indicating whether the master will
write to the slave (logic low) or read from it (logic high). After each 8-bits sequence follows a bit called
Acknowledge. After the first Acknowledge bit in most cases comes another addressing sequence but this
9) Results:
Procedure:
i. Firstly, i made the functions for I2C initialization and configured its registers by using datasheet of
PIC16F877A as shown.
ii. I also read the timing diagram of I2C master mode.
iii. Then I made functions for start and stop condition of I2C communication in which we enabled the
start and stop condition by SEN (bit 0) and PEN (bit 1).
iv. Then I made functions for data transmission in which I use SSPBUF register for data write.
v. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set.
vi. After the ninth clock, the SSPIF bit is set and the master clock is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA unchanged.
vii. After this I made circuit diagram in proteus as shown in output and simulated the program.
Conclusion:
In this lab, I have explored, learned and implemented I2C communication protocol. I have learned the
behavior of I2C communication at the beginners level and practiced it.