1)Define Interrupt Vector Table.

Illustrate how to find address of an interrupt service rou ne

corresponding to a given interrupt in 8086.

The interrupt vector (or interrupt pointer) table is the link between an interrupt type code and the
procedure that has been designated to service interrupts associated with that code.The interrupt
Vector table contains the IP (Instruc on Pointer) and CS (Code Segment base address)of all the
interrupt types stored sequen ally from the address 0000:0000 to 0000:03FFH.

➢ The interrupt type number N is mul plied by 4 and this hexadecimal mul plica on gives the offset
address of in the code segment with base address 0000H (IVT) at which the IP and CS of the ISR are
stored

2. Explain how the INT n instruc on finds the star ng address of its interrupt service rou ne in IVT
with example.

The first 1Kbyte of memory of 8086 (00000 to003FF) is set aside as a table for storing the star ng
addresses of Interrupt Service Procedures (ISP). Since 4-bytes are required for storing star ng
addresses of ISPs, the table can hold 256 Interrupt procedures. The star ng address of an ISP is o en
called the Interrupt Vector or Interrupt Pointer. Therefore, the table is referredas Interrupt Vector
Table. The interrupt type number N is mul plied by 4 and this hexadecimal mul plica on gives the
offset address of in the code segment with base address 0000H (IVT) at which the IP and CS of the
ISR are stored

Eg:- For interrupt 21h, the address in the IVT is 21h * 4 = 0x0024. Assume the IVT entry at 0x0024
holds 0x1234 (offset) and 0x5678. The complete address of the ISR would be 0x5678:0x1234. The
CPU jumps to this address to execute the ISR.

3. Differen ate between maskable and non-maskable interrupts of 8086.

Maskable

The interrupts whose request can be either accepted or rejected by the processor are called
maskable interrupts.

When maskable interrupt occur, it can be handled a er execu ng the current instruc on.

Maskable interrupts help to handle lower priority tasks.

Maskable interrupts used to interface with peripheral device.

RST6.5, RST7.5, and RST5.5 of 8085 are some common examples of maskable Interrupts.

Non-Maskable

The interrupts whose request has to be definitely accepted (or cannot be rejected) by the processor
are called non-maskable interrupts.

When non-maskable interrupts occur, the current instruc ons and status are stored in stack for the
CPU to handle the interrupt.

Non-maskable interrupt help to handle higher priority tasks such as watchdog mer.

Non maskable interrupt used for emergency purpose e.g power failure, smoke detector etc

Trap of 8085 microprocessor is an example for non-maskable interrupt.

4. Explain the stack structure of 8086

The stack is a block of memory that may be used for temporarily storing the contents of the registers
inside the CPU. It is a top-down data structure whose elements are accessed using the stack pointer
(SP) which gets decremented by two as we store a data word in the stack and gets incremented by
two as we retrieve a data word from the stack back to the CPU register.

● The stack segment, like any other segment, may have a memory block of a maximum of 64 Kbytes
loca ons and thus may overlap with any other segments. The stack Segment register (SS) contains
the base address of the stack segment in the memory. In 8086 microprocessor-based system, the
stack is created by loading a 16-bit base address in the Stack Segment (SS) register and a 16-bit offset
address in Stack Pointer (SP). The 20-bit physical address of the stack is computed by mul plying the
contents of the SS register by 10H and then adding the contents of SP to this product. Here the
content of SP is the offset address of the stack.

5. Define DMA. State the list of opera ons performed by DMA controller in DMA transfer opera on.

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest rate. It
allows the device to transfer the data directly to/from memory without any interference of the CPU.

Following is the sequence of opera ons performed by a DMA −

• Ini ally, when any device has to send data between the device and the memory, the device has to
send DMA request (DRQ) to DMA controller.

• The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert the HLDA.

• Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU leaves
the control over bus and acknowledges the HOLD request through HLDA signal.

• Now the CPU is in HOLD state and the DMA controller has to manage the opera ons over buses
between the CPU, memory, and I/O devices.

6. Discuss how 8254 is used as square wave generator.

7. Jus fy the statement: “DMA controlled data transfer faster than CPU controlled data transfer”.

Suppose any device which is connected to input-output port wants to transfer data to memory, first
of all it will send input-output port address and control signal, input-output read to input-output
port, then it will send memory address and memory write signal to memory where data has to be
transferred. In normal input-output technique the processor becomes busy in checking whether any
input-output opera on is completed or not for next input-output opera on, therefore this technique
is slow. This problem of slow data transfer between input-output port and memory or between two
memory is avoided by implemen ng Direct Memory Access (DMA) technique. This is faster as the
microprocessor/computer is bypassed and the control of address bus and data bus is given to the
DMA controller.

8. Write the func on of the following control signals in 8255. RD', WR', Ao. A1, RESET, CS'

9. Differen ate between microprocessors and microcontrollers.

10. Explain program status word (PSW) of 8051 microcontroller.

11. with a neat diagram, explain the stack structure of 8086

• PUSH: Push to stack

The PUSH instruc on decrements the stack pointer (SP) by 2 and copies a word from a specified
source to the loca on in the stack segment to which the stack pointer points.

Eg: MOV AX, 5522H

• POP: Pop from stack

The POP instruc on copies a word from the stack loca on pointed to by the stack pointer to a
des na on specified in the instruc on.

Eg;-PUSH AX

12.List the events performed in 8086 when an interrupt occurs.

13.With a neat diagram explain the architecture of 8259, Programmable interrupt controller.

Data Bus Buffer This tristate bidirec onal buffer interfaces internal 8259A bus to the microprocessor
system data bus. Control words, status and vector informa on pass through buffer during read or
write opera ons.

Read /Write Control Logic This circuit accepts and decodes commands from the CPU. This also allows
the status of the 8259A to be transferred onto the data bus.

Interrupt Request Register (IRR): The interrupts at IRQ input lines are handled by Interrupt Request
Register internally. IRR stores all the interrupt requests in it in order to serve them one by one on a
priority basis.
Priority Resolver This unit determines the priori es of the interrupt requests appearing
simultaneously. The highest priority is selected and stored in the corresponding bit of ISR during the
INTA pulse. The IRO has the highest priority while the IR7 has the lowest one.

In-Service Register (ISR) This stores all the interrupt requests those are being served, i.e ISR keeps a
track of the requests being served.

Interrupt Mask Register (IMR) This register stores the bits required to mask the interrupts.

Control Logic This block manages the interrupt and interrupt acknowledge signals to be sent to the
CPU for serving one of the eight interrupt requests. This also accepts interrupt acknowledge (INTA)
signal from the CPU (8086) that causes the 8259A to release vector address onto the data bus.

Cascade Buffer/Comparator This block stores and compares the ID's of all the 8259As used in the
system in a cascade configura on. The three 1/0 pins CASO - CAS2 act as output when the 8259A is
used as a master. The same pins act as input when 8259 is in slave mode.

14. Design an interface between 8086 and two 4K x 8 EPROMs and two 4K x 8 RAM chips. Select
suitable address maps.
15. Explain the opera ng modes of 8255.
16. With a neat diagram, explain the features and architecture of 8257, DMA controller
17. Explain the opera ng modes of 8254, programmable interval mer.

8253/54 can be operated in 6 different modes. In this chapter, we will discuss these opera onal
modes.

i. Mode 0 ─ Interrupt on Terminal Count

It is used to generate an interrupt to the microprocessor a er a certain interval. Ini ally the output is
low a er the mode is set. The output remains LOW a er the count value is loaded into the counter.

ii. Mode 1 – Programmable One Shot

It can be used as a mono stable mul -vibrator. The gate input is used as a trigger input
in this mode. The output remains high un l the count is loaded and a trigger is applied.

iii. Mode 2 – Rate Generator

The output is normally high a er ini aliza on. Whenever the count becomes zero,

another low pulse is generated at the output and the counter will be reloaded.

iv. Mode 3 – Square Wave Generator

This mode is similar to Mode 2 except the output remains low for half of the mer

period and high for the other half of the period.

v. Mode 4 − So ware Triggered Mode

In this mode, the output will remain high un l the mer has counted to zero, at which

point the output will pulse low and then go high again. The count is latched when the GATE

signal goes LOW. On the terminal count, the output goes low for one clock cycle then goes

HIGH. This low pulse can be used as a strobe.

vi. Mode 5 – Hardware Triggered Mode

This mode generates a strobe in response to an externally generated signal. This mode

is similar to mode 4 except that the coun ng is ini ated by a signal at the gate input, which

means it is hardware triggered instead of so ware triggered. A er it is ini alized, the output

goes high. When the terminal count is reached, the output goes low for one clock cycle.