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Overview of Electronic Packaging Evolution

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Overview of Electronic Packaging Evolution

108033113 Youtin Su
Power Mechanical Engineering Dept.
National Tsing Hua University

Abstract: In this report, we introduce the 2. 1970s


evolution of electronic packaging technology 2.1. Era of DIPs
over time, including packaging from early In 1960s, TO with leads was used for IC,
time to CSP packaging. but with the I/O pins increased, the round
body of TO was no longer suitable. The
Keywords: Packaging, TO, PTH, DIP, SIP, rectangular appearance of DIP, which can
SMT, QFP, SOP, BGA, CSP. increase I/O pins with simple layout, and the
density of the components made DIP a
Introduction: With the rapid development mainstay of the industry in 1970s.
of the semiconductor industry, IC chips
become smaller and smaller, but require 2.2. first PGA
more and more I/Os. This situation forces the Musashi Semiconductor Works is
electronic packaging technology to upgrade Hitachi Corporation's oldest and largest
and meet the requirements. Since the TOP semiconductor factory. The first PGA (pin
(transistor outline package) was first used in grid array) was developed at Musashi Works
1960s, packaging technology has been in 1974, which has 52-pin and higher
continuously innovated. Realizing the mounting efficiency.
history of package is necessary and important.
2.3. first QFP
1. 1960s As mentioned before, Musashi Works
1.1. Era of TO not only developed the first PGA but also
On December 16, 1947, William give birth to the first QFP (quad flat package)
Shockley, John Bardeen, and Walter Brattain in 1977, which was called FPP (flat plastic
succeeded in making the first transistor at package) when it was first developed. The
Bell Labs. With the application of transistors, first QFP was 14mm in width, 20mm in
TO packaging technology has begun to length, and 2mm in thickness.
develop and be used in 1960s.
3. 1980s
1.2. first DIP 3.1. Era of QFPs
The first DIP (dual in-line package) was With the demand for memory products
invented by Don Forbes, Rex Rice, and and portable devices grew, DIP with dual
Bryant Buck Rogers of Fairchild sides and the PTH (pin through hole)
Semiconductor in 1964, which had 14 leads. mechanism couldn’t meet the needs. QFP
had two major advantages. Due to the 5. 2000s
quadruple sides of QFP, the package outline 5.1 Era of Advanced Packaging
of QFP became smaller than that of DIP. It In 2000s, with the increase in the
allowed QFP to contain more I/Os in same requirement of electronic product
area. Also, with the mechanism of SMT performance and the integration of functions,
(surface mount technology), which QFP packaging become more and more advanced,
featured, it enabled us to package on both including SiP (system in package), FCBGA
sides of PCB boards. QFP has better (flip chip ball grid array), WLCSP(wafer
dimension efficiency than DIP and SOP level chip size package), 3D WLP (3
(small out-line package), which made it a dimensional wafer level package), FO-WLP
mainstream technology in 1980s. (Fan-Out wafer level package), FO-PoP
(Fan-Out package on package), Embedded
4. 1990s SiP, etc.
4.1. Era of BGA
The research of BGA (ball grid array) 6. Conclusion
started in 1960s. However, it didn’t enter the Packaging technology has been
market until early 1990s. BGA is a kind of pursuing small size and high efficiency, such
area array technology. When the demand as changing from dual sides to quadruple
came to hundreds of I/Os, the pitch between sides, or from planer to 3D. From the past to
pin needs to be smaller, which increase the the present, many packaging methods have
difficulty of production. Furthermore, the been invented, some are still in use, and some
previous fine lead was easy to bend. With have been eliminated by time, so when we try
BGA design, it eliminates the production to design a new packaging method, finding
difficulty and warping defects but also an approach can stand the test of time is our
improve the performance by low inductance best choice.
pins.
7. References
4.2. CSP concept 1. https://polymerinnovationblog.com/pol
Junichi Kasai of Fujitsu Limited, ymers-electronic-packaging-
Kawasaki, Japan, and Gen Murakami of introduction-flip-chip-packaging/
Hitachi Cable proposed the concept of CSP 2. https://anysilicon.com/semiconductor-
(chip size package) in 1992. CSP has 2 packaging-history-trends/
meaning, one for chip size package and the 3. https://ieeexplore.ieee.org/author/3795
other is chip scale package. For chip scale 8612800
package, the area of packaging is usually not 4. https://www.shmj.or.jp/english/packagi
greater than 1.2 times the area of the die. ng/pac70s.html
In late 1990s, CSP started mass production 5. https://www.youtube.com/watch?v=F
due to its less area than BGA. Y5V600ceuU

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