electronics

Article
An X-Band State Adjustable Low Noise Amplifier Using
Current Reuse Technique
Yujun Wang 1,2,3 , Lixi Wan 2 , Zhengli Wang 4 , Haitao Zhang 1,2 , Yunqian Song 1,2 , Xiaobin Zhang 1,2
and Zhi Jin 1, *

1 Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China

2 University of Chinese Academy of Sciences, Beijing 100029, China
3 Chengdu Tiger Microelectronics Research Institute Co., Ltd., Chengdu 610000, China
4 School of Automation Engineering, University of Electronic Science and Technology of China,
Chengdu 611731, China
* Correspondence: jinzhi@ime.ac.cn

Abstract: This article presents an on-chip state-adjustable 8 GHz~12 GHz low-noise amplifier (LNA).
It has two characteristics. First, an improved current reuse topology is proposed. By connecting a
small capacitor in parallel with the drain of the first-stage transistor, the bandwidth is expanded and
the in-band flatness is improved. Second, an innovative adaptive bias circuit is designed to cope
with the influence of temperature and process on the performance of the amplifier, and a design
method for on-chip adjustment of the chip state is proposed for the first time. As a result of these
technologies, the chip area is 1.1 mm × 0.8 mm, the chip provides 24.4 dB nominal gain with merely
0.75 dB noise at 10 GHz, and yields 14.5 dBm output power at 1 dB compression point (OP1dB) when
biased at 30 mA quiescent current, meanwhile, gain, OP1dB, and quiescent current can be adjusted
on-chip. This design improves the comprehensive performance of X-band LNA and provides more
flexibility for system engineers in application. The chip is fabricated using Win Semiconductors’
0.15 um InGaAs pHEMT E-mode process.

Keywords: LNA; current reuse; gain adjustable; noise

Citation: Wang, Y.; Wan, L.; Wang, Z.;

Zhang, H.; Song, Y.; Zhang, X.; Jin, Z.
An X-Band State Adjustable Low 1. Introduction
Noise Amplifier Using Current Reuse The low noise amplifier (LNA) is one of the important components in the front end of
Technique. Electronics 2023, 12, 696. the radar receiver, and its noise figure directly affects the sensitivity of the receiver. At the
https://doi.org/10.3390/ same time, it is hoped that it has a wider bandwidth to capture a wider range of signals;
electronics12030696 higher gain flatness within the operating bandwidth will ensure the dynamic range of the
Academic Editor: Yide Wang receiver is not degraded. Small size and low power consumption are the constant pursuit
of radar receivers, especially for phased array radars.
Received: 18 December 2022 From the design point of view, these parameters all affect each other. For example, the
Revised: 4 January 2023
input standing wave ratio and noise are contradictory, because when matching the input
Accepted: 13 January 2023
impedance of the transistor, the minimum noise impedance and the optimal standing wave
Published: 31 January 2023
impedance are conjugates of each other. At the same time, increasing the current can reduce
the noise, because the minimum noise of a transistor is inversely proportional to the trans-
conductance, and the trans-conductance is proportional to the drain current. The power
Copyright: © 2023 by the authors.
consumption and linearity are also contradictory. Therefore, to obtain better indicators
Licensee MDPI, Basel, Switzerland. for each parameter, many attempts have been made, and various LNA architectures have
This article is an open access article been designed.
distributed under the terms and The cascode amplifier can provide relatively flat gain and noise in broadband [1], but
conditions of the Creative Commons usually the gain is not high. It can be increased by increasing the number of stages, but
Attribution (CC BY) license (https:// the noise will also deteriorate [2]. Ref. [3], which is based on complementary metal oxide
creativecommons.org/licenses/by/ semiconductor (CMOS) technology, adopts the structure of resistive shunt-shunt feedback,
4.0/). and realizes the gain of 17 dB and the noise of 3 dB under the single-stage cascode structure

Electronics 2023, 12, 696. https://doi.org/10.3390/electronics12030696 https://www.mdpi.com/journal/electronics

Electronics 2023, 12, 696 2 of 15

by adding an L-type passive matching. Ref. [4] adds an inductor at the source stage of
the common source amplifier to achieve simultaneous noise and impedance matching.
Ref. [5] adopts noise canceling common gate LNA structure, using inductively degenerated
common source stage in parallel with common gate stage instead of common source stage.
The current reuse [6,7] architecture is widely used in CMOS circuits, especially in the case
of low power consumption. Ref. [8] uses noise cancellation and current reuse techniques
to design a 3.19 GHz~8.8 GHz LNA. Ref. [9] is based on current reuse technique and
adopts shunt-shunt resistive feedback and degenerative parallel inductance and capaci-
tance (LC) technique to achieve high gain and low noise factor for a 3.1 GHz~10.6 GHz
wideband LNA.
However, based on III-V compound technology, few articles have been reported
on LNA using current reuse architecture. For broadband LNAs, most literatures adopt
common-source (CS) or cascode structures. Ref. [10] designs an X-band LNA based on the
GaAs process using a three-stage CS structure. Ref. [11], based on GaN-on-SiC technology,
designs a medium-power LNA in which the first two stages adopt current reuse architecture
and the final stage adopt a CS structure.
The current reuse architecture can provide higher gain while ensuring lower noise, and
is small in size and low in power consumption. It is a structure suitable for receiver front-
end amplifier. However, the conventional structure cannot obtain enough bandwidth. In
this paper, the current reuse architecture is improved to expand the bandwidth. Moreover,
the front end of the receiver is usually affected by the environment because it is close to the
external antenna end, and the tape-out process will also drift, resulting in a large change
in the performance of the amplifier. This paper designs an LNA that is less affected by
temperature and process for the front end of the receiver, and whose state is still adjustable
after tape-out.

2. Principle Design
2.1. Current Reuse Architecture
Figure 1 shows the schematic of a current reuse LNA. On the direct current (DC) path,
M1 and M2 are connected in series and share current. The power supply voltage drain
drain (VDD) powers the drain of M2 through a choke inductor L4. M2 is turned on at a
certain gate voltage VG2. The current flows through the source of M2 to the drain of M1
Electronics 2023, 12, x FOR PEER REVIEW 3 of 15
through a choke inductor L2, and M1 is turned on at a certain gate voltage VG1. The source
of M1 is connected in series with the inductor L3 to improve the stability of the amplifier.

Vg2 Vdd

L4

R4 OUT

M2 C3
Vg1
C2

L2
R1

C5

IN M1

C1 L3

Figure 1.
Figure 1. Simplified
Simplified Schematic
Schematic of
of aa Current
Current Reuse
Reuse LNA.
LNA.

The current reuse architecture can be regarded as two-cascaded CS amplifiers which

share the same amount of current. The input radio frequency (RF) signal is first amplified
by M1, coupled to the gate of M2 via capacitor C2, and output after being amplified by
M2 in the second stage. C5 provides RF ground for M2.
 C1 L3

Figure 1. Simplified Schematic of a Current Reuse LNA.

Electronics 2023, 12, 696 3 of 15

The current reuse architecture can be regarded as two-cascaded CS amplifiers which

share the same amount of current. The input radio frequency (RF) signal is first amplified
The current
by M1, coupled to the reuse
gatearchitecture can be regarded
of M2 via capacitor C2, andas two-cascaded
output after beingCS amplified
amplifiers bywhich
M2 inshare the same
the second amount
stage. of current.
C5 provides RFThe inputfor
ground radio
M2.frequency (RF) signal is first amplified
by
TheM1, coupledcommon-source
first-stage to the gate of M2amplifier
via capacitor C2, andUsually,
is analyzed. output after being amplified
the alternating by M2
current
(AC)ininput
the second stage.of
impedance C5the
provides RF ground
transistor for M2.
is relatively low, and the gate needs to be con-
nected inThe first-stage
series common-source
with a resistance for inputamplifier
impedanceis analyzed.
matching,Usually, theincreases
but this alternating current
noise
(AC) input impedance of the transistor is relatively low, and
power and degrades efficiency. Adding an inductance in series with the source of the the gate needs to be connected
in series
transistor canwith a resistance
create a resistiveforinput
inputimpedance
impedancewithoutmatching, but this
adding increases
noise noise
resistors, power
which is and
degrades
called inductive efficiency. Adding an inductance
source degeneration. Figure 2a in series
is the with
basic ACthe source
circuit of the
using thetransistor
inductor can
create in
placed a resistive
series withinputtheimpedance
source of the without
device,adding noise resistors,
and Figure which is model
2b is a simplified called inductive
of its
source degeneration.
equivalent circuit, where Figure 2a is the basic AC circuit using
(the gate-drain parasitic capacitance), the inductor L placed
(the drain-source
s in series
with the source
parasitic capacitance) andof the device, and Figure 2b is a simplified model of its
(the drain-source conductive channel resistance) are ig- equivalent circuit,
where C
nored here. gd (the gate-drain parasitic capacitance), C ds ( the drain-source parasitic capacitance)
and Rds (the drain-source conductive channel resistance) are ignored here.
OUT
IN G D OUT
Vi I
IN
M1 Rd Cgs Vc
gmVc Rd
Ri

Ls s

Ls

(a) (b)
Figure 2. Common-source
Figure low-noise
2. Common-source amplifier.
low-noise (a) Basic
amplifier. AC circuit.
(a) Basic (b) Simplified
AC circuit. equivalent
(b) Simplified circuit.
equivalent circuit.

Forinput
For an an input current
current I at
I at the theofgate
gate of the transistor,
the transistor, the (theCgs
the (the gate-source
gate-source parasiticpara-
I
sitic capacitance)
capacitance) voltage = voltage V = , the
, cthe transistor’s
jωCgs transistor’s
gate-to-ground voltage is shown inisEqua-
gate-to-ground voltage shown in
tion Equation
(1): (1):
 
I 1 gm L s
V= + Ri I + jωL g I + jωLs ( I + gm Vc )= I + Ri + jωL g + jωLs + (1)
jωCgs V= + jωC + gs + ( + ) Cgs (1)
where Ri represents the input resistance of the undepleted part of the gate under channel,
gm represents the transconductance. The input impedance looking into the gate is shown
in Equation (2):  
V gm L s
1
Z= = Ri + + j ω Ls + L g − (2)
I Cgs ωCgs
From the input impedance, it can be concluded that to obtain a 50 Ω input impedance
at the operating frequency, appropriate values of L g and Ls need to be selected so that Cgs
is resonated at the operating frequency, and ( gm /Cgs ) Ls needs to be set equal to 50 Ω.

gm L s
Ri + = 50
Cgs
 

1
j ω Ls + L g − =0
ωCgs
So the series inductor Ls can be chosen to match the input resistance of the amplifier
to 50, and the inductor L g can be chosen to cancel the residual input reactance, which is
usually capacitive.

2.2. Adaptive Bias Circuit

In order to reduce the influence of temperature, process fluctuation and voltage change,
a current mirror plus source-negative feedback bias circuit is designed. The basic schematic
diagram is shown in Figure 3. Resistor R1 and transistor M1 form an input stage to convert
 to 50, and the inductor can be chosen to cancel the residual input reactance, which is
usually capacitive.

2.2. Adaptive Bias Circuit

Electronics 2023, 12, 696 In order to reduce the influence of temperature, process fluctuation and voltage 4 of 15
change, a current mirror plus source-negative feedback bias circuit is designed. The basic
schematic diagram is shown in Figure 3. Resistor R1 and transistor M1 form an input stage to
convert
currentcurrent into voltage,
into voltage, By adjusting
By adjusting gate-source
gate-source voltage
voltage , draincurrent
VGS , drain current I = = Vin −VGS. .
in R1
Here
Herethethegate
gateofofM1M1 isis connected
connected to to the
the drain,
drain, forming
formingaa diode-like
diode-likeconnection,
connection,which whichcan canbe be
equivalent
equivalenttotoaaresistor.
resistor.M2 M2isisthetheoutput
outputstage, which
stage, which converts
converts voltage
voltage into
intocurrent, its its
current, gate is
gate
used as voltage
is used as voltageinput, andand
input, its drain is used
its drain as current
is used output.
as current WhenWhen
output. the channel lengthlength
the channel mod-
ulation effecteffect
modulation is ignored and the
is ignored andinfluence of theofprocess
the influence is ignored,
the process it is considered
is ignored, that that
it is considered the
mobility μ of µthe
the mobility oftransistor
the transistor and and
the deviation of the
the deviation of unit gategate
the unit oxide capacitance
oxide capacitance C can be
ox can
ignored. ThenThen
be ignored. the circuit
the circuitcan accurately
can accuratelyreplicate the current
replicate regardless
the current of process
regardless and tem-
of process and
temperature
perature variations,
variations, and itsand its output
output currentcurrent
is only is only related
related to the
to the ratio ratio
of the of the transistor
transistor size, i.e.,
( ⁄ ) (W/L)2
size,=i.e., Iout∙ = ,(so
( ⁄ ) W/L
· Iin
as) to , so as to
stabilize thestabilize
workingthe working
state state of the amplifier.
of the amplifier.
1

Vin

V out
R1 Iin
VGS
Iout

M1 M2

Figure
Figure3.3.Schematic
Schematicof
ofcurrent
currentmirror
mirrorcircuit.
circuit.

3. Circuit Design
3.1. Process Selection
The GaAs pseudomorphic high electron mobility transistor (pHEMT) process has two
types: E-mode and D-mode. In order to obtain even lower noise, analyze the influence
of different processes on noise, the high-frequency noise figure of the transistor can be
obtained from the transistor equivalent circuit and can be expressed as Equation (3) [12]:
"  2 #
f
NF = Fp 1 + (3)
fT

where Fp represents the white noise of the transistor. It can be seen that the higher the
cut-off frequency of the transistor, the smaller the noise of the transistor itself; and the
higher the frequency of the transistor, the bigger the noise figure.
If the influence of parasitic inductance and resistance is ignored, the cut-off frequency
of the transistor depends on Cgs , Cgd and gm , can be expressed as Equation (4) [13]:

g
ft = rm (4)
C
2πCgs 1 + 2 Cgd
gs

The typical peak gm value of 0.15 µm E-mode pHEMT process is about twice that of
0.15 µm D-mode pHEMT process, however, for a transistor of the same size, the difference
of the drain capacitance and source capacitance between these two processes is negligible.
The cut-off frequency of 0.15 µm E-mode pHEMT process is about 1.2 times that of D-mode
process [14].
 = ,
(4)

The typical peak value of 0.15 μm E-mode pHEMT process is about twice that of
0.15 μm D-mode pHEMT process, however, for a transistor of the same size, the difference
Electronics 2023, 12, 696 of the drain capacitance and source capacitance between these two processes is negligible.
5 of 15
The cut-off frequency of 0.15 μm E-mode pHEMT process is about 1.2 times that of D-
mode process [14].
Thusthe
Thus theE-mode
E-modeprocess
processwith
withhigher
highertransistor
transistorcut-off
cut-offfrequency
frequencyisisadopted
adoptedfor
forthis
this
design.
design.

3.2.
3.2.Circuit
CircuitDesign
Design
3.2.1.
3.2.1. CircuitTopology
Circuit Topology
Designed
Designedusing
usingPE15
PE15process
processofofWin
WinSemiconductors,
Semiconductors,Figure
Figure44isisthe
theschematic
schematicofofthe
the
proposed X-band LNA.
proposed X-band LNA.
Vdd

C8

Vg2
First stage
L4

C6
L1 R3 R4 OUT

M2 C3

IN M1 L2
C2

C1 L3

R1
C5

Second
R2 stage
C4

R5 Gain
Vg1
adjusting

R7 R8 R9 R10

Bias circuit
R6
C7

M3 M4 M5 M6

Figure 4. Schematic of the proposed LNA.

From the cut-off frequency Formula (4), it can be seen that large trans-conductance or
small inter-electrode capacitance can yield a high cut-off frequency, which is contradictory,
because a large-size transistor has higher trans-conductance, but also larger inter-electrode
capacitance, so there should be trade-off between the gate width and parallel gate fingers
during the design to obtain better noise figures.
After careful comparative analysis, both stages use a 4 × 50 um transistor. As Figure 4
show, L1 and L2 provide DC paths, R1, R2, C4, and L1 form the feedback loop. Among
them, M3~M6 and M1 form a current mirror. In order to reduce the influence of channel-
length modulation, by connecting M3, M4, M5, and M6 in series, the gate is short-circuited,
which is equivalent to increasing L. W remains unchanged, which is equivalent to a
transistor of W/4L. The longer the channel, the higher the drain voltage, and the higher
the replication accuracy.
The current of the entire amplifier depends mainly on the first-stage, and an on-chip
voltage divider is used to adjust the first-stage gate voltage, thereby through controlling
the bias current of the first-stage transistor, the current of the amplifier is controlled.
The specific current trimming function is achieved by reserving four pads on the
chip and bonding the pads to either the power supply or ground to adjust the ratio of the
potential divider.
The bias circuit helps to resist the variation of the quiescent operating point caused by
process and temperature variation. A resistor of about 1 kΩ is connected in series between
the bias circuit and the gate of the first stage transistor to reduce the noise caused by the
bias circuit. Meanwhile, an extra pad is reserved for the gate of the second stage transistor,
 voltage divider is used to adjust the first-stage gate voltage, thereby through controlling
the bias current of the first-stage transistor, the current of the amplifier is controlled.
The specific current trimming function is achieved by reserving four pads on the chip
and bonding the pads to either the power supply or ground to adjust the ratio of the po-
tential divider.
Electronics 2023, 12, 696 The bias circuit helps to resist the variation of the quiescent operating point caused 6 of 15
by process and temperature variation. A resistor of about 1 kΩ is connected in series be-
tween the bias circuit and the gate of the first stage transistor to reduce the noise caused
by the
and the bias circuit.point
operating Meanwhile, an extracan
of the transistor padbeisadjusted
reservedby forexternally
the gate of the second
providing the stage
gate
transistor, and the operating point of the
voltage, which can be used as a debugging method. transistor can be adjusted by externally provid-
ing the gate voltage, which can be used as a debugging method.
3.2.2. Matching Design
3.2.2.First
Matching Design
select the intermediate frequency point and find the optimal source and load
impedance. In the design process,
First select the intermediate it is necessary
frequency to find
point and findout
the the best noise
optimal sourcematching
and load
impedance
impedance.and best power
In the design matching
process, impedance,
it is necessary drawout
to find thethe
circular diagram
best noise as shown
matching im-
in Figure and
pedance 5, and
thefind
best the balance
power pointimpedance,
matching of the two in the the
draw circular diagram.
circular diagram Asasshown
shownin in
Figure
Figure 5,5, the
andimpedance is about
find the balance point63of+the
j50,two
andinthen the impedance
the circular diagram.matching
As showndesign
in Figureis
carried out.
5, the impedance is about 63 + j50, and then the impedance matching design is carried out.

0.4

3.0

0.3

4.0

0.2 5.0

-0.2 -5.0

-4.0
.3
-0
.0
-3

.4
-0

Figure5.5.Gain
Figure Gainand
andNoise
Noisecircles
circlesdiagram.
diagram.

3.2.3. Gain Design

As the gain of the microwave transistor decreases with frequency [15], so the gain
in the entire frequency band will show a negative slope trend. To obtain the best noise
and gain matching over the entire frequency band, the matching parameters need to be
adjusted, some measures can be taken to improve the gain at the high frequency end.
(1) Influence of feedback inductance
L1, C4, and R2 form the feedback circuit of the first-stage amplifier, which is used to
widen the frequency band. The easier the frequency band passed by the feedback circuit,
the smaller the output power. Therefore, the in-band flatness can be optimized by adjusting
the feedback. For example, the inductance of the front stage L1 can be increased. At this
time, the LC resonance frequency decreases, and the input voltage standing wave ratio
(VSWR) will move to the low end, as shown in Figure 6.
(2) Architecture improvements
In addition, the traditional current reuse architecture is improved. A small capacitor is
connected to the ground in parallel with the drain of the first-stage transistor. The capacitor
acts as a channel for high frequency, so the high frequency part is less fed back, which can
suppress high-frequency feedback, thereby improving the high-frequency output gain and
expanding the bandwidth.
It can be seen from Figure 6 that before the improvement (without C6), the gain of the
traditional architecture starts to decrease after the frequency reaches 10 GHz, and the gain
decreases by about 3 dB when the frequency reaches 12 GHz. After the improvement (with
 gain matching over the entire frequency band, the matching parameters need to be ad-
justed, some measures can be taken to improve the gain at the high frequency end.
(1) Influence of feedback inductance
L1, C4, and R2 form the feedback circuit of the first-stage amplifier, which is used to
Electronics 2023, 12, 696 widen the frequency band. The easier the frequency band passed by the feedback circuit, 7 of 15
the smaller the output power. Therefore, the in-band flatness can be optimized by adjust-
ing the feedback. For example, the inductance of the front stage L1 can be increased. At
this
C6),time,
underthetheLC resonance
new frequency
architecture decreases,
the gain decreasesand thelittle
very inputwhen
voltage
the standing wave
high frequency
ratio
band(VSWR)
reaches will moveand
12 GHz, to the
the low end, asband
frequency shown in Figure 6. extended to 12 GHz.
is successfully

Figure
Figure6.6.Effect
Effectof
ofinductance
inductanceon
onGain
Gainand
andInput
Inputreturn
returnloss.
loss.

(3) Architecture
(2) Influence of improvements
inter-stage capacitance
In addition,
There the traditional
are other influencingcurrent
factors,reuse architecture
such as increasing is improved.
the inter-stageA capacitance,
small capacitor
and
isthe
connected
noise can toalso
thebe
ground in parallel
reduced. However,with the
the VSWRdrainbecomes
of the first-stage
worse, as transistor.
shown in The ca-7;
Figure
Electronics 2023, 12, x FOR PEER REVIEW 8 of 15
pacitor acts asthe
In addition, a channel for high
source stage frequency,
grounding wiresocan
thebe
high frequency
shortened, butpart
the is less fed
VSWR back,
becomes
which
worse can
also.suppress high-frequency feedback, thereby improving the high-frequency out-
put gain and expanding the bandwidth.
It can be seen from Figure 6 that before the improvement (without C6), the gain of
the traditional architecture starts to decrease after the frequency reaches 10 GHz, and the
gain decreases by about 3 dB when the frequency reaches 12 GHz. After the improvement
(with C6), under the new architecture the gain decreases very little when the high fre-
quency band reaches 12 GHz, and the frequency band is successfully extended to 12 GHz.
(3) Influence of inter-stage capacitance
There are other influencing factors, such as increasing the inter-stage capacitance,
and the noise can also be reduced. However, the VSWR becomes worse, as shown in Fig-
ure 7; In addition, the source stage grounding wire can be shortened, but the VSWR be-
comes worse also.

(a) (b)
Figure
Figure 7. 7.Effect
Effectofof inter-stage
inter-stage capacitance
capacitance onon S-parameters
S-parameters (a)(a)
andand
NFNF (b).
(b).

(4)(4) Influence
Influenceofofsource
sourceresistance
resistance
Thesource
The sourceofofthe
thefirst
firststage
stageamplifier
amplifierisisconnected
connectedtotothe
thenegative
negativefeedback
feedbackcircuit
circuittoto
the ground, and the small-signal model is analyzed as shown in Figure 8. When therethere
the ground, and the small-signal model is analyzed as shown in Figure 8. When is nois
no source resistor, calculate the voltage
source resistor, calculate the voltage gain: gain:
𝐴 = −𝑔 ∗ 𝑅 , (5)
Av =𝑣 − gm ∗𝑚Rd 𝑑 (5)
where
𝑊
𝑔𝑚 = μ ∗ 𝐶𝑜𝑥 ∗ ∗ (𝑉𝐺𝑆 − 𝑉𝑡ℎ ), (6)
𝐿

with source resistors, calculate the voltage gain:

𝑔𝑚∗(𝑟𝑜 ∥𝑅𝑑 ) 𝑔𝑚∗𝑅𝑑
𝐴𝑣 = − ≈ . (7)
1+𝑔𝑚 ∗𝑅𝑠 1+𝑔𝑚 ∗𝑅𝑠
 the ground, and the small-signal model is analyzed as shown in Figure 8. When there is
no source resistor, calculate the voltage gain:
=− ∗ , (5)

Electronics 2023, 12, 696 where 8 of 15

=μ∗ ∗ ∗( − ), (6)
with source resistors, calculate the voltage gain:
where
∗(W∥ ) ∗
gm = µ=∗C −ox ∗ ∗ (V
≈GS − Vth ). (6)
(7)
L∗ ∗

with When
sourcethe
resistors, calculate
small-signal the voltage gain:changes due to the change of the mobility
trans-conductance
μ of the transistor and the capacitance of the unit gate oxide, the state of the amplifier
will change, and this change is gm ∗ (rsmall
relatively o k Rddue m ∗influence
) to gthe Rd of source resistor ( (7)
),
Av = − ≈
1 + g m ∗ R s 1 + g m ∗ R s
and the larger the value of , the smaller the state change of the amplifier.

Vin Vout

Vc g m Vc ro Rd

RLs

Figure 8. Small-signal model with source resistance.

When
As the small-signal
shown in Figure 9,trans-conductance
it is assumed here changes
that thedue to the change
conduction of the mobility
parameter , com-µ
of the transistor
posed of μ and and , deviates by aboutC20%.
the capacitance ox of It
the
canunit gate that
be seen oxide, the Rs
when state of the amplifier
increases, the gain
will change,
of the andbecomes
amplifier this change is relatively
smaller, but thesmall due topoint
operating the influence of source
of the amplifier resistor
is more (Rs ),
stable,
and the larger the value of R
and the change of the amplifier s , the smaller the state change of the amplifier.
gain with process and temperature is smaller.
As shown in Figure 9, it is assumed here that the conduction parameter Kn , composed
of µ and Cox , deviates by about 20%. It can be seen that when Rs increases, the gain9ofofthe
Electronics 2023, 12, x FOR PEER REVIEW 15
amplifier becomes smaller, but the operating point of the amplifier is more stable, and the
change of the amplifier gain with process and temperature is smaller.

Figure
Figure 9.
9. Effect
Effect of
of source
source resistance
resistance on
on Gain.
Gain.

3.2.4. Stability
3.2.4. Stability Design
Design
The source
The source of
of the
the first
first stage
stage transistor
transistor is
is connected
connectedwith
withaamicro-strip
micro-stripline
lineas
asaadegen-
degen-
eration inductor to improve the stability of the amplifier, which also benefits
eration inductor to improve the stability of the amplifier, which also benefits the input the input
match. The
match. Theeffect
effectofofadding
adding this
this series
series micro-strip
micro-strip on on
the the stability
stability factor
factor is simulated
is simulated and
and calculated,
calculated, as Figure
as Figure 10 shows.
10 shows. After adding
After adding a micro-strip,
a micro-strip, the stability
the stability factor Kfactor K is
is greater
than 1, and ｜Δ｜is less than 1, according to Rollet’s condition [16], the amplifier is uncon-
ditional stability.
 Figure 9. Effect of source resistance on Gain.

3.2.4. Stability Design

The source of the first stage transistor is connected with a micro-strip line as a degen-
Electronics 2023, 12, 696 9 of 15
eration inductor to improve the stability of the amplifier, which also benefits the input
match. The effect of adding this series micro-strip on the stability factor is simulated and
calculated, as Figure 10 shows. After adding a micro-strip, the stability factor K is greater
greater
than than｜Δ｜is
1, and 1, and |∆|is less1,than
less than 1, according
according to Rollet’s
to Rollet’s condition
condition [16], the[16], the amplifier
amplifier is uncon- is
unconditional
ditional stability.
stability.

Figure
Figure 10.
10. Stability
Stability factor
factor simulation
simulation and
and calculation.
calculation.

3.2.5. Final
3.2.5. Final Layout
Layout
Electronics 2023, 12, x FOR PEER REVIEW AllAll performance
performance parameters
parametersaffect
affect each
each other
other [17].
[17]. The
Thetrend
trend is
is that
that the
the more
more slope
10 slope
of 15
of the gain, the better the VSWR. It is necessary to consider all parameters in a
of the gain, the better the VSWR. It is necessary to consider all parameters in a balanced balanced
manner and
manner and find
find the
the optimal
optimal combination.
combination. The
The photograph
photograph is is shown
shown in in Figure
Figure 11.11.

Figure 11. Die photograph of the proposed LNA.

Figure 11. Die photograph of the proposed LNA.

4.4.Experimental
ExperimentalResults
Results
4.1. Test Methods and Results
4.1. Test Methods and Results
TheS-parameters
The S-parametersmeasurement
measurementisiscarried
carriedoutouton
onaaprobe
probeplatform
platformwithwithaacalibrated
calibrated
vector network analyzer. When the bias adjusting pads are left open, by default thethe
vector network analyzer. When the bias adjusting pads are left open, by default chipchip
is
biased with 5 V 30 mA at room temperature. The input power of the VNA is set to −20 dBm,to
is biased with 5 V 30 mA at room temperature. The input power of the VNA is set
−20 dBm,
which which guarantees
guarantees enough SNR enough
while SNR while
keeping thekeeping
output the output
power power
within the within the linear
linear region of
region
the VNAofreceiver.
the VNA receiver. data
Measured Measured
(dotteddata (dotted
lines) lines) andresults
and simulation simulation
(solidresults (solid
lines) show
lines)conformance.
good show good conformance. As shown
As shown in Figure ininput
12, the Figure 12, the
return lossinput return
is less lossdB,
than −10 is less
andthan
the
− 10 dB, and the output return loss is less than − 17 dB within the entire operation
output return loss is less than −17 dB within the entire operation frequency range. The meas- frequency
ured gain is about 24.4 dB with excellent flatness, and can well extend its operation fre-
quency down to 6 GHz. Figure 13 shows the measured stability factor curve.
 4.1. Test Methods and Results
The S-parameters measurement is carried out on a probe platform with a calibrated
vector network analyzer. When the bias adjusting pads are left open, by default the chip is
biased with 5 V 30 mA at room temperature. The input power of the VNA is set to −20 dBm,
which guarantees enough SNR while keeping the output power within the linear region of
Electronics 2023, 12, 696
the VNA receiver. Measured data (dotted lines) and simulation results (solid lines) 10 of 15
show
good conformance. As shown in Figure 12, the input return loss is less than −10 dB, and the
output return loss is less than −17 dB within the entire operation frequency range. The meas-
range.
ured Theismeasured
gain about 24.4 gain
dB iswith
about 24.4 dBflatness,
excellent with excellent flatness,
and can and can
well extend its well extendfre-
operation its
operation
quency frequency
down to 6 GHz.down to 613
Figure GHz. Figure
shows 13 shows stability
the measured the measured
factor stability
curve. factor curve.

Electronics 2023, 12, x FOR PEER REVIEW 11 of 15

Figure
Figure 12.
12. Simulated
Simulated and
and measured
measured S-parameters
S-parameters of
of the
the proposed
proposed LNA.
LNA.

Figure
Figure 13.
13. Measured
Measured stability
stability factor
factor of
of the
the proposed
proposed LNA.
LNA.

Because the VNA

Because VNA the theprobe
probeplatform
platformequipped
equippedhas hasnononoise measurement
noise measurement option, the
option,
die is assembled onto a test fixture shown in Figure 14, then the noise figure
the die is assembled onto a test fixture shown in Figure 14, then the noise figure is meas- is measured
with with
ured a dedicated noise noise
a dedicated analyzer. Finally,
analyzer. the insertion
Finally, loss of loss
the insertion the input
of theRF connector
input and the
RF connector
micro-strip
and line is de-embedded
the micro-strip as shownas
line is de-embedded in shown
Figure 15, the noise
in Figure 15,figure is less
the noise than is
figure 0.8less
dB
within
than 0.8the
dBentire
withinfrequency
the entire range, and is range,
frequency as low and
as 0.65 dB@6
is as low GHz. It also
as 0.65 dB@6showsGHz.that the
It also
outputthat
shows 1 dBthe
gain compression
output 1 dB gainpoint is between point
compression 14 dBm and 15.6 dBm
is between 14 dBmat room temperature,
and 15.6 dBm at
which is fair enough for a LNA biased with only 30 mA. Figure
room temperature, which is fair enough for a LNA biased with only 30 mA. Figure 1616 shows the measured
two-tone
shows thetest curve, and
measured the OIP3
two-tone test of the LNA
curve, canOIP3
and the be calculated
of the LNAto be
can26.56 dBm.
be calculated to be
26.56 dBm.
The feasibility of the proposed LNA is commonly entrenched using a pertinent figure
of merit (FoM) that calibrate its accomplishment. The FoM is included with band-width
(BW), gain, output power at 1 dB compression point, noise temperature (noise figure),
power consumption, and area to meet wide-band low power system target given as Equa-
Electronics 2023, 12, x FOR PEER REVIEW 12 of 15
Electronics 2023, 12, x FOR PEER REVIEW 12 of 15
Electronics 2023, 12, x FOR PEER REVIEW 12 of 15

Electronics 2023, 12, 696 11 of 15

Chip area(mm2) 1.5 × 1 3.0 × 1.5 2.1 × 1.2 0.03276 0.53 0.77 2.31 1.5 × 1.5 1.3 × 1.3 1.68 × 0.49 1.1 × 0.8
Chip area(mm2 2) 1.5 × 1 3.0 × 1.5 2.1 × 1.2 0.03276 0.53 0.77 2.31 1.5 × 1.5 1.3 × 1.3 1.68 × 0.49 1.1 × 0.8
Chip area(mm
FoM ) 1.50.02 ×1 3.00.004
× 1.5 2.10.07
× 1.2 0.03276
0.14 0.53
0.014 0.77
0.03 2.31
0.03 1.5 ×0.04
1.5 1.3 ×0.02
1.3 1.68 × 0.2
0.49 1.1 × 0.38
0.8
FoM 0.02 0.004 0.07 0.14 0.014 0.03 0.03 0.04 0.02 0.2 0.38
FoM 0.02 0.004 0.07 0.14 0.014 0.03 0.03 0.04 0.02 0.2 0.38

Figure
Figure 14.Test
Figure14.
14. Test
Test fixture
fixture
fixture of
ofof
thethe proposed
proposed
the LNA.
LNA.
proposed LNA.
Figure 14. Test fixture of the proposed LNA.
P1dB/dBm

NF/dB

Figure
Figure 15.NF
Figure15.
15. NF
NF and
NFand
and P1dB
andP1dB
P1dB
P1dB comparison
comparison
comparison
comparison curve
curve
curve
curve of
ofof
the the
ofthe
theproposed
proposed
proposed
proposed LNA.
LNA.
LNA.
LNA.
Amplitude/dBm

Figure16.
Figure 16.Measured
MeasuredOIP3
OIP3curve
curveof
ofthe
theproposed
proposedLNA.
LNA.
Figure16.
Figure 16.Measured
Measured OIP3
OIP3 curve
curve of the
of the proposed
proposed LNA.
LNA.
Electronics 2023, 12, 696 12 of 15

The feasibility of the proposed LNA is commonly entrenched using a pertinent fig-
ure of merit (FoM) that calibrate its accomplishment. The FoM is included with band-
width (BW), gain, output power at 1 dB compression point, noise temperature (noise
figure), power consumption, and area to meet wide-band low power system target given
as Equation (8) [18,19]:

BW[GHz]∗Gain[dB]∗OP1dB[mW]
FoM = (8)
Te [K]∗PDC [mW]∗Area[mm2 ]

The larger the value, the better the overall performance. Table 1 encapsulates the
measured performance of the proposed LNA and compares it with advanced LNAs that
have similar frequency bands. It is clear from Table 1 that the higher values of FoM of the
proposed LNA prove better in comparison with other LNAs.

Table 1. X band LNA Performance comparison.

[10] [11] [20] [21] [7] [8] [22] [23] [24] [25] This Work
Year 2009 2018 2016 2019 2014 2017 2019 2020 2021 2022 2022
GaAs 65 130 180 InGaAs
Tech. 0.07-GaAs 0.25-GaN 0.1-GaAs 0.18-GaAs 0.25-GaAs 0.15-GaAs
pHEMT nm-CMOS nm-CMOS nm-CMOS pHEMT
Design Current- Current- Current- Current- Current-
CS Cascode CS CS Cascode Cascode
method reuse+CS reuse reuse reuse reuse
Frequency
7~11 8~12 6~11 3.1~4.7 6.5~9 2.8~7.5 7.5~10.5 8~12 3~12 4~15 8~12
(GHz)
Gain (dB) 29 25 25 17.6 23 9 28 22.5 16.9 17~21 24.4
NF 1.6~2.1/
(dB)/K 1/75 2.5/225 1.3/101 2.2/191 3.2/316 3.6/374 1.4/110 1/75 2.9/275 0.75/55
129~180
OP1dB
(dBm)/mW
1/1.26 20/100 16/39.8 −15.2/0.03 −5.4/0.29 −1.5/0.71 10/10 10/10 8.9/7.76 14/25.1 14.5/28.2

VSWR 1.8 1.4 3 / 1.2 / 1.7 / 1.9 2.0 1.4

Power
(mW) 62.2 2600 273 0.97 7.15 3.8 125 126 127 266.5 150

Chip area
1.5 × 1 3.0 × 1.5 2.1 × 1.2 0.03276 0.53 0.77 2.31 1.5 × 1.5 1.3 × 1.3 1.68 × 0.49 1.1 × 0.8
(mm2 )
FoM 0.02 0.004 0.07 0.14 0.014 0.03 0.03 0.04 0.02 0.2 0.38

4.2. Gain Adjustment Effect

Four pads are reserved on the chip as shown in Figure 11, and the operating point
of the chip can be adjusted by bonding these reserved pads to VDD or GrouND (GND),
and then the gain and current of the chip can be adjusted. This adjustment method can be
achieved through a simple gold wire. Bonding is performed on-chip, and no additional
power supply is required.
When the reserved pads are all floating, the typical current is 30 mA. When VG1C
is bonded to the VDD pad, the current will increase by 8 mA. At this time, the gain will
increase by 1.5 dB, and the P1dB will increase by 1.5 dB; when VG1D is bonded to the VDD
pad, the current will increase by 3.5 mA. At this time, the gain is increased by 0.9 dB, and
the P1dB is increased by 0.7 dB; when VG1A is bonded to the GND pad, the current will
decrease by 4 mA. At this time, the gain will be decreased by 1.0 dB, and the P1dB will
be decreased by 1.0 dB; when VG1B is bonded to the GND pad, the current will decrease
by 8.5 mA. At this time, the gain will be decreased by 1.8 dB, and the P1dB is reduced by
2.6 dB. The above adjustments have little effect on noise and standing waves.
In addition, the chip also reserves a gate voltage control pad VG2. The VDD voltage
divide ratio across the current reuse architecture can be adjusted by applying a voltage to
pad VG2 from an external power supply.
Table 2 takes the frequency point 10 GHz as an example to show the effect of the gain
adjustment by different bonding scheme, of course, more gain states can also be obtained
through different combinations of bonding schemes.
 Electronics 2023, 12, 696 13 of 15

Table 2. Chip gain under different bonding schemes at 10 GHz.

Bonding Way Gain (dB) OP1dB (dBm) NF (dB) Current (mA)

VG1B pad bond to GND pad 22.92 13.1 0.71 21.3
VG1A pad bond to GND pad 23.5 14.7 0.712 26.1
Floating all adjustable pads 24.4 15.7 0.716 30
VG1D pad bond to VDD pad 25.4 16.46 0.722 33.5
VG1C pad bond to VDD pad 26.18 17.3 0.734 38

In addition, thanks to the structure of current reuse, the two-stage amplifiers are
connected in series on DC, dividing VDD to the two-stage transistors. The amplifier
supports a wider power supply voltage range, which can support +4 V to +6.5 V. When the
power supply changes, the amplifier state is shown in the Table 3 below.

Table 3. Chip state under different voltages at 10 GHz.

Power Supply (V) Gain (dB) Output P1dB (dBm) NF (dB) Current (mA)
+4.0 23.3 13.1 0.736 22.3
+5.0 24.4 15.7 0.716 30
+6.5 25 18.5 0.725 41.5

4.3. Temperature Effect

Usually, the performance of a chip changes greatly with temperature. Thanks to the
Electronics 2023, 12, x FOR PEER REVIEW 14 of 15
active bias circuit, the gain variation is only about 1.5 dB and the current drift is only about
3 mA within the operating temperature range of −40 ◦ C to +85 ◦ C, as shown in Figure 17.

Figure
Figure 17.
17. Gain vs. temperature
Gain vs. temperaturecurve
curveofofthe
theproposed
proposed LNA.
LNA.

Table 44 gives
Table givesan
anoverview
overviewofofthe
thechip performance.
chip performance.

Table 4. Measured performance summary.

Process: PE15
Frequency: 8 GHz~12 GHz
Gain: 24.4 ± 0.1 dB
NF: 0.75 dB
OP1dB: greater than 14.5 dBm
Electronics 2023, 12, 696 14 of 15

Table 4. Measured performance summary.

Process: PE15
Frequency: 8 GHz~12 GHz
Gain: 24.4 ± 0.1 dB
NF: 0.75 dB
OP1dB: greater than 14.5 dBm
Power consumption: 150 mW (5 V supply)
Area: 1.1 mm × 0.8 mm

5. Conclusions
An 8 GHz~12 GHz LNA is implemented based on current reuse architecture with PE15
process. It features ultra-low noise figure, high gain and extremely low power consumption,
which is suitable for radar receiver front-end. This design has three innovations:
Firstly, the current reuse architecture is improved in this paper. By connecting a small
capacitor in parallel with the drain of the first-stage transistor, the function of expanding
the frequency band is achieved and the flatness of the X-band LNA is improved.
Secondly, an innovative bias circuit is designed based on GaAs process. The first point
is to improve the accuracy of current replication by short-circuiting the gates of multiple
transistors, which is equivalent to increasing the gate length. The second point is to improve
the linearity under large signal by adding an RC circuit in the bias circuit.
Thirdly, a design method for on-chip state adjustment is proposed. Through different
pad-bonding combinations the gain adjustment range of the chip is greater than 3 dB, the
OP1dB adjustment range is greater than 4 dB, and the current adjustment range is greater
than 16 mA.

Author Contributions: Writing—original draft preparation, Y.W.; resources, L.W.; supervision, Z.W.;
data curation, H.Z., Y.S. and X.Z.; project administration, Z.J. All authors have read and agreed to the
published version of the manuscript.
Funding: This research received no external funding.
Conflicts of Interest: The authors declare no conflict of interest.

References
1. Chen, K.; Lin, Y.-S.; Lu, S.-S. Analysis and design of a 1.6-28-GHz compact wideband LNA in 90-nm CMOS using a π-match
input network. IEEE Trans. Microw. Theory Tech. 2010, 58, 2092–2104. [CrossRef]
2. He, Q.; Feng, M. Low-power, high-gain, and high-linearity SiGe BiCMOS wide-band low-noise amplifier. IEEE J. Solid State
Circuits 2004, 39, 956–959.
3. Li, Z.; Liu, S.; Zhang, C.; Zhuang, Y. A 2–20GHz SiGe HBT single-stage cascode LNA with linearity enhancement. Microelectron. J.
2019, 86, 130–139. [CrossRef]
4. Mahmoudidaryan, P.; Medi, A. Codesign of Ka-Band integrated limiter and low noise amplifier. IEEE Trans. Microw. Theory Tech.
2016, 64, 2843–2852. [CrossRef]
5. Sabzi, M.; Kamarei, M.; Razban, T.; Mahe, Y. New noise cancellation topology in common-gate LNAs. Microelectron. J. 2020, 100,
104800. [CrossRef]
6. Noh, N.; Hashim, A.; Tan, K.; Yong, Y. Design and analysis of the Current Reuse Technique and Folded Cascode Power
Constrained Simultaneous Noises and Input Matching LNAs with distributed and lumped parasitic. In Proceedings of the 2010
IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, Malaysia, 6–9 December 2010.
7. Li, Z.; Sun, L.; Huang, L. A 6-9 GHz UWB balun-LNA employing current-reuse with preamplifier and CCC buffer. Analog. Integr.
Circuits Signal Process. 2014, 79, 291–299. [CrossRef]
8. Reddy, K.V.; Sravani, K.; Prashantha Kumar, H. Low power ultra wide-band balun LNA using noise cancellation and current-reuse
techniques. Microelectron. J. 2017, 61, 114–122. [CrossRef]
9. Ragheb, A.N.; Fahmy, G.A.; Ashour, I.; Ammar, A. A 3.1-10.6 GHz Low Power High Gain UWB LNA Using Current Reuse
Technique. In Proceedings of the 2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012), Kuala
Lumpur, Malaysia, 12–14 June 2012.
Electronics 2023, 12, 696 15 of 15

10. Kettle, S.B.D. Broadband X-band low noise amplifier based on 70 nm GaAs metamorphic high electron mobility transistor
technology for deep space and satellite communication networks and oscillation issues. IET Microw. Antennas Propag. 2010, 4,
1208–1215.
11. Colangeli, S.; Vittori, M.; Ciccognani, W.; Limiti, E. Three-stage GaN-on-SiC medium-power LNA exploiting a current-reuse
architecture. Int. J. RF Microw. Comput. Aided Eng. 2018, 28, e21423. [CrossRef]
12. Chen, X.; Zhang, Q. Transistor Principle and Design; Electronic Industry Press: Beijing, China, 2007; pp. 242–244.
13. Dambrine, G.; Cappy, A.; Heliodore, F.; Playez, E. A new method for determining the FET small-signal equivalent circuit. IEEE
Trans. Microw. Theory Tech. 1988, 36, 1151. [CrossRef]
14. Win Semiconductors. WIN PE15-00 and PL15-12 Technology Summary; TS1703001/TS1205001; Win Semiconductors: Taiwan, China,
2017/2020; p. 3/1.
15. Robertson, I.D.; Lucyszyn, S. RFIC and MMIC Design and Technology; The Institution of Engineering and Technology: London, UK,
2001; pp. 184–190.
16. Pozar, D.M. Microwace Engineering; Hamilton Printing: New York, NY, USA, 2011; pp. 586–587.
17. Awang, Z. “Microwave Systems Design” Chapter 1, S-Parameters and Circuit Responses; Springer Verlag: Berlin, Germany, 2013; pp.
5–7.
18. Brederlow, R.; Weber, W.; Sauerer, J.; Donnay, S.; Wambacq, P.; Vertregt, M. A mixed-signal design roadmap. IEEE Des. Test. 2001,
18, 34–46. [CrossRef]
19. Linten, D.; Thijs, S.; Natarajan, M.; Wambacq, P.; Jeamsaksiri, W.; Ramos, J.; Mercha, A.; Jenei, S.; Donnay, S.; Decoutere, S. A 5-ghz
fully integrated esd-protected low-noise amplifier in 90-nm rf cmos. IEEE J. Solid-State Circuits 2005, 40, 1434–1442. [CrossRef]
20. Le, P.; Thong, V.; Binh, P. Broadband GaAs pHEMT LNA Design for T/R Module application. Vietnam. J. Sci. Technol. 2016, 54,
584. [CrossRef]
21. Kishore, K.H.; Rajan, V.S.; Sanjay, R.; Venkataramani, B. Reconfigurable low voltage low power dual-band self-cascode current-
reuse quasidifferential LNA for 5G. Microelectron. J. 2019, 92, 104602. [CrossRef]
22. Sabzi, M.; Medi, A. Analysis and design of multi-stage wideband LNA using simultaneously noise and impedance matching
method. Microelectron. J. 2019, 86, 97–104. [CrossRef]
23. Laxmi, M.; Nagaveni, H.; Karthik, S. Compact X Band MMIC Low Noise Amplifier for Radar Applications. In Proceedings of the
2020 IEEE Internaional Conference for Innovation in Technology (INOCON), Bengaluru, India, 6–8 November 2020.
24. El Bakkali, M.; Touhami, N.A.; Elhamadi, T.-E.; Elftouh, H.; Lamsalli, M. High gain 0.18 µm-GaAs MMIC cascode-distributed
low-noise amplifier for UWB application. Microelectron. J. 2021, 108, 104970. [CrossRef]
25. Liu, W.; Lei, H.; Liu, H.; Jiang, P. Design of an ultra-wideband LNA using transformer matching method. Integration 2022, 87,
122–136. [CrossRef]

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