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A 0.6-V Low-Power Variable-Gain LNA in

0.18-μm CMOS Technology
Jian-Yu Hsieh, and Kuei-Yu Lin

signal, variable gain can improve linearity correspondingly

Abstract—A 0.6-V low-power variable-gain LNA by using and avoid signal distortion and poor bit error rate (BER). There
0.18-μm CMOS process has been proposed. By using a tunable are a lot of variable-gain LNAs has been proposed [4]-[7].
negative-feedback capacitor technology, variable gain can be These papers control the biased voltages for achieving gain
achieved. Moreover, forward body biasing, input feedback
capacitor, current-reuse and multiple-gate topologies are utilized variation. However, it will result in the biased current variation
for realizing low power consumption, small chip area, and high which might let the biased transistors leave perfect operation
linearity. The measured results show the power gain and IIP3 region. When the transistors go into the triode region, the
ranges from 4 dB to 10 dB and 0 dBm, respectively at 2.8 GHz. isolation will degrade. In this paper, a tunable
The power consumption is 0.6 mW. negative-feedback capacitor technology has been proposed for
solving the problem. The capacitance of the proposed tunable
Index Terms—LNA, CMOS, variable gain, high linearity, low
negative-feedback capacitor can be controlled for adjusting the
power consumption.
gain without cost more power. Moreover, an input feedback
capacitor has been proposed for helping the input impedance
I. INTRODUCTION matching. The introduction of the input feedback capacitor can
reduce the size of the inductors and the transistors. Hence, the
R ecently, low-power circuit design has become an
important topic because of the energy-hungry components
chip area and power consumption can be lowered.
This paper is organized as follows. Section II presents the
of the advanced portable devices. The radio-frequency (RF)
circuit architecture and design consideration of the LNA.
circuits generally cost major power consumption of the portable
Sections III shows the measured results. Section IV concludes
devices, especially low-noise amplifiers (LNAs). LNAs require
this paper.
efficient power consumption for executing signal amplifying
and noise suppressing. Hence, there exists a trade-off between
II. CIRCUIT ARCHITECTURE AND DESIGN CONSIDERATION
power consumption and power gain (S21). The design
parameters of LNAs include low noise figure (NF), high A schematic of the proposed LNA in 0.18-μm CMOS
linearity (IIP3), high S21 and low power consumption. For technology has shown in Fig. 1. The input impedance matching
lowering power consumption, a lot of methods, such as body network of the LNA is consist of inductors (LG and LS),
forward biasing [1], current-reuse [2] and folded topologies, capacitors (CG and CF), a resistor RG and transistors (M1 and
have been proposed. These works can achieve great M2). In general, LG requires a large chip area to achieve input
performance. For linearity improvement, the power matching. By using the feedback capacitor CF, an input
consumption can be increased. However, it is not suitable for impedance ZIN can be derived as follows [8]:
low-power design. Hence, multiple-gate topology has been g m LS  1 
ZIN = + j  LG + LS − , (1)
developed [3]. The third-order harmonic can be eliminated by Cgs + CF  Cgs + CF 

this way. Generally, the variable-gain function is used after the
where gm and Cgs are the transconductance and
signal down conversion in a receiver. Moreover, variable gain
gate-to-source capacitance of M1 and M2, respectively. In order
has become an important function for an LNA recently. Large
to achieve impedance matching, the real part of Eq. (1) must be
amplitude of the input radio-frequency (RF) signal might result
50 Ω and the imaginary part must be zero. Thus, according to
in the saturation of the LNA and following circuits in the
Eq. (1), using a larger CF results in smaller Cgs, gm, and LG
receiver. Depending on different amplitude of the input RF
values, thereby reducing the sizes of M1, M2 and LG as well as
the power and area consumptions. Smaller sizes of M1 and M2
Manuscript received August 10, 2018. This work was supported in part by the result in lower power consumption. The current-reuse M3 can
National Science Council of the R.O.C. under Contract MOST 107-2221-E-197 help improve the gain. Smaller LG results in smaller chip area.
-032.
J. Y. Hsieh is with the Department of Electronic Engineering, National Ilan
Moreover, the forward body biasing is applied to the chip to
University, 260, Taiwan (e-mail: jyhsieh@niu.edu.tw). reduce VT of transistors in the entire LNA. The reduction of VT
Kuei-Yu Lin is with the Department of Electronic Engineering, National Ilan realizes low-VDD operation and provide more flexibility on the
University, 260, Taiwan.

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VDD 20

R1 LO 10
R4

Power Gain (dB)

RFout
R2 CO 0
M3 VB2
R6

M4 -10
CM CB
LM VB2 = 0.6 V
-20 VB2 = 0.3 V
R3
CG LG VB2 = 0 V
RFin M1 M2
-30
CT
R5 1 2 3 4 5
Frequency (GHz)
VB1
Fig. 4. The measured power gain of the proposed LNA.
CF
LS 10 -20

Fig. 1. The schematic of the proposed LNA. 0

-30

Return Loss (dB)

Isolation (dB)
Znf
LG R Lg elg2 rg 2
erg Cgd1
-10
-40
Cgs1 gm vgs1
RS i g2 vgs1 i d2 2
in,out -20

es2 Input -50

rs -30 Output
Isolation
ers2
-40 -60
LS 3 1 4 2 5
Frequency (GHz)
RLs Fig. 5. The measured return loss and isolation of the proposed LNA.

els2
f is the bulk fermi potential. In this paper, the voltage
Fig. 2. The schematic of the noise equivalent circuit of M1 in the proposed LNA. between body and source is biased reversely (VSB  0 V) for
reducing VT. According to simulation, VT of NMOS transistor
can be reduced to 0.38 V when the body-to-source voltage VBS
equal to 0.45 V. For further reducing the supply voltage and
power consumption, the current-reuse cascode topology (M1,
M2 and M3) is realized in this LNA. The inductor LM provides
high impedance for the signal but low impedance for the bias
current. Hence, the signal can go through CM and is amplified
by M3. By this way, the cascode topology will be transferred
into the cascade one but costs a bias current for reducing the
power consumption. The output impedance matching network
is realized by an inductor LO, a capacitor CO and M3. LO is used
to block the signal and resonate with CO and the parasitic
capacitance of M3. For realizing the gain variation, a capacitor
CB and a NMOS transistor M4 are proposed. The gate of M4 is
controlled by the voltage VB2. Thus, the path of CB and M4 just
Fig. 3. The chip micrograph of the proposed LNA.
looks like a negative-feedback variable capacitator. The gain of
the common-gate amplifier M3 can be adjusted by VB2. The bias
circuit design. The body effect caused by the voltage across the current will not flow into CB. Hence, the gain variation will not
source and body of a transistor. The VT of a NMOS can be cause the bias current varies. For improving the linearity, the
expressed as follows [9]: multiple-gate topology (M1 and M2) is proposed. M1 and M2 are
VT = VT0 +   2f + VSB − 2f  , (2) biased at saturation and subthreshold regions, respectively. The
fundamental terms of the signals in M1 and M2 will be added at
Where VT0 is the threshold voltage with zero-body-source
the drains. But the third-order harmonics of the signals will be
voltage, i.e., VSB = 0 V.  is the body effect coefficient, and
eliminated. M1 and M2 share LS for reducing chip area. Hence,

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10 20
Third Order
9 10
10
9
Fundamental

Output Power (dBm)

Noise Figure (dB)
8
7 VB2 = 0.6 V
8
Noise Figure (dB)

6
5
4
VB2 = 0.3 V 0
3
2 VB2 = 0 V
2.25 2.5 2.75 3

7 Frequency (GHz)

-10
6
-20
5
-30
4
-40
3 -30 -25 -20 -15 -10 -5 0 5
2 2.25 2.5 2.75 3 Input Power (dBm)
Frequency (GHz) Fig. 7. The measured IIP3 of the proposed LNA.
Fig. 6. The measured noise figure of the proposed LNA.
[Cgs1 + Cgd1 (1 + g m R L )](LG + LS )
the input third-order intercept point (IIP3) can be improved. QI = . (8)
[Cgs1 + Cgd1 (1 + g m R L )](R S + R par ) + g m LS
The noise equivalent circuit of the first stage is depicted
in Fig. 2 considering the noise effect of the transistor M1. es, elg, Where the transconductance of M1 is gm. I and QI represent
erg, els, ers represent the thermal-noise voltages of the source the resonant frequency and the quality factor of the S21
resistance RS, series resistance RLg of gate inductor LG, resulting from the input network (LG, LS, and M1). ZL(s)
transistor gate resistance rg, series resistance RLs of source represents the output load of M1, which is an output network
inductor LS and transistor source resistance rs, respectively. ig consisting of an inductor Lout, a resistor RL, and a capacitor Cout
and id represent the gate-induced-noise current and with the following equivalent impedance:
channel-resistance thermal-noise current. The frequency (R L + R SL ) 2 Q 2L + R L R SL
response of the noise factor F of the LNA can be expressed as s3 R 2L + s2 L R L [ ] + sR L R SL 2L
(R L + R SL )Q L
follows [16]: Z L (s) = , (9)

2 2 (s2 + s L + 2L )[s + (R L + R SL )Q L L ]
R par δαω2 C2gs1 R S γ  s  s QL
F 1+ + +   + +1 , (3)
RS 5g m αR S g m ω
 nf  ω nf Q nf where
where  (the ratio of gm to zero-bias drain conductance gd0) is 1
ωL = , (10)
about 0.85 in deep-submicron MOSFETs; k is the Boltzmann Lout Cout
constant.  and  are the coefficients of gate noise and and
channelnoise. Based on the measured results in [17],  of 7.5 1 L
and  of 1.2 are adopted for the following NF calculation. The QL =  out . (11)
R L + R SL Cout
resonance frequency nf of the NF is
1 Where RSL is the parasitic series resistance of the inductor
ωnf = . (4)
(LG + LS )[Cgs1 + Cgd1 (1 + g m R L )] Lout. L and QL represent the resonant frequency and the
quality factor of the S21 resulting from the output load ZL(s). L
The quality factor Qnf of the NF is
and QL determine the frequency of highest S21 and the
1 L G + LS bandwidth of the frequency response of S21.
Qnf =  (if R par R S ), (5)
R S Cgs1 + Cgd1 (1 + g m R L )
III. MEASUREMENT RESULTS OF THE VCO
where Rpar (= R Lg + rg + rs + R Ls ) is the total series parasitic
The proposed LNA chip was fabricated by 0.18-μm
resistance. nf and Qnf determine the frequency of lowest NF
CMOS technology. The chip micrograph is illustrated in Fig. 3.
and the bandwidth of the frequency response of NF.
The chip area occupies 0.9 mm x 1 mm, including pads, and
The frequency response of S21 of the first stage
bypass capacitors. The proposed LNA is measured on wafer.
considering M1 can be expressed as follows:
The supply voltage is 0.6 V. The measured operating frequency
2g m I2
S21 =  ZL (s), (6) is 2.8 GHz. The measured power gain ranges from 4 dB to 10

s 2 + s I + 2I dB under gain control voltage VB2 is from 0 V to 0.6 V as
QI shown in Fig. 4. When the gain is 10 dB, the measured results
where can be illustrated as follows. The measured return loss and
1 isolation can be shown in Fig. 5. The input return loss is -9 dB.
ωI = , (7)
(LG + LS )[Cgs1 + Cgd1 (1 + g m R L )] The measured output return loss is -30 dB. The measured
and isolation is -30 dB. The measured noise figure (NF) ranges

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2019.2902301, IEEE
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TABLE I
PERFORMANCE COMPARISON OF STATE-OF-THE-ART LNA

Parameter This Work [10] [11] [12] [13] [14] [15]

CMOS Process (nm) 180 180 180 130 130 65 90
Frequency (GHz) 2.8 0.75–3 2.4 1.8–2.4 2.4 2.14 2.4
Supply Voltage (V) 0.6 1.8 1.8 1.2 0.4 0.6 1.2
Power Gain (dB) 4–10 26 14.7 21 13.1 9.2 9.7
Noise Figure (dB) 4 4.8–10 4.8 3.2–3.5 5.3 2.8 4.4
IIP3 (dBm) 0 -24 2 -16–-11 12.2 N/A -4
Power Dissipation(mW) 0.6 42 0.6 9.6 0.06 0.4 0.7
FOM 37 27 38 5 67 N/A 30

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