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THE 8 INTERNATIONAL SYMPOSIUM ON ADVANCED TOPICS IN ELECTRICAL ENGINEERING

May 23-25, 2013
Bucharest, Romania

A 14-bit and 70-dB Dynamic Range,

Continuous Time, Sigma Delta Modulator
Dragoş Ducu
Microchip Technology, Bucharest Romania,
dragos.ducu@microchip.com

Abstract-This paper presents a new circuit realization for multi gressive quantization noise-shaping and efficiently improves
bit continuous time sigma delta modulator. The converter has signal-to-quantization noise ratio.
been designed in a 0.18 um TSMC technology and achieves a The general form of nth order integrator filter is shown is
maximum signal-to-noise ratio (SNR) of 70 dB in a 1 MHz
equation 1. Where ω is the unity-gain frequency of all inte-
bandwidth and dissipates 5mW from a 1.8 V supply when
clocked at 100MHz. The convertor has a third-order active-RC grators. The choice for the ratios between k1, k2 and k3 is
loop filter, a 4-bit flash quantizer and errors are corrected by determined by considerations concerning stability, maximum
Data Weighted Averaging (DWA). The DWA technique is used input level, signal-to-noise ratio and parameter spread due to
for reducing DAC noise due to component mismatches. A multi- non-ideal processing.
bit non-return-to-zero (NRZ) DACs is adopted to reduce clock
jitter sensitivity. The performance of the circuits was demon-
strated using HSPICE at low voltage operation of 1.8V. . (1)

I. INTRODUCTION
Sigma-delta modulation techniques have been extended in
moderate and high accuracy analog/mixed-signal IC applica-
tions, such as analog-to-digital data converters (ADCs), digi-
tal-to-analog data converters (DACs), frequency synthesizers,
and power amplifiers [1]. Recently, there has been a tremend-
ous interest in modulators built using continuous-time loop
filters [2]. The reasons why continuous-time delta sigma
modulators (CT-DSMs) are attractive are the following. First,
the inherent anti-aliasing characteristics of the CT ΣΔ ADCs Fig.1 Third order feed-forward Sigma Delta Modulator.
reduce the performance requirement of the anti-aliasing filter
further and hence reduce the power consumption of the tran- B. Architecture
sceiver. Second, the bandwidth requirement of the operational The schematic of loop filter is shown in Figure 2. In this de-
amplifiers (op amps) in CT ΣΔ ADCs is much lower than that sign, an active-RC integrator is chosen for the three stages of
of the op amps in DT ones for a given sampling rate, so the the third-order loop filter because it has high linearity and
CT ΣΔ ADCs are more suitable for broadband applications easy interface with DACs. If active-RC integrators were used,
[3]. Hence we propose a low-voltage, lower power consump- resistive loading increases the power requirements due to the
tion and high resolution CT ΣΔ modulator. Figure 1 shows need for buffer stages. The advantages of this implementation
the block diagram of CT- ΣΔ modulator. A CT- ΣΔ modulator are high linearity and high output signal swing, and it also
is characterized by the number of levels or number of bits of provides a good virtual ground for the modulator feed-back
the internal quantizer. A single bit CT- ΣΔ modulator is high- DAC. All resistors are implemented with poly-silicon and
ly linear. But, as the order of the modulator gets higher, the capacitors are poly-poly capacitors. The input-referred noise
higher order noise transfer function (NTF) suffers from the of the loop filter is significantly dominated by the thermal
signal dependent stability limitation. noise from the input resistors and input differential pair of the
II. METHOD first op-amp [4]. In order to mitigate the thermal noise effect
from input resistor R1, the large value 100 K has been cho-
A. Basic principle sen. The poles in the op-amps introduce excess delay in the
Sigma-delta modulator has proven to be very suitable in low loop filter, which can potentially cause instability in the mod-
frequency, high performance application. In Figure 1 is ulator. One way of mitigating this problem with power dissi-
shown the cascaded integrators with feed-forward summation pation sacrifice, is to use wideband op-amps. An alternative
architecture. This was chosen to implement the loop filter. approach is to use low-speed op-amps and compensate for the
The third order loop filter of a modulator provides more ag- delay introduced by the loop filter. In Figure 3 is shown the

978-1-4673-5980-1/13/$31.00 ©2013 IEEE

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 adder of feedforward coefficients. All resistors of this adder
are poly resistors.

Fig.4. Fully differential amplifier.

Fig.2. Schematic of the loop filter.

Fig.3. Schematic of the summation coefficients. Fig.5. Common mode feedback circuit.

C. Fully Differential Amplifier and CMFB D. Comparator

The fully differential operational amplifier is the most critical The purpose of the comparator in a sigma delta modulator is
block of the sigma delta modulator, which determines the to quantize a signal in the loop and provide the digital output
whole performance of the ADC [5]. The operational amplifier of the modulator [6].
is designed as a fully differential self biased folded cascode The regenerative latch comparator shown in Figure 6 has
and is shown in Figure 4. The folded cascade is a single stage been implemented in current design. The comparator is diffe-
operational amplifier using the load capacitance CL as rential-difference architecture. This topology is based on two
compensation capacitor. The fully differential topology has cross-coupled flip-flops and two differential pairs. Two diffe-
been chosen to minimize the effects clock-feed through and rential transistors (M0a, M0b and M0c, M0d) pairs are used
as inputs for voltage reference and input signal. The small
DC offsets and other non ideal secondary effects. The
input difference output of the differencing circuit is quickly
operational amplifier is designed to meet the following
regenerated to a rail-to-rail signal by the high gain of the re-
requirements. The gain bandwidth product GB should be at
generation flip-flops. Finally, the NAND-based SR latch is
least 5 times higher than the switching frequency of quantizer. faster than NOR-based equivalent because the NOR version
The DC-gain should be higher than 40 dB and the phase has PMOS transistors in series, while in the NAND version,
margin PM should be about 70 degrees. The common mode the NMOS transistors are stacked; also, the NOR causes low
feedback is implemented using the CMFB circuit shown in output crossing point. During reset, the switches M5a and
Figure 5. M5b disconnect S and R of the SR latch from the sensing
This circuit is connected to the positive and negative output of nodes (aa and bb). The inputs of the latch are pulled up to
the operational amplifier. The output signal of the CMFB Vdd by M6a and M6b, causing the latch to keep its state. M7
circuit Vctrl is connected to the gate of M12. The CMFB cir- is closed, equalizing the sensing node voltages. A mismatch
cuit creates negative feedback from the outputs to the gate of between the two differential input voltages causes an unequal
M12. This ensures that the output common mode voltage is amount of current to be injected into the sensing nodes. When
stabilized around a specific operating point which is ideally switch M7 is released, the first regeneration phase starts, and
0V. The CMFB is designed to consume little power and util- the small current imbalance will cause the cross coupled tran-
ize relatively small transistor, in order to minimize the capaci- sistors M3a and M3b to pull down one of the sensing nodes
tive loading of the operational amplifier outputs. The feed- [7].
back signal Vctrl should be equal to 0 V when the common
mode voltage at the outputs is 0 V.

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 As shown in Figure 8, a multi-bit current-steering DAC, feeds
current to the virtual grounds of the active-RC integrators,
therefore good DAC linearity can be achieved.
The dynamic performance of current-steering DAC’s is li-
mited by the feed-through of the control signals to the output
lines. The coupling of the switching control signals to the
output lines through the parasitic gate-drain capacitance of the
switching transistors is also a source of glitches.

Fig.6. Schematic of the comparator.

E. Flash 4-bit ADC

In ΣΔ modulators, the main specifications for the quantizer are
offset, speed, area and power consumption requirements.
Moreover the quantizer has to operate at the speed required by
the oversampling process. Therefore it must be implemented Fig.8. Multi bit current steering DAC.
as a flash ADC [8]. To achieve high resolution, 14 bits in our
case the multibit quantizer is required. Multibit quantizer has
less nonlinearity than 1-bit quantizer and the stability is im- G. Data Weighted Average
proved. The block diagram of the 4-bit flash ADC used in the The nonlinearity problem of the feedback DAC can be solved
quantizer is shown in Figure 7. It consists of 15 differential by using dynamic element matching (DEM) techniques. Of
comparators, a resistor ladder, and a thermal to binary encoder. all DEM techniques, the data weighted averaging (DWA)
These comparators compare the input signal with reference algorithm, is an effective and simple technique to realize the
voltages by a resistor ladder biased by the full scale reference. DEM. The register points to the next unused element and ro-
Consequently, the comparator outputs constitute a thermome- tates according to the input codes. This operation ensures that
ter code, which is converted to binary by the encoder. The all the elements are used an equal number of times in a certain
reference voltages are read differentially to reject common period. Consequently, the errors introduced by the mismatch
mode switching noise. of the elements are averaged to zero quickly.
Good attenuation of DAC noise due to component mis-
matches can be pro-vided by the DWA algorithm, which
ideally can achieve a first-order DAC noise shaping. The
block diagram of the DWA logic is shown in Figure 9. The
input of the DWA logic is connected to the four-bit quantizer
output. The 16-bit thermometer decoders produce the two
indexes from outputs of 4-bit adder and 4-bit register. The
output codes from binary to thermometer decoder are
summed by XOR gate when the carry signal of the adder is
low and when the carry signal is high the signals are summed
by XNOR gate. The DWA algorithm selects DAC compo-
nents cyclically one by one. No unit is reselected before all
the others are selected.

Fig.7. 4-bit Flash Quantizer.

F. DAC
The purpose of a feedback DAC in a closed-loop sigma delta
modulator is to convert the modulators digital output back
into an analog form to be compared to its analog input [9].
The performance of the closed-loop sigma delta modulator is
completely dependent on the accuracy of its feedback DAC. Fig.9. Data Weighted Average Block.

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 III. RESULTS modulator has been presented. The current design of fully
The proposed continuous time third order sigma-delta differential amplifier has the next performance: 40MHz
modulator circuit was simulated by HSPICE in 180nm CMOS bandwidth, 75dB gain, 70° phase margin and the power
TSMC technology. The power supply for this circuit is only consumption is 800uW. The clock frequency used for testing
Vdd = 1.8 V and Vref = 0.7 V was chosen. is 10MHz. This modulator has been designed using 180nm
Figure 10 and Figure 11 shows the Gain and phase of the CMOS TSMC technology. This modulator underlies the
fully differential operational amplifier and SNDR. The gain third-order Delta-Sigma ADC, accomplishing the 14-bits and
of amplifier is around 75dB and the phase margin is 70°. 68dB SNDR, 1MHz bandwidth and the power consumption is
Figure 11 show the SNDR of the architecture modulator 5mW at 1.8V power supply. Table 1 shows the comparisons
presented in Figure 1. with other literature.
TABLE I
PERFORMANCE COMPARISON WITH OTHER LITERATURE
Parameter This work [3] [10]
Technology 0.18um 0.18um 0.5um
Voltage(V) 1.8 1.2 3.3
BW(MHz) 1 10 1.1
SNDR(dB) 68 48 83
ENOB(bits) 14 7.7 >14
Power(mW) 5 19.8 62

Fig.10. Open loop gain, phase for fully differential amplifier.

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