GND and AGND
GND and AGND
GND and AGND
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Weekly Progress
1. Digital Isolator Design Guide
2. Addressing High-Voltage Design Challenges With Reliable and
Affordable Isolation Technologies
3. CMU 009 Digital Isolator Capacitance
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Digital Isolator Design Guide
Parameters of Interest
• Isolation Performance:
– and
– and
• Timing Parameters:
– Data rate
– Propagation Delay
– Glitch Filter
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Digital Isolator Design Guide
Parameters of Interest
• Common Mode Transient Immunity (CMTI):
– CMTI indicates the isolator’s ability to tolerate fast changes in the potential
difference between its grounds, or in other words, fast changes in common
mode, without causing bit errors. High CMTI indicates a robust isolation
channel.
• Power Consumption:
– Creepage and Clearance: Distance along the surface of the package and through the air
between pins on one side of the isolator to the pins on the other side. System level standards
mandate minimum values of these parameters based on the working voltage, the peak transient
voltage, and the surge voltage.
– Comparative Tracking Index (CTI) indicates the ability of the package mold compound to
handle steady high voltage without surface degradation. A higher CTI allows the use of smaller4
packages for the same working voltage.
Digital Isolator Design Guide
Decoupling Capacitors
• “When connecting a capacitor between the power and ground planes,
the power supply is actually loaded with a series resonant circuit, whose
frequency dependent R-L-C components represent the equivalent circuit
of a real capacitor. Figure shows the parasitic components of an initial
equivalent circuit and their conversion into a series resonant circuit”.
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Digital Isolator Design Guide
Decoupling Capacitors
Note that the ESR is frequency dependent, and contrary to
popular belief, does not reach its minimum at SRF. The
impedance Z.
The reason why the paralleling of capacitors in a distributed
decoupling network works is because the total capacitance
increases to CTOT = C × n, where n is the number of
decoupling capacitors used. And with Xc = 1/(ω × C), the
capacitor impedance is reduced to Xc = 1/(n × ω × C) for
frequencies below SRF. Similarly, this holds true for the
inductance. Here LTOT = L/n, and because XL = ω × L, the
impedance decreases to XL = ω × L/n for frequencies above
SRF. Designing a solid decoupling network must include lower
frequencies down to dc, which requires the implementation of
large bypass capacitors. Therefore, to provide sufficient low
impedance at low frequencies, place 1-μF to 10-μF tantalum
capacitors at the output of voltage regulators and at the point
where power is supplied to the PCB. For the higher frequency
range, place several 0.1-μF or 0.01-μF ceramic capacitors next 6
to every high-speed switching IC.
Addressing High-Voltage Design Challenges With Reliable and Affordable
Isolation Technologies
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Addressing High-Voltage Design Challenges With Reliable and Affordable
Isolation Technologies
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CMU 009 Digital Isolator Capacitance
ADU Digital Isolator for AGND and DGND 1000pF at 30MHz Capacitance 1000pF at 150MHz Capacitance
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CMU 009 Digital Isolator Capacitance
Testing at Low Frequency
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CMU 009 Digital Isolator Capacitance
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CMU 009 Digital Isolator Capacitance
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