5 4 3 2 1

3V3

100K
C1 100nF U1I

M7 P13
3V3 G12 GND_1 GND_30 K15
VIN 1V0 M13 GND_2 GND_31 M1

R13
GND_3 GND_32

6
U2 SGM706-SYS8 G16 N4
VIN 3 2 L1 4.7uH 2 7 N8 GND_4 GND_33 N14

VBST
IN SW VCC RESET PS_POR_B H7 GND_5 GND_34 A8
8 N12 GND_6 GND_35 R20

100nF
100nF
100nF
WDO H9 GND_7 GND_36 A18

33K
22uF

22uF

22uF
P7 GND_8 GND_37 W2

GND
D
R1 10K 5 4 R18 100K 4 6 H11 GND_9 GND_38 B1 D
EN VFB 3V3 PFI WDI GND_10 GND_39
P11 L12
C2

C3

C4

C99
C100
C101

GND
TPS563201 R19 10K 1 5 H13 GND_11 GND_40 B11

R2
3V3 MR PFO GND_12 GND_41

1
P17 M11
U6 H19 GND_13 GND_42 C4
GND_14 GND_43

3
R12 N10
J2 GND_15 GND_44 C14

100K
T3 GND_16 GND_45 P9
J8 GND_17 GND_46 K11
T13 GND_18 GND_47 R8
J12 GND_19 GND_48 D17
U16 GND_20 GND_49 T7

R3
K5 GND_21 GND_50 E10
V19 GND_22 GND_51 V9
K7 GND_23 GND_52 E20
W12 GND_24 GND_53 Y5
C9 GND_25 GND_54 F3
Y15 GND_26 GND_55 L8
K13 GND_27 GND_56 F7
U6 GND_28 GND_57 L18
C8 100nF GND_29 GND_58 G10
GND_59

1V8 XC7Z010/020-CLG400

6
U3
VIN 3 2 L2 4.7uH 3V3 R4 1K 1 2

VBST
IN SW D1

100nF
100nF
100nF
10K

10K

100K
22uF

22uF

22uF
C C

5 GND 4
EN VFB
C9

C10

C11

C92
C95
C96
TPS563201

R7
1
R5

R6

1V35 U1H 3V3

3

75K
1 Q1 D2 K6
1V0 MMBT3904 A3 VCCO_DDR_502_1 VCCO_0
VCCO_DDR_502_2
3

H4 U11
VCCO_DDR_502_3 VCCO_13_1
2

R9 33R 1 Q2 V4 W7
MMBT3904 P2 VCCO_DDR_502_4 VCCO_13_2 T8

R8
R5 VCCO_DDR_502_5 VCCO_13_3 Y10
VCCO_DDR_502_6 VCCO_13_4
2

L3
E5 VCCO_DDR_502_7 VCCO_34
G1 VCCO_DDR_502_8
U1 VCCO_DDR_502_9 R15
C12 100nF VCCO_DDR_502_10 VCCO_34_1 N19
F1 1V0 VCCO_34_2 T18
VCCO_34_3 Y20
M
H10 VCCO_34_4 W17
1V35 F2 G11 VCCBRAM_1 VCCO_34_5 V14
VCCBRAM_2 VCCO_34_6
6

U4 M
VIN 3 2 L3 4.7uH 3V3 3V3
VBST

IN SW
B6 F18
100NF
100NF
100NF
100NF

1V8 D7 VCCO_MIO0_500_1 VCCO_35_1 J17

75K

22uF

22uF

R10 VCCO_MIO0_500_2 VCCO_35_2 K20

22uF

GND

B
5 4 1V8 VCCO_35_3 M16 B
EN VFB VIN VCCO_35_4 C19
C14

C15

C29
C30
C31
C32

TPS563201 E15 VCCO_35_5 H14

REGULATED
C13

R11

100K
VCCO_MIO1_501_1 VCCO_35_6
1

5V ONLY B16 1V8

D12 VCCO_MIO1_501_2
A13 VCCO_MIO1_501_3
4 VCCO_MIO1_501_4 R9
100K

3 1V0 VCCAUX_1 N11

2 VCCAUX_2 L11
1 P8 VCCAUX_3 N9
JP4 R7 VCCPINT_1 VCCAUX_4 P10
Power_Header_SMT J7 VCCPINT_2 VCCAUX_5 J11
R12

L7 VCCPINT_3 VCCAUX_6 1V0

N7 VCCPINT_4
G7 VCCPINT_5
VCCPINT_6 L13
C16 100nF VCCINT_1 N13
1V8 VCCINT_2 M12
VCCINT_3 R13
F8 VCCINT_4 G13
3V3 VCCO_34 K8 VCCPAUX_1 VCCINT_5 J13
VCCPAUX_2 VCCINT_6
6

U5 M8 K12
VIN 3 2 L4 4.7uH R14 0R H8 VCCPAUX_3 VCCINT_7 H12
VBST

IN SW R15 0R G9 VCCPAUX_4 VCCINT_8 P12

VCCPAUX_5 VCCINT_9 1V8
100nF
100nF
100nF
100nF
10K

10K

33K
22uF

22uF

22uF
GND

5 4 G8 F11
EN VFB VCCPLL VCCBATT_0
C17

C18

C19

C93
C94
C97
C98

TPS563201
R17

A A
1
R64

R65

XC7Z010/020-CLG400
3

10K

1 Q4
1V35 MMBT3904
3

R63 33R 1 Q3 Title

MMBT3904
R20

QMTECH-ZYNQ7000_BAJIE_BOARD
2

Size Document Number Rev

Custom<Doc> <1>

Date: Saturday, January 04, 2020 Sheet 1 of 4

5 4 3 2 1
 5 4 3 2 1

100 ohms differential trace

impedance
Routing top or bottom
U7

DDR_RESETN T2
RESET#
D DDR_CLK+ J7 N3 DDR_A0 D
DDR_CLK- K7 CK A0 P7 DDR_A1
DDR_CKE K9 CK# A1 P3 DDR_A2
DDR_CS L2 CKE A2 N2 DDR_A3
DDR_RAS J3 CS# A3 P8 DDR_A4
DDR_CAS K3 RAS# A4 P2 DDR_A5 U1E
DDR_WE L3 CAS# A5 R8 DDR_A6
WE# A6 R2 DDR_A7 C20 100NF DDR_VREF P6 V3
DDR_D0 E3 A7 T8 DDR_A8 H6 PS_DDR_VREF1_502 PS_DDR_DQ31_502 V2
DDR_D1 F7 DQ0 A8 R3 DDR_A9 PS_DDR_VREF0_502 PS_DDR_DQ30_502 W3
DDR_D2 F2 DQ1 A9 L7 DDR_A10 PS_DDR_DQ29_502 Y2
DDR_D3 F8 DQ2 A10/AP R7 DDR_A11 PS_DDR_DQ28_502 Y4
DDR_D4 H3 DQ3 A11 N7 DDR_A12 DDR_A14 F4 PS_DDR_DQ27_502 W1
DDR_D5 H8 DQ4 A12/BC# T3 DDR_A13 DDR_A13 D4 PS_DDR_A14_502 PS_DDR_DQ26_502 Y3
DDR_D6 G2 DQ5 A13 T7 DDR_A14 DDR_A12 E4 PS_DDR_A13_502 PS_DDR_DQ25_502 V1
DDR_D7 H7 DQ6 A14 M7 DDR_A11 G4 PS_DDR_A12_502 PS_DDR_DQ24_502 U3
DDR_D8 D7 DQ7 A15 M2 DDR_BA0 DDR_A10 F5 PS_DDR_A11_502 PS_DDR_DQ23_502 U2
DDR_D9 C3 DQ8 BA0 N8 DDR_BA1 DDR_A9 J4 PS_DDR_A10_502 PS_DDR_DQ22_502 U4
DDR_D10 C8 DQ9 BA1 M3 DDR_BA2 DDR_A8 K1 PS_DDR_A9_502 PS_DDR_DQ21_502 T4
DDR_D11 C2 DQ10 BA2 DDR_A7 K4 PS_DDR_A8_502 PS_DDR_DQ20_502 R1
DDR_D12 A7 DQ11 K1 DDR_ODT DDR_A6 L4 PS_DDR_A7_502 PS_DDR_DQ19_502 R3
DDR_D13 A2 DQ12 ODT DDR_A5 L1 PS_DDR_A6_502 PS_DDR_DQ18_502 P3
DDR_D14 B8 DQ13 B2 DDR_A4 M4 PS_DDR_A5_502 PS_DDR_DQ17_502 P1
DDR_D15 A3 DQ14 VDD1 G7 DDR_A3 K3 PS_DDR_A4_502 PS_DDR_DQ16_502 J1 DDR_D15
C DQ15 VDD2 R9 DDR_A2 M3 PS_DDR_A3_502 PS_DDR_DQ15_502 H1 DDR_D14
C

DDR_DQS1+ C7 VDD3 K2 DDR_A1 K2 PS_DDR_A2_502 PS_DDR_DQ14_502 H2 DDR_D13

DDR_DQS1- B7 UDQS VDD4 K8 DDR_A0 N2 PS_DDR_A1_502 PS_DDR_DQ13_502 J3 DDR_D12
UDQS# VDD5 N1 1V35 PS_DDR_A0_502 PS_DDR_DQ12_502 H3 DDR_D11
DDR_DQS0+ F3 VDD6 N9 PS_DDR_DQ11_502 G3 DDR_D10
DDR_DQS0- G3 LDQS VDD7 R1 PS_DDR_DQ10_502 E3 DDR_D9
LDQS# VDD8 D9 DDR_BA2 J5 PS_DDR_DQ9_502 E2 DDR_D8
DDR_DQM1 D3 VDD9 DDR_BA1 R4 PS_DDR_BA2_502 PS_DDR_DQ8_502 E1 DDR_D7
DDR_DQM0 E7 UDM A9 DDR_BA0 L5 PS_DDR_BA1_502 PS_DDR_DQ7_502 C1 DDR_D6
LDM VSS1 B3 PS_DDR_BA0_502 PS_DDR_DQ6_502 D1 DDR_D5
VSS2 E1 PS_DDR_DQ5_502 D3 DDR_D4
1V35 A1 VSS3 G8 PS_DDR_DQ4_502 A4 DDR_D3
A8 VDDQ1 VSS4 J2 DDR_RESETNB4 PS_DDR_DQ3_502 A2 DDR_D2
C1 VDDQ2 VSS5 J8 DDR_RAS P4 PS_DDR_DRST_B_502 PS_DDR_DQ2_502 B3 DDR_D1
C9 VDDQ3 VSS6 M1 DDR_CAS P5 PS_DDR_RAS_B_502 PS_DDR_DQ1_502 C3 DDR_D0
D2 VDDQ4 VSS7 M9 DDR_CS N1 PS_DDR_CAS_B_502 PS_DDR_DQ0_502
E9 VDDQ5 VSS8 P1 DDR_WE M5 PS_DDR_CS_B_502
F1 VDDQ6 VSS9 P9 PS_DDR_WE_B_502
H2 VDDQ7 VSS10 T1 Y1
H9 VDDQ8 VSS11 T9 PS_DDR_DM3_502 T1
VDDQ9 VSS12 DDR_CKE N3 PS_DDR_DM2_502 F1 DDR_DQM1
J1 B1 DDR_CLK+ L2 PS_DDR_CKE_502 PS_DDR_DM1_502 A1 DDR_DQM0
J9 NC1 VSSQ1 B9 DDR_CLK- M2 PS_DDR_CKP_502 PS_DDR_DM0_502
L1 NC2 VSSQ2 D1 PS_DDR_CKN_502
B B
L9 NC3 VSSQ3 D8
NC4 VSSQ4 E2 W5
VSSQ5 E8 DDR_ODT N5 PS_DDR_DQS_P3_502 W4
VSSQ6 F9 PS_DDR_ODT_502 PS_DDR_DQS_N3_502 R2
DDR_VREF M8 VSSQ7 G1 PS_DDR_DQS_P2_502 T2
VREFCA VSSQ8 G9 PS_DDR_DQS_N2_502 G2 DDR_DQS1+
VSSQ9 R21 100R H5 PS_DDR_DQS_P1_502 F2 DDR_DQS1-
DDR_VREF H1 L8 R22 100R G5 PS_DDR_VRP_502 PS_DDR_DQS_N1_502 C2 DDR_DQS0+
100NF

100NF

VREFDQ ZQ 1V35 PS_DDR_VRN_502 PS_DDR_DQS_P0_502 B2 DDR_DQS0-

R23 PS_DDR_DQS_N0_502

MT41K256M16TW-107:P 240R 1%
C21

C22

XC7Z010/020-CLG400

1V35

DDR_CLK+
1V35
R25
C23 R24 100R
A A
100nF 1K 1%
DDR_CLK-
100NF

100NF

100NF

100NF

DDR_VREF
C24 DDR_RESETN
100nF
R26
C33 Title
C25

C26

C27

C28

1K 1%
100nF R27
4.7K QMTECH-ZYNQ7000_BAJIE_BOARD
Size Document Number Rev
B <Doc> <1>

Date: Saturday, January 04, 2020 Sheet 1 of 1

5 4 3 2 1
 5 4 3 2 1

PS_RST
U1C JP2 2
R19 BANK34_R19 1 2 SW1
IO_0_34 VCCO_34 3 4 VCCO_34
T11 BANK34_T11 BANK34_P20 BANK34_N20
IO_L1P_T0_34 T10 BANK34_T10 BANK34_T19 5 6 BANK34_R19
IO_L1N_T0_34 T12 BANK34_T12 BANK34_U20 7 8 BANK34_T20
IO_L2P_T0_34 U12 BANK34_U12 BANK34_W20 9 10 BANK34_V20
IO_L2N_T0_34 U13 BANK34_P19 11 12 BANK34_N18
IO_L3P_T0_DQS_PUDC_B_34 V13 BANK34_R16 13 14 BANK34_R17 1
D IO_L3N_T0_DQS_34
IO_L4P_T0_34
V12 BANK34_V12 BANK34_U17 15
17
16
18
BANK34_T16 D
W13 BANK34_W13 BANK34_T17 BANK34_R18
IO_L4N_T0_34 T14 BANK34_T14 BANK34_U18 19 20 BANK34_U19
IO_L5P_T0_34 T15 BANK34_T15 BANK34_W18 21 22 BANK34_W19
IO_L5N_T0_34 P14 BANK34_V17 23 24 BANK34_V18
IO_L6P_T0_34 R14 BANK34_P14 VCCO_34 BANK34_V16 25 26 BANK34_W16
IO_L6N_T0_VREF_34 Y16 BANK34_Y16 BANK34_V15 27 28 BANK34_W15
IO_L7P_T1_34 Y17 BANK34_Y17 BANK34_Y18 29 30 BANK34_Y19
IO_L7N_T1_34 W14 BANK34_W14 BANK34_Y16 31 32 BANK34_Y17
IO_L8P_T1_34 Y14 BANK34_Y14 BANK34_W14 33 34 BANK34_Y14
IO_L8N_T1_34 T16 BANK34_T16 R268 BANK34_T14 35 36 BANK34_T15
IO_L9P_T1_DQS_34 U17 BANK34_U17 BANK34_P14 37 38 BANK34_U14
IO_L9N_T1_DQS_34 1K 39 40
V15 BANK34_V15 BANK34_V12 BANK34_W13
IO_L10P_T1_34 W15 BANK34_W15 BANK34_T12 41 42 BANK34_U12
IO_L10N_T1_34 U14 BANK34_U14 BANK34_T10 43 44 BANK34_T11
IO_L11P_T1_SRCC_34 U15 45 46
IO_L11N_T1_SRCC_34 U18 BANK34_U18 47 48
IO_L12P_T1_MRCC_34 VIN 49 50
U19 BANK34_U19 2
IO_L12N_T1_MRCC_34 N18 BANK34_N18 HDR_25X2
IO_L13P_T2_MRCC_34 P19 BANK34_P19 SW2
IO_L13N_T2_MRCC_34 N20 BANK34_N20
IO_L14P_T2_SRCC_34 P20 BANK34_P20
IO_L14N_T2_SRCC_34 T20 BANK34_T20
IO_L15P_T2_DQS_34 U20 BANK34_U20
IO_L15N_T2_DQS_34 V20 BANK34_V20
IO_L16P_T2_34 W20 BANK34_W20 1
IO_L16N_T2_34 Y18 BANK34_Y18
IO_L17P_T2_34 Y19 BANK34_Y19
IO_L17N_T2_34 V16 BANK34_V16
IO_L18P_T2_34 W16 BANK34_W16
IO_L18N_T2_34 R16 BANK34_R16
IO_L19P_T3_34 R17 BANK34_R17
IO_L19N_T3_VREF_34 T17 BANK34_T17
IO_L20P_T3_34 R18 BANK34_R18
IO_L20N_T3_34 V17 BANK34_V17
C IO_L21P_T3_DQS_34
IO_L21N_T3_DQS_34
V18 BANK34_V18 C
W18 BANK34_W18
IO_L22P_T3_34 W19 BANK34_W19
IO_L22N_T3_34 N17
IO_L23P_T3_34 P18
IO_L23N_T3_34 P15
IO_L24P_T3_34 P16
IO_L24N_T3_34 T19 BANK34_T19
IO_25_34

XC7Z010/020-CLG400

U1D

G14
IO_0_35 C20
IO_L1P_T0_AD0P_35 BANK35_C20
B20 BANK35_B20 J10
IO_L1N_T0_AD0N_35 B19
IO_L2P_T0_AD8P_35 HDMI_TX_HPD
A20 HDMI_TX_CEC BANK35_F19 1 7 BANK35_F20
IO_L2N_T0_AD8N_35 E17 BANK35_G19 2 8 BANK35_G20
IO_L3P_T0_DQS_AD1P_35 D18 BANK35_H18 3 9 BANK35_H20
IO_L3N_T0_DQS_AD1N_35 D19 BANK35_J19 4 10 BANK35_J20
IO_L4P_T0_35 BANK35_D19
D20 BANK35_D20 5 11
IO_L4N_T0_35 E18 6 12
IO_L5P_T0_AD9P_35 BANK35_E18 3V3 3V3
E19 BANK35_E19
IO_L5N_T0_AD9N_35 F16
IO_L6P_T0_35 F17 PMOD
IO_L6N_T0_VREF_35 M19 BANK35_M19
IO_L7P_T1_AD2P_35 M20 BANK35_M20 J11
IO_L7N_T1_AD2N_35 M17
B IO_L8P_T1_AD10P_35
IO_L8N_T1_AD10N_35
M18 BANK35_M18 BANK35_K19 1 7 BANK35_L19 B
L19 BANK35_L19 BANK35_L20 2 8 BANK35_M18
IO_L9P_T1_DQS_AD3P_35 L20 BANK35_L20 BANK35_M20 3 9 BANK35_M19
IO_L9N_T1_DQS_AD3N_35 K19 BANK35_K19 BANK35_L17 4 10 BANK35_L16
IO_L10P_T1_AD11P_35 J19 BANK35_J19 5 11
IO_L10N_T1_AD11N_35 L16 BANK35_L16 6 12
IO_L11P_T1_SRCC_35 3V3 3V3
L17 BANK35_L17
IO_L11N_T1_SRCC_35 K17
IO_L12P_T1_MRCC_35 BANK35_K17
K18 BANK35_K18 PMOD
IO_L12N_T1_MRCC_35 H16 R71 100R
IO_L13P_T2_MRCC_35 H17 SYS_CLK 2 1 R267 1K
IO_L13N_T2_MRCC_35 3V3
J18 Red D4 J12
IO_L14P_T2_AD4P_SRCC_35 H18 BANK35_H18
IO_L14N_T2_AD4N_SRCC_35 F19 BANK35_F19 1 7 MIO_2
IO_L15P_T2_DQS_AD12P_35 MIO_1 MIO_2
F20 BANK35_F20 MIO_3 MIO_3 2 8 MIO_4 MIO_4
IO_L15N_T2_DQS_AD12N_35 G17 MIO_5 3 9 MIO_6
IO_L16P_T2_35 MIO_5 MIO_6
G18 MIO_7 MIO_7 4 10 MIO_8 MIO_8
IO_L16N_T2_35 J20 BANK35_J20 5 11
IO_L17P_T2_AD5P_35 H20 BANK35_H20 6 12
IO_L17N_T2_AD5N_35 3V3 3V3
G19 BANK35_G19
IO_L18P_T2_AD13P_35 G20 BANK35_G20
IO_L18N_T2_AD13N_35 H15 PMOD
IO_L19P_T3_35 G15
IO_L19N_T3_VREF_35 K14
IO_L20P_T3_AD6P_35 J14
IO_L20N_T3_AD6N_35 N15
IO_L21P_T3_DQS_AD14P_35 N16
IO_L21N_T3_DQS_AD14N_35 L14
IO_L22P_T3_AD7P_35 L15
IO_L22N_T3_AD7N_35 M14
IO_L23P_T3_35 M15
IO_L23N_T3_35 K16
IO_L24P_T3_AD15P_35 J16
IO_L24N_T3_AD15N_35 J15
IO_25_35
A A
XC7Z010/020-CLG400

Title

QMTECH-ZYNQ7000_BAJIE_BOARD
Size Document Number Rev

A <Doc> <1>
Date: Sheet of
Saturday, January 04, 2020 2 4
5 4 3 2 1
 5 4 3 2 1

3V3

3V3 U1F U1G

PS_RST
R35 J1 C7
1K PS_POR_B_500 E7 PS_CLK PS_POR_B B10 R28 4.7k
1 PS_CLK_500 PS_SRST_B_501 1V8
E11 R30 1K 1V8
2 TCK PS_MIO_VREF_501 R31 1K
FPGA_DONE 3 TDO E6
4 TDI PS_MIO0_500 A7 A19
5 PS_MIO1_500 MIO_1 PS_MIO16_501 ETH_TXCK

1
TMS B8 MIO_2 R32 20K JTAG Cascade mode E14 ETH_TXD0
D D2 6 PS_MIO2_500 D6 MIO_3 R33 20K PS_MIO17_501 B18 D
PS_MIO3_500 Default SD CARD Boot PS_MIO18_501 ETH_TXD1
JTAG B7 MIO_4 R34 20K 3V3 D10 ETH_TXD2
Red PS_MIO4_500 A6 MIO_5 R36 20K PS_MIO19_501 A17
PS_MIO5_500 3V3 PS_MIO20_501 ETH_TXD3
A5 MIO_6 R37 20K PLL Enabled F14 ETH_TXCTL
PS_MIO6_500 D8 MIO_7 R29 20K PS_MIO21_501 B17
PS_MIO7_500 BANK500 voltage is 3.3V PS_MIO22_501 ETH_RXCK

2
D5 MIO_8 R38 20K 3V3 BANK501 voltage is 1.8V D11 ETH_RXD0
PS_MIO8_500 B5 2 1 R266 1K PS_MIO23_501 A16
PS_MIO9_500 3V3 PS_MIO24_501 ETH_RXD1
R39 E9 Red D3 F15 ETH_RXD2
1K PS_MIO10_500 C6 PS_MIO25_501 A15
PS_MIO11_500 PS_MIO26_501 ETH_RXD3
D9 MIO_12 D13 ETH_RXCTL
PS_MIO12_500 E8 PS_MIO27_501 C16
PS_MIO13_500 MIO_13 PS_MIO28_501
C5 C13
PS_MIO14_500 C8 MIO_2 PS_MIO29_501 C15
PS_MIO15_500 MIO_2 PS_MIO30_501
MIO_3 MIO_3 E16
MIO_4 PS_MIO31_501 A14
MIO_4 PS_MIO32_501
R265 1K XC7Z010/020-CLG400 MIO_5 MIO_5 D15
MIO_6 PS_MIO33_501 A12
MIO_6 PS_MIO34_501
MIO_7 MIO_7 F12
MIO_8 PS_MIO35_501 A11
MIO_8 PS_MIO36_501 HDMI_TX_SCK
3V3 A10

22
21
20
19
18
PS_MIO37_501 HDMI_TX_SDA
U17 E13
U1B PS_MIO38_501 C18

NC11
NC10
NC9
NC8
NC7
6 PS_MIO39_501 D14 SD_CLK
VDD 9 V5 PS_MIO40_501 C17 SD_CMD
C RST NC_1 U7 PS_MIO41_501 E12 SD_D0
C
4.7uF C105
C35

NC_2 V7 PS_MIO42_501 A9 SD_D1

NC_3 3V3 PS_MIO43_501
T9 F13 SD_D2
NC_4 U10 R41 4.7K PS_MIO44_501 B15 SD_D3
100nF

3 23 NC_5 Y7 PS_MIO45_501 D16

29 GND CTS 24 NC_6 Y6 PS_MIO46_501 B14 SD_CD
GND_TP RTS 26 NC_7 Y9 PS_MIO47_501 B12
R82

TXD MIO_13 NC_8 PS_MIO48_501

25 MIO_12 Y8 1 OE VDD 4 C12
RXD NC_9 V8 C34 PS_MIO49_501 B13
NC_10 W8 33.3333 MHz 100NF PS_MIO50_501 B9
NC_11 W10 2 VSS PS_CLK PS_MIO51_501
OUT 3 C10
10K

J4 NC_12 PS_MIO52_501 ETH_MDC

W9 C11 ETH_MDIO
9 8 28 NC_13 U9 PS_MIO53_501
G4 1 R81 4.7K 7 VBUS DTR 12 NC_14 U8 Y1
8 Vcc 2 5 REGIN SUSPEND 11 NC_15 W11 XC7Z010/020-CLG400
G3 D- 3 4 D- SUSPEND 2 NC_16 Y11
7 D+ 4 D+ RI 1 NC_17 T5 SG-8002JC-33.3333M-PCB
G2 ID 5 DCD 27 NC_18 U5
GND DSR NC_19
NC1
NC2
NC3
NC4
NC5
NC6

6 Y12
G1 NC_20 Y13
MINI_USB CP2102N NC_21 V11 U1A
NC_22
10
13
14
15
16
17

V10
NC_23 V6 M9 J6 TMS
NC_24 W6 M10 DXP_0 TMS_0 F9 TCK
B B
NC_25 DXN_0 TCK_0 G6 TDI
TDI_0 F6 TDO
XC7Z010/020-CLG400 TDO_0
Use Internal VREF.
3V3 L9
1V8 K10 VREFP_0
VREFN_0 R11 FPGA_DONE
U9 DONE_0 L6 R40 4.7k
PROGRAM_B_0 3V3
5 21 3V3 R70 R10 R42 4.7k 3V3
VCCA VCCB0 K9 INIT_B_0
L10 VP_0
VN_0 3V3
SD_D0 6 18 Micro SD_2
SD_D1 7 DAT0A DAT0B0 16 4.7k N6
SD_D2 1 DAT1A DAT1B0 23 1 RSVDVCC3 R6
SD_D3 3 DAT2A DAT2B0 22 2 DAT2 M6 RSVDVCC2 T6
DAT3A DAT3B0 CD/DAT3 3V3 CFGBVS_0 RSVDVCC1
SD_CLK 9 19 3
SD_CMD 4 CLKA CLKB0 20 4 CMD
CMDA CMDB0 3V3 VDD
5
6 CLK J9
VSS 1V8 VCCADC_0
24 7 J10 F10
SEL 8 DAT0 GNDADC_0 RSVDGND
R68 DAT1
4.7K SD_CD R43
GND1
GND2
GND3
GND4

17 3V3 1V8 R69 330R 9 XC7Z010/020-CLG400

VCCB1 14 CD
A
DAT0B1 15 A
4.7k DAT1B1 8 J2
DAT2B1
10
11
12
13

2 10
11 GND_1 DAT3B1 13
25 GND_2 CLKB1 12
GND_3 CMDB1 Title
TXS02612RTWR
QMTECH-ZYNQ7000_BAJIE_BOARD
Size Document Number Rev
B <Doc> <1>

Date: Saturday, January 04, 2020 Sheet 3 of 4

5 4 3 2 1
 5 4 3 2 1

L8 4.7uH
REG_OUT AVDD10 DVDD10
1V8 3V3 3V3 3V3

REG_OUT

DVDD10
DVDD10

AVDD10
AVDD10
AVDD10
C43 C91
4.7uF 100nF

U8 R72

48

28
36

15
21
37

40

41

44
45
9
3

6
0R
D D

REG_OUT

DVDD10_1
DVDD10_2

DVDD33_1
DVDD33_2
DVDD33_3

AVDD10_1
AVDD10_2
AVDD10_3

AVDD33_1
AVDD33_2

VDDREG_1
VDDREG_2
4.7K R66 3V3

10
15
16
3V3 HR911130A
ETH_RXD0 ETH_RXD0 1V8 R62 4.7K ETH_RXD0 14 34 14

SHLD1
SHLD2
SHLD3
ETH_RXD1 R61 4.7K ETH_RXD1 16 RXD0/SELRGV LED0/PHY_AD0 35 R73 560R 13 Yellow_LED+
ETH_RXD1 1V8 RXD1/TXDLY LED1/PHY_AD1 Yellow_LED-
ETH_RXD2 ETH_RXD2 1V8 R58 4.7K ETH_RXD2 17 32 4.7K R46 3V3 12
ETH_RXD3 R59 4.7K ETH_RXD3 18 RXD2/AN0 LED2/RXDLY 4.7K R67 R44 560R 11 Green_LED-
ETH_RXD3 1V8 RXD3/AN1 Green_LED+
ETH_RXCTL ETH_RXCTL R60 4.7K ETH_RXCTL 13
19 RXCTL/PHY_AD2
ETH_RXCK RXC 11 9
23 MDI[3]- 10 8 MDI_3-
ETH_TXD0 TXD0 MDI[3]+ MDI_3+
ETH_TXD1 24
25 TXD1 8 6
ETH_TXD2 TXD2 MDI[2]- MDI_2-
ETH_TXD3 26 7 5
27 TXD3 MDI[2]+ MDI_2+
ETH_TXCTL TXCTL
ETH_TXCK 22 5 7
TXC RTL8211E_VL MDI[1]- 4 4 MDI_1-
MDI[1]+ MDI_1+
ETH_MDIO ETH_MDIO 1V8 R57 1.5K ETH_MDIO 31 2 3
30 MDIO MDI[0]- 1 2 MDI_0-
ETH_MDC MDC MDI[0]+ MDI_0+
1
C TCT C

4.7K R55 20 C40 P1

4.7K R54 33 INTB 100nF
3V3 PMEB
22pF C36 29
PS_POR_B 4.7K R56 38 PHYRSTB
3V3 ENSWREG
3
4
Y2 42 39 R53 2.49K
25MHz 43 CKXTAL1 RSET
2 46 CKXTAL2 12

GND_1
GND_2
1 SYS_CLK CLK125 NC

22pF C37

47
49
3V3
U16 P3
C102 100nF 24 16 HDMI_CLK+ BANK35_K17 HDMI_TYPEA
VCCA CLK+ 15 HDMI_CLK- BANK35_K18
CLK- 1 HDMI_D2+
18 HDMI_D0+ DATA2+ 2
D0+ BANK35_E18 DATA2S
B 17 HDMI_D0- BANK35_E19 3 HDMI_D2- B
5 D0- DATA2- 4 HDMI_D1+
LS_OE 21 HDMI_D1+ DATA1+ 5
D1+ BANK35_D19 DATA1S
12 20 HDMI_D1- BANK35_D20 6 HDMI_D1-
CT_HPD D1- DATA1- 7 HDMI_D0+
23 HDMI_D2+ DATA0+ 8
D2+ BANK35_C20 DATA0S
22 HDMI_D2- BANK35_B20 9 HDMI_D0-
D2- DATA0- 10 HDMI_CLK+
2 8 SCL_B CLK+ 11
HDMI_TX_SCK SCL_A SCL_B CLKS
HDMI_TX_SDA 3 9 SDA_B 12 HDMI_CLK-
4 SDA_A SDA_B 10 HPD_B CLK- 13 CEC_B
HDMI_TX_HPD HPD_A HPD_B CEC
HDMI_TX_CEC 1 7 CEC_B 14
11 CEC_A CEC_B 13 NC 15 SCL_B
VIN VCC5V 5V_OUT HDMI_5V SCL 16 SDA_B
C103 100nF 100nF C104 SDA 17
GND_1
GND_2
GND_3

CEC/GND 18
+5V HDMI_5V
19 HPD_B
HPDET
TPD12S016
T1
T2
T3
T4
6
14
19

20
21
22
23

A A

R264
0R

Title
QMTECH-ZYNQ7000_BAJIE_BOARD
Size Document Number Rev
B <Doc> <1>

Date: Saturday, January 04, 2020 Sheet 4 of 4

5 4 3 2 1