Sitronix ST7567

ST
Sitronix 65 x 132 Dot Matrix LCD Controller/Driver

ST7565S
FEATURES
z Direct display of RAM data through the display data High-accuracy voltage adjustment circuit (Thermal
RAM. gradient –0.05%/°C ) V5 voltage regulator resistors
z RAM capacity : 65 x 132 = 8580 bits equipped internally, V1 to V4 voltage divider resistors
z Display duty selectable by select pin equipped internally, electronic volume function
1/65 duty : 65 common x 132 segment equipped internally, voltage follower.
1/49 duty : 49 common x 132 segment z CR oscillator circuit equipped internally (external
1/33 duty : 33 common x 132 segment clock can also be input)
1/55 duty : 55 common x 132 segment z Extremely low power consumption Operating power
1/53 duty : 53 common x 132 segment when the built-in power supply is used (an example)
z High-speed 8-bit MPU interface (The chip can be 60uA (VDD – VSS = VDD – VSS2 =3.0 V, Quad voltage,
connected directly to the both the 80x86 series MPUs V5 – VDD = – 11.0 V).
and the 68000 series MPUs) Conditions: When displays pattern OFF and the
/Serial interfaces are supported. normal mode is selected.
z Abundant command functions z Power supply operate on the low 1.8 voltage
Display data Read/Write, display ON/OFF, Normal/ Logic power supply
Reverse display mode, page address set, display start VDD – VSS = 1.8V to 3.3 V (+10% Range)
line set, column address set, status read, display all Boost reference voltage: VDD – VSS2 = 1.8V to 3.3V
points ON/OFF, LCD bias set, electronic volume, Booster maximum voltage limited
read/modify/write, segment driver direction selects, VOUT= -13V (+10% Range)
power saver, static indicator, common output status Liquid crystal drive power supply:
select, V5 voltage regulation internal resistor ratio set. VDD – V5 = 4.0V to 13.0 V
z Static drive circuit equipped internally for indicators. z Wide range of operating temperatures: –40 to 85°C
(1 system, with variable flashing speed.) z CMOS process
z Low-power liquid crystal display power supply circuit z Shipping forms include bare chip and TCP.
equipped internally. z These chips not designed for resistance to light or
Booster circuit (with Boost ratios of 2X/3X/4X/5X/6X resistance to radiation.
, where the step-up voltage reference power
supply can be input externally).
GENERAL DESCRIPTION
The ST7565S is a single-chip dot matrix LCD driver that can of a 16x16 dot kanji font).
be connected directly to a microprocessor bus. 8-bit parallel Moreover, the capacity of the display can be extended
or serial display data sent from the microprocessor is stored through the use of master/slave structures between chips.
in the internal display data RAM and the chip generates a The chips are able to minimize power consumption
LCD drive signal independent of the microprocessor. because no external operating clock is necessary for the
Because the chips in the ST7565S contain 65x132 bits of display data RAM read/write operation. Furthermore,
display data RAM and there is a 1-to-1 correspondence because each chip is equipped internally with a low-power
between the LCD panel pixels and the internal RAM bits, LCD driver power supply, resistors for LCD driver power
these chips enable displays with a high degree of freedom. voltage adjustment and a display clock CR oscillator circuit,
The ST7565S chips contain 65 common output circuits and the ST7565S can be used to create the lowest power display
132 segment output circuits, so that a single chip can drive a system with the fewest components for high-performance
65x132 dot display (capable of displaying 8 columnsx4 rows portable devices.
PART NO. VRS temperature gradient VRS range

ST7565S -0.05%/°C -2.1V ±0.03V
Ver 0.3c 1/73 2002/07/22

ST7565S
ST7565S Pad Arrangement
Chip Size: 9,336μm x 1,000 μm
Bump Pitch: 58μm(Min.)
Bump Size: PAD No. 001〜012 40μm x 90μm
PAD No. 013〜102 56μm x 60μm
PAD No. 103〜114 40μm x 90μm
PAD No. 115 102μm x 37.5μm
PAD No. 116〜128 90μm x 40μm
PAD No. 129〜276 40μm x 90μm
PAD No. 277〜289 90μm x 40μm
PAD No. 290 102μm x 37.5μm
Bump Height: 18μm(Typ)
Chip Thickness: 660μm
15 15
30um um um 38um
15 um
39um 15 15 30um
15 um
um um
22um 30um 22um 38um 30um

(3528,395)
114 13 12 1
115 ．．．．．．．．．．．． 290
．
ST7565S Y ．
．
PAD DIAGRAM X ．
．．
． (0,0) ．
．．
．．
．
．
128 277
．．．．．．．
129 276
(-4558,-410)
(4558,-410)
z VOUT maximum -13V (+10% Range)

z ST7565S Temperature gradient = -0.05%/°C
z Logic power supply VDD – VSS = 1.8V to 3.3 V (+10% Range)
z Add new booster ratio 5 times and 6 times
z Use select pin to define display duty as following table 15um 15um
SEL 3 , 2 , 1 DUTY BIAS
0,0,0 1/65 1/9 or 1/7
24um 38um
0,0,1 1/49 1/8 or 1/6
0,1,0 1/33 1/6 or 1/5 15um
30um
0,1,1 1/55 1/8 or 1/6 15um
1,0,0 1/53 1/8 or 1/6
38um
1, X , X ----- -----
Ver 0.3c 2/73 2002/07/22

ST7565S
Pad Center Coordinates (1/65 Duty)

Units: μm
PAD 47 CAP1+ 927 389
PIN Name X Y
No. PAD
PIN Name X Y
1 COM[53] 4241 374 No.
2 COM[54] 4183 374 48 CAP3- 853 389
3 COM[55] 4125 374 49 CAP3- 779 389
4 COM[56] 4067 374 50 CAP1+ 705 389
5 COM[57] 4009 374 51 CAP1+ 631 389
6 COM[58] 3951 374 52 CAP1- 557 389
7 COM[59] 3893 374 53 CAP1- 483 389
8 COM[60] 3835 374 54 CAP2- 409 389
9 COM[61] 3777 374 55 CAP2- 335 389
10 COM[62] 3719 374 56 CAP2+ 261 389
11 COM[63] 3661 374 57 CAP2+ 187 389
12 COMS1 3603 374 58 CAP4- 113 389
13 FRS 3443 389 59 CAP4- 39 389
14 FR 3369 389 60 VSS -35 389
15 CL 3295 389 61 VSS -109 389
16 /DOF 3221 389 62 VRS -183 389
17 VSS 3147 389 63 VRS -257 389
18 /CS1 3073 389 64 VDD -331 389
19 CS2 2999 389 65 VDD -405 389
20 VDD 2925 389 66 V1 -479 389
21 /RES 2851 389 67 V1 -553 389
22 A0 2777 389 68 V2 -627 389
23 VSS 2703 389 69 V2 -701 389
24 /WR(R/W) 2629 389 70 V3 -775 389
25 /RD(E) 2555 389 71 V3 -849 389
26 VDD 2481 389 72 V4 -923 389
27 D0 2407 389 73 V4 -997 389
28 D1 2333 389 74 V5 -1071 389
29 D2 2259 389 75 V5 -1145 389
30 D3 2185 389 76 VR -1219 389
31 D4 2111 389 77 VR -1293 389
32 D5 2037 389 78 VDD -1367 389
33 D6 1963 389 79 VDD -1441 389
34 D7 1889 389 80 TEST0 -1515 389
35 VDD 1815 389 81 TEST1 -1589 389
36 VDD 1741 389 82 TEST2 -1663 389
37 VDD 1667 389 83 TEST3 -1737 389
38 VSS 1593 389 84 TEST4 -1811 389
39 VSS 1519 389 85 TEST5 -1885 389
40 VSS2 1445 389 86 VDD -1959 389
41 VSS2 1371 389 87 M/S -2033 389
42 VOUT 1297 389 88 CLS -2107 389
43 VOUT 1223 389 89 VSS -2181 389
44 CAP5- 1149 389 90 C86 -2255 389
45 CAP5- 1075 389 91 P/S -2329 389
46 CAP1+ 1001 389 92 VDD -2403 389
Ver 0.3c 3/73 2002/07/22

ST7565S
93 /HPM -2477 389 145 SEG[8] -3339 -374
94 VSS -2551 389 146 SEG[9] -3281 -374
PAD PAD
PIN Name X Y PIN Name X Y
No. No.
95 IRS -2625 389 147 SEG[10] -3223 -374
96 VDD -2699 389 148 SEG[11] -3165 -374
97 SEL1 -2773 389 149 SEG[12] -3107 -374
98 VSS -2847 389 150 SEG[13] -3049 -374
99 SEL2 -2921 389 151 SEG[14] -2991 -374
100 VDD -2995 389 152 SEG[15] -2933 -374
101 SEL3 -3069 389 153 SEG[16] -2875 -374
102 VSS -3143 389 154 SEG[17] -2817 -374
103 COM[31] -3606 374 155 SEG[18] -2759 -374
104 COM[30] -3664 374 156 SEG[19] -2701 -374
105 COM[29] -3722 374 157 SEG[20] -2643 -374
106 COM[28] -3780 374 158 SEG[21] -2585 -374
107 COM[27] -3838 374 159 SEG[22] -2527 -374
108 COM[26] -3896 374 160 SEG[23] -2469 -374
109 COM[25] -3954 374 161 SEG[24] -2411 -374
110 COM[24] -4012 374 162 SEG[25] -2353 -374
111 COM[23] -4070 374 163 SEG[26] -2295 -374
112 COM[22] -4128 374 164 SEG[27] -2237 -374
113 COM[21] -4186 374 165 SEG[28] -2179 -374
114 COM[20] -4244 374 166 SEG[29] -2121 -374
115 (NC) -4542 404 167 SEG[30] -2063 -374
116 COM[19] -4542 351 168 SEG[31] -2005 -374
117 COM[18] -4542 293 169 SEG[32] -1947 -374
118 COM[17] -4542 235 170 SEG[33] -1889 -374
119 COM[16] -4542 177 171 SEG[34] -1831 -374
120 COM[15] -4542 119 172 SEG[35] -1773 -374
121 COM[14] -4542 61 173 SEG[36] -1715 -374
122 COM[13] -4542 3 174 SEG[37] -1657 -374
123 COM[12] -4542 -55 175 SEG[38] -1599 -374
124 COM[11] -4542 -113 176 SEG[39] -1541 -374
125 COM[10] -4542 -171 177 SEG[40] -1483 -374
126 COM[9] -4542 -229 178 SEG[41] -1425 -374
127 COM[8] -4542 -287 179 SEG[42] -1367 -374
128 COM[7] -4542 -345 180 SEG[43] -1309 -374
129 COM[6] -4267 -374 181 SEG[44] -1251 -374
130 COM[5] -4209 -374 182 SEG[45] -1193 -374
131 COM[4] -4151 -374 183 SEG[46] -1135 -374
132 COM[3] -4093 -374 184 SEG[47] -1077 -374
133 COM[2] -4035 -374 185 SEG[48] -1019 -374
134 COM[1] -3977 -374 186 SEG[49] -961 -374
135 COM[0] -3919 -374 187 SEG[50] -903 -374
136 COMS2 -3861 -374 188 SEG[51] -845 -374
137 SEG[0] -3803 -374 189 SEG[52] -787 -374
138 SEG[1] -3745 -374 190 SEG[53] -729 -374
139 SEG[2] -3687 -374 191 SEG[54] -671 -374
140 SEG[3] -3629 -374 192 SEG[55] -613 -374
141 SEG[4] -3571 -374 193 SEG[56] -555 -374
142 SEG[5] -3513 -374 194 SEG[57] -497 -374
143 SEG[6] -3455 -374 195 SEG[58] -439 -374
144 SEG[7] -3397 -374 196 SEG[59] -381 -374
Ver 0.3c 4/73 2002/07/22

ST7565S
197 SEG[60] -323 -374 245 SEG[108] 2461 -374
198 SEG[61] -265 -374 PAD
PIN Name X Y
PAD No.
PIN Name X Y -374
No. 246 SEG[109] 2519
199 SEG[62] -207 -374 247 SEG[110] 2577 -374
200 SEG[63] -149 -374 248 SEG[111] 2635 -374
201 SEG[64] -91 -374 249 SEG[112] 2693 -374
202 SEG[65] -33 -374 250 SEG[113] 2751 -374
203 SEG[66] 25 -374 251 SEG[114] 2809 -374
204 SEG[67] 83 -374 252 SEG[115] 2867 -374
205 SEG[68] 141 -374 253 SEG[116] 2925 -374
206 SEG[69] 199 -374 254 SEG[117] 2983 -374
207 SEG[70] 257 -374 255 SEG[118] 3041 -374
208 SEG[71] 315 -374 256 SEG[119] 3099 -374
209 SEG[72] 373 -374 257 SEG[120] 3157 -374
210 SEG[73] 431 -374 258 SEG[121] 3215 -374
211 SEG[74] 489 -374 259 SEG[122] 3273 -374
212 SEG[75] 547 -374 260 SEG[123] 3331 -374
213 SEG[76] 605 -374 261 SEG[124] 3389 -374
214 SEG[77] 663 -374 262 SEG[125] 3447 -374
215 SEG[78] 721 -374 263 SEG[126] 3505 -374
216 SEG[79] 779 -374 264 SEG[127] 3563 -374
217 SEG[80] 837 -374 265 SEG[128] 3621 -374
218 SEG[81] 895 -374 266 SEG[129] 3679 -374
219 SEG[82] 953 -374 267 SEG[130] 3737 -374
220 SEG[83] 1011 -374 268 SEG[131] 3795 -374
221 SEG[84] 1069 -374 269 COM[32] 3853 -374
222 SEG[85] 1127 -374 270 COM[33] 3911 -374
223 SEG[86] 1185 -374 271 COM[34] 3969 -374
224 SEG[87] 1243 -374 272 COM[35] 4027 -374
225 SEG[88] 1301 -374 273 COM[36] 4085 -374
226 SEG[89] 1359 -374 274 COM[37] 4143 -374
227 SEG[90] 1417 -374 275 COM[38] 4201 -374
228 SEG[91] 1475 -374 276 COM[39] 4259 -374
229 SEG[92] 1533 -374 277 COM[40] 4542 -345
230 SEG[93] 1591 -374 278 COM[41] 4542 -287
231 SEG[94] 1649 -374 279 COM[42] 4542 -229
232 SEG[95] 1707 -374 280 COM[43] 4542 -171
233 SEG[96] 1765 -374 281 COM[44] 4542 -113
234 SEG[97] 1823 -374 282 COM[45] 4542 -55
235 SEG[98] 1881 -374 283 COM[46] 4542 3
236 SEG[99] 1939 -374 284 COM[47] 4542 61
237 SEG[100] 1997 -374 285 COM[48] 4542 119
238 SEG[101] 2055 -374 286 COM[49] 4542 177
239 SEG[102] 2113 -374 287 COM[50] 4542 235
240 SEG[103] 2171 -374 288 COM[51] 4542 293
241 SEG[104] 2229 -374 289 COM[52] 4542 351
242 SEG[105] 2287 -374 290 (NC) 4542 404
243 SEG[106] 2345 -374
244 SEG[107] 2403 -374
Ver 0.3c 5/73 2002/07/22

ST7565S

Units: μm
PAD PAD
No. No.
1 COM[37] 4241 374 48 CAP3- 853 389
2 COM[38] 4183 374 49 CAP3- 779 389
3 COM[39] 4125 374 50 CAP1+ 705 389
4 COM[40] 4067 374 51 CAP1+ 631 389
5 COM[41] 4009 374 52 CAP1- 557 389
6 COM[42] 3951 374 53 CAP1- 483 389
7 COM[43] 3893 374 54 CAP2- 409 389
8 COM[44] 3835 374 55 CAP2- 335 389
9 COM[45] 3777 374 56 CAP2+ 261 389
10 COM[46] 3719 374 57 CAP2+ 187 389
11 COM[47] 3661 374 58 CAP4- 113 389
12 COMS1 3603 374 59 CAP4- 39 389
13 FRS 3443 389 60 VSS -35 389
14 FR 3369 389 61 VSS -109 389
15 CL 3295 389 62 VRS -183 389
16 /DOF 3221 389 63 VRS -257 389
17 VSS 3147 389 64 VDD -331 389
18 /CS1 3073 389 65 VDD -405 389
19 CS2 2999 389 66 V1 -479 389
20 VDD 2925 389 67 V1 -553 389
21 /RES 2851 389 68 V2 -627 389
22 A0 2777 389 69 V2 -701 389
23 VSS 2703 389 70 V3 -775 389
24 /WR(R/W) 2629 389 71 V3 -849 389
25 /RD(E) 2555 389 72 V4 -923 389
26 VDD 2481 389 73 V4 -997 389
27 D0 2407 389 74 V5 -1071 389
28 D1 2333 389 75 V5 -1145 389
29 D2 2259 389 76 VR -1219 389
30 D3 2185 389 77 VR -1293 389
31 D4 2111 389 78 VDD -1367 389
32 D5 2037 389 79 VDD -1441 389
33 D6 1963 389 80 TEST0 -1515 389
34 D7 1889 389 81 TEST1 -1589 389
35 VDD 1815 389 82 TEST2 -1663 389
36 VDD 1741 389 83 TEST3 -1737 389
37 VDD 1667 389 84 TEST4 -1811 389
38 VSS 1593 389 85 TEST5 -1885 389
39 VSS 1519 389 86 VDD -1959 389
40 VSS2 1445 389 87 M/S -2033 389
41 VSS2 1371 389 88 CLS -2107 389
42 VOUT 1297 389 89 VSS -2181 389
43 VOUT 1223 389 90 C86 -2255 389
44 CAP5- 1149 389 91 P/S -2329 389
45 CAP5- 1075 389 92 VDD -2403 389
46 CAP1+ 1001 389 93 /HPM -2477 389
47 CAP1+ 927 389 94 VSS -2551 389
Ver 0.3c 6/72 2002/07/22

ST7565S
PAD PAD
No. No.
95 IRS -2625 389 147 SEG[10] -3223 -374
96 VDD -2699 389 148 SEG[11] -3165 -374
97 SEL1 -2773 389 149 SEG[12] -3107 -374
98 VSS -2847 389 150 SEG[13] -3049 -374
99 SEL2 -2921 389 151 SEG[14] -2991 -374
100 VDD -2995 389 152 SEG[15] -2933 -374
101 SEL3 -3069 389 153 SEG[16] -2875 -374
102 VSS -3143 389 154 SEG[17] -2817 -374
103 Reserve -3606 374 155 SEG[18] -2759 -374
104 Reserve -3664 374 156 SEG[19] -2701 -374
105 Reserve -3722 374 157 SEG[20] -2643 -374
106 Reserve -3780 374 158 SEG[21] -2585 -374
107 Reserve -3838 374 159 SEG[22] -2527 -374
108 Reserve -3896 374 160 SEG[23] -2469 -374
109 Reserve -3954 374 161 SEG[24] -2411 -374
110 Reserve -4012 374 162 SEG[25] -2353 -374
111 COM[23] -4070 374 163 SEG[26] -2295 -374
112 COM[22] -4128 374 164 SEG[27] -2237 -374
113 COM[21] -4186 374 165 SEG[28] -2179 -374
114 COM[20] -4244 374 166 SEG[29] -2121 -374
115 (NC) -4542 404 167 SEG[30] -2063 -374
116 COM[19] -4542 351 168 SEG[31] -2005 -374
117 COM[18] -4542 293 169 SEG[32] -1947 -374
118 COM[17] -4542 235 170 SEG[33] -1889 -374
119 COM[16] -4542 177 171 SEG[34] -1831 -374
120 COM[15] -4542 119 172 SEG[35] -1773 -374
121 COM[14] -4542 61 173 SEG[36] -1715 -374
122 COM[13] -4542 3 174 SEG[37] -1657 -374
123 COM[12] -4542 -55 175 SEG[38] -1599 -374
124 COM[11] -4542 -113 176 SEG[39] -1541 -374
125 COM[10] -4542 -171 177 SEG[40] -1483 -374
126 COM[9] -4542 -229 178 SEG[41] -1425 -374
127 COM[8] -4542 -287 179 SEG[42] -1367 -374
128 COM[7] -4542 -345 180 SEG[43] -1309 -374
129 COM[6] -4267 -374 181 SEG[44] -1251 -374
130 COM[5] -4209 -374 182 SEG[45] -1193 -374
131 COM[4] -4151 -374 183 SEG[46] -1135 -374
132 COM[3] -4093 -374 184 SEG[47] -1077 -374
133 COM[2] -4035 -374 185 SEG[48] -1019 -374
134 COM[1] -3977 -374 186 SEG[49] -961 -374
135 COM[0] -3919 -374 187 SEG[50] -903 -374
136 COMS2 -3861 -374 188 SEG[51] -845 -374
137 SEG[0] -3803 -374 189 SEG[52] -787 -374
138 SEG[1] -3745 -374 190 SEG[53] -729 -374
139 SEG[2] -3687 -374 191 SEG[54] -671 -374
140 SEG[3] -3629 -374 192 SEG[55] -613 -374
141 SEG[4] -3571 -374 193 SEG[56] -555 -374
142 SEG[5] -3513 -374 194 SEG[57] -497 -374
143 SEG[6] -3455 -374 195 SEG[58] -439 -374
144 SEG[7] -3397 -374 196 SEG[59] -381 -374
145 SEG[8] -3339 -374 197 SEG[60] -323 -374
146 SEG[9] -3281 -374 198 SEG[61] -265 -374
Ver 0.3c 7/72 2002/07/22

ST7565S
PAD PAD
No. No.
199 SEG[62] -207 -374 246 SEG[109] 2519 -374
200 SEG[63] -149 -374 247 SEG[110] 2577 -374
201 SEG[64] -91 -374 248 SEG[111] 2635 -374
202 SEG[65] -33 -374 249 SEG[112] 2693 -374
203 SEG[66] 25 -374 250 SEG[113] 2751 -374
204 SEG[67] 83 -374 251 SEG[114] 2809 -374
205 SEG[68] 141 -374 252 SEG[115] 2867 -374
206 SEG[69] 199 -374 253 SEG[116] 2925 -374
207 SEG[70] 257 -374 254 SEG[117] 2983 -374
208 SEG[71] 315 -374 255 SEG[118] 3041 -374
209 SEG[72] 373 -374 256 SEG[119] 3099 -374
210 SEG[73] 431 -374 257 SEG[120] 3157 -374
211 SEG[74] 489 -374 258 SEG[121] 3215 -374
212 SEG[75] 547 -374 259 SEG[122] 3273 -374
213 SEG[76] 605 -374 260 SEG[123] 3331 -374
214 SEG[77] 663 -374 261 SEG[124] 3389 -374
215 SEG[78] 721 -374 262 SEG[125] 3447 -374
216 SEG[79] 779 -374 263 SEG[126] 3505 -374
217 SEG[80] 837 -374 264 SEG[127] 3563 -374
218 SEG[81] 895 -374 265 SEG[128] 3621 -374
219 SEG[82] 953 -374 266 SEG[129] 3679 -374
220 SEG[83] 1011 -374 267 SEG[130] 3737 -374
221 SEG[84] 1069 -374 268 SEG[131] 3795 -374
222 SEG[85] 1127 -374 269 Reserve 3853 -374
223 SEG[86] 1185 -374 270 Reserve 3911 -374
224 SEG[87] 1243 -374 271 Reserve 3969 -374
225 SEG[88] 1301 -374 272 Reserve 4027 -374
226 SEG[89] 1359 -374 273 Reserve 4085 -374
227 SEG[90] 1417 -374 274 Reserve 4143 -374
228 SEG[91] 1475 -374 275 Reserve 4201 -374
229 SEG[92] 1533 -374 276 Reserve 4259 -374
230 SEG[93] 1591 -374 277 COM[24] 4542 -345
231 SEG[94] 1649 -374 278 COM[25] 4542 -287
232 SEG[95] 1707 -374 279 COM[26] 4542 -229
233 SEG[96] 1765 -374 280 COM[27] 4542 -171
234 SEG[97] 1823 -374 281 COM[28] 4542 -113
235 SEG[98] 1881 -374 282 COM[29] 4542 -55
236 SEG[99] 1939 -374 283 COM[30] 4542 3
237 SEG[100] 1997 -374 284 COM[31] 4542 61
238 SEG[101] 2055 -374 285 COM[32] 4542 119
239 SEG[102] 2113 -374 286 COM[33] 4542 177
240 SEG[103] 2171 -374 287 COM[34] 4542 235
241 SEG[104] 2229 -374 288 COM[35] 4542 293
242 SEG[105] 2287 -374 289 COM[36] 4542 351
243 SEG[106] 2345 -374 290 (NC) 4542 404
244 SEG[107] 2403 -374
245 SEG[108] 2461 -374
Ver 0.3c 8/72 2002/07/22

ST7565S

Units: μm
PAD PAD
No. No.
1 COM[21] 4241 374 48 CAP3- 853 389
2 COM[22] 4183 374 49 CAP3- 779 389
3 COM[23] 4125 374 50 CAP1+ 705 389
4 COM[24] 4067 374 51 CAP1+ 631 389
5 COM[25] 4009 374 52 CAP1- 557 389
6 COM[26] 3951 374 53 CAP1- 483 389
7 COM[27] 3893 374 54 CAP2- 409 389
8 COM[28] 3835 374 55 CAP2- 335 389
9 COM[29] 3777 374 56 CAP2+ 261 389
10 COM[30] 3719 374 57 CAP2+ 187 389
11 COM[31] 3661 374 58 CAP4- 113 389
12 COMS1 3603 374 59 CAP4- 39 389
13 FRS 3443 389 60 VSS -35 389
14 FR 3369 389 61 VSS -109 389
15 CL 3295 389 62 VRS -183 389
16 /DOF 3221 389 63 VRS -257 389
17 VSS 3147 389 64 VDD -331 389
18 /CS1 3073 389 65 VDD -405 389
19 CS2 2999 389 66 V1 -479 389
20 VDD 2925 389 67 V1 -553 389
21 /RES 2851 389 68 V2 -627 389
22 A0 2777 389 69 V2 -701 389
23 VSS 2703 389 70 V3 -775 389
24 /WR(R/W) 2629 389 71 V3 -849 389
25 /RD(E) 2555 389 72 V4 -923 389
26 VDD 2481 389 73 V4 -997 389
27 D0 2407 389 74 V5 -1071 389
28 D1 2333 389 75 V5 -1145 389
29 D2 2259 389 76 VR -1219 389
30 D3 2185 389 77 VR -1293 389
31 D4 2111 389 78 VDD -1367 389
32 D5 2037 389 79 VDD -1441 389
33 D6 1963 389 80 TEST0 -1515 389
34 D7 1889 389 81 TEST1 -1589 389
35 VDD 1815 389 82 TEST2 -1663 389
36 VDD 1741 389 83 TEST3 -1737 389
37 VDD 1667 389 84 TEST4 -1811 389
38 VSS 1593 389 85 TEST5 -1885 389
39 VSS 1519 389 86 VDD -1959 389
40 VSS2 1445 389 87 M/S -2033 389
41 VSS2 1371 389 88 CLS -2107 389
42 VOUT 1297 389 89 VSS -2181 389
43 VOUT 1223 389 90 C86 -2255 389
44 CAP5- 1149 389 91 P/S -2329 389
45 CAP5- 1075 389 92 VDD -2403 389
46 CAP1+ 1001 389 93 /HPM -2477 389
47 CAP1+ 927 389 94 VSS -2551 389
Ver 0.3c 9/73 2002/07/22

ST7565S
PAD PAD
No. No.
95 IRS -2625 389 147 SEG[10] -3223 -374
96 VDD -2699 389 148 SEG[11] -3165 -374
97 SEL1 -2773 389 149 SEG[12] -3107 -374
98 VSS -2847 389 150 SEG[13] -3049 -374
99 SEL2 -2921 389 151 SEG[14] -2991 -374
100 VDD -2995 389 152 SEG[15] -2933 -374
101 SEL3 -3069 389 153 SEG[16] -2875 -374
102 VSS -3143 389 154 SEG[17] -2817 -374
103 Reserve -3606 374 155 SEG[18] -2759 -374
104 Reserve -3664 374 156 SEG[19] -2701 -374
105 Reserve -3722 374 157 SEG[20] -2643 -374
106 Reserve -3780 374 158 SEG[21] -2585 -374
107 Reserve -3838 374 159 SEG[22] -2527 -374
108 Reserve -3896 374 160 SEG[23] -2469 -374
109 Reserve -3954 374 161 SEG[24] -2411 -374
110 Reserve -4012 374 162 SEG[25] -2353 -374
111 Reserve -4070 374 163 SEG[26] -2295 -374
112 Reserve -4128 374 164 SEG[27] -2237 -374
113 Reserve -4186 374 165 SEG[28] -2179 -374
114 Reserve -4244 374 166 SEG[29] -2121 -374
115 (NC) -4542 404 167 SEG[30] -2063 -374
116 Reserve -4542 351 168 SEG[31] -2005 -374
117 Reserve -4542 293 169 SEG[32] -1947 -374
118 Reserve -4542 235 170 SEG[33] -1889 -374
119 Reserve -4542 177 171 SEG[34] -1831 -374
120 COM[15] -4542 119 172 SEG[35] -1773 -374
121 COM[14] -4542 61 173 SEG[36] -1715 -374
122 COM[13] -4542 3 174 SEG[37] -1657 -374
123 COM[12] -4542 -55 175 SEG[38] -1599 -374
124 COM[11] -4542 -113 176 SEG[39] -1541 -374
125 COM[10] -4542 -171 177 SEG[40] -1483 -374
126 COM[9] -4542 -229 178 SEG[41] -1425 -374
127 COM[8] -4542 -287 179 SEG[42] -1367 -374
128 COM[7] -4542 -345 180 SEG[43] -1309 -374
129 COM[6] -4267 -374 181 SEG[44] -1251 -374
130 COM[5] -4209 -374 182 SEG[45] -1193 -374
131 COM[4] -4151 -374 183 SEG[46] -1135 -374
132 COM[3] -4093 -374 184 SEG[47] -1077 -374
133 COM[2] -4035 -374 185 SEG[48] -1019 -374
134 COM[1] -3977 -374 186 SEG[49] -961 -374
135 COM[0] -3919 -374 187 SEG[50] -903 -374
136 COMS2 -3861 -374 188 SEG[51] -845 -374
137 SEG[0] -3803 -374 189 SEG[52] -787 -374
138 SEG[1] -3745 -374 190 SEG[53] -729 -374
139 SEG[2] -3687 -374 191 SEG[54] -671 -374
140 SEG[3] -3629 -374 192 SEG[55] -613 -374
141 SEG[4] -3571 -374 193 SEG[56] -555 -374
142 SEG[5] -3513 -374 194 SEG[57] -497 -374
143 SEG[6] -3455 -374 195 SEG[58] -439 -374
144 SEG[7] -3397 -374 196 SEG[59] -381 -374
145 SEG[8] -3339 -374 197 SEG[60] -323 -374
146 SEG[9] -3281 -374 198 SEG[61] -265 -374
Ver 0.3c 10/73 2002/07/22

ST7565S
PAD PAD
No. No.
199 SEG[62] -207 -374 246 SEG[109] 2519 -374
200 SEG[63] -149 -374 247 SEG[110] 2577 -374
201 SEG[64] -91 -374 248 SEG[111] 2635 -374
202 SEG[65] -33 -374 249 SEG[112] 2693 -374
203 SEG[66] 25 -374 250 SEG[113] 2751 -374
204 SEG[67] 83 -374 251 SEG[114] 2809 -374
205 SEG[68] 141 -374 252 SEG[115] 2867 -374
206 SEG[69] 199 -374 253 SEG[116] 2925 -374
207 SEG[70] 257 -374 254 SEG[117] 2983 -374
208 SEG[71] 315 -374 255 SEG[118] 3041 -374
209 SEG[72] 373 -374 256 SEG[119] 3099 -374
210 SEG[73] 431 -374 257 SEG[120] 3157 -374
211 SEG[74] 489 -374 258 SEG[121] 3215 -374
212 SEG[75] 547 -374 259 SEG[122] 3273 -374
213 SEG[76] 605 -374 260 SEG[123] 3331 -374
214 SEG[77] 663 -374 261 SEG[124] 3389 -374
215 SEG[78] 721 -374 262 SEG[125] 3447 -374
216 SEG[79] 779 -374 263 SEG[126] 3505 -374
217 SEG[80] 837 -374 264 SEG[127] 3563 -374
218 SEG[81] 895 -374 265 SEG[128] 3621 -374
219 SEG[82] 953 -374 266 SEG[129] 3679 -374
220 SEG[83] 1011 -374 267 SEG[130] 3737 -374
221 SEG[84] 1069 -374 268 SEG[131] 3795 -374
222 SEG[85] 1127 -374 269 Reserve 3853 -374
223 SEG[86] 1185 -374 270 Reserve 3911 -374
224 SEG[87] 1243 -374 271 Reserve 3969 -374
225 SEG[88] 1301 -374 272 Reserve 4027 -374
226 SEG[89] 1359 -374 273 Reserve 4085 -374
227 SEG[90] 1417 -374 274 Reserve 4143 -374
228 SEG[91] 1475 -374 275 Reserve 4201 -374
229 SEG[92] 1533 -374 276 Reserve 4259 -374
230 SEG[93] 1591 -374 277 Reserve 4542 -345
231 SEG[94] 1649 -374 278 Reserve 4542 -287
232 SEG[95] 1707 -374 279 Reserve 4542 -229
233 SEG[96] 1765 -374 280 Reserve 4542 -171
234 SEG[97] 1823 -374 281 Reserve 4542 -113
235 SEG[98] 1881 -374 282 Reserve 4542 -55
236 SEG[99] 1939 -374 283 Reserve 4542 3
237 SEG[100] 1997 -374 284 Reserve 4542 61
238 SEG[101] 2055 -374 285 COM[16] 4542 119
239 SEG[102] 2113 -374 286 COM[17] 4542 177
240 SEG[103] 2171 -374 287 COM[18] 4542 235
241 SEG[104] 2229 -374 288 COM[19] 4542 293
242 SEG[105] 2287 -374 289 COM[20] 4542 351
243 SEG[106] 2345 -374 290 (NC) 4542 404
244 SEG[107] 2403 -374
245 SEG[108] 2461 -374
Ver 0.3c 11/73 2002/07/22

ST7565S

Units: μm
PAD PAD
No. No.
1 COM[43] 4241 374 48 CAP3- 853 389
2 COM[44] 4183 374 49 CAP3- 779 389
3 COM[45] 4125 374 50 CAP1+ 705 389
4 COM[46] 4067 374 51 CAP1+ 631 389
5 COM[47] 4009 374 52 CAP1- 557 389
6 COM[48] 3951 374 53 CAP1- 483 389
7 COM[49] 3893 374 54 CAP2- 409 389
8 COM[50] 3835 374 55 CAP2- 335 389
9 COM[51] 3777 374 56 CAP2+ 261 389
10 COM[52] 3719 374 57 CAP2+ 187 389
11 COM[53] 3661 374 58 CAP4- 113 389
12 COMS1 3603 374 59 CAP4- 39 389
13 FRS 3443 389 60 VSS -35 389
14 FR 3369 389 61 VSS -109 389
15 CL 3295 389 62 VRS -183 389
16 /DOF 3221 389 63 VRS -257 389
17 VSS 3147 389 64 VDD -331 389
18 /CS1 3073 389 65 VDD -405 389
19 CS2 2999 389 66 V1 -479 389
20 VDD 2925 389 67 V1 -553 389
21 /RES 2851 389 68 V2 -627 389
22 A0 2777 389 69 V2 -701 389
23 VSS 2703 389 70 V3 -775 389
24 /WR(R/W) 2629 389 71 V3 -849 389
25 /RD(E) 2555 389 72 V4 -923 389
26 VDD 2481 389 73 V4 -997 389
27 D0 2407 389 74 V5 -1071 389
28 D1 2333 389 75 V5 -1145 389
29 D2 2259 389 76 VR -1219 389
30 D3 2185 389 77 VR -1293 389
31 D4 2111 389 78 VDD -1367 389
32 D5 2037 389 79 VDD -1441 389
33 D6 1963 389 80 TEST0 -1515 389
34 D7 1889 389 81 TEST1 -1589 389
35 VDD 1815 389 82 TEST2 -1663 389
36 VDD 1741 389 83 TEST3 -1737 389
37 VDD 1667 389 84 TEST4 -1811 389
38 VSS 1593 389 85 TEST5 -1885 389
39 VSS 1519 389 86 VDD -1959 389
40 VSS2 1445 389 87 M/S -2033 389
41 VSS2 1371 389 88 CLS -2107 389
42 VOUT 1297 389 89 VSS -2181 389
43 VOUT 1223 389 90 C86 -2255 389
44 CAP5- 1149 389 91 P/S -2329 389
45 CAP5- 1075 389 92 VDD -2403 389
46 CAP1+ 1001 389 93 /HPM -2477 389
47 CAP1+ 927 389 94 VSS -2551 389
Ver 0.3c 12/72 2002/07/22

ST7565S
PAD PAD
No. No.
95 IRS -2625 389 147 SEG[10] -3223 -374
96 VDD -2699 389 148 SEG[11] -3165 -374
97 SEL1 -2773 389 149 SEG[12] -3107 -374
98 VSS -2847 389 150 SEG[13] -3049 -374
99 SEL2 -2921 389 151 SEG[14] -2991 -374
100 VDD -2995 389 152 SEG[15] -2933 -374
101 SEL3 -3069 389 153 SEG[16] -2875 -374
102 VSS -3143 389 154 SEG[17] -2817 -374
103 Reserve -3606 374 155 SEG[18] -2759 -374
104 Reserve -3664 374 156 SEG[19] -2701 -374
105 Reserve -3722 374 157 SEG[20] -2643 -374
106 Reserve -3780 374 158 SEG[21] -2585 -374
107 Reserve -3838 374 159 SEG[22] -2527 -374
108 COM[26] -3896 374 160 SEG[23] -2469 -374
109 COM[25] -3954 374 161 SEG[24] -2411 -374
110 COM[24] -4012 374 162 SEG[25] -2353 -374
111 COM[23] -4070 374 163 SEG[26] -2295 -374
112 COM[22] -4128 374 164 SEG[27] -2237 -374
113 COM[21] -4186 374 165 SEG[28] -2179 -374
114 COM[20] -4244 374 166 SEG[29] -2121 -374
115 (NC) -4542 404 167 SEG[30] -2063 -374
116 COM[19] -4542 351 168 SEG[31] -2005 -374
117 COM[18] -4542 293 169 SEG[32] -1947 -374
118 COM[17] -4542 235 170 SEG[33] -1889 -374
119 COM[16] -4542 177 171 SEG[34] -1831 -374
120 COM[15] -4542 119 172 SEG[35] -1773 -374
121 COM[14] -4542 61 173 SEG[36] -1715 -374
122 COM[13] -4542 3 174 SEG[37] -1657 -374
123 COM[12] -4542 -55 175 SEG[38] -1599 -374
124 COM[11] -4542 -113 176 SEG[39] -1541 -374
125 COM[10] -4542 -171 177 SEG[40] -1483 -374
126 COM[9] -4542 -229 178 SEG[41] -1425 -374
127 COM[8] -4542 -287 179 SEG[42] -1367 -374
128 COM[7] -4542 -345 180 SEG[43] -1309 -374
129 COM[6] -4267 -374 181 SEG[44] -1251 -374
130 COM[5] -4209 -374 182 SEG[45] -1193 -374
131 COM[4] -4151 -374 183 SEG[46] -1135 -374
132 COM[3] -4093 -374 184 SEG[47] -1077 -374
133 COM[2] -4035 -374 185 SEG[48] -1019 -374
134 COM[1] -3977 -374 186 SEG[49] -961 -374
135 COM[0] -3919 -374 187 SEG[50] -903 -374
136 COMS2 -3861 -374 188 SEG[51] -845 -374
137 SEG[0] -3803 -374 189 SEG[52] -787 -374
138 SEG[1] -3745 -374 190 SEG[53] -729 -374
139 SEG[2] -3687 -374 191 SEG[54] -671 -374
140 SEG[3] -3629 -374 192 SEG[55] -613 -374
141 SEG[4] -3571 -374 193 SEG[56] -555 -374
142 SEG[5] -3513 -374 194 SEG[57] -497 -374
143 SEG[6] -3455 -374 195 SEG[58] -439 -374
144 SEG[7] -3397 -374 196 SEG[59] -381 -374
145 SEG[8] -3339 -374 197 SEG[60] -323 -374
146 SEG[9] -3281 -374 198 SEG[61] -265 -374
Ver 0.3c 13/72 2002/07/22

ST7565S
PAD PAD
No. No.
199 SEG[62] -207 -374 246 SEG[109] 2519 -374
200 SEG[63] -149 -374 247 SEG[110] 2577 -374
201 SEG[64] -91 -374 248 SEG[111] 2635 -374
202 SEG[65] -33 -374 249 SEG[112] 2693 -374
203 SEG[66] 25 -374 250 SEG[113] 2751 -374
204 SEG[67] 83 -374 251 SEG[114] 2809 -374
205 SEG[68] 141 -374 252 SEG[115] 2867 -374
206 SEG[69] 199 -374 253 SEG[116] 2925 -374
207 SEG[70] 257 -374 254 SEG[117] 2983 -374
208 SEG[71] 315 -374 255 SEG[118] 3041 -374
209 SEG[72] 373 -374 256 SEG[119] 3099 -374
210 SEG[73] 431 -374 257 SEG[120] 3157 -374
211 SEG[74] 489 -374 258 SEG[121] 3215 -374
212 SEG[75] 547 -374 259 SEG[122] 3273 -374
213 SEG[76] 605 -374 260 SEG[123] 3331 -374
214 SEG[77] 663 -374 261 SEG[124] 3389 -374
215 SEG[78] 721 -374 262 SEG[125] 3447 -374
216 SEG[79] 779 -374 263 SEG[126] 3505 -374
217 SEG[80] 837 -374 264 SEG[127] 3563 -374
218 SEG[81] 895 -374 265 SEG[128] 3621 -374
219 SEG[82] 953 -374 266 SEG[129] 3679 -374
220 SEG[83] 1011 -374 267 SEG[130] 3737 -374
221 SEG[84] 1069 -374 268 SEG[131] 3795 -374
222 SEG[85] 1127 -374 269 Reserve 3853 -374
223 SEG[86] 1185 -374 270 Reserve 3911 -374
224 SEG[87] 1243 -374 271 Reserve 3969 -374
225 SEG[88] 1301 -374 272 Reserve 4027 -374
226 SEG[89] 1359 -374 273 Reserve 4085 -374
227 SEG[90] 1417 -374 274 COM[27] 4143 -374
228 SEG[91] 1475 -374 275 COM[28] 4201 -374
229 SEG[92] 1533 -374 276 COM[29] 4259 -374
230 SEG[93] 1591 -374 277 COM[30] 4542 -345
231 SEG[94] 1649 -374 278 COM[31] 4542 -287
232 SEG[95] 1707 -374 279 COM[32] 4542 -229
233 SEG[96] 1765 -374 280 COM[33] 4542 -171
234 SEG[97] 1823 -374 281 COM[34] 4542 -113
235 SEG[98] 1881 -374 282 COM[35] 4542 -55
236 SEG[99] 1939 -374 283 COM[36] 4542 3
237 SEG[100] 1997 -374 284 COM[37] 4542 61
238 SEG[101] 2055 -374 285 COM[38] 4542 119
239 SEG[102] 2113 -374 286 COM[39] 4542 177
240 SEG[103] 2171 -374 287 COM[40] 4542 235
241 SEG[104] 2229 -374 288 COM[41] 4542 293
242 SEG[105] 2287 -374 289 COM[42] 4542 351
243 SEG[106] 2345 -374 290 (NC) 4542 404
244 SEG[107] 2403 -374
245 SEG[108] 2461 -374
Ver 0.3c 14/72 2002/07/22

ST7565S

Units: μm
PAD PAD
No. No.
1 COM[41] 4241 374 48 CAP3- 853 389
2 COM[42] 4183 374 49 CAP3- 779 389
3 COM[43] 4125 374 50 CAP1+ 705 389
4 COM[44] 4067 374 51 CAP1+ 631 389
5 COM[45] 4009 374 52 CAP1- 557 389
6 COM[46] 3951 374 53 CAP1- 483 389
7 COM[47] 3893 374 54 CAP2- 409 389
8 COM[48] 3835 374 55 CAP2- 335 389
9 COM[49] 3777 374 56 CAP2+ 261 389
10 COM[50] 3719 374 57 CAP2+ 187 389
11 COM[51] 3661 374 58 CAP4- 113 389
12 COMS1 3603 374 59 CAP4- 39 389
13 FRS 3443 389 60 VSS -35 389
14 FR 3369 389 61 VSS -109 389
15 CL 3295 389 62 VRS -183 389
16 /DOF 3221 389 63 VRS -257 389
17 VSS 3147 389 64 VDD -331 389
18 /CS1 3073 389 65 VDD -405 389
19 CS2 2999 389 66 V1 -479 389
20 VDD 2925 389 67 V1 -553 389
21 /RES 2851 389 68 V2 -627 389
22 A0 2777 389 69 V2 -701 389
23 VSS 2703 389 70 V3 -775 389
24 /WR(R/W) 2629 389 71 V3 -849 389
25 /RD(E) 2555 389 72 V4 -923 389
26 VDD 2481 389 73 V4 -997 389
27 D0 2407 389 74 V5 -1071 389
28 D1 2333 389 75 V5 -1145 389
29 D2 2259 389 76 VR -1219 389
30 D3 2185 389 77 VR -1293 389
31 D4 2111 389 78 VDD -1367 389
32 D5 2037 389 79 VDD -1441 389
33 D6 1963 389 80 TEST0 -1515 389
34 D7 1889 389 81 TEST1 -1589 389
35 VDD 1815 389 82 TEST2 -1663 389
36 VDD 1741 389 83 TEST3 -1737 389
37 VDD 1667 389 84 TEST4 -1811 389
38 VSS 1593 389 85 TEST5 -1885 389
39 VSS 1519 389 86 VDD -1959 389
40 VSS2 1445 389 87 M/S -2033 389
41 VSS2 1371 389 88 CLS -2107 389
42 VOUT 1297 389 89 VSS -2181 389
43 VOUT 1223 389 90 C86 -2255 389
44 CAP5- 1149 389 91 P/S -2329 389
45 CAP5- 1075 389 92 VDD -2403 389
46 CAP1+ 1001 389 93 /HPM -2477 389
47 CAP1+ 927 389 94 VSS -2551 389
Ver 0.3c 15/72 2002/07/22

ST7565S
PAD PAD
No. No.
95 IRS -2625 389 147 SEG[10] -3223 -374
96 VDD -2699 389 148 SEG[11] -3165 -374
97 SEL1 -2773 389 149 SEG[12] -3107 -374
98 VSS -2847 389 150 SEG[13] -3049 -374
99 SEL2 -2921 389 151 SEG[14] -2991 -374
100 VDD -2995 389 152 SEG[15] -2933 -374
101 SEL3 -3069 389 153 SEG[16] -2875 -374
102 VSS -3143 389 154 SEG[17] -2817 -374
103 Reserve -3606 374 155 SEG[18] -2759 -374
104 Reserve -3664 374 156 SEG[19] -2701 -374
105 Reserve -3722 374 157 SEG[20] -2643 -374
106 Reserve -3780 374 158 SEG[21] -2585 -374
107 Reserve -3838 374 159 SEG[22] -2527 -374
108 Reserve -3896 374 160 SEG[23] -2469 -374
109 COM[25] -3954 374 161 SEG[24] -2411 -374
110 COM[24] -4012 374 162 SEG[25] -2353 -374
111 COM[23] -4070 374 163 SEG[26] -2295 -374
112 COM[22] -4128 374 164 SEG[27] -2237 -374
113 COM[21] -4186 374 165 SEG[28] -2179 -374
114 COM[20] -4244 374 166 SEG[29] -2121 -374
115 (NC) -4542 404 167 SEG[30] -2063 -374
116 COM[19] -4542 351 168 SEG[31] -2005 -374
117 COM[18] -4542 293 169 SEG[32] -1947 -374
118 COM[17] -4542 235 170 SEG[33] -1889 -374
119 COM[16] -4542 177 171 SEG[34] -1831 -374
120 COM[15] -4542 119 172 SEG[35] -1773 -374
121 COM[14] -4542 61 173 SEG[36] -1715 -374
122 COM[13] -4542 3 174 SEG[37] -1657 -374
123 COM[12] -4542 -55 175 SEG[38] -1599 -374
124 COM[11] -4542 -113 176 SEG[39] -1541 -374
125 COM[10] -4542 -171 177 SEG[40] -1483 -374
126 COM[9] -4542 -229 178 SEG[41] -1425 -374
127 COM[8] -4542 -287 179 SEG[42] -1367 -374
128 COM[7] -4542 -345 180 SEG[43] -1309 -374
129 COM[6] -4267 -374 181 SEG[44] -1251 -374
130 COM[5] -4209 -374 182 SEG[45] -1193 -374
131 COM[4] -4151 -374 183 SEG[46] -1135 -374
132 COM[3] -4093 -374 184 SEG[47] -1077 -374
133 COM[2] -4035 -374 185 SEG[48] -1019 -374
134 COM[1] -3977 -374 186 SEG[49] -961 -374
135 COM[0] -3919 -374 187 SEG[50] -903 -374
136 COMS2 -3861 -374 188 SEG[51] -845 -374
137 SEG[0] -3803 -374 189 SEG[52] -787 -374
138 SEG[1] -3745 -374 190 SEG[53] -729 -374
139 SEG[2] -3687 -374 191 SEG[54] -671 -374
140 SEG[3] -3629 -374 192 SEG[55] -613 -374
141 SEG[4] -3571 -374 193 SEG[56] -555 -374
142 SEG[5] -3513 -374 194 SEG[57] -497 -374
143 SEG[6] -3455 -374 195 SEG[58] -439 -374
144 SEG[7] -3397 -374 196 SEG[59] -381 -374
145 SEG[8] -3339 -374 197 SEG[60] -323 -374
146 SEG[9] -3281 -374 198 SEG[61] -265 -374
Ver 0.3c 16/72 2002/07/22

ST7565S
PAD PAD
No. No.
199 SEG[62] -207 -374 246 SEG[109] 2519 -374
200 SEG[63] -149 -374 247 SEG[110] 2577 -374
201 SEG[64] -91 -374 248 SEG[111] 2635 -374
202 SEG[65] -33 -374 249 SEG[112] 2693 -374
203 SEG[66] 25 -374 250 SEG[113] 2751 -374
204 SEG[67] 83 -374 251 SEG[114] 2809 -374
205 SEG[68] 141 -374 252 SEG[115] 2867 -374
206 SEG[69] 199 -374 253 SEG[116] 2925 -374
207 SEG[70] 257 -374 254 SEG[117] 2983 -374
208 SEG[71] 315 -374 255 SEG[118] 3041 -374
209 SEG[72] 373 -374 256 SEG[119] 3099 -374
210 SEG[73] 431 -374 257 SEG[120] 3157 -374
211 SEG[74] 489 -374 258 SEG[121] 3215 -374
212 SEG[75] 547 -374 259 SEG[122] 3273 -374
213 SEG[76] 605 -374 260 SEG[123] 3331 -374
214 SEG[77] 663 -374 261 SEG[124] 3389 -374
215 SEG[78] 721 -374 262 SEG[125] 3447 -374
216 SEG[79] 779 -374 263 SEG[126] 3505 -374
217 SEG[80] 837 -374 264 SEG[127] 3563 -374
218 SEG[81] 895 -374 265 SEG[128] 3621 -374
219 SEG[82] 953 -374 266 SEG[129] 3679 -374
220 SEG[83] 1011 -374 267 SEG[130] 3737 -374
221 SEG[84] 1069 -374 268 SEG[131] 3795 -374
222 SEG[85] 1127 -374 269 Reserve 3853 -374
223 SEG[86] 1185 -374 270 Reserve 3911 -374
224 SEG[87] 1243 -374 271 Reserve 3969 -374
225 SEG[88] 1301 -374 272 Reserve 4027 -374
226 SEG[89] 1359 -374 273 Reserve 4085 -374
227 SEG[90] 1417 -374 274 Reserve 4143 -374
228 SEG[91] 1475 -374 275 COM[26] 4201 -374
229 SEG[92] 1533 -374 276 COM[27] 4259 -374
230 SEG[93] 1591 -374 277 COM[28] 4542 -345
231 SEG[94] 1649 -374 278 COM[29] 4542 -287
232 SEG[95] 1707 -374 279 COM[30] 4542 -229
233 SEG[96] 1765 -374 280 COM[31] 4542 -171
234 SEG[97] 1823 -374 281 COM[32] 4542 -113
235 SEG[98] 1881 -374 282 COM[33] 4542 -55
236 SEG[99] 1939 -374 283 COM[34] 4542 3
237 SEG[100] 1997 -374 284 COM[35] 4542 61
238 SEG[101] 2055 -374 285 COM[36] 4542 119
239 SEG[102] 2113 -374 286 COM[37] 4542 177
240 SEG[103] 2171 -374 287 COM[38] 4542 235
241 SEG[104] 2229 -374 288 COM[39] 4542 293
242 SEG[105] 2287 -374 289 COM[40] 4542 351
243 SEG[106] 2345 -374 290 (NC) 4542 404
244 SEG[107] 2403 -374
245 SEG[108] 2461 -374
Ver 0.3c 17/72 2002/07/22

ST7565S
BLOCK DIAGRAM
SEG131
COM63
COMS
COM0
SEG0
VDD
V1
COMS
V2
V3 132 SEGMENT 64 COMMON
V4
V5 DRIVERS DRIVERS
COM output control circuit
Voltage Display data latch circuit
Display timing generator circuit

HPM
follower FRS
circuit
Line address circuit
M/S
Page address circuit
V5 CL
I/O buffer
VR Voltage DOF
DISPLAY DATA RAM
VRS Regulator FR
circuit
IRS
65 X 132 = 8580 Bits
VOUT
CAP1+
Voltage Column address circuit
CAP1-
CAP2+ booster
CAP2- circuit
Oscillator
CAP3+
circuit
CAP4- CLS
CAP5- Power Supply
Circuit
VSS2
Status Command decoder Bus holder

VSS
MPU INTERFACE ( Parallel and Serial )

SEL1
SEL2
SEL3
E(/RD)
RW(/WR)
A0
CS1
CS2
/RES
C86
P/S
D0
D1
D2
D3
D4
D5
D6(SCL)
D7(SI)
Ver 0.3c 18/72 2002/07/22

ST7565S
PIN DESCRIPTIONS
Power Supply Pins
Pin Name I/O Function No. of Pins

Power
VDD Shared with the MPU power supply terminal Vcc. 13
Supply
Power
VSS This is a 0V terminal connected to the system GND. 10
Supply
Power This is the reference power supply for the step-up voltage circuit for the
VSS2 2
Supply liquid crystal drive.
Power This is the internal-output VREG power supply for the LCD power supply
VRS 2
Supply voltage regulator.
This is a multi-level power supply for the liquid crystal drive. The voltage Supply
applied is determined by the liquid crystal cell, and is changed through the use of
a resistive voltage divided or through changing the impedance using an op. amp.
Voltage levels are determined based on VDD, and must maintain the relative
magnitudes shown below.
VDD (= V0) ≧V1 ≧V2 ≧V3 ≧V4 ≧V5

V1, V2,
Power
V3, V4, When the power supply turns ON, the internal power supply circuits produce the 10
Supply
V5 V1 to V4 voltages shown below. The voltage settings are selected using the LCD
bias set command.
1/65 DUTY 1/49 DUTY 1/33 DUTY 1/55 DUTY 1/53 DUTY
V1 1/9*V5,1/7*V5 1/8*V5,1/6*V5 1/6*V5,1/5*V5 1/8*V5,1/6*V5 1/8*V5,1/6*V5
V2 2/9*V5,2/7*V5 2/8*V5,2/6*V5 2/6*V5,2/5*V5 2/8*V5,2/6*V5 2/8*V5,2/6*V5
V3 7/9*V5,5/7*V5 6/8*V5,4/6*V5 4/6*V5,3/5*V5 6/8*V5,4/6*V5 6/8*V5,4/6*V5
V4 8/9*V5,6/7*V5 7/8*V5,5/6*V5 5/6*V5,4/5*V5 7/8*V5,5/6*V5 7/8*V5,5/6*V5
LCD Power Supply Pins

DC/DC voltage converter. Connect a capacitor between this terminal and
CAP1+ O 4
the CAP1- terminal.
CAP1– O 2
the CAP1+ terminal.
CAP2+ O 2
the CAP2- terminal.
CAP2– O 2
the CAP2+ terminal.
CAP3– O 2
the CAP1+ terminal.
CAP4– O 2
the CAP2+ terminal.
CAP5– O 2
the CAP1+ terminal.
VOUT O 2
VSS.
Output voltage regulator terminal. Provides the voltage between VDD and
V5 through a resistive voltage divider.
VR I 2
IRS = “L” : the V5 voltage regulator internal resistors are not used .
IRS = “H” : the V5 voltage regulator internal resistors are used .
Ver 0.3c 19/72 2002/07/22

ST7565S
System Bus Connection Pins

This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit
D5 to D0 standard MPU data bus.
When the serial interface is selected (P/S = “L”) :
D6 (SCL) I/O D7 : serial data input (SI) ; D6 : the serial clock input (SCL).
8
D7 (SI) D0 to D5 are set to high impedance.
When the chip select is not active, D0 to D7 are set to high impedance.
This is connect to the least significant bit of the normal MPU address bus,
and it determines whether the data bits are data or a command.
A0 I A0 = “H”: Indicates that D0 to D7 are display data.
1
A0 = “L”: Indicates that D0 to D7 are control data.
When /RES is set to “L,” the settings are initialized.

I 1
/RES
The reset operation is performed by the /RES signal level.
This is the chip select signal. When /CS1 = “L” and CS2 = “H,” then the
/CS1 I chip select becomes active, and data/command I/O is enabled.
2
CS2
• When connected to an 8080 MPU, this is active LOW.
(E) This pin is connected to the /RD signal of the 8080 MPU, and the
ST7565S series data bus is in an output status when this signal is “L”.
/RD I • When connected to a 6800 Series MPU, this is active HIGH.
1
(E) This is the 6800 Series MPU enable clock input terminal.
• When connected to an 8080 MPU, this is active LOW.

(R/W) This terminal connects to the 8080 MPU /WR signal. The signals on
the data bus are latched at the rising edge of the /WR signal.
• When connected to a 6800 Series MPU:
I This is the read/write control signal input terminal.
1
/WR
(R/W) When R/W = “H”: Read.
When R/W = “L”: Write.
This is the MPU interface switch terminal.

C86 = “H”: 6800 Series MPU interface.
C86 I C86 = “L”: 8080 MPU interface.
1
This is the parallel data input/serial data input switch terminal.

P/S = “H”: Parallel data input.
P/S = “L”: Serial data input.
The following applies depending on the P/S status:
P/S Data/Command Data Read/Write Serial Clock

P/S I “H” A0 D0 to D7 /RD, /WR X 1
“L” A0 SI (D7) Write only SCL (D6)
When P/S = “L”, D0 to D5 fixed “H”.

/RD (E) and /WR (R/W) are fixed to either “H” or “L”.
With serial data input, It is impossible read data from RAM .
Ver 0.3c 20/72 2002/07/22

ST7565S
Terminal to select whether or enable or disable the display clock internal
oscillator circuit.
CLS I CLS = “H” : used Internal oscillator circuit . 1
CLS = “L” : used external clock input .(internal oscillator is disable)
When CLS = “L”, input the display clock through the CL terminal.
This terminal selects the master/slave operation for the ST7565S Series chips.
Master operation outputs the timing signals that are required for the LCD display, while
slave operation input the timing signals required for the liquid crystal display,
Synchronizing the liquid crystal display system.
M/S = “H” Master operation
M/S = “L” Slave operation
M/S I Oscillator
Power 1
M/S CLS Circuit
Supply CL FR FRS DOF
Circuit
“H” Enabled Enabled Output Output Output Output
“H”
“L” Disabled Enabled Input Output Output Output
“H” Disabled Disabled Input Input Output Input
“L”
“L” Disabled Disabled Input Input Output Input
This is the display clock input terminal

The following is true depending on the M/S and CLS status.
M/S CLS CL
CL I/O “H” Output 1
“H”
“L” Input
“H” Input
“L”
“L” Input
FR O This is the liquid crystal alternating current signal terminal. 1
/DOF O This is the LCD blanking control terminal. 1

This is the output terminal for the static drive.
FRS O This terminal is only enabled when the static indicator display is ON 1
and is used in conjunction with the FR terminal.
This terminal selects the resistors for the V5 voltage level adjustment.
IRS = “H”: Use the internal resistors
IRS I
IRS = “L”: Do not use the internal resistors. The V5 voltage level is
1
regulated by an external resistive voltage divider attached to the VR terminal
This is the power control terminal for the power supply circuit for liquid crystal
drive.
I 1
/HPM /HPM = “H”: Normal mode
/HPM = “L”: High power mode
These pins are DUTY selection.
SEL 3 , 2 , 1 DUTY BIAS
0,0,0 1/65 1/9 or 1/7
SEL3 0,0,1 1/49 1/8 or 1/6

SEL2 I 0,1,0 1/33 1/6 or 1/5 3
SEL1
0,1,1 1/55 1/8 or 1/6
1,0,0 1/53 1/8 or 1/6
1, X , X ----- -----
These are terminals for IC testing.

TEST0 ~ 5 I 6
They are set to open.
Ver 0.3c 21/72 2002/07/22

ST7565S
LCD Driver Pins

These are the LCD segment drive outputs. Through a combination of the
contents of the display RAM and with the FR signal, a single level is selected
from VDD, V2, V3, and V5.
Output Voltage
RAM DATA FR
SEG0 Normal Display Reverse Display
to O H H VDD V2 132
SEG131
H L V5 V3
L H V2 VDD
L L V3 V5
Power save VDD
Through a combination of the contents of the scan data and with the FR
signal, a single level is selected from VDD, V1, V4, and V5.
Scan Data FR Output Voltage

COM0 H H V5
to O H L VDD 67
COMn
L H V1
L L V4
Power save VDD
These are the COM output terminals for the indicator. Both terminals output
the same signal.
COMS O 2
Leave these open if they are not used.
Ver 0.3c 22/72 2002/07/22

ST7565S
DESCRIPTION OF FUNCTIONS
The MPU Interface
Selecting the Interface Type

With the ST7565S chips, data transfers are done through an “H” or “L” it is possible to select either parallel
8-bit parallel data bus (D7 to D0) or through a serial data data input or serial data input as shown in Table 1.
input (SI). Through selecting the P/ S terminal polarity to the
Table 1
P/S /CS1 CS2 A0 /RD /WR C86 D7 D6 D5~D0
H: Parallel Input /CS1 CS2 A0 /RD /WR C86 D7 D6 D5~D0

L: Serial Input /CS1 CS2 A0 — — — SI SCL (HZ)
“—” indicates fixed to either “H” or to “L”
The Parallel Interface

When the parallel interface has been selected (P/S =“H”), 8080-system MPU or a 6800 Series MPU (shown in Table 2)
then it is possible to connect directly to either an by selecting the C86 terminal to either “H” or to “L”.
Table 2
R/W(/WR
C86 (P/S=H) /CS1 CS2 A0 E(/RD) D7~D0
)
H: 6800 Series /CS1 CS2 A0 E R/W D7~D0
L: 8080 Series /CS1 CS2 A0 /RD /WR D7~D0
Moreover, data bus signals are recognized by a combination

of A0, /RD (E), /WR (R/W) signals, as shown in Table 3.
Table 3
Shared 6800 Series 8080 Series
Function
A0 R/W /RD /WR
1 1 0 1 Reads the display data
1 0 1 0 Writes the display data
0 1 0 1 Status read
0 0 1 0 Write control data (command)
Ver 0.3c 23/72 2002/07/22

ST7565S
The Serial Interface
When the serial interface has been selected (P/S = “L”) then The A0 input is used to determine whether or the serial data
when the chip is in active state (/CS1 = “L” and CS2 = “H”) input is display data or command data; when A0 = “H”, the
the serial data input (SI) and the serial clock input (SCL) can data is display data, and when A0 = “L” then the data is
be received. The serial data is read from the serial data input command data. The A0 input is read and used for detection
pin in the rising edge of the serial clocks D7, D6 through D0, every 8th rising edge of the serial clock after the chip
in this order. This data is converted to 8 bits parallel data in becomes active. Figure 1 is a serial interface signal chart.
the rising edge of the eighth serial clock for the processing.
CS1
CS2
SI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A0
Figure 1
* When the chip is not active, the shift registers and the counter are reset to their initial states.
* Reading is not possible while in serial interface mode.
* Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that operation
be rechecked on the actual equipment.
The Chip Select

The ST7565S have two chip select terminals: /CS1 and CS2. When the chip select is inactive, D0 to D7 enter a high
The MPU interface or the serial interface is impedance state, and the A0, /RD, and /WR inputs are
enabled only when /CS1 = “L” and CS2 = “H”. inactive. When the serial interface is selected, the shift
register and the counter are reset.
The Accessing the Display Data RAM and the Internal Registers
Data transfer at a higher speed is ensured since the MPU is the first data read cycle (dummy) stores the read data in the
required to satisfy the cycle time (tCYC) requirement alone in bus holder, and then the data is read from the bus holder to
accessing the ST7565S. Wait time may not be considered. the system bus at the next data read cycle.
And, in the ST7565S, each time data is sent from the MPU, a There is a certain restriction in the read sequence of the
type of pipeline process between LSIs is performed through display data RAM. Please be advised that data of the
the bus holder attached to the internal data bus. Internal data specified address is not generated by the read instruction
bus. issued immediately after the address setup. This data is
For example, when the MPU writes data to the display data generated in data read of the second time. Thus, a dummy
RAM, once the data is stored in the bus holder, then it is read is required whenever the address setup
written to the display data RAM before the next data write or write cycle operation is conducted.
cycle. Moreover, when the MPU reads the display data RAM, This relationship is shown in Figure 2.
Ver 0.3c 24/72 2002/07/22

ST7565S
The Busy Flag
When the busy flag is “1” it indicates that the ST7565S is (tCYC) is maintained, it is not necessary to check for this flag
running internal processes, and at this time no command before each command. This makes vast improvements in
aside from a status read will be received. The busy flag is MPU processing capabilities possible.
outputted to D7 pin with the read instruction. If the cycle time
Writing
WR
MPU
DATA N N+1 N+2 N+3

Internal Timing
BUS Holder N N+1 N+2 N+3
Write Signal
Reading
WR
MPU
RD
DATA N N n n+1
Address Preset
Internal Timing
Read Signal
Column Address Preset N Increment N+1 N+2
Bus Holder N n n+1 n+2
Address Set Dummy Data Read

Data Read #n
#n Read #n+1
Figure 2
Ver 0.3c 25/72 2002/07/22

ST7565S
Display Data RAM
The display data RAM stores the dot data for the LCD. It has freedom.
a 65 (8 page x 8 bit +1) x 132 bit structure. Moreover, reading from and writing to the display RAM from
As is shown in Figure 3, the D7 to D0 display data from the the MPU side is performed through the I/O buffer, which is an
MPU corresponds to the LCD display common direction; independent operation from signal reading for the liquid
there are few constraints at the time of display data transfer crystal driver. Consequently, even if the display data RAM is
when multiple ST7565S are used, thus and display accessed asynchronously during liquid crystal display, it will
structures can be created easily and with a high degree of not cause adverse effects on the display (such as flickering).
D0 0 1 1 1 0 COM0
D1 1 0 0 0 0 COM1
D2 0 0 0 0 0 COM2
D3 0 1 1 1 0 COM3
D4 1 0 0 0 0 COM4
- -
Display data RAM Liquid crystal display
Figure 3
The Page Address Circuit
Page address of the display data RAM is specified through Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is a special
the Page Address Set Command. The page address must be RAM for icons, and only display data D0 is used.
specified again when changing pages to perform access. (see Figure 4)
The Column Addresses

The display data RAM column address is specified by the it is necessary to respective both the page address and the
Column Address Set command. The specified column column address.
address is incremented (+1) with each display data Furthermore, as is shown in Table 4, the ADC command
read/write command. This allows the MPU display data to be (segment driver direction select command) can be used to
accessed continuously. Moreover, the incrementing of reverse the relationship between the display data RAM
column addresses stops with 83H. Because the column column address and the segment output. Because of this,
address is independent of the page address, when moving, the constraints on the IC layout when the LCD module is
for example, from page 0 column 83H to page 1 column 00H, assembled can be minimized. As is shown in Figure 4,
Table 4
SEG Output
ADC SEG0 SEG 131
(D0) “0” 0 (H) → Column Address → 83 (H)
(D0) “1” 83 (H) ← Column Address ← 0 (H)
The Line Address Circuit
The line address circuit, as shown in Table 4, specifies the for ST7565S , the detail is shown page.11 The display area
line address relating to the COM output when the contents of is a 65 line area for the ST7565S.
the display data RAM are displayed. Using the display start If the line addresses are changed dynamically using the
line address set command, what is normally the top line of display start line address set command, screen scrolling,
the display can be specified (this is the COM0 output when page swapping, etc. can be performed.
the common output mode is normal, and the COM63 output
Ver 0.3c 26/72 2002/07/22

ST7565S
Page Address Line When the common COM
Data output is normal
D3 D2 D1 D0 Address Output
D0 00H COM0
D1 01H COM1
D2 02H COM2
D3 03H COM3
0 0 0 0 Page 0
D4 04H COM4
D5 05H COM5
D6 06H COM6
D7 07H COM7
D0 08H COM8
D1 09H COM9
D2 0AH COM10
D3 0BH COM11
0 0 0 1 Page 1
D4 0CH COM12
D5 0DH COM13
D6 0EH COM14
D7 0FH COM15
D0 10H COM16
D1 11H COM17
D2 12H COM18
D3 13H COM19
0 0 1 0 Page 2
D4 14H COM20
D5 15H COM21
D6 16H COM22
D7 17H COM23
D0 18H COM24
D1 19H COM25
D2 1AH COM26
D3 1BH COM27
0 0 1 1 Page 3
D4 1CH COM28
D5 1DH COM29
D6 1EH COM30
D7 1FH COM31
D0 20H COM32
D1 21H COM33
D2 22H COM34
D3 23H COM35
0 1 0 0 Page 4
D4 24H COM36
D5 25H COM37
D6 26H COM38
D7 27H COM39
D0 28H COM40
D1 29H COM41
D2 2AH COM42
D3 2BH COM43
0 1 0 1 Page 5
D4 2CH COM44
D5 2DH COM45
D6 2EH COM46
D7 2FH COM47
D0 30H COM48
D1 31H COM49
D2 32H COM50
D3 33H COM51
0 1 1 0 Page 6
D4 34H COM52
D5 35H COM53
D6 36H COM54
D7 37H COM55
D0 38H COM56
D1 39H COM57
D2 3AH COM58
D3 3BH COM59
0 1 1 1 Page 7
D4 3CH COM60
D5 3DH COM61
D6 3EH COM62
D7 3FH COM63
1 0 0 0 D0 Page 8 COMS
Regardless of the display
Column
07 7C
06 7D
D0 D0
7B
7E
7F
start line address,

00
01
02
03
04
05
06
07
08
80
81
82
83
addres
0
ADC
1/65duty => 64th line,

s
1/49duty =>48th line.

7D
7C
7E
7B
7F
83
82
81
80
08
05
04
03
02
01
00
1/33duty =>32th line,

1/55duty =>54th line,
S123
S124
S125
S126
S127
S128
S129
S130
S131
LCD
Out
S0
S1
S2
S3
S4
S5
S6
S7
S8
1/53duty =>52th line.
Figure 4
Ver 0.3c 27/72 2002/07/22

ST7565S
The Display Data Latch Circuit
The display data latch circuit is a latch that temporarily stores status, and display all points ON/OFF commands control
the display data that is output to the liquid crystal only the data within the latch, they do not change
driver circuit from the display data RAM. the data within the display data RAM itself.
Because the display normal/reverse status, display ON/OFF
The Oscillator Circuit

This is a CR-type oscillator that produces the display clock. When CLS = “L” the oscillation stops, and the external
The oscillator circuit is only enabled when M/S= “H” and CLS clock is input through the CL terminal.
= “H”.
Display Timing Generator Circuit

The display timing generator circuit generates the timing accessed asynchronously during liquid crystal display, there
signal to the line address circuit and the display data latch is absolutely no adverse effect (such as
circuit using the display clock. The display data is latched into flickering) on the display.
the display data latch circuit synchronized with the display Moreover, the display timing generator circuit generates the
clock, and is output to the data driver output terminal. common timing and the liquid crystal alternating current
Reading to the display data liquid crystal driver circuits is signal (FR) from the display clock. It generates a drive wave
completely independent of accesses to the display data RAM form using a 2 frame alternating current drive method, as is
by the MPU. Consequently, even if the display data RAM is shown in Figure 5, for the liquid crystal drive circuit.
Two-frame alternating current drive waveform
64 65 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6
CL
FR
VDD
V1
COM0
V4
V5
VDD
V1
COM1
V4
V5
RAM
Data
VDD
V2
SEGn
V3
V5
Figure 5
Ver 0.3c 28/72 2002/07/22

ST7565S
The Common Output Status Select Circuit
In the ST7565S chips, the COM output scan direction can be (See Table 6.) Consequently, the constraints in IC layout at
selected by the common output status select command. the time of LCD module assembly can be minimized.
Table 6
COM Scan Direction
Status
1/65 DUTY 1/49 DUTY 1/33 DUTY 1/55 DUTY 1/53 DUTY
Normal COM0 → COM63 COM0 → COM47 COM0 → COM31 COM0 → COM53 COM0 → COM51
Reverse COM63 → COM0 COM47 → COM0 COM31 → COM0 COM53 → COM0 COM51 → COM0
Com Common output pins

Duty
dir com[0:15] com[16:23] com[24:26] com[27:36] com[37:39] com[40:47] com[48:63] coms
0 com[0:63] coms
1/65
1 com[63:0] coms
0 com[0:23] reserve com[24:47] coms
1/49
1/33
1/55
1/53
The LCD Driver Circuits

These are a 187-channel that generates four voltage levels crystal drive voltage output.
for driving the LCD . The combination of the display data, the Figure 6 shows examples of the SEG and COM output
COM scan signal, and the FR signal produces the liquid wave form.
Ver 0.3c 29/72 2002/07/22

ST7565S
VDD
FR VSS
COM0
VDD
V1
COM1 V2
COM2 COM0 V3
V4
COM3
V5
COM4 VDD
COM5 V1
V2
COM6
COM1 V3
COM7 V4
V5
COM8 VDD
V1
COM9
V2
COM10 COM2 V3
COM11
V4
V5
COM12 VDD
COM13 V1
V2
COM14
SEG0 V3
V4
SEG 0 1 2 3 4 V5
VDD
V1
V2
SEG1 V3
V4
V5
V5
V4
V3
V2
V1
COM0 to
VDD
SET0
-V1
-V2
-V3
-V4
-V5
V5
V4
V3
V2
V1
COM0 to
VDD
SET1
-V1
-V2
-V3
-V4
-V5
Figure 6
Ver 0.3c 30/72 2002/07/22

ST7565S
The Power Supply Circuits
The power supply circuits are low-power consumption power voltage follower circuits ON or OFF independently through
supply circuits that generate the voltage levels required for the use of the Power Control Set command. Consequently, it
the LCD drivers. They are Booster circuits, voltage regulator is possible to make an external power supply and the internal
circuits, and voltage follower circuits. They are only enabled power supply function somewhat in parallel. Table 7 shows
in master operation. The power supply circuits can turn the the Power Control Set Command 3-bit data control function,
Booster circuits, the voltage regulator circuits, and the and Table 8 shows reference combinations.
Table 7
Status
bit function
“1” “0”
D2 Booster circuit control bit ON OFF

D1 Voltage regulator circuit control bit (V/R circuit) ON OFF
D0 Voltage follower circuit control bit (V/F circuit) ON OFF
The Control Details of Each Bit of the Power Control Set Command
Table 8
External
Voltage Voltage Voltage Step-up
Use Settings D2 D1 D0 voltage
booster regulator follower input
voltage
Only the internal power supply is used 1 1 1 ON ON ON VSS2 Used

Only the voltage regulator circuit and the
0 1 1 OFF ON ON VOUT, VSS2 Open
voltage follower circuit are used
Only the V/F circuit is used 0 0 1 OFF OFF ON V5, VSS2 Open
Only the external power supply is used 0 0 0 OFF OFF OFF V1 to V5 Open
Reference Combinations
* The “step-up system terminals” refer CAP1+, CAP1–, CAP2+, CAP2–, and CAP3–.
* While other combinations, not shown above, are also possible, these combinations are not recommended
because they have no practical use.
The Step-up Voltage Circuits

Using the step-up voltage circuits equipped within the 4X step-up: Connect capacitor C1 between CAP1+ and
ST7565S chips it is possible to product a 2X,3X,4X,5X or 6X CAP1–, between CAP2+ and CAP2–, between
step-up of the VDD – VSS2 voltage levels. CAP1+ and CAP3–, and between VSS2 and
6X step-up: Connect capacitor C1 between CAP1+ and VOUT, to produce a voltage level in the negative
CAP1–, between CAP2+ and CAP2–, between direction at the VOUT terminal that is 4 times the
CAP1+ and CAP3–, between CAP2+ and voltage level between VDD and VSS2.
CAP4–,between CAP1+ and CAP5–, and 3X step-up: Connect capacitor C1 between CAP1+ and CAP1–, between
between VSS2 and VOUT, to produce a voltage CAP2+ and CAP2– and between VSS2 and VOUT, and short
level in the negative direction at the VOUT between CAP3– and VOUT to produce voltages
terminal that is 6 times the voltage level level in the negative direction at the VOUT
between VDD and VSS2. terminal that is 3 times the voltage difference
5X step-up: Connect capacitor C1 between CAP1+ and between VDD and VSS2.
CAP1–, between CAP2+ and CAP2–, between 2X step-up: Connect capacitor C1 between CAP1+ and
CAP1+ and CAP3–, between CAP2+ and CAP1–, and between VSS2 and VOUT, leave
CAP4–,and between VSS2 and VOUT, to CAP2+ open, and short between CAP2–,
produce a voltage level in the negative direction CAP3– and VOUT to produce a voltage in the
at the VOUT terminal that is 5 times the voltage negative direction at the VOUT terminal that Is
level between VDD and VSS2. twice the voltage between VDD and VSS2.
The step-up voltage relationships are shown in Figure 7.
Ver 0.3c 31/72 2002/07/22

ST7565S
VSS2 VSS2 VSS2

C1 C1 C1
VOUT VOUT VOUT
CAP3- CAP3- CAP3-

C1
ST7565S
ST7565S
ST7565S
CAP1+ CAP1+ CAP1+
C1 C1 C1
CAP1- CAP1- CAP1-
CAP2- CAP2- CAP2-

C1 C1
CAP2+ CAP2+ OPEN CAP2+
OPEN CAP4- OPEN CAP4- OPEN CAP4-

OPEN CAP5- OPEN CAP5- OPEN CAP5-
4x step-up voltage circuit 3x step-up voltage circuit 2x step-up voltage circuit

VDD=0V VDD=0V VDD=0V
VSS2=-3V VSS2=-3V
VSS2=-3V
VOUT=3xVSS2=-9V VOUT=2xVSS2=-6V
VOUT=4xVSS2=-12V
3x step-up voltage relationships 2x step-up voltage relationships
4x step-up voltage relationships
VSS2 VSS2
C1 C1
VOUT VOUT
CAP3- CAP3-
C1 C1
ST7565S
ST7565S
CAP1+ CAP1+
C1 C1
CAP1- CAP1-
CAP2- CAP2-
C1 C1
CAP2+ CAP2+
C1 C1
CAP4- C1 CAP4-
OPEN CAP5- CAP5-
5x step-up voltage circuit 6x step-up voltage circuit

VDD=0V VDD=0V
VSS2=-2V VSS2=-2V
VOUT=5xVSS2=-10V VOUT=6xVSS2=-12V
5x step-up voltage relationships 6x step-up voltage relationships
Figure 7
* The VSS2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rated value.
Ver 0.3c 32/72 2002/07/22

ST7565S
The Voltage Regulator Circuit
The step-up voltage generated at VOUT outputs the LCD function and internal resistors for the V5 voltage regulator,
driver voltage V5 through the voltage regulator circuit. systems can be constructed without having to include
Because the ST7565S chips have an internal high-accuracy high-accuracy voltage regulator circuit components.
fixed voltage power supply with a 64-level electronic volume (VREG thermal gradients approximate -0.05%/°C)
(A) When the V5 Voltage Regulator Internal Resistors Are Used

Through the use of the V5 voltage regulator internal resistors adjust the liquid crystal display brightness. The V5 voltage
and the electronic volume function the liquid crystal power can be calculated using equation A-1 over the range where
supply voltage V5 can be controlled by commands alone | V5 | < | VOUT |.
(without adding any external resistors), making it possible to
( Rb
V5 = 1 +
Ra )
V EV
Rb α
=(1 + ) ( 162 )
1- V REG
Ra
α
[∵ V = ( 1 - 162
EV ) V ] REG
VDD
VEV(constant voltage supply+electronic volume)

Internal Ra
V5
Internal Rb
Figure 8
Ver 0.3c 33/72 2002/07/22

ST7565S
VREG is the IC-internal fixed voltage supply, and its voltage at Ta = 25°C is as shown in Table 9.
Table 9
Part no. Equipment Type Thermal Gradient VREG
ST7565S Internal Power Supply –0.05 %/°C –2.1V
α is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic
volume registers. Table 10 shows the value for α depending on the electronic volume register settings.
Rb/Ra is the V5 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V5 voltage regulator
internal resistor ratio set command. The (1 + Rb/Ra) ratio assumes the values shown in Table 11 depending on the 3-bit data
settings in the V5 voltage regulator internal resistor ratio register.
Table 10
D5 D4 D3 D2 D1 D0 α
0 0 0 0 0 0 63
0 0 0 0 0 1 62
0 0 0 0 1 0 61
: :
: :
1 1 1 1 0 1 2
1 1 1 1 1 0 1
1 1 1 1 1 1 0
V5 voltage regulator internal resistance ratio register value and (1 + Rb/Ra) ratio (Reference value)
Table 11
Register ST7565S
D2 D1 D0 (1) –0.05 %/°C
0 0 0 3.0
0 0 1 3.5
0 1 0 4.0
0 1 1 4.5
1 0 0 5.0
1 0 1 5.5
1 1 0 6.0
1 1 1 6.5
Figures 9, 10 show V5 voltage measured by values of the internal resistance ratio resistor for V5 voltage adjustment and electric
volume resister for each temperature grade model.
Ver 0.3c 34/73 2002/07/22

ST7565S
V5
UNIT:V Ta = 25 °C and booster off ,regulator,follower on VSS=-3V
-15
-14
-13 111
-12 110
-11 101
-10
100
-9 011
-8 010
-7 001
-6 000
V5 voltage regulator
-5
internal resistor ratio set
-4
D2,D1,D0
-3
-2
-1 Electronic volume registered
0 D5 ~ D0
00H 1FH 3FH
Figure 9 : (1) For ST7565S the Thermal Gradient = -0.05%/°C
The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register.
Setup example: When selecting Ta = 25°C and V5 = –7V for an ST7565S on which Temperature gradient = –0.05%/°C.
Using Figure 9 and the equation A-1, the following setup is enabled.
At this time, the variable range and the notch width of the V5 voltage is, as shown Table 13, as dependent on the electronic
volume.
Table 12
Register
Contents
D5 D4 D3 D2 D1 D0
For V5 voltage regulator — — — 0 1 0
Electronic Volume 1 0 0 1 0 1
Table 13
V5 Min Typ Max Units
Variable Range –8.4 (63 levels) –7.0 (central value) –5.1 (0 level) [V]
Notch width 51 [mV]
Ver 0.3c 35/73 2002/07/22

ST7565S
(B) When an External Resistance is Used (The V5 Voltage Regulator Internal Resistors Are Not Used) (1)
The liquid crystal power supply voltage V5 can also be set by controlling the liquid crystal power supply voltage V5
without using the V5 voltage regulator internal resistors (IRS through commands.
terminal = “L”) by adding resistors Ra’ and Rb’ between VDD In the range where | V5 | < | VOUT |, the V5 voltage can be
and VR, and between VR and V5, respectively. When this is calculated using equation B-1 based on the external
done, the use of the electronic volume function makes it resistances Ra’ and Rb’.
possible to adjust the brightness of the liquid crystal display
( Rb'
V5 = 1 +
Ra' )
V EV
Rb' α
=(1 + ) ( 162 )
1- V REG
Ra'
α
[∵ V = ( 1 - 162
EV ) V ] REG
VDD
VEV(fixed voltage power supply+electronic volume)

External
resistor Ra'
V5
External
resistor Rb'
Figure 11
Setup example: When selecting Ta = 25°C and V5 = –7 V for

ST7565S the temperature gradient = –0.05%/°C.
Rb'
When the central value of the electron volume register is = 3.12
(D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α = 31 and Ra'
VREG = –2.1V so, according to equation B-1,
Ra' = 340kΩ
( Rb'
V5 = 1 +
Ra' ) (
1-
α
162 )
VREG Rb' = 1060kΩ
Rb' 31
-7V = ( 1 + ) ( 162 )
1- (-2.1)
Ra' At this time, the V5 voltage variable range and notch
width, based on the electron volume function, is as
Moreover, when the value of the current running through given in Table 14.
Ra’ and Rb’ is set to 5 uA,
Consequently, by equations B-2 and B-3,

Table 14
Notch width 52 [mV]
Ver 0.3c 36/73 2002/07/22

ST7565S
(C) When External Resistors are Used (The V5 Voltage Regulator Internal Resistors Are Not Used) (2)
When the external resistor described above are used, adding crystal display brightness.
a variable resistor as well makes it possible to perform fine In the range where | V5 | < | VOUT | the V5 voltage can be
adjustments on Ra’ and Rb’, to set the liquid crystal drive calculated by equation C-1 below based on the R1 and R2
voltage V5. In this case, the use of the electronic volume (variable resistor) and R 3 settings, where R 2 can
function makes it possible to control the liquid crystal power be subjected to fine adjustments (Δ R2).
supply voltage V 5 by commands to adjust the liquid
( R3+R2-ΔR2
V5 = 1 +
R1+ΔR2 )
V EV
R3+R2-ΔR2 α
=(1 +
R1+ΔR2 ) ( 162 )
1- VREG
α
[∵ V = ( 1 - 162
EV ) V ] REG
VDD
VEV(fixed voltage power supply+electronic volume)

Ra' External
resistor R1
ΔR2 V5
External
resistor R2
VR
External
Rb' resistor R3
Figure 12
Setup example: When selecting Ta = 25°C and V5 = –5 to –9

V (using R2) for an ST7565S the temperature gradient With this, according to equation C-2, C-3 and C-4,
= –0.05%/°C.
When the central value for the electronic volume register is R1 = 264kΩ
set at (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α =
31 and VREG = –2.1 V so, according to equation C-1, when Δ R2 = 211kΩ
R2 = 0 Ω, in order to make V5 = –9 V,
R3 = 925kΩ
R3+R2 31
-9V= 1 +( R1 ) ( 1 - 162 ) (-2.1) The V5 voltage variable range and notch width based on the
electron volume function is as shown in Table 15.
When ΔR2 = R2, in order to make V = –5 V,
R3 31
-5V= 1 +( R1+R2 ) ( 1 - 162 ) (-2.1)
When the current flowing VDD and V5 is set to 5 uA,
Table 15
Notch width 53 [mV]
Ver 0.3c 37/72 2002/07/22

ST7565S
* When the V5 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the
voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands.
Moreover, it is necessary to provide a voltage from VOUT when the Booster circuit is OFF.
* The VR terminal is enabled only when the V5 voltage regulator internal resistors are not used (i.e. the IRS terminal = “L”).
When the V5 voltage regulator internal resistors are used (i.e. when the IRS terminal = “H”), then the VR terminal
is left open.
* Because the input impedance of the VR terminal is high, it is necessary to take into consideration short leads, shield
cables, etc. to handle noise.
The LCD Voltage Generator Circuit

The V5 voltage is produced by a resistive voltage divider when the voltage follower changes the impedance, it
within the IC, and can be produced at the V1, V2, V3, and V4 provides V1, V2, V3 and V4 to the liquid crystal drive circuit.
voltage levels required for liquid crystal driving. Moreover,
High Power Mode

The power supply circuit equipped in the ST7565S chips has the display be checked on actual equipment to determine
very low power consumption (normal mode: HPM = “H”). whether or not to use this mode. Moreover, if the
However, for LCDs or panels with large loads, this low-power improvement to the display is inadequate even after high
power supply may cause display quality to degrade. When power mode has been set, then it is necessary to add a liquid
this occurs, setting the HPM terminal to “L” (high power mode) c r y s t a l d r i v e p o w e r s u p p l y
can improve the quality of the display. We recommend that externally.
The Internal Power Supply Shutdown Command Sequence

The sequence shown in Figure 13 is recommended for power supply in power saver mode and then turning
shutting down the internal power supply, first placing the the power supply OFF.
Sequence Details Command address

(Command, status) D7 D6 D5 D4 D3 D2 D1 D0
Step1 Display OFF 1 0 1 0 1 1 1 0 Power saver
Step2 Display all points ON 1 0 1 0 0 1 0 1 commands
End Internal power supply OFF (compound)
Figure 13
The temperature grade of the Internal Power Supply for ST7565S (-0.05%/°C) :
8.735V Ta=-40°C , V5=8.735V
Ta=25°C , V5=8.460V
8.460V
Ta=85°C , V5=8.206V
8.206V
V5 0V Ta
-40°C -20°C 0°C 25°C 50°C 85°C
Figure 14
Ver 0.3c 38/72 2002/07/22

ST7565S
Reference Circuit Examples
Figure 15 shows reference circuit examples.
1. When used all of the step-up circuit, voltage regulating circuit and V/F circuit
(1) When the voltage regulator internal resistor (2) When the voltage regulator internal resistor
is used. is not used.
(Example where VSS2 = VSS, with 4x step-up) (Example where VSS2 = VSS, with 4x step-up)
VDD VDD
IRS M/S IRS M/S
VSS2 VSS2
VSS C1 VSS C1
VOUT VOUT
CAP3- CAP4- CAP3- CAP4-

C1 C1
CAP1+ CAP5- CAP1+ CAP5-
C1 C1
CAP1- CAP1-
CAP2+ CAP2+
C1 C1
CAP2- CAP2-
R3
ST7565S
ST7565S
V5 V5
VR R2 VR
VDD VDD R1
VDD VDD
C2 C2
V1 V1
C2 C2
V2 V2
C2 C2
V3 V3
C2 C2
V4 V4
C2 C2
V5 V5
2. When the voltage regulator circuit and V/F circuit alone are used
(1) When the V 5 voltage regulator internal resistor (2) When the V 5 voltage regulator internal resistor
is not used. is used.
VDD VDD
IRS M/S IRS M/S
VSS2 VSS2
VSS VSS
VOUT VOUT
External External
power CAP3- CAP4- power CAP3- CAP4-
supply supply
CAP1- CAP1-
CAP2+ CAP2+
CAP2- CAP2-
R3
ST7565S
ST7565S
V5 V5
R2 VR VR
VDD R1 VDD
VDD VDD
C2 C2
V1 V1
C2 C2
V2 V2
C2 C2
V3 V3
C2 C2
V4 V4
C2 C2
V5 V5
3. When the V/F circuit alone is used 4. When the built-in power is not used
Ver 0.3c 39/72 2002/07/22

ST7565S
VDD
VDD
VSS
IRS M/S IRS M/S
VSS2 VSS2
VSS
VOUT VOUT
CAP3- CAP4- CAP3- CAP4-
CAP1- CAP1-
CAP2+ CAP2+
External
power CAP2- CAP2-
supply
ST7565S
ST7565S
V5 V5
VR VR
VDD VDD
VDD VDD
C2
V1 V1
C2
V2 V2
C2
V3 External power supply V3
C2
V4 V4
C2
V5 V5
5. When the built-in power circuit is used to drive a liquid built-in voltage follower.
crystal panel heavily loaded with AC or DC, it is Examples of shared reference settings When V5 can vary
recommended to connect an external resistor to stabilize between –8 and 12 V
potentials of V1, V2, V3 and V4 which are output from the
VDD,V0
Item Set value units

R4 R4
c1 1.0 to 4.7 uF
c2 0.1 to 4.7 uF
C2
V1
C1 and C2 are determined by the size of
ST7565S
V2
the LCD being driven
V3
V4
R4 R4
V5
Reference set value R4: 100KΩ ~ 1MΩ It is recommended crystal display and the drive waveform.
to set an optimum resistance value R4 taking the liquid
Figure 15
* 1. Because the VR terminal input impedance is high, use short leads and shielded lines.
* 2. C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive
voltage.
Example of the Process by which to Determine the Settings:
• Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside.
• Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that stabilizes the
liquid crystal drive voltages (V1 to V5). Note that all C2 capacitors must have the same capacitance value.
• Next turn all the power supplies ON and determine C1.
Ver 0.3c 40/72 2002/07/22

ST7565S
The Reset Circuit
When the /RES input comes to the “L” level, these LSIs
return to the default state. Their default states are as follows:
1. Display OFF On the other hand, when the reset command is used, the
2. Normal display above default settings from 11 to 19 are only executed.
3. ADC select: Normal (ADC command D0 = “L”) When the power is turned on, the IC internal state becomes
4. Power control register: (D2, D1, D0) = (0, 0, 0) unstable, and it is necessary to initialize it using the /RES
5. Serial interface internal register data clear terminal. After the initialization, each input terminal should
6. LCD power supply bias rate: be controlled normally.
1/65 DUTY = 1/9 bias Moreover, when the control signal from the MPU is in the
1/49,1/55,1/53 DUTY = 1/8 bias high impedance, an over current may flow to the IC. After
1/33 DUTY = 1/6 bias applying a current, it is necessary to take proper measures to
7. All-indicator lamps-on OFF (All-indicator lamps ON/OFF prevent the input terminal from getting into the high
command D0 = “L”) impedance state.
8. Power saving clear If the internal liquid crystal power supply circuit is not used on
9. V 5 voltage regulator internal resistors Ra and Rb ST7565S,it is necessary that /RES is “H” when the external
separation liquid crystal power supply is turned on. This IC has the
10. Output conditions of SEG and COM terminals function to discharge V5 when /RES is “L,” and the external
SEG=VDD , COM=VDD power supply short-circuits to V DD when /RES is “L.”
11. Read modify write OFF While /RES is “L,” the oscillator and the display timing
12. Static indicator OFF Static indicator register : (D1, D2) = generator stop, and the CL, FR, FRS and /DOF terminals are
(0, 0) fixed to “H.” The terminals D0 to D7 are not affected. The
13. Display start line set to first line VDD level is output from the SEG and COM output terminals.
14. Column address set to Address 0 This means that an internal resistor is connected between
15. Page address set to Page 0 VDD and V5.
16. Common output status normal When the internal liquid crystal power supply circuit is not
17. V5 voltage regulator internal resistor ratio set mode clear used on other models of ST7565S series, it is necessary that
18. Electronic volume register set mode clear Electronic /RES is “L” when the external liquid crystal power supply is
volume register : turned on.
(D5, D4, D3, D2, D1, D0) = (1, 0. 0, 0, 0,0) While /RES is “L,” the oscillator works but the display timing
19. Test mode clear generator stops, and the CL, FR, FRS and /DOF terminals
are fixed to “H.” The terminals D0 to D7 are not affected.
Ver 0.3c 41/72 2002/07/22

ST7565S
COMMANDS
The ST7565S identify the data bus signals by a combination of A0, /RD (E), /WR(R/W) signals. Command interpretation and
execution does not depend on the external clock, but rather is performed through internal timing only, and
thus the processing is fast enough that normally a busy check is not required.
In the 8080 MPU interface, commands are launched by inputting a low pulse to the RD terminal for reading, and inputting a low
pulse to the /WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read mode when an “H” signal
is input to the R/W terminal and placed in a write mode when a “L” signal is input to the R/W terminal and then the command is
launched by inputting a high pulse to the E terminal. Consequently, the 6800 Series MPU interface is different than the 80x86
Series MPU interface in that in the explanation of commands and the display commands the status read and display data read
/RD (E) becomes “1(H)”. In the explanations below the commands are explained using the 8080 Series MPU interface as the
example.
When the serial interface is selected, the data is input in sequence starting with D7.
<Explanation of Commands>
Display ON/OFF
This command turns the display ON and OFF.
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2
D0 D1 Setting
0 1 0 1 0 1 0 1 1 1 1 Display ON
0 Display OFF
When the display OFF command is executed when in the display all points ON mode, power saver mode is entered. See the
section on the power saver for details.
Display Start Line Set
This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further details
see the explanation of this function in “The Line Address Circuit”.
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Line address

0 1 0 0 1 0 0 0 0 0 0 0
0 0 0 0 0 1 1
0 0 0 0 1 0 2
↓ ↓
1 1 1 1 1 0 62
1 1 1 1 1 1 63
Page Address Set

This command specifies the page address corresponding to the low address when the MPU accesses the display data RAM
(see Figure 4). Specifying the page address and column address enables to access a desired bit of the display data RAM.
Changing the page address does not accompany a change in the status display.
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Page address

0 1 0 1 0 1 1 0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
↓ ↓
0 1 1 1 7
1 0 0 0 8
Ver 0.3c 42/72 2002/07/22

ST7565S
Column Address Set
This command specifies the column address of the display data RAM shown in Figure 4. The column address is split into two
sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the display data RAM
is accessed, the column address automatically increments (+1), making it possible for the MPU to continuously read from/write
to the display data. The column address increment is topped at 83H. This does not change the page address continuously. See
the function explanation in “The Column Address Circuit,” for details.
E R/W
Column
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0 address
High bits → 0 1 0 0 0 0 1 A7 A6 A5 A4 0 0 0 0 0 0 0 0 0
Low bits → 0 A3 A2 A1 A0 0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 1 0 2
↓ ↓
1 0 0 0 0 0 1 0 130
1 0 0 0 0 0 1 1 131
Status Read
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 BUSY ADC ON/OFF RESET 0 0 0 0
BUSY = 1: it indicates that either processing is occurring internally or a reset condition is in process.
BUSY BUSY = 0: A new command can be accepted . if the cycle time can be satisfied, there is no need to check
for BUSY conditions.
This shows the relationship between the column address and the segment driver.
ADC 0: Normal (column address n ↔ SEG n)
1: Reverse (column address 131-n ↔ SEG n)
(The ADC command switches the polarity.)
ON/OFF: indicates the display ON/OFF state.
ON/OFF 0: Display ON
1: Display OFF
(This display ON/OFF command switches the polarity.)
This indicates that the chip is in the process of initialization either because of a /RES signal or because of a
reset command.
RESET
0: Operating state
1: Reset in progress
Display Data Write

This command writes 8-bit data to the specified display data RAM address. Since the column address is automatically
incremented by “1” after the write, the MPU can write the display data.
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 Write data
Ver 0.3c 43/72 2002/07/22

ST7565S
Display Data Read
This command reads 8-bit data from the specified display data RAM address. Since the column address is automatically
incremented by “1” after the read, the CPU can continuously read multiple-word data. One dummy read is required immediately
after the column address has been set. See the function explanation in “Display Data RAM” for the explanation of accessing the
internal registers. When the serial interface is used, reading of the display data becomes unavailable.
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 Read data
ADC Select (Segment Driver Direction Select)

This command can reverse the correspondence between the display RAM data column address and the segment driver output.
Thus, sequence of the segment driver output pins may be reversed by the command. See the column address circuit (page
1–20) for the detail. Increment of the column address (by “1”) accompanying the reading or writing the display data is done
according to the column address indicated in Figure 4.
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Setting

0 1 0 1 0 1 0 0 0 0 0 Normal
1 Reverse
Display Normal/Reverse
This command can reverse the lit and unlit display without overwriting the contents of the display data RAM. When this is done
the display data RAM contents are maintained.
E R/W

0 1 0 1 0 1 0 0 1 1 0 RAM Data “H”
LCD ON voltage (normal)
1 RAM Data “L”
LCD ON voltage (reverse)
Display All Points ON/OFF

This command makes it possible to force all display points ON regardless of the content of the display data RAM. The contents
of the display data RAM are maintained when this is done. This command takes priority over the display normal/reverse
command.
E R/W

0 1 0 1 0 1 0 0 1 0 0 Normal display mode
1 Display all points ON
When the display is in an OFF mode, executing the display all points ON command will place the display in power save mode.
For details, see the Power Save section.
Ver 0.3c 44/72 2002/07/22

ST7565S
LCD Bias Set
This command selects the voltage bias ratio required for the liquid crystal display.
E R/W Select Status
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 1/65duty 1/49duty 1/33duty 1/55duty 1/53duty

1 0 1 0 0 0 1 0 1/9 bias 1/8 bias 1/6 bias 1/8 bias 1/8 bias
0 1 0
1 1/7 bias 1/6 bias 1/5 bias 1/6 bias 1/6 bias
Read/Modify/Write
This command is used paired with the “END” command. Once this command has been input, the display data read command
does not change the column address, but only the display data write command increments (+1) the column address. This mode
is maintained until the END command is input. When the END command is input, the column address returns to the address it
was at when the read/modify/write command was entered. This function makes it possible to reduce the load on the MPU when
there are repeating data changes in a specified display region, such as when there is a blanking cursor.
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 1 1 0 0 0 0 0
* Even in read/modify/write mode, other commands aside from display data read/write commands can also be used.
Page address set
Column address set
Read-modify-write cycle
Dummy read
Data read
Data write
NO
Changes
Finished ?
YES
END
Figure 24 Command Sequence For read modify write
Ver 0.3c 45/72 2002/07/22

ST7565S
Return
Column address N N+1 N+2 N+3 N+m N
Read-modify-write mode set End
Figure 25
End
This command releases the read/modify/write mode, and returns the column address to the address it was at when the mode
was entered.
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 1 1 0 1 1 1 0
Reset
This command initializes the display start line, the column address, the page address, the common output mode, the V5 voltage
regulator internal resistor ratio, the electronic volume, and the static indicator are reset, and the read/modify/write mode and
test mode are released. There is no impact on the display data RAM. See the function explanation in “Reset” for details.
The reset operation is performed after the reset command is entered.
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 1 1 0 0 0 1 0
The initialization when the power supply is applied must be done through applying a reset signal to the /RES terminal. The reset
command must not be used instead.
Common Output Mode Select

This command can select the scan direction of the COM output terminal. For details, see the function explanation in
“Common Output Mode Select Circuit.”
E R/W Selected Mode

A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0
1/65duty 1/49duty 1/33duty 1/55duty 1/53duty
1 1 0 0 0 * * * Normal COM0→COM63 COM0→COM47 COM0→COM31 COM0→COM53 COM0→COM51
0 1 0 Reverse COM63→COM0 COM47→COM0 COM31→COM0 COM53→COM0 COM51→COM0
1
* Disabled bit
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ST7565S
Power Controller Set
This command sets the power supply circuit functions. See the function explanation in “The Power Supply Circuit,” for details
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Selected Mode

0 0 1 0 1 0 Booster circuit: OFF
1 Booster circuit: ON
0 Voltage regulator circuit: OFF
0 1 0
1 Voltage regulator circuit: ON
0 Voltage follower circuit: OFF
1 Voltage follower circuit: ON
V5 Voltage Regulator Internal Resistor Ratio Set

This command sets the V5 voltage regulator internal resistor ratio. For details, see the function explanation is “The Voltage
Regulator circuit " and table 11 .
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Rb/Ra Ratio

0 0 1 0 0 0 0 0 Small
0 0 1
0 1 0
0 1 0
↓ ↓
1 1 1
1 1 1 Large
The Electronic Volume (Double Byte Command)

This command makes it possible to adjust the brightness of the liquid crystal display by controlling the LCD drive voltage V5
through the output from the voltage regulator circuits of the internal liquid crystal power supply. This command is a two byte
command used as a pair with the electronic volume mode set command and the electronic volume register set
command, and both commands must be issued one after the other.
The Electronic Volume Mode Set

When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume mode
has been set, no other command except for the electronic volume register command can be used. Once the electronic
volume register set command has been used to set data into the register, then the electronic volume mode is released.
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 0 0 0 0 0 0 1
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ST7565S
Electronic Volume Register Set
By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V5 assumes one
of the 64 voltage levels.
When this command is input, the electronic volume mode is released after the electronic volume register has been set.
E R/W
A0 /RD /WR D7 D6 D5 D4D3 D2 D1 D0 | V5 |

* * 0 00 0 0 1 Small
* * 0 00 0 1 0
* * 0 00 0 1 1
0 1 0
↓ ↓
* * 1 1 1 1 1 0
* * 1 1 1 1 1 1 Large
* Inactive bit (set “0”)
When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0)
The Electronic Volume Register Set Sequence
electronic volume mode set
electronic volume register set
Electronic volume mode clear

NO
Set complete ?
YES
Figure 26
Static Indicator (Double Byte Command)

This command controls the static drive system indicator display. The static indicator display is controlled by this command only,
and is independent of other display control commands.
This is used when one of the static indicator liquid crystal drive electrodes is connected to the FR terminal, and the other is
connected to the FRS terminal. A different pattern is recommended for the static indicator electrodes than for the dynamic drive
electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes.
The static indicator ON command is a double byte command paired with the static indicator register set command, and thus
one must execute one after the other. (The static indicator OFF command is a single byte command.)
Static Indicator ON/OFF
When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static
indicator ON command has been entered, no other command aside from the static indicator register set command can be used.
T h i s m o d e is clea red whe n dat a is se t in the r egist er by th e st atic ind ic at or reg is te r set com mand .
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Static Indicator

1 0 1 0 1 1 0 0 OFF
0 1 0
1 ON
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ST7565S
Static Indicator Register Set
This command sets two bits of data into the static indicator register, and is used to set the static indicator into a blinking mode.
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Indicator Display State

* * * * * * 0 0 OFF
0 1 ON (blinking at approximately one second intervals)
0 1 0
1 0 ON (blinking at approximately 0.5 second intervals)
1 1 ON (constantly on)
* Disabled bit (set “0”)
Static Indicator Register Set Sequence
Static indicator mode set
Static indicator register set
Static indicator mode clear

NO
Set complete ?
YES
Figure 27
Power Save (Compound Command)
When the display all points ON is performed while the display is in the OFF mode, the power saver mode is entered, thus
greatly reducing power consumption.
The power saver mode has two different modes: the sleep mode and the standby mode. When the static indicator is OFF, it is
the sleep mode that is entered. When the static indicator is ON, it is the standby mode that is entered.
In the sleep mode and in the standby mode, the display data is saved as is the operating mode that was in effect before the
power saver mode was initiated, and the MPU is still able to access the display data RAM.
Refer to figure 28 for power save off sequence.
Static indicator ON
Static indicator OFF
Display OFF
Display OFF
Display all point ON

Display all point ON
Standby mode
Sleep mode
Power save OFF

Power save OFF
( Display all point OFF )
Display all point OFF
Static indicator ON (2 bytes)
Standby mode cancel

Sleep mode cancel
Figure 28
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ST7565S
Sleep Mode
This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption
current is reduced to a value near the static current. The internal modes during sleep mode are as follows:
1. The oscillator circuit and the LCD power supply circuit are halted.
2. All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VDD level.
Standby Mode
The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate,
providing the minimum required consumption current for the static drive. The internal modes are in the following states during
standby mode.
1 The LCD power supply circuits are halted. The oscillator circuit continues to operate.
2 The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs output a VDD level.
The static drive system does not operate.
When a reset command is performed while in standby mode, the system enters sleep mode.
* When an external power supply is used, it is recommended that the functions of the external power supply circuit be stopped
when the power saver mode is started. For example, when the various levels of liquid crystal drive voltage are provided by
external resistive voltage dividers, it is recommended that a circuit be added in order to cut the electrical current flowing
through the resistive voltage divider circuit when the power saver mode is in effect. The ST7565S series chips have a liquid
crystal display blanking control terminal /DOF. This terminal enters an “L” state when the power saver mode is launched.
Using the output of /DOF, it is possible to stop the function of an external power supply circuit.
* When the master is turned on, the oscillator circuit is operable immediately after the powering on.
The Booster Ratio (Double Byte Command)

This command makes it possible to select step-up ratio. It is used when the power control set have turn on the internal booster
circuit. This command is a two byte command used as a pair with the booster ratio select mode set command and the booster
ratio register set command, and both commands must be issued one after the other.
Booster Ratio Select Mode Set
When this command is input, the Booster ratio register set command becomes enabled. Once the booster ratio select mode has
been set, no other command except for the booster ratio register command can be used. Once the booster ratio register
set command has been used to set data into the register, then the booster ratio select mode is released.
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 1 1 1 1 0 0 0
Booset Ratio Register Set

By using this command to set two bits of data to the booster ratio register,it can be select what kind of the booster ratio can be
used.
When this command is input, the booster ratio select mode is released after the booster ratio register has been set.
E R/W
D7 D6 D5 D4 D3 D2 D1 D0 Booster
A0 /RD /WR ratio
select
* * * * * * 0 0 2x,3x,4x
0 1 0 * * * * * * 0 1 5x
* * * * * * 1 1 6x
* Inactive bit (set “0”)
When the booster ratio select function is not used, set this to (0, 0) 2x,3x,4x step-up mode
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ST7565S
The booster ratio Register Set Sequence
booster ratio select mode set
booster ratio register set
Booster ratio select mode clear

NO
Set complete ?
YES
Figure 29
NOP
Non-OPeration Command
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 1 1 0 0 0 1 1
Test
This is a command for IC chip testing. Please do not use it. If the test command is used by accident, it can be cleared by
applying a “L” signal to the /RES input by the reset command or by using an NOP.
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 1 1 1 1 1 * *
* Inactive bit
Note: The ST7565S maintain their operating modes until something happens to change them. Consequently, excessive
external noise, etc., can change the internal modes of the ST7565S . Thus in the packaging and system design it is
necessary to suppress the noise or take measure to prevent the noise from influencing the chip. Moreover, it is
recommended that the operating modes be refreshed periodically to prevent the effects of unanticipated
noise.
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ST7565S
Table 16: Table of ST7565S Commands (Note) *: disabled data
Command Code
Command Function
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 1 1 1 0 LCD display ON/OFF
(1) Display ON/OFF 0 1 0
1 0: OFF, 1: ON
Sets the display RAM display start
(2) Display start line set 0 1 0 0 1 Display start address
line address
Sets the display RAM page
(3) Page address set 0 1 0 1 0 1 1 Page address
address
(4) Column address set 0 1 0 0 0 0 1 Most significant Sets the most significant 4 bits of
upper bit column address the display RAM column address.
Column address set 0 1 0 0 0 0 0 Least significant Sets the least significant 4 bits of
lower bit column address the display RAM column address.
(5) Status read 0 0 1 Status 0 0 0 0 Reads the status data
(6) Display data write 1 1 0 Write data Writes to the display RAM
(7) Display data read 1 0 1 Read data Reads from the display RAM
Sets the display RAM address
1 0 1 0 0 0 0 0
(8) ADC select 0 1 0 SEG output correspondence
1
0: normal, 1: reverse
Sets the LCD display normal/
(9) Display normal/ 1 0 1 0 0 1 1 0
0 1 0 reverse
reverse 1
0: normal, 1: reverse
Display all points
(10) Display all points 1 0 1 0 0 1 0 0
0 1 0 0: normal display
ON/OFF 1
1: all points ON
Sets the LCD drive voltage bias
1 0 1 0 0 0 1 0
(11) LCD bias set 0 1 0 ratio
1
0: 1/9 bias, 1: 1/7 bias (ST7565S)
Column address increment
(12) Read/modify/write 0 1 0 1 1 1 0 0 0 0 0 At write: +1
At read: 0
(13) End 0 1 0 1 1 1 0 1 1 1 0 Clear read/modify/write
(14) Reset 0 1 0 1 1 1 0 0 0 1 0 Internal reset
Select COM output scan direction
(15) Common output 1 1 0 0 0 * * *
0 1 0 0: normal direction
mode select 1
1: reverse direction
0 0 1 0 1 Operating Select internal power supply
(16) Power control set 0 1 0
mode operating mode
(17) V5 voltage regulator
0 0 1 0 0 Resistor Select internal resistor
internal resistor ratio 0 1 0
ratio ratio(Rb/Ra) mode
set
(18) Electronic volume
mode set 1 0 0 0 0 0 0 1 Set the V5 output voltage
0 1 0
Electronic volume 0 0 Electronic volume value electronic volume register
register set
(19) Static indicator
1 0 1 0 1 1 0 0 0: OFF, 1: ON
ON/OFF
0 1 0 1
Static indicator
0 0 0 0 0 0 0 Mode Set the flashing mode
register set
select booster ratio
1 1 1 1 1 0 0 0
00: 2x,3x,4x
(20) Booster ratio set 0 1 0 0 0 0 0 0 0 step-up
01: 5x
value
11: 6x
Display OFF and display all
(21) Power saver
points ON compound command
(22) NOP 0 1 0 1 1 1 0 0 0 1 1 Command for non-operation
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ST7565S
Command for IC test. Do not
(23) Test 0 1 0 1 1 1 1 * * * *
use this command
COMMAND DESCRIPTION
Instruction Setup: Reference
(1) Initialization
Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG pin) and V1 and V4 (COM
pin) are output through the LCD driving output pins SEG and COM. When electric charge is remaining in the smoothing
capacitor connecting between the LCD driving voltage output pins (V1 ~ V5) and the VDD pin, the picture on the display may
become totally dark instantaneously when the power is turned on. To avoid occurrence of such a failure, we recommend the
following flow when turning on the power.
1. When the built-in power is being used immediately after turning on the power:
Turn ON the power and keeping

the /RES pin = “L”.
When the power is stabilized
Release the reset state. (/RES pin = “H”)
Initialized state (Default) *1
Function setup by command input

(User setup)
(11) LCD bias setting *2
Arrange to execute all the
(8) ADC selection *3
procedures from releasing the
(15) Common output state selection *4
reset state through setting the
power control within 5ms.
(In case of other models)
Function setup by command input execute the procedures from
(User setup) turning on the power to setting
(17) Setting the built-in resistance radio the power control in 5ms.
for regulation of the V5 voltage *5
(18) Electronic volume control *6
Function setup by command input

(User setup)
(16) Power control setting *7
This concludes the initialization
* The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing
capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment.
Notes: Refer to respective sections or paragraphs listed below.

*1: Description of functions; Resetting circuit
*2: Command description; LCD bias setting
*3: Command description; ADC selection
*4: Command description; Common output state selection
*5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of
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ST7565S
the V5 voltage
*6: Description of functions; Power circuit & Command description; Electronic volume control
*7: Description of functions; Power circuit & Command description; Power control setting
2. When the built-in power is not being used immediately after turning on the power:
Turn ON the VDD-VSS power keeping the

/RES pin = “L”.
When the power is stabilized
Release the reset state. (/RES pin = “H”) Arrange to start the
power saver within
5ms after releasing the
Initialized state (Default) *1 reset state. (In case of
other models) execute
the procedures from
turning on the power
Power saver START
to setting the power
(multiple commands) *8
control in 5ms.
Function setup by command input (User

setup)
(11) LCD bias setting *2
(8) ADC selection *3
(15) Common output state selection *4

setup)
(17) Setting the built-in resistance radio
for regulation of the V5 voltage *5
(18) Electronic volume control *6
Power saver OFF *8

Arrange to start power
control setting within
Function setup by command input (User 5ms after turning OFF
setup) the power saver.
(16) Power control setting *7
This concludes the initialization
* The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing
capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment.
Notes: Refer to respective sections or paragraphs listed below.

*1: Description of functions; Resetting circuit
*2: Command description; LCD bias setting
*3: Command description; ADC selection
*4: Command description; Common output state selection
*5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V5
voltage
*6: Description of functions; Power circuit & Command description; Electronic volume control
*7: Description of functions; Power circuit & Command description; Power control setting
*8: The power saver ON state can either be in sleep state or stand-by state.
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ST7565S
Command description; Power saver START (multiple commands)
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ST7565S
(2) Data Display
End of initialization

setup)
(2) Display start line set *9
(3) Page address set *10
(4) Column address set *11

setup)
(6) Display data write *12

setup)
(1) Display ON/OFF *13
End of data display
Notes: Reference items

*9: Command Description; Display start line set
*10: Command Description; Page address set
*11: Command Description; Column address set
*12: Command Description; Display data write
*13: Command Description; Display ON/OFF
Avoid displaying all the data at the data display start (when the display is ON) in white.
(3) Power OFF *14
Optional status
Set the time ( t L ) from reset
active to turning off the VDD -
VSS power (VDD - VSS = 1.8V)
setup) longer than the time (tH) when
(20) Power save *15 the potential of V5 ~ V1
becomes below the threshold
voltage (approximately 1V) of
the LCD panel. For tH, refer to
Reset active (/RES pin = “L”) the <Reference Data> of this
event. When t H is too long,
insert a resistor between V5
VDD – VSS power OFF and VDD to reduce it.
Notes: Reference items
*14: The logic circuit of this IC’s power supply VDD - VSS controls the driver of the LCD power supply VDD - V5. So, if the
power supply VDD - VSS is cut off when the LCD power supply VDD - V5 has still any residual voltage, the driver
(COM. SEG) may output any uncontrolled voltage. When turning off the power, observe the following basic
procedures:
• After turning off the internal power supply, make sure that the potential V5 ~ V1 has become below the threshold
voltage of the LCD panel, and then turn off this IC’s power supply (VDD - VSS). 6. Description of Function, 6.7 Power
Circuit
*15: After inputting the power save command, be sure to reset the function using the /RES terminal until the power
supply VDD - VSS is turned off. 7. Command Description (20) Power Save
*16: After inputting the power save command, do not reset the function using the /RES terminal until the power supply
VDD - VSS is turned off. 7. Command Description (20) Power Save
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ST7565S
Refresh
It is recommended to turn on the refresh sequence regularly at a specified interval.
Refresh sequence
Reset command or NOP command
Set all commands to the ready state
Refreshing of DRAM
Precautions on Turning off the power

<Turning the power (VDD - VSS) off>
1) Power Save (The LCD powers (VDD - V5) are off.) → Reset input → Power (VDD - VSS) OFF
• Observe tL > tH.
• When tL < tH, an irregular display may occur.
Set tL on the MPU according to the software. tH is determined according to the external capacity C2 (smoothing
capacity of V5 ~ V1) and the driver’s discharging capacity.
Reset Power Off
Power save
tL
VDD
1.8V
RES
VDD
SEG
Since the power (VDD-VSS) is cut off,the
output comes not to be fixed.
VDD
COM
About 1V:below Vth of the LCD Panel

V1
V2
V3
V4
V5 tH
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ST7565S
<Turning the power (VDD - VSS) off : When command control is not possible.>
2) Reset (The LCD powers (VDD - VSS) are off.) → Power (VDD - VSS) OFF
• Observe tL > tH.
• When tL < tH, an irregular display may occur.
For tL, make the power (VDD - VSS) falling characteristics longer or consider any other method. tH is
determined according to the external capacity C2 (smoothing capacity of V5 to V1) and the driver’s discharging
capacity.
Reset Power Off
tL
VDD 1.8V
RES
VDD
SEG
Since the power (VDD-VSS) is cut off,the
output comes not be fixed.
VDD
COM
About 1V:below Vth of the LCD Panel

V1
V2
V3
V4
V5 tH
<Reference Data>
V5 voltage falling (discharge) time (tH) after the process of operation → power save → reset.
V5 voltage falling (discharge) time (tH) after the process of operation → reset.
100
VDD-VSS(V)
V5 voltage falling time (mSec)
1.8
2.4
50
3.0
4.0
5.0
0 0.5 1.0
C2 : V1 to V5 capacity (uF)
Figure 31
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ST7565S
ABSOLUTE MAXIMUM RATINGS

Unless otherwise noted, VSS = 0V
Table 17
Parameter Symbol Conditions Unit
Power Supply Voltage VDD –0.3 ~ +5.0 V
Power supply voltage (VDD standard) VSS2 –4.0 ~ -1.8 V
Power supply voltage (VDD standard) V5, VOUT –16.0 ~ +0.3 V
Power supply voltage (VDD standard) V1, V2, V3, V4 V5 to +0.3 V
Input voltage VIN –0.3 to VDD + 0.3 V
Output voltage VO –0.3 to VDD + 0.3 V
Operating temperature TOPR –40 to +85 °C

Storage temperature TCP –55 to +100
TSTR °C
Bare chip –55 to +125
VCC VDD VDD
GND VSS
VSS2,V1 to V4
V5.,VOUT
System (MPU) side ST7565S chip side
Figure 30
Notes and Cautions

1. The VSS2, V1 to V5 and VOUT are relative to the VDD = 0V reference.
2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VDD ≧ V1 ≧ V2 ≧ V3 ≧ V4 ≧ V5.
3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is
recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the LSI
outside of these conditions may not only result in malfunctions of the LSI, but may have a negative impact on the LSI
reliability as well.
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ST7565S
DC CHARACTERISTICS
Unless otherwise specified, VSS = 0 V, VDD = 3.0 V ± 10%, Ta = –40 to 85°C
Table 18
Rating Applicable
Item Symbol Condition Units
Min. Typ. Max. Pin
Operating Voltage (1) Vss -3.3 — -1.8 V Vss*1
Operating Voltage (2) VSS2 (Relative to VDD) –3.3 — –1.8 V VSS2
–13.0 — –4.0 V5 *2
Operating Voltage (3) VSS2 (Relative to VDD) 0.4 x V5 — VDD V V1, V2
V5 — 0.6 x V5 V3, V4
High-level Input Voltage VIHC 0.8 x VDD — VDD V *3
Low-level Input Voltage VILC VSS — 0.2 x VDD V *3
High-level Output Voltage VOHC IOH = –0.5 mA 0.8 x VDD — VDD V *4
Low-level Output Voltage VOLC IOL = 0.5 mA VSS — 0.2 x VDD V *4
Input leakage current ILI VIN = VDD or VSS –1.0 — 1.0 μA *5
Output leakage current ILO VIN = VDD or VSS –3.0 — 3.0 μA *6

Ta = V5 = –13.0 V — 2.0 3.5
Liquid Crystal Driver ON 25°C SEGn
RON KΩ
Resistance (Relative V5 = –8.0 V — 3.2 5.4 COMn *7
To VDD)
Static Consumption Current ISSQ — 0.01 2 μA VSS, VSS2
V5 = –13.0 V(Relative To
VDD)
Output Leakage Current I5Q — 0.01 10 μA V5
Input Terminal Capacitance CIN Ta = 25°C , f = 1 MHz — 5.0 8.0 pF

Internal
fOSC 17 20 24 kHz *8
Oscillator 1/65 duty
Ta = 25°C
External 1/33 duty
fCL 17 20 24 kHz CL
Oscillator Input
Frequency Internal
fOSC 1/49 duty 25 30 35 kHz *8
Oscillator
1/53 duty Ta = 25°C
External
fCL 1/55 duty 25 30 35 kHz CL
Input
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ST7565S
Table 19
Rating Applicable
Item Symbol Condition Units
Min. Typ. Max. Pin
Input voltage VSS2 (Relative To VDD) –3.3 — –1.8 V VSS2
Supply Step-up output
VOUT (Relative To VDD) –13.0 — — V VOUT
voltage Circuit
Internal Power
Voltage regulator
Circuit Operating VOUT (Relative To VDD) –13.0 — –6.0 V VOUT
Voltage
Voltage Follower
Circuit Operating V5 (Relative To VDD) –13.0 — –4.0 V V5 * 9
Voltage
Ta = 25°C , (Relative To VDD)
Base Voltage VRS –2.07 –2.10 –2.13 V *10
–0.05%/°C
• Dynamic Consumption Current : During Display, with the Internal Power Supply OFF Current consumed by total ICs
when an external power supply is used .
Table 20
Rating
Test pattern Symbol Condition Units Notes
Min. Typ. Max.
Display Pattern VDD = 3.0 V,
OFF
IDD V5 – VDD = –11.0 V
— 16 27 μA *11
Display Pattern VDD = 3.0 V,

Checker
IDD V5 – VDD = –11.0 V
— 19 32 μA *11
• Dynamic Consumption Current : During Display, with the Internal Power Supply ON
Table 21
Rating
Test pattern Symbol Condition Units Notes
Min. Typ. Max.
VDD = 3.0 V, Normal Mode — 60 100
Display
Pattern OFF
IDD Quad step-up voltage. μA *12
V5 – VDD = –11.0 V High-Power Mode — 98 163
Display VDD = 3.0 V, Normal Mode — 70 117

Pattern IDD Quad step-up voltage. μA *12
Checker V5 – VDD = –11.0 V High-Power Mode — 105 175
• Consumption Current at Time of Power Saver Mode : VSS = -3.0 V ± 10%
Table 22
Rating
Item Symbol Condition Units Notes
Min. Typ. Max.
Sleep mode IDD Ta = 25°C — 0.1 4
μA
Standby Mode IDD Ta = 25°C — 5 10
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ST7565S
• The Relationship Between Oscillator Frequency fOSC, Display Clock Frequency fCL and the Liquid Crystal Frame
Rate Frequency fFR
Table 23
Item fCL fFR
Used internal oscillator circuit fOSC / 4 fOSC / (4*65)

1/65 DUTY
Used external display clock External input (fCL) fCL / 260
1/49 DUTY
1/33 DUTY
1/55 DUTY
1/53 DUTY
(fFR is the liquid crystal alternating current period, and not the FR signal period.)
References for items market with *

*1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden
fluctuations to the voltage while the MPU is being accessed.
*2 The operating voltage range for the VDD system and the V5 system is. This applies when the external power supply is
being used.
*3 The A0, D0 to D5, D6 (SCL), D7 (SI), /RD (E), /WR (R/W), /CS1, CS2, CLS, CL, FR, M/S, C86, P/S, /DOF, /RES, IRS, and
/HPM terminals.
*4 The D0 to D7, FR, FRS, /DOF, and CL terminals.
*5 The A0, /RD (E), /WR (R/W), /CS1, CS2, CLS, M/S, C86, P/S, /RES, IRS, and /HPM terminals.
*6 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and /DOF terminals are in a high impedance state.
*7 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the
various power supply terminals (V 1 , V 2 , V 3 , and V 4 ). These are specified for the operating voltage (3) range.
RON = 0.1 V /ΔI (Where ΔI is the current that flows when 0.1 V is applied while the power supply is ON.)
*8 See Table 23 for the relationship between the oscillator frequency and the frame rate frequency.
*9 The V5 voltage regulator circuit regulates within the operating voltage range of the voltage follower.
*10 This is the internal voltage reference supply for the V5 voltage regulator circuit. In the ST7565S , the temperature range
approximately –0.05%/°C.
*11, 12 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on.
The ST7565S is 1/9 biased. Does not include the current due to the LCD panel capacity and wiring capacity.
Applicable only when there is no access from the MPU.
*12 It is the value on a ST7565S having the VREG temperature gradient is –0.05%/°C when the V5 voltage regulator
internal resistor is used.
Ver 0.3c 62/73 2002/07/22

ST7565S
TIMING CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
tAW8 tAH8
CS1
(CS2="1")
tCYC8
tCCLR,tCCLW
WR,RD
tCCHR,tCCHW
tDH8
tDS8
D0 to D7
(Write)
tACC8 tOH8
D0 to D7
(Read)
Figure 37
Table 24
(VDD = 3.3V , Ta =25°C)
Rating
Item Signal Symbol Condition Units
Min. Max.
Address hold time tAH8 0 —
Address setup time A0 tAW8 0 —
System cycle time tCYC8 240 —
Enable L pulse width (WRITE) tCCLW 80 —
WR
Enable H pulse width (WRITE) tCCHW 80 —
Enable L pulse width (READ) tCCLR 140 — Ns
RD
Enable H pulse width (READ) tCCHR 80
WRITE Data setup time tDS8 40 —
WRITE Address hold time tDH8 0 —
D0 to D7
READ access time tACC8 CL = 100 pF — 70
READ Output disable time tOH8 CL = 100 pF 5 50
Ver 0.3c 63/73 2002/07/22

ST7565S
Table 25
(VDD = 2.7 V , Ta = 25°C )
Rating
Min. Max.
WR
Enable L pulse width (READ) tCCLR 220 — ns
RD
Enable H pulse width (READ) tCCHR 180 —
D0 to D7
Table 26
(VDD = 1.8V , Ta = 25°C )
Rating
Min. Max.
WR
Enable L pulse width (READ) tCCLR 360 — ns
RD
Enable H pulse width (READ) tCCHR 280
D0 to D7
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tCCLW and tCCLR are specified as the overlap between /CS1 being “L” (CS2 = “H”) and /WR and /RD being at the “L” level.
Ver 0.3c 64/73 2002/07/22

ST7565S
A0
R/W
tAW6 tAH6
CS1
(CS2="1")
tCYC6
tCCLR,tCCLW
E
tCCHR,tCCHW
tDH6
tDS6
D0 to D7
(Write)
tACC6 tOH6
D0 to D7
(Read)
System Bus Read/Write Characteristics 2 (For the 6800 Series MPU)

Figure 38
Table 27
(VDD = 3.3 V , Ta = 25°C )
Rating
Min. Max.
Enable L pulse width (WRITE) tEWLW 80 —
WR
Enable H pulse width (WRITE) tEWHW 80 —
Enable L pulse width (READ) tEWLR 80 — ns
RD
Enable H pulse width (READ) tEWHR 140
D0 to D7
Ver 0.3c 65/73 2002/07/22

ST7565S
Table 28
(VDD = 2.7V , Ta =25°C )
Rating
Min. Max.
WR
RD
Enable H pulse width (READ) tEWHR 180 —
D0 to D7
Table 29
(VDD =1.8V , Ta =25°C )
Rating
Min. Max.
WR
RD
Enable H pulse width (READ) tEWHR 280 —
D0 to D7
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tEWLW and tEWLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and E.
Ver 0.3c 66/73 2002/07/22

ST7565S
The Serial Interface
tCCSS tCSH
CS1
(CS2="1")
tSAS tSAH
A0
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS tSDH
SI
Figure 39
Table 30
(VDD = 3.3V, Ta =25°C )
Rating
Min. Max.
Serial Clock Period Tscyc 50 —
SCL “H” pulse width SCL Tshw 25 —
SCL “L” pulse width TSLW 25 —
Address setup time TSAS 20 —
A0
Address hold time Tsah 10 — ns
Data setup time Tsds 20 —
SI
Data hold time TSDH 10 —
CS-SCL time Tcss 20 —
CS
CS-SCL time Tcsh 40 —
Table 31
(VDD =2.7V , Ta =25°C )
Rating
Min. Max.
Serial Clock Period Tscyc 100 —
SCL “H” pulse width SCL TSHW 50 —
A0
Address hold time TSAH 20 — ns
Data setup time TSDS 30 —
SI
CS-SCL time TCSS 30 —
CS
CS-SCL time TCSH 60 —
Ver 0.3c 67/73 2002/07/22

ST7565S
Table 32
(VDD = 1.8V , Ta = 25°C )
Rating
Min. Max.
Serial Clock Period TSCYC 200 —
SCL “H” pulse width SCL TSHW 80 —
A0
Address hold time TSAH 30 — ns
Data setup time TSDS 60 —
SI
CS-SCL time TCSS 40 —
CS
CS-SCL time TCSH 100 —
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
Ver 0.3c 68/73 2002/07/22

ST7565S
Reset Timing
tRW
RES
tR
Internal
During reset Reset complete
status
Figure 41
Table 36
(VDD = 3.3V , Ta = –40 to 85°C )
Rating
Min. Typ. Max.
Reset time tR — — 0.5 us
Reset “L” pulse width /RES tRW 0.5 — — us
Table 37
(VDD = 2.7V , Ta = –40 to 85°C )
Rating
Min. Typ. Max.
Reset time tR — — 1 us
Reset “L” pulse width /RES tRW 1 — — us
Table 38
(VDD = 1.8V , Ta = –40 to 85°C )
Rating
Min. Typ. Max.
Reset time tR — — 1.5 us
Reset “L” pulse width /RES tRW 1.5 — — us
*1 All timing is specified with 20% and 80% of VDD as the standard.
Ver 0.3c 69/73 2002/07/22

ST7565S
THE MPU INTERFACE (REFERENCE EXAMPLES)

The ST7565S Series can be connected to either 80X86 Series MPUs or to 68000 Series MPUs. Moreover, using the serial
interface it is possible to operate the ST7565S series chips with fewer signal lines.
The display area can be enlarged by using multiple ST7565S Series chips. When this is done, the chip select signal can be
used to select the individual ICs to access.
(1) 8080 Series MPUs

VDD
VCC VDD
A0 A0 C86
A1 to A7 CS1
Decoder
IORQ CS2
ST7565S
MPU
DO to D7 DO to D7
RD RD
WR WR
RES RES P/S
GND VSS
RESET
VSS
Figure 42-1
(2) 6800 Series MPUs
VDD
VCC VDD
A0 A0 C86
A1 to A15 CS1
ST7565S
Decoder
VMA CS2
MPU
DO to D7 DO to D7
E E
R/W R/W
RES RES P/S
GND RESET VSS
VSS
Figure 42-2
(3) Using the Serial Interface
VDD or VSS
VCC VDD
A0 A0 C86
CS1
ST7565S
A1 to A7 Decoder
CS2
MPU
Port 1 SI
Port 2 SCL
RES RES P/S
GND RESET VSS
VSS
Figure 42-3
Ver 0.3c 70/73 2002/07/22

ST7565S
CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE

EXAMPLE)
The liquid crystal display area can be enlarged with ease through the use of multiple ST7565S Series chips. Use a same
equipment type.
(1) ST7565S (master) ↔ ST7565S (slave)
VDD
M/S CLS CLS M/S
FR FR
ST7565S
ST7565S
Master
CL CL
Slave
DOF DOF
Output Input
VSS
VDD
M/S CLS CLS M/S
FR FR
ST7565S
ST7565S
Master
CL CL
Slave
DOF DOF
Output Input
VSS
Figure 43-1
Ver 0.3c 71/73 2002/07/22

ST7565S
(2) Single-chip Structure
132 X 65 Dots
ST7565S
Master
Figure 43-2
(3) Double-chip Structure
264 x 65 Dots
COM SEG SEG COM

ST7565S ST7565S
Master Figure 43-3 Slave
Ver 0.3c 72/73 2002/07/22

ST7565S
Revisions
Version 0.1 - Preliminary.
Version 0.2 - update Pad Center Coordinates page 2,3,4,5
Version 0.2a - update ABSOLUTE MAXIMUM RATINGS and DC CHARACTERISTICS
Version 0.2b - update DC CHARACTERISTICS , Pad Arrangement
Version 0.2c - update AC CHARACTERISTICS (serial)
Version 0.2d - update PIN DESCRIPTIONS M/S
Version 0.2e - update ABSOLUTE MAXIMUM RATINGS and DC CHARACTERISTICS
Version 0.2f - update Master and Slave reference example.
Version 0.3 - update Pad Center Coordinates (1/65 , 1/49 , 1/33 , 1/55 , 1/53 Duty) page 3..17
Version 0.3a - update Pad Diagram page2 and v5 regulator voltage diagram(figure 9) page35
Version 0.3b - Logic power supply VDD – VSS = 1.8V to 3.3 V (+10% Range) , VOUT= -13V (+10% Range)
Version 0.3c - Modify page-38 The temperature grade of the Internal Power Supply for ST7565S (-0.05%/°C) Figure 14
Ver 0.3c 73/73 2002/07/22

Sitronix ST7567

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ST

Sitronix 65 x 132 Dot Matrix LCD Controller/Driver

PART NO. VRS temperature gradient VRS range

Ver 0.3c 1/73 2002/07/22

22um 30um 22um 38um 30um

z VOUT maximum -13V (+10% Range)

Ver 0.3c 2/73 2002/07/22

Pad Center Coordinates (1/65 Duty)

Ver 0.3c 3/73 2002/07/22

Ver 0.3c 4/73 2002/07/22

Ver 0.3c 5/73 2002/07/22

Pad Center Coordinates (1/49 Duty)

Ver 0.3c 6/72 2002/07/22

Ver 0.3c 7/72 2002/07/22

Ver 0.3c 8/72 2002/07/22

Pad Center Coordinates (1/33 Duty)

Ver 0.3c 9/73 2002/07/22

Ver 0.3c 10/73 2002/07/22

Ver 0.3c 11/73 2002/07/22

Pad Center Coordinates (1/55 Duty)

Ver 0.3c 12/72 2002/07/22

Ver 0.3c 13/72 2002/07/22

Ver 0.3c 14/72 2002/07/22

Pad Center Coordinates (1/53 Duty)

Ver 0.3c 15/72 2002/07/22

Ver 0.3c 16/72 2002/07/22

Ver 0.3c 17/72 2002/07/22

COM output control circuit

Voltage Display data latch circuit

Display timing generator circuit

Status Command decoder Bus holder

MPU INTERFACE ( Parallel and Serial )

Ver 0.3c 18/72 2002/07/22

Pin Name I/O Function No. of Pins

VDD (= V0) ≧V1 ≧V2 ≧V3 ≧V4 ≧V5

LCD Power Supply Pins

Pin Name I/O Function No. of Pins

Ver 0.3c 19/72 2002/07/22

Pin Name I/O Function No. of Pins

When /RES is set to “L,” the settings are initialized.

• When connected to an 8080 MPU, this is active LOW.

This is the MPU interface switch terminal.

This is the parallel data input/serial data input switch terminal.

P/S Data/Command Data Read/Write Serial Clock

“L” A0 SI (D7) Write only SCL (D6)

When P/S = “L”, D0 to D5 fixed “H”.

Ver 0.3c 20/72 2002/07/22

This is the display clock input terminal

FR O This is the liquid crystal alternating current signal terminal. 1

/DOF O This is the LCD blanking control terminal. 1

SEL3 0,0,1 1/49 1/8 or 1/6

These are terminals for IC testing.

Ver 0.3c 21/72 2002/07/22

Pin Name I/O Function No. of Pins

Scan Data FR Output Voltage

Ver 0.3c 22/72 2002/07/22

Selecting the Interface Type

H: Parallel Input /CS1 CS2 A0 /RD /WR C86 D7 D6 D5~D0

The Parallel Interface