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Short Circuit Current Characteristics Analysis and Improved Current Limiting

Strategy for Three-phase Three-leg Inverter under Asymmetric Short Circuit
Fault

Article in IEEE Transactions on Power Electronics · October 2017

DOI: 10.1109/TPEL.2017.2759161

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 Short Circuit Current Characteristics Analysis and
Improved Current Limiting Strategy for
Three-phase Three-leg Inverter under
Asymmetric Short Circuit Fault
Zhigang Liang, Xinchun Lin, Member, IEEE, Yong Kang, Bofeng Gao and He Lei

Abstract— Three-phase three-leg inverter is one of the

most popular topologies for inverters. When short-circuit I. INTRODUCTION
fault occurs, the inverter is generally switched to the Three-phase inverters have played a key role in various
current-controlled mode from voltage-controlled mode to occasions, such as power supplies for industrial applications,
limit the fault currents. In this situation, the inverter medical equipment, traction devices, household appliances,
becomes equivalent to a symmetric, three-phase, positive inverter-based distributed generation system, etc[1]-[5]. In
sequence current source. However, the voltage limiting these applications, the inverters are controlled as the high
may happen under asymmetrical fault. In this paper, a quality voltage source to supply local loads. In practical
closed-loop model based on time-domain is originally operations, inverters probably suffer from various abnormal
developed as a means to investigate the fault current conditions[6-8], in which the short-circuit fault is one of the
characteristics under asymmetrical fault. Based on the severest cases for inverters. The semiconductor switches
proposed model, a more intuitive insight into fault might be damaged without proper measures when a short
currents is presented as follows. 1) The positive sequence circuit fault occurs at the load side, because the short-circuit
fundamental component of three-phase currents can still currents usually far exceed the rated currents of the inverter.
track the symmetric current references. 2) The magnitude To protect the semiconductor switches from damage under
of fault phase currents (ignoring the harmonics) will vary the short circuit fault, the inverter can be shut down by
between 1 and 3 times of magnitude of current limiting blocking the gate driver signals of the semiconductor
references. Based on the conclusion, although the switches. This may be a feasible protection for inverter
magnitudes of fault phase currents can be reduced by feeding a single load. However, when the inverter feeds a
adopting smaller current limiting references, the actual large network including some critical loads, shutdown in the
magnitudes of fault phase currents will still vary in a case of fault is usually unacceptable. To ensure a high
range depending on the load impendence of healthy phase. reliability and continuity of power supply for a large network,
Therefore, the reliable action of the protection devices is the inverter should be able to ride-through the fault without
greatly affected and the selective protection cannot be shutdown. Different from the fault ride-through control of
realized. Furthermore, in order to achieve completely grid-connected inverter [9]-[13], the typical fault ride-through
controllable fault currents under asymmetrical fault, two schemes [14]-[18] for stand-alone inverter can be described
alternative current limiting strategies are presented with a as follows. In the normal state, the inverter works in voltage-
reverse current limiting references, and with a current controlled mode (VCM). When a short-circuit fault occurs,
limiting references based on the introduced phase angle the inverter is switched to current-controlled mode (CCM)
regulation. The theoretical results are validated by and the inverter behaves as a current source until the short-
simulations and experimental results. circuit fault is cleared by the protection devices (fuses or
 circuit breakers). After the fault is cleared, the inverter will
Index Terms—Current limiting references, voltage return back to the VCM from CCM. Therefore, the critical
limiting, short-circuit fault, three-phase three-leg inverter loads can be continuously supplied by the inverter. The
process of fault ride-through control can be divided into three
tasks: 1) fault detection; 2) current limiting control; and 3)
voltage recovery control during fault clearance. In this paper,
Manuscript received May 28, 2017, revised July 18, 2016 and accepted attention is paid to the current limiting control.
Sep. 16, 2017. ( Corresponding Author: Xinchun Lin) Various current limiting strategies for inverter under short-
Z. Liang, X. Lin, Y. Kang and B. Gao are with the State Key Laboratory of
Advanced Electromagnetic Engineering and Technology, School of Electrical circuit fault have been proposed. In [14]-[16], when a fault is
and Electronic Engineering, Huazhong University of Science and detected, the inverter is switched to a maximum RMS current
Technology, Wuhan 40074, China (e-mail: Lzhigang_1989@163.com; limiting loop from normal dual loop. As only the maximum
linxinchun2002@sina.com; ykang@mail.hust.edu.cn; RMS output current is controlled, the response is slow
fenbo0537@gmail.com)
H. Lei is with the State Grid Laboratory for Hydro-thermal Power compared with instantaneous current control. Besides, the
Resources Optimal Allocation & Simulation Technology ， State Grid instantaneous control for each phase current cannot be
HBEPC Economic & Technology Research Institute, Wuhan 430077,Hubei obtained. Generally, when the inverter works in VCM, the
Province，China (e-mail: regallyhust@hotmail.com). dual loop (outer voltage loop and inner current loop) control

1
is adopted and implemented based on the synchronous (dq) as follows. 1) The positive sequence fundamental component
reference frame. In dual loop control structure, the output of of three-phase currents can still track the symmetrical current
the voltage controller is regarded as the current reference in references even though the current of healthy phase is
the current loop. If the current limiting blocks are placed in uncontrollable. 2) The magnitude of fault phase currents
the output of the voltage controller, the inner current loop can (ignoring the harmonics) will vary between 1 and 3 times of
provide the function of current limiting [19]-[23]. As a result, the magnitude of current limiting references depending on the
when short-circuit fault occurs, the inverter will be switched load impendence of healthy phase. Based on above
to CCM as the voltage controller is rapidly saturated. The conclusion, it can be seen that the current limiting loop is not
inductor currents of the inverter can be completely controlled broken completely under asymmetrical fault. Although the
when symmetric three-phase fault occurs. In this case, the magnitudes of fault phase currents can be reduced by
inverter becomes equivalent to a three-phase, symmetric, and adopting smaller current limiting references, the actual
positive sequence current source. However, if the inverter magnitudes of fault phase currents will still vary. As a result,
experiences an asymmetrical short-circuit fault, the output the reliable action of the protection devices is greatly affected.
voltage limiting will happen [19]-[21]. As a result, the fault Furthermore, in order to achieve completely controllable fault
currents will not be completely controllable. Furthermore, the currents under asymmetrical fault, two alternative current
semiconductor switches safety, inductive components limiting strategies, referred to as Method I and Method II, are
saturation, and the reliability of the protection system will be further presented. Method I represents the current limiting
affected. strategy based on a reverse current limiting references.
For three-phase four-leg topology inverter [19]-[21] and Method II represents the current limiting strategy with the
three-phase combined topology inverter [14], [15], the current limiting references regulated by the introduced phase
voltage limitting problem can be avoided under asymmetrical angle. For Method I, the output current of every phase can be
fault if the independent control of each phase in the stationary completely controlled to track the current limiting references
abc-frame is adopted. This is because the output voltage of during asymmetrical fault. Meanwhile, the output voltage of
each phase can be regulated independently and the inductor healthy phase is controlled to approximate zero to avoid the
current of each phase can also be controlled separately in the voltage limiting. For Method II, the healthy phase can still
stationary reference frame. As a result, when asymmetrical keep appropriate output voltage during fault ride-through
fault occurs, the fault phases can be switched to CCM, while while the current of every phase can be completely controlled.
the healthy phases still operate in VCM. However, this The theoretical analysis and proposed method are validated
scheme is not applicable to the three-phase three-leg topology by simulation and experimental results.
inverter which is also one of the most popular topologies for Based on above analysis, this paper is organized as follows.
inverters. The key difference among three-phase three-leg In Section II-A, the mechanism of voltage limiting under
topology inverter, four-leg three-phase topology inverter, and asymmetrical fault is discussed. Furthermore, the fault current
three-phase combined topology inverter, is that each phase for characteristics are investigated under the voltage limiting in
three-phase three-leg inverter is not completely independent section II-B. Two novel current limiting strategies are
whether the control is implemented in the stationary reference presented in Sections III. Sections IV and V validate the
frame or in the synchronous reference frame, considering the theoretical analysis by simulations and experimental results.
inherent constraint that the sum of three phase inductor Finally, Section VI concludes this paper.
currents is always zero because of no zero-sequence current
path for three-phase three-leg topology inverter. II. FAULT CURRENT CHARACTERISTICS BASED ON DUAL LOOP
For grid-connected three-phase three-leg inverter, the fault UNDER ASYMMETRICAL FAULT
ride-through control under asymmetrical voltage sags has
been widely investigated [9]-[13]. However, these methods A. Mechanism of Output Voltage Limiting under
are not applicable to the stand-alone inverter. This paper Asymmetrical Fault
focuses on the current limiting control of stand-alone three- Fig. 1 shows the configuration and control diagram of three
phase three-leg inverter during asymmetrical fault. Firstly, the phase three-leg inverter. L is the filter inductor and C is the
mechanism of the voltage limiting for three-phase three-leg filter capacitor. The equivalent series resistors of L and are
inverter under asymmetrical fault is discussed in detail based relatively small and ignored here. If the inverter needs to
on synchronous reference frame. When voltage limiting supply single-phase load, a Δ/yn-connected transformer is
occurs, the currents of the healthy phases and fault phases are
generally placed behind the filter capacitor. Synchronous
both distorted. The fault current characteristics have influence
reference frame vector control is the most popular technique
on the semiconductor switches safety, inductive components
for the control of the inverter and has been demonstrated to
saturation, and the reliability of the protection system.
However, the current literatures [19]-[21] do not further provide good performance. The control diagram in
provide an efficient method or intuitive insight into fault synchronous dq-frame is also shown in Fig. 1, the dual loop
current characteristics for stand-alone inverter under (outer voltage loop and inner current loop) control is
asymmetrical fault. Furthermore, in this paper, a closed-loop generally adopted and implemented based on synchronous
model is originally developed as a means to investigate dq-frame (o axis is uncontrollable for three-phase three-leg
current characteristics of fault phases considering the inverter). The outer- and inner- loops with typical
influence of the voltage limiting. Based on the proposed proportional-integral (PI) controller regulate the capacitor
model, a more intuitive insight into fault currents is presented voltages and inductor currents, respectively. In oder to

2
Fig. 1. Topology of three-phase three-leg inverter and control diagram in synchronous dq-frame

provide the function of current limiting, the current limiter is CCM. Assuming that three-phase symmetrical short circuit
placed in the outputs of voltage controllers. The load current fault appears, the output voltages of the inverter are reduced
feed-forward is used to attenuate disturbances from load. to be close to zero as the short circuit impedance of three
Generally, the voltage of inverter has a maximum limit Vlimit phases are generally very small. Therefore, (3) does not
which is determined by a finite DC-link voltage. Therefore, as exceed Vlimit and the inner current loop can work well. In this
shown in Fig. 1, the voltage limiter is generally adopted to situation, the inverter can be controlled as a three-phase
limit the maximum voltage [24]-[26]. The voltage limiter will symmetrical current source. However, when asymmetrical
be triggered if the amplitude of voltage vector is located fault (corresponding to single-phase fault of inverter with
outside the maximum circle of the hexagon, i.e. the following Δ/yn-connected transformer) appears, the result will be
condition holds true: different from that of symmetrical short-circuit fault. Suppose
short circuit fault appears between phases b and c, the
urd2  urq2  Vlim it (1)
equivalent circuit is shown in Fig. 2, in which the equivalent
where Vlimit (i.e. Vdc 3 ) represents the amplitude of voltage loads are shown by delta connected equivalent impedances.
vector located the maximum circle of the hexagon in vector Zab and Zca represent the equivalent load impedances between
diagram, while urd and urq represent the control voltage of d- phases a and b, and between phases c and a, respectively. Zf
and q-axis. Neglecting the switching action of the inverter, represents the short circuit impedance between phases b and c.
meanwhile, suppose the voltage limiter is not triggered, then According to Fig. 2 and the Appendix A, the arm line
urd_limit=urd, urq_limit=urq (urd_limit, urq_limit is the output voltage of voltages under asymmetrical fault can be approximately
voltage limiter). Therefore, according to (2), the amplitude of expressed as (5), showing the circuit constraint relationship.
the output voltage vector can be further expressed as (3)  Z ca Z ab iLa
uab  uca 
 ua   Z ab  Z ca (5)
 urd _ lim it    u  0
   Tabc  dq  ub  ( 2)  bc
 urq _ lim it  u 
 c Furthermore, substituting (5) into (3), the amplitude of
voltage vector under asymmetrical fault can be expressed as
2 2
urd2 _ lim it  urq2 _ lim it  uab  ubc2  uca
2
(3) 2 Z ab Z ca iLa
3 urd2 _ lim it  urq2 _ lim it  (6)
where 3 Z ab  Z ca

2  cos t cos t  2 3 cos t  2 3 

Tabc dq   
3   sin t  sin t  2 3  sin t  2 3 

(4)
ua, ub and uc represent the arm-voltage of each phase,
referenced to N. ω is the fundamental angular frequency.uab,
ubc and uca represent the arm line voltages of
inverter,respectively.
Eq. (3) shows the relationship between the voltage vector
and arm line voltages of the inverter. In normal condition,
with the appropriate circuit design, (3) should not exceed the
voltage limiting, Vlimit. Under fault conditions, the outer Fig. 2. Equivalent circuit when asymmetrical fault occurs between phase b
voltage control loop is broken and the inverter is switched to and c.

3
 Generally, the reference of the d-axis is set to the rated load (i.e. λab=λca=1) before the asymmetrical fault
magnitude of current limiting references and the q-axis is set occurs, the voltage limiting will occur under asymmetrical
to zero under short circuit fault in dq-frame. If the voltage fault. However, if the inverter works under 2 times rated-load
limiter is not triggered, the current of phase a will track the (i.e. λab=λca=2) before the asymmetrical fault occurs, the
current limiting reference. Therefore, the current of phase a in voltage limiting does not occur under asymmetrical fault.
_ lim it  I L _ lim it cos t .

abc-frame can be expressed as iLa  iLa Based on previous analysis, the voltage limiting block will
be triggered in most conditions under asymmetrical fault. The
Where IL_limit is the magnitude of current limiting reference,
voltage limiting strategy in [26] and [27] is generally adopted
and generally is 2 ～ 3 times of the magnitude of rated for three phase inverter, and the scheme is shown in Fig. 4. In
inductor current, ILM. If IL_limit=2·ILM is chosen. (6) can be which, when voltage limiter is triggered, the voltage vector on
further expressed as the maximum circle within the hexagon is chosen and
2 Z ab Z ca iLa orientated in the same direction as the reference voltage
urd2 _ lim it  urq2 _ lim it 
3 Z ab  Z ca vector. That is, the amplitude of the voltage vector is limited,
yet the phase angle is still conserved. Then, the relationship
2
 Z n I L _ lim it cos t (7) between urdq_limit and urdq can be expressed as:
3  ab  ca 
urdq if ( urdq  Vlim it )
4 

 mnVlim it cos t urdq _ limit   urdq (11)
ab  ca Vlimit if ( urdq  Vlim it )
 2
 urd  urq
2
where λab=Zn/Zab and λca=Zn/Zca, represent the overload ratio, 
(Zn represents the nominal load impedance). mn=VM /Vlimit, is When the voltage limiting occurs, based on previous
defined as the ratio between the amplitude of the nominal
analysis, (12) can be obtained
phase voltage, VM, and the amplitude of the maximum limit
voltage, Vlimit. According to Fig.2, in normal state, VM can be urd2 _ lim it  urq2 _ lim it  Vlim it (12)
expressed as |Zn|ILM/3. Thus, |Zn|ILM/3=mnVlimit. For the sake of According to (6) and (12), the current of healthy phase
convenience, suppose the impedance angle of the actual loads
(phase a) can be expressed as
is similar to that of the nominal load in normal condition
before short circuit fault occurs, then 0<λab, λca≤2. So λab, iLa

if ( urdq  Vlim it )

_ lim it
λca→0 represents no-load and λab=λca=2 represents 2 times 
iLa   Z ca Z ab (13)
rated-load.  3Vlim it 2 if ( urdq  Vlim it )
According to (7), if (8) holds true. Then the output voltage 
 Z ab  Z ca
limiter will be triggered. As a result, the output voltage will
where urdq  urd2  urq2 . (13) shows the amplitude of the
be limited.
4mnVlim it  ab  ca   Vlim it (8) inductor current of healthy phase is decided by the limited
voltage and load impedance when the voltage limiting occurs,.
For sake of convenience, (8) can be also expressed as Therefore, the current of healthy phase will be distorted. As a
 ab  ca  4mn  1 (9) result, the control effectiveness of fault phase currents will be
mn is typically in the range of [0.7, 0.9] for inverter. according also affactted. In the following section, the current
to (9), Fig. 3(a) can be obtained. From Fig. 3(a), the output characteristics of fault phases are further investigated.
voltage limiting will occur for most loads. Particularly, if B. The fault current characteristics
λab=λca=λ, (9) can be further simplified as Fig. 5 shows the equivalent current limiting control system
 2mn  1 (10) including the current limiting controller, voltage limiting
According to (10), Fig. 3(b) can be obtained. It can be block, equivalent SVPWM and circuit constraints. the current
seenthat the voltage limiting will occur for most loads under limiting controller is based on PI controller. The voltage
asymmetrical fault. Particularly, if the inverter works under limiting is implemetented by (11). The modulation signals of
SVPWM are equivalent to the sum of the equivalent injected
zero-sequence voltage, uz and the sinusoidal fundamental
modulation signals, urx_limit (x=a,b,c). With the switching
action neglected, ux= urx_limit + uz. The

Fig. 3. Relationship among the voltage limiting, λab, λca, λab and mn under Fig. 4. Principle of voltage limiting
asymmetrical fault

4
 Fig. 5. Current limiting control system considering voltage limiting

circuit constraints are decided by (5) under asymmetrical fault. distorted while the voltage limiter is triggered, the fault phase
Based on the equivalent SVPWM and the circuit currents will also be distorted considering the sum of three
constraints shown in Fig. 5, one can get phase currents is zero. Generally, the distorted current mainly
ubc   urb _ lim it  uz    urc _ lim it  uz   urb _ lim it  urc _ lim it  0 includes the low-order harmonics. The inductor currents can
be approximately expressed as
(14)
 iLa   cos t  i     cos t  i   
According to the control system shown in Fig. 5, urb_limit      
and urc_limit in (14) can be obtained by (15)  iLb   I L1  cos t  i   120    I L1  cos t  i   120  
i     
 ura _ lim it 
 urd _ lim it 
 Lc   cos t  i   120    cos t  i   120  
 
 urb _ lim it   T2 r /3 s  u    cos  nt   ni    
u   rq _ lim it     
 r c _ lim it   I Ln   cos  nt   ni   120   
    
 cos  nt   ni   120   
 urd  (15)
if ( urdq  Vlim it ) 
T2 r /3 s      
  urq   cos  nt  ni   
 n  2,3,4...

 urd   I  
 Vlim it T cos  nt  ni   120   
 u2  u2 2 r /3 s   if ( urdq  Vlim it )  Ln   
 urq   
 rd rq 
  cos  n t   ni   120   
where (20)
 cos t  sin t  where IL1+ and IL1- are the magnitudes of positive- and
  negative- sequence fundamental component. ILn+ and ILn- are
T2 r /3s   cos t  2 3  sin t  2 3  (16)
the magnitudes of positive- and negative- sequences of nth
 
 cos t  2 3  sin t  2 3  harmonics, respectively, correspondingly, φni+ and φni- (-π
Substituting (16) into (15), then substituting (15) into (14) ≤φni+, φni- ≤ π) are the initial phases, respectively.
yields Furthermore, by the frame transformation, iLd and iLq in
sin t  urd  cos t  urq  0 (17) synchronous reference frame can be expressed as
 iLd   cos i    cos  2t  i   
It can be seen that (17) is obtained based on the voltage
   I L1    I L1 
  sin  2t    
limiting block, equivalent SVPWM and circuit constraints  iLq   sin i    i 
shown in Fig. 5.
Furthermore, according to the current limiting controller
  cos   n  1 t  ni    
 I Ln    
shown in Fig. 5, urd and urq can be expressed as   sin   n  1 t  ni     (21)
 
   
rd _ 0  K p  iLd _ lim it  iLd   K i t  iLd _ lim it  iLd  dt
u  u 
t

 rd
n  2,3,4...   cos   n  1 t  ni    
   I Ln   
0
(18)
 urq  urq _ 0  K p  iLq Lq  i t  Lq _ lim it Lq 
  sin   n  1 t  ni    
t

 i  K i 
 i dt 
 _ lim it
0   
where urd_0 and urq_0 are the outputs of current controller Discretizing (21), then, substituting (21) into (19), finally,
before the fault occur. t0 is the initial moment of fault and t is substituting (19) into (17) yields,
the moment when the fault is cleared. For the sake of g dpi   sin  kTs  g qpi   cos kTs  g kp  sin  kTs  i   
convenience, suppose t0=m π/ω (m is positive integer). In a C1 C2
digital control system, (18) can also be expressed as
g ki  cos  kTs  i    g ki  cos  kTs  i  

  iLd _ limit  iLd  kTs Ts
N

 u rd  u rd _ 0  K p i 
Ld _ limit  iLd  kT s   K i    g nkp  sin  n kTs  ni    g nkp  sin  n kTs  ni   
 j 0 n  2,3,4...

 u  u  K  i
p Lq _ limit  iLq  kTs    K i   iLq _ limit  iLq  kTs  Ts
 g cos  n kTs  ni    g nki  cos  n kTs  ni   
N
  nki 
 rq rq _ 0
j 0
n  2,3,4...

(19)  
n  2,3,4...
g nki  cos  kTs  ni    
n  3,5,7,9
g nki  cos  kTs  ni  
where Ts is control period. N is overall sample times before
the fault is cleared. As the current of healthy phase is 0

5
 (22) components of the three phase inductor currents can be
where approximately expressed as
    iLa1  0
 urd _ 0   K p  K iTs    iLd _ lim it  I L1 cos i  
N

 g dpi   (27)
  j 0  iLb1  iLc1  I Lb1 cos(t  ib1 )

   where ILb1 is the magnitude of fundamental component of
 urq _ 0   K p  K iTs    iLq _ lim it  I L1 sin i  
N
g phase-b. φib1 is the initial phase angle of fundamental
 qpi   j 0 
 component of phase-b .
 g kp   K p I L1 Substituting (27) into (26) yields

iLa1   aI Lb1 cos(t  ib1 )  a 2 I Lb1 cos(t  ib1 )  3
(23)
 g ki   K i I L1 2
g (28)
 K p I Ln   3e j 90 I Lb1 cos(t  ib1 ) 3
 nkp 
 g nki   K p I Ln  According to (28), the magnitude of the fundamental

 g nki   K i I Ln   n  1  n  3,5, 7,9 component of fault phase currents can be obtained and
 expressed as
 g nki   K i I Ln   n  1  n  3,5, 7,9
I Lb1  3I L1 (29)
 N 
From gdpi+ and gqpi+ given in (23),  K p  KiTs     ,if Note that IL1+=IL_limit, thus I Lb1  3I L _ lim it . This indicates
 j 0 
that the magnitude of the fundamental component of fault
the errors for the terms i 
Ld _ lim it  I L1 cos i   phase currents will be 3 times of the magnitude of current
and  i
Lq _ lim it  I L1 sin i   both exist in the steady state in limiting references when the asymmetrical fault occurs under
no load.
CCM, then gdpi    and gqpi    . However, the other On the other hand, if the inverter operates under 2 times
terms in (23) are finite. Considering gdpi+ and gqpi+ only exists rated-load (i.e. λab=λca=2) before the asymmetrical fault
in C1 and C2 in (22), in order to ensure that (22) holds true, occurs, the voltage limiting does not occur when the
(24) should be satisfied asymmetrical fault occurs. Therefore, the system is still linear.
 iLd
 _ lim it  I L1 cos i    0
 The current limiting control loop can work well. In this case,
  (24) the inductor currents can be controlled to track the current
 iLq _ lim it  I L1 sin i    0
 limiting references and the magnitude of each phase current
According to (24), one can get will be equal to IL_limit.
2 2 Therefore, the magnitude of fundamental component of
I L1  iLd _ limit  iLq _ limit  I L _ limit (25)
fault phase currents will vary between 1 and 3 times of the
This shows that the positive-sequence fundamental
magnitude of current limiting references when load
component of three-phase inductor currents can still track the
impedance of healthy phase vary in the range from no load to
current limiting reference. (the proposed method applied in
the stationary abc-frame is given in Appendix B.) 2 times rated-load.
However, the actual fault inductor currents are distorted It can be seen that the presented analysis in this section
under asymmetrical fault. Therefore, the characteristics of offers an intuitive insight into current characteristics during
fault phase inductor currents need to be further investigated. asymmetrical fault: 1) the positive sequence fundamental
By means of the symmetrical components method, the component of three-phase inductor currents can still track the
following relationship exists between fundamental current limiting references. 2) The magnitudes of
components, iLx1 (x=a, b, c), and the positive-sequence fundamental components of fault phase currents will vary
components of inductor currents. between 1 and 3 times of the magnitude of current limiting
 iLa1  1 a a 2   iLa1  references depending on load impedance of healthy phase.
  1   It can be seen that when the voltage limiting occurs, the
 iLa1   3 1 a a   iLb1 
2
(26) magnitudes of fault phase currents still exceed the current
i  1 1 1   i 
 L0     Lc1  limiting references, which pose challenges to semiconductor
switches safety. Although the magnitudes of fault phase
where a  e j120 , a2  e j 240 . currents can be reduced by adopting smaller current limiting
As the actual currents are influenced by the load impedance references, the actual magnitudes of fault phase currents still
of healthy phase under output voltage limiting, two extreme vary in a range depending on the load impendence of healthy
instances are demonstrated, i.e. the inverter operates under no phase. As a result, the reliable action of the protection devices
load and 2 times rated-load before the asymmetrical fault will be seriously affected. To avoid these problems, the actual
occurs. According to the analysis in Section II-A, if the output currents should be completely controlled to track the
inverter operates under no load before fault occurs, the references during asymmetrical fault. Therefore, in section III,
voltage limiter is most likely to be triggered after the two alternative current limiting strategies are further proposed
asymmetrical fault occurs. Condering the current of healthy to obtain completely controllable fault currents.
phase is approximately zero under no load, the fundamental

6
 III. PROPOSED CURRENT LIMITING STRATEGIES keep appropriate voltage to continuously supply load. From
Based on the previous analysis, in order to achieve (30), if iLa is not controlled to be zero, but designed
completely controllable fault currents, the output voltage coordinately according to the impedances Zab and Zca, the
limiting should be firstly avoided under asymmetrical fault. output voltage limiting can also be avoided. In the meantime,
Suppose asymmetrical fault appears between the phase b and from (32), the healthy phase can also keep appropriate
c, according to the analysis in Section II, if the following voltage supplying load even during fault ride-through.
condition holds true, the output voltage limiting will not Actually, it is unnecessary to detect the actual impedance of
occur healthy phase. As known to all, in the normal state, the
inverter is controlled as voltage source, the inductor current
2 Z ca Z ab iLa
urd2  urq2   Vlim it (30) iLa depends on the normal voltage and the load impedance of
3 Z ab  Z ca healthy phase. Therefore, if the inverter supplies linear load,
From (30), the amplitude of the output voltage vector the post-fault current of phase a is controlled to keep
depends on the load impendence and the current of healthy consistent with the pre-fault current during asymmetrical fault,
phase. Generally, the load impendence is uncontrollable. as a result, the post-fault voltage of healthy phase can keep
Therefore, the current of healthy phase (phase a) should be approximate to pre-fault voltage. If the inverter supplies
appropriately controlled to avoid to trigger the voltage limiter. nonlinear load, the reference of post-fault current of healthy
From this perspective, two alternative current limiting phase will be kept consistent with the fundamental
strategies are presented based on a reverse current limiting component of pre-fault current. By means of the discrete
references, referred to as Method I, and the current limiting Fourier algorithm [28], [29], the pre-fault current of phase a
references with the phase angle regulation, referred to as can be easily acquired. However, there exists the inherent
Method II. constraint that the sum of three phase inductor currents is
always zero for three phase three-leg inverter. Therefore, the
A. Method I
phase angle, β, is introduced, and, correspondingly, the novel
Obviously, if the current of healthy phase is controlled to current limiting references are given as follows:
_ lim it  I La cos   t  ia 
be zero during asymmetrical fault, from (30), the output iLa


voltage limiting will not occur for any load. Considering the 

actual current should meet the constraint iLa  iLb  iLc  0 for iLb _ lim it  I L _ lim it cos t  ia    (33)

three-phase three-leg inverter, the current limiting reference iLc _ lim it  I L _ lim it cos t  ia   

  
should also meet the constraint iLa _ lim it  iLb _ lim it  iLc _ lim it  0 to where ILa and φia (-π ≤φia ≤ π) are the magnitude and initial
obtain completely controllable currents. Therefore, the angle of fundamental component of pre-fault current of phase
current limiting references of fault phases (i.e. phase b and c) a, respectively. β is introduced to regulate the phase angle to
  
should be reverse. Based on above analysis, the current meet the constraint iLa _ lim it  iLb _ lim it  iLc _ lim it  0 . The current
limiting references in the stationary abc-frame can be given reference of the phase b is β lagging to that of the phase a,
by while the current reference of the phase c is β leading to that
iLa of the phase a. β depends on the magnitude of pre-fault
_ limit  0
 current of phase a. The phasor diagram of the current limiting
iLb _ limit  I L _ limit cos t  i 

(31) references based on phase angle regulation is shown in Fig. 6.
    
iLc _ limit   I L _ limit cos t  i 
I La _ lim it , I Lb _ lim it and I Lc _ lim it represent the phasor of iLa _ lim it ,
 
With the current limiting references in (31), as well as iLb _ lim it and iLc _ lim it ,respectively. Suppose ILa varies in the

appropriate closed-loop control, the voltage limiting will not range of [0, 2ILM] for healthy phase while IL_limit is equal to
occur and the current of each phase can be completely 2·ILM for fault phases. As shown in Fig. 6, β will vary in the
controlled. According to Appendix A, under asymmetrical range of [90°, 120°]. Particularly, if ILa=2ILM (i.e. 200% rated-
fault, the output voltages uobc ≈0 and uoab≈-uoca, meanwhile, load), then β=120°, the current limitng references in (33)
uoab can be expressed as become equivalent to symmetric positive sequence current
Z Z i
uoab  uoca  ca ab La (32)
Z ab  Z ca
As the post-fault current of healthy phase is controlled to
be close to zero, the post-fault voltage uoab will be also
appropriately zero during fault ride-through.
B. Method II
1) Principle
In Method I, the inductor current of each phase can be
completely controlled. However, the voltage of healthy phase
will be appropriately zero during fault ride-through. Fig. 6. Phasor diagram of the current limiting references based on phase
Generally, it is also expected that the healthy phase should angle regulation

7
references. If ILa=0 (i.e. no-load), then β=90°. In this situation, As a result, uoab is 0-600 lagging to the pre-fault voltage
the current limiting references of fault phases (i.e. phase b uoab_n and the magnitude of uoab varies in the range [ 3 2 , 1]
and c) will be reversed, thus, Method II becomes equivalent
p.u. (i.e. [0.866, 1] p.u.). Due to uoca=-uoab, correspondingly
to Method I.
OC' represents the phasor of uoca. C' will shift in line CE.
2) Evaluation of the Output Voltages Therefore, uoca is 0-600 leading to the pre-fault value uoca_n
As demonstrated in Appendix A, when asymmetrical fault and the magnitude of uoca also varies in the range [ 3 2 , 1]
appears between phase b and c, uobc≈0 and uoab≈-uoca. p.u..
Meanwhile, uoab can be expressed as If a Δ/yn-connected transformer is placed behind the filter
Z Z i capacitor, the inverter can supply single-phase load. In this
uoab  ca ab La (34)
Z ab  Z ca situation, the single-phase fault in the secondary side of the
With delta connected equivalent impedances, the pre-fault transformer can be equivalent to the phase-phase fault in the
current of phase a can be expressed as (35). With Method II, primary side of the transformer. Therefore, the previous
the post-fault current of phase a is controlled to keep analysis is also applicable to single-phase fault for VSIs with
consistent with the pre-fault current under linear load. Δ/yn-connected transformer. For three-phase three-leg
assuming the the post-fault current of phase a can track the inverters with Δ/yn-connected transformer, with Method II,
reference of phase a, the post-fault current of phase a can also the healthy phase in the secondary side of the transformer still
be expressed as (35) keep considerable voltage supplying single-phase load even
uoab _ n uoca _ n during fault ride-through.
iLa   (35) If the inverter supplies the nonlinear loads, with Method II,
Z ab Z ca the current limiting reference of healthy phase will be
where uoab_n and uoca_n are the pre-fault voltages. substituting designed as the fundamental component of pre-fault current.
(35) into (34) , uoab can be further expressed as In this case, the post-fault voltage of healthy phase will be
Z Z i Z ca uoab _ n Z ab uoca _ n distorted.
uoab  ca ab La   (36) Based on previous analysis, the characteristics of the
Z ab  Z ca Z ab  Z ca Z ab  Z ca
proposed two current limiting strategies are presented in
Considering λab=Zn/Zab, λca=Zn/Zca (0≤λab, λca≤2), thus, Table I.
Zca/(Zab+Zca)=λab/(λab+λca). Define λab/(λab+λca)=ξ, (0≤ξ≤1), so
3) Acquisition of Proposed Current Limiting References
Zca /(Zab+Zca)=ξ, and Zab/(Zab+Zca)=1-ξ. Therefore, (36) can
be rewritten as In order to obtain the current limiting reference for Method
uoab    uoab _ n  1     uoca _ n (37) II, (33) can be further rewritten as
_ lim it  I La cos  t  ia 
Fig. 7 shows the phasor diagram of uoab and uoca during iLa




asymmetrical fault. As shown in Fig. 7, OA, OB and OC iLb _ lim it  I L _ lim it  cos t  ia  cos   sin t  ia  sin  
represent the phasor of the pre-fault voltage uoab_n, uobc_n and 
uoca_n, respectively. OO' represent the phasor of ξ· uoab_n and iLc _ lim it  I L _ lim it  cos t  ia  cos   sin t  ia  sin  

O'A=(1-ξ) uoab _n. O'A' is parallelal to OF and OA  OA , (38)
considering O'A'A is equilateral triangle. Then O'A'=-(1-ξ) From (38), ILa, cos(ωt-φia), sin(ωt-φia), cosβ and sinβ
uoca_n. So OA'=ξ·uoab_n -(1-ξ) uoca_n,, represents the phasor of need to be calculated to get the current limiting references.
uoab, as shown in Fig.37. Particularly, from (37), if ξ=1 (i.e. The previous analysis has mentioned that the current
no load between phase c and a), uoab is equal to pre-fault limiting reference of phase a during asymmetrical fault is
voltage, uoab_n. Similarly, if ξ=0 (i.e. no load between phase a designed to keep consistent with the fundamental
and b), uoab is equal to pre-fault voltage, -uoca_n. Therefore, component of pre-fault current. Therefore, by applying the
from Fig. 7, when ξ vary in the range of [0, 1], A' will shift in discrete Fourier transform (DFT) algorithm [28], [29] to the
line AF. pre-fault current of phase a, ILa, cos(ωt-φia)and sin(ωt-φia) can

TABLE I
THE COMPARISON OF THE PROPOSED TWO METHODS
Method
Method I Method II
Items
healthy
zero pre-fault current
phase
Output the current limiting the current limiting
current references with reverse references with
fault
phase angle and regulated phase angle
phase
required current and required current
limiting magnitude limiting magnitude
healthy be close to rated
zero
Output phase voltage
voltage fault
zero zero
phase
Fig. 7. Phasor diagram of line voltage based on phase angle regulation

8
be easily acquired. The detailed process is not repeated here.
  
_ lim it  iLb _ lim it  iLc _ lim it  0
Furthermore, considering iLa , TABLE II

according to (38), the following equation can be obtained Parameter Value Parameter Value

cos t  ia   I La  2I L _ lim it cos    0 (39) DC-link

voltage: udc
650 V
Fundamental
frequency: fo
50 Hz

Eq. (39) should hold true for any angle ωt. Therefore, (40) Rated line-
line Switching
can be obtained voltage
380 V
frequency: fsw
10 kHz
I La  2I L _ limit cos   0 (40) (RMS): Vn
The proportional
Finally, cosβ and sinβ can be expressed as Rated
and integral (PI)
active 4 kW Kp-v=6.44, Ki-v=820
  I La parameters of
cos   2 I
power: Po
voltage controller
 L _ lim it Rated The PI parameters
 (41) current 6A of inner current Kp-i=15.4, Ki-i=1250
 4 I L2 _ lim it  I La
2
(RMS): IN controller
sin   2 I L _ lim it Filter
The PI parameters
Kp-lim=14,
 inductor: L
2.7 mH of proposed current
Ki-lim=937.5
limiting controller
ILa is obtained by applying the DFT algorithm to pre-fault The gain and cutoff
current of phase a. Based on above analysis, ILa, cos(ωt-φia), Filter KR=300,
frequency
capacitor: 3.3 μF
sin(ωt-φia), cosβ and sinβ can be obtained, respectively. C
parameters of ωc =6 rad  s 1
Finally, the current limiting reference of each phase can be resonant controller
obtained.
short-circuit fault appears between phase b and c, and the
C. Implementation of the Proposed Current Limiting Strategy
magnitude of the current limiting references, IL_limit, is set to
The current limiting control is implemented in the be 17A.
stationary abc-frame, as shown in Fig. 8. The process of
current limiting strategy can be described as follows. In A. Case I (λab= λca=0)
normal state, the inverter works under the dual loop control. Fig. 9(a) and (b) show the simulation results of current
Once short circuit fault occurs at the load side, the inverter is limiting control based on symmetric current references. For
instantly switched to inner-loop control as the output of the the sake of convenience, the reference of the d-axis is set to
voltage controller is rapidly saturated. In the meantime, for the magnitude of current limiting references and the q-axis is
asymmetrical short-circuit fault, the output voltages of the set to zero. From Fig. 9(a) and (b), when asymmetrical short-
fault phases and healthy phase will be different. Here, by circuit fault appears between phase b and c, the line voltages
means of the output voltage characteristics, the fault type can uoab and uoca are flat-topping sinusoidal waves due to the
be rapidly identified and the current limiting references are voltage limiting. And the currents of fault phases, iLb and iLc,
assigned correspondingly. Then, the inverter is switched to are distorted. Fig. 10(a) further shows waveform of d axis
the proposed current limiting loop from inner current loop. In current. Fig. 10(b) shows the FFT analysis of the d-
order to provide precise control of the currents, a current axiscurrent. It can be seen that d-axis current mainly contains
limiting controller consisting of a proportional integral (PI) DC component and second-order ripple, which represents the
controller and a resonant compensator is adopted [30]. positive- and negative- components of the post-fault currents,
However, for symmetrical short-circuit fault, the inverter respectively. As shown in Fig. 10(b), the value of DC
still works in inner current loop and does not switched to the component is 16.81A which shows that the positive
proposed current limiting loop. component is almost equal to IL_limit (IL_limit=17A), and this
IV. SIMULATION RESULTS verifies the theoretical analysis. On the other hand, Fig. 11(a)
and (b) show the FFT analysis of the post-fault current of
In order to verify the theoretical analysis and the
phase b and c, respectively. Where, the magnitudes of
effectiveness of the proposed current limiting strategies, A
fundamental components are 28.9A and 29.3A, respectively,
4kW three-phase three-leg inverter is established in
phase b and c, respectively. Where, the magnitudes of
MATLAB/Simulink. The parameters are given in Table II.
fundamental components are 28.9A and 29.3A, respectively,
Three cases are carried out when the inverter works
respectively under no-load (λab=λca=0), rated-load (λab=λca=1) whose numbers are close to the theoretical results, 3 · IL_limit
and 2 times rated-load (λab=λca=2). Suppose the asymmetrical (i.e. 29.44A).

Fig. 8. Implement of current limiting control strategy

9
 short-circuit fault appears between phase b and c, line
voltages uoab and uoca are flat-topping sinusoidal waves. And
the currents of fault phases, iLb and iLc, are distorted. Fig. 14(a)
shows waveform of d axis current. From the FFT analysis of
the d axis current shown in Fig. 14(b), the DC component is
16.71A. This shows that the positive component is almost
equal to IL_limit, which verifies the theoretical analysis. In
addition, from Fig. 13 (b), the magnitudes of fundamental
Fig. 9. Simulation results under current limiting control based on symmetric components of post-fault currents of phase b and c are 19.41A
current references when the inverter works under no load before and 20.09A, respectively, which are within the range of
asymmetrical fault occurs (a) Voltage waveforms (b) Current waveforms [IL_limit, 3 ·IL_limit] (correspondingly, [17A, 29.44A]). The
results also verify the theoretical analysis in Section II-B.
Fig. 15(a) and (b) show the simulation results of Method I.
From Fig. 15(b), the post-fault currents of phase b and c are
reverse, and their magnitudes are controlled to be 2IL_limit. The
post-fault current of phase a is close to zero. From Fig. 15(a),
the output voltages are almost zero during fault ride-through.
Fig. 15(c) and (d) show the simulation results of Method II.
From Fig. 15(d), the magnitudes of the post-fault currents
of phase b and c are 2IL_limit. In the meantime, the post-fault
Fig. 10. Analysis results. (a) Waveform of d axis current and (b) FFT current of phase a can keep consistent with the pre-fault
analysis of d axis post-fault current
current with Method II. From Fig. 15(c), the line voltages uab

Fig. 11. FFT analysis of post-fault currents of (a) phase b, and (b) phase c Fig. 13. Simulation results under current limiting control based on
symmetric current references when asymmetrical fault occurs under rated-
load (a) Voltage waveform (b) Current waveform

Fig. 12. Simulation results under Method I when the inverter works under no
load before asymmetrical fault occurs (a) Voltage waveforms (b) Current
waveforms
Fig. 14. Analysis results. (a) Waveforms of d- axis current and (b) FFT
Fig. 12(a) and (b) show the simulation results of Method I. analysis of d axis post-fault current
From Fig. 12(b), the post-fault currents of phase b and c are
not distorted and their magnitudes are controlled to be 2IL_limit
during asymmetrical fault. It is worth noting that uoab and uoca
are not rapidly reduced to zero, as shown in Fig. 12(a). This is
because that the post-fault current of phase a is controlled to
be close to zero, in the meantime, there are no loads to
discharge the output filter capacitors. According to the
analysis in Section III-B, Method II becomes equivalent to
Method I when asymmetrical fault occurs under no load.
Therefore, the results of Method II will be consistent with that
in Fig. 12(a) and (b), and not repeated again.
B. Case II (λab= λca=1)
Fig. 13(a) and (b) show the post-fault voltages and currents
under current limiting control based on symmetric current Fig. 15. Simulation results of voltages and currents when asymmetrical fault
references. From Fig. 13(a) and (b), when asymmetrical occurs under rated load. (a)(b) Method I. (c)(d) Method II.

10
Fig. 16. Simulation results when asymmetrical fault occurs under 2 times
overload. (a)(b) Current limiting control based on symmetric current
references. (c)(d) Method I. (e)(f) Method II.

and uca keep 86.6% (i.e. 3 2 ) of the magnitude of rated

voltage during fault ride-through. Fig. 17. (a) The experimental platform and (b) The schematic diagram of this
C. Case III (λab= λca=2) platform
As shown in Fig. 16(a) and (b), the inverter works under 2 be 17A.
times rated-load before short circuit fault occurs. According A. Case I (λab= λca=0)
to the analysis in Section II, when asymmetrical fault occurs
Fig. 18(a) shows the experimental results of current
in this situation, the voltage limiting does not occur. From Fig.
limiting control based on symmetric current references. From
16(a), the post-fault voltages are not distorted. Therefore, the
Fig. 18(a), the inverter works under no-load before fault
inductor currents are also distorted, and their magnitudes are
occurs. When asymmetrical fault occurs, the post-fault
controlled to be 2IL_limit.
voltages uoab and uoca are flat-topping sinusoidal waves due to
Fig. 16(c) and (d) show the experimental results of Method
the voltage limiting. And the currents of fault phases, iLb and
I. From Fig. 16 (d), the post-fault currents of phase b and c
iLc, are distorted. Fig. 19 shows the FFT analysis of the
are reverse, and their magnitudes are controlled to be 2IL_limit. currents of phase b and c. From Fig. 19, the magnitudes of
The post-fault current of phase a is controlled to be close to their fundamental component are 29.1A and 29.4A,
zero. Fig. 16(e) and (f) show the experimental results of
respectively, which are close to theoretical value, 3 · IL_limit
Method II. From Fig. 16(f), the magnitudes of the post-fault
(i.e. 29.44A). Because of the shortage of experimental
currents of phase b and c are 2IL_limit. In the meantime, the
equipment, it is difficult to observe waveforms of d- and q-
post-fault current of phase a can keep consistent with the pre-
axis currents in the experiment. However, from Fig. 18(a), the
fault current with Method II. Fig. 16(e) shows uab and uca can voltages and currents are almost consistent with the
keep 86.6% (i.e. 3 2 ) of the magnitude of rated voltage simulation results. Therefore, the experiment results can also
during fault ride-through. verify the theoretical analysis in Section II-B.
In summary, various simulation results prove the validity Fig. 18(b) shows the experimental results of Method I.
of the short circuit current characteristics analysis and the From Fig. 18(b), the magnitudes of post-fault currents of
effectiveness of the proposed current limiting strategies. phase b and c are controlled to be 2IL_limit. The post-fault
current of phase a is controlled to be close to zero. When
V. EXPERIMENTAL RESULTS asymmetrical fault occurs under no load, Method II becomes
The experiments are performed on a rated 4-kW platform. equivalent to Method I. Therefore, in this condition, the
Fig. 17(a) and (b) show the test setup and its schematic results of Method II are consistent with that in Fig. 18(b), and
diagram, respectively. The parameters of the prototype have the results will not be repeated again.
been listed in Table II. The inverter is controlled by a DSP
(TMS320F2812). A 0-8kW resistive load box is connected to B. Case II (λab= λca=1)
the inverter. Therefore, the different load conditions can be Fig. 20(a)-(c) show the experimental results when
easily realized. asymmetrical fault occurs under rated load. The experimental
Three cases are carried out when the inverter works results of Fig. 20(a) are almost consistent with the simulation
respectively under no-load (λab=λca=0), rated-load (λab=λca=1) results. Therefore, the experimental results can also prove the
and 2 times rated-load (λab=λca=2). Suppose the asymmetrical validity of the theoretical analysis in Section II. Fig. 20(b)
magnitude of the current limiting references, IL_limit, is set to and (c) show that the experimental results of Method I and

11
Method II, respectively. It can be seen that the post-fault of the magnitude of rated voltage during fault ride-through.
currents of phase b and c can be controlled to be 2IL_limit. For Therefore, the healthy phase can continuously supply load
Method I, the post-fault current of phase a is controlled to be even during fault ride-through.
close to zero. For Method II, the post-fault current of phase a C. Case III (λab= λca=2)
can be controlled to keep consistent with the pre-fault current.
Fig.20(d)-(f) show the experimental results when
In addition, from Fig. 20(c), uab and uca keep 86.6% (i.e. 3 2 ) asymmetrical fault occurs under 2 times rated-load.
According to the analysis in Section II-A, in this situation, the
voltage limiting does not occur. Therefore, From Fig. 20(d),
the post-fault voltages are not distorted. The inductor currents
are not distorted, and their magnitudes are controlled to be
2IL_limit. The results verify the theoretical analysis in Section
II-A. In addition, from Fig. 20(e) and (f), the experimental
results also verify the theoretical analysis of Method I and
Method II, respectively.
VI. CONCLUSION
Generally, in order to limit the short-circuit currents, the
Fig. 18 Experimental results when the inverter works under no load before inverters are switched to the current-controlled mode from
asymmetrical fault occurs. (a) Current limiting control based on symmetric voltage-controlled mode when short-circuit fault occurs. In
current references. (b)Method I this situation, the inverter becomes equivalent to a symmetric,
three-phase, positive sequence current source. However, the
voltage limiting may occur under asymmetrical short circuit
fault. In this paper, the mechanism of the voltage limiting of
three phase three leg inverter under asymmetrical fault is
discussed in detail. Furthermore, a closed-loop model is
original developed as a means to investigate the fault current
characteristics under the voltage limiting. Based on the
Fig. 19. Experimental results: FFT analysis of post-fault currents of (a)
proposed model, a more intuitive insight into fault currents is
phase b, and (b) phase c presented. In order to achieve completely controllable fault
currents under asymmetrical fault, two alternative current
limiting strategies are presented with a reverse current
limiting references(Method I), and with the current limiting
references by the regulating phase angle (Method II).
Thetheoretical analysis and proposed current limiting
strategies are both validated by simulation and experimental
results.
APPENDIX A
The equivalent circuit under asymmetrical fault is shown in
Fig. 2. The currents flowing through the filter capacitances
are relatively small in comparison with the inductor current,
and are ignored in this paper. Thus, the inductor current is
approximately equal to the output current. Furthermore,
according to Fig. 2, applying Kirchhoff's current law (KCL)
and Kirchhoff's voltage law (KVL), (A1) can be obtained.
iLa  ioab  ioca

iLb  iobc  ioab (A1)
i Z  i Z  i Z  0
 oab ab obc f oca bc
The line voltages can be expressed as
 Z ca iLa  Z F iLb
uoab  Z  Z  Z Z ab
 ab ca f

Fig. 20 Experimental results when the inverter works under rated load before
  Z F  Z ca  iLa  Z ca iLc (A2)
asymmetrical fault occurs. (a) Current limiting control based on symmetric
current references. (b) Method I. (c) Method II. Experimental results when
uobc  Z ab  Z ca  Z f
Zf
asymmetrical fault occurs under 2 times rated-load. (d) Current limiting

control based on symmetric current references. (e) Method I. (f) Method II.

uoca  uoab  uobc

12
Fig. A1. Current limiting control system based on the abc-frame considering voltage limiting. (a) the voltage limiting block is implemented in abc-frame and (b)
the voltage limiting block is implemented in dq-frame.

Note that Zf<<Zab and Zf<<Zca under asymmetrical fault, 2 2

thus, (A2) can be further simplified as where uab  ubc2  uca2  urd2  urq2 .
3
 Z ca Z ab iLa
uoab  Z  Z
On one hand, from Fig. A1(b), the purple line section
 ab ca including the voltage limiting block and circuit constraints of
 (A3)
uobc  0
main is nonlinear as of the voltage limiting, meanwhile, has
uoca  uoab been analyzed in this paper. On the other hand, A2(a) and (b)
is still linear and is not affected by the voltage limiting.
where uoab, uobc and uoca are the output line voltages in load Therefore, the proposed analysis method can also be easily
side. Eq. (A3) shows the output voltages are decided by the extended to analyze the control system based on abc-frame.
inductor current and load impedances.
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14
 Zhigang Liang was born in Anhui, China, in 1989.
He received the B.E. degree from Hebei University of
Science and Technology, Shijiazhuang, China, in 2011.
He is currently working toward the Ph.D. degree with
the School of Electrical and Electronic Engineering,
Huazhong University of Science and Technology,
Wuhan, China.
His research interests include three-level converters,
power electronic converter and related control
techniques.

Xinchun Lin (M’12), Corresponding Author, received

the B.E. and Ph.D. degrees in electrical engineering from
Huazhong University of Science and Technology,
Wuhan, China, in1998, and 2003, respectively. Since
2003, he was a Senior Engineer at Santak Eletronic
(Shenzhen) Co., Ltd. In 2006, he joined Huazhong
University of Science and Technology as a Lecturer and
was promoted to an Associate Professor in 2008. From
September 2013 to September 2014, he was a Visiting
Scholar at Florida State University, Tallahassee, FL, USA. His research
interests include the fields linked with power electronic converter, power
electronic applications in power system, and related control techniques.

Yong Kang was born in Hubei Province, China, in

1965. He received the B.E., M.E., and Ph.D. degrees
from the Huazhong University of Science and
Technology (HUST), Wuhan, China, in 1988, 1991,
and 1994, respectively.
In 1994, he joined the School of Electrical and
Electronic Engineering, HUST, where he became a
Professor in 1998. He is the author or coauthor of more
than 200 technical papers published in journals and conferences. His research
interests include power electronic converter, ac drivers, electromagnetic
compatibility, and renewable energy generation system.
Dr. Kang received the Delta Scholar Award from the Delta Environmental
and Educational Foundation in 2005, and supported by the Program for New
Century Excellent Talents in University from the Chinese Ministry of
Education in 2004. Currently, he serves as the vice chairman of the China
UPS standard committee and the Associate Editor for the JOURNAL OF
POWER ELECTRONICS.

Bofeng Gao was born in Shanxi, China, in 1992. He

received the B.E. degree from Hohai University, Nan
Jing, China, in 2015. He is currently working toward
the M.E. degree with the School of Electrical and
Electronic Engineering, Huazhong University of
Science and Technology, Wuhan, China.
His research interests include power electronic
converter and related control techniques.

He Lei was born in Hubei province, China, in 1985.

He received Ph.D. degrees from Huazhong University
of Science and Technology, Wuhan, China, in 2014. He
is currently an Engineer with the State Grid HBEPC
Economic & Technology Research Institute.
His current research interests include power
electronic converters and their digital control
techniques.

15
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